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File indexing completed on 2025-05-11 08:23:57

0001 /*
0002  * @file
0003  * @ingroup powerpc_psim
0004  * @brief Implementations for interrupt mechanisms for Time Test 27
0005  */
0006 
0007 /*
0008  *  The license and distribution terms for this file may be
0009  *  found in the file LICENSE in this distribution or at
0010  *  http://www.rtems.org/license/LICENSE.
0011  */
0012 
0013 #ifndef _RTEMS_TMTEST27
0014 #error "This is an RTEMS internal file you must not include directly."
0015 #endif
0016 
0017 #ifndef __tm27_h
0018 #define __tm27_h
0019 
0020 #include <bsp/irq.h>
0021 
0022 /*
0023  *  Stuff for Time Test 27
0024  */
0025 
0026 #define MUST_WAIT_FOR_INTERRUPT 1
0027 
0028 static void nullFunc(void) {}
0029 static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
0030                                               0,
0031                                               (rtems_irq_enable)nullFunc,
0032                                               (rtems_irq_disable)nullFunc,
0033                                               (rtems_irq_is_enabled) nullFunc};
0034 
0035 static inline void Install_tm27_vector( rtems_interrupt_handler handler )
0036 {
0037   clockIrqData.hdl = handler;
0038   if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
0039     printk("Error installing clock interrupt handler!\n");
0040     rtems_fatal_error_occurred(1);
0041   }
0042 }
0043 
0044 #define Cause_tm27_intr()  \
0045   do { \
0046     uint32_t _clicks = 1; \
0047     __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
0048   } while (0)
0049 
0050 
0051 #define Clear_tm27_intr() \
0052   do { \
0053     uint32_t _clicks = 0xffffffff; \
0054     __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
0055   } while (0)
0056 
0057 #define Lower_tm27_intr() \
0058   do { \
0059     uint32_t _msr = 0; \
0060     _ISR_Set_level( 0 ); \
0061     __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
0062     _msr |=  0x8002; \
0063     __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
0064   } while (0)
0065 
0066 #endif