psim/include/psim.h

0001 /*
0002  *  PSIM addresses and constants based upon the configuration
0003  *  of devices used in the script provided by RTEMS.
0004  */
0005
0006 #ifndef __PSIM_h
0007 #define __PSIM_h
0008
0009 /*
0010  * RAM Information
0011  */
0012
0013 extern char RamBase[];
0014 extern char RamSize[];
0015
0016 /*
0017  * RamBase/RamSize is defined by the linker script;
0018  * CPP symbols are AFAIK unused and deprecated.
0019  */
0020 #define PSIM_RAM_SIZE ((unsigned long)RamSize)
0021 #define PSIM_RAM_BASE ((void*)RamBase)
0022
0023 /*
0024  * NVRAM/RTC Structure and Information
0025  */
0026
0027 #define PSIM_RTC_FREEZE 0xc0
0028 #define PSIM_RTC_UPDATE 0x00
0029
0030 typedef struct {
0031   volatile uint8_t Control; /* 0x04 */
0032   volatile uint8_t Second;  /* 0x05 */
0033   volatile uint8_t Minute;  /* 0x06 */
0034   volatile uint8_t Hour;    /* 0x07 */
0035   volatile uint8_t Day;     /* 0x08 */
0036   volatile uint8_t Date;    /* 0x09 */
0037   volatile uint8_t Month;   /* 0x0a */
0038   volatile uint8_t Year;    /* 0x0b */
0039 } psim_rtc_t;
0040
0041 /*
0042  *  System V IPC Semaphore -- Read Only
0043  */
0044
0045 typedef struct {
0046   volatile uint32_t  obtain_value;  /* 0x00 */
0047   volatile uint32_t  lock;          /* 0x04 */
0048   volatile uint32_t  unlock;        /* 0x08 */
0049 } psim_sysv_sem_t;
0050
0051 typedef struct {
0052   /* 0x0c000000 - 0x0c007FFF - AMD 29F040 */
0053   volatile uint8_t Flash[ 512 * 1024 ];
0054
0055   /* 0x0c080000 - 0x0c0FFFFF - NVRAM/NVRAM */
0056   volatile uint8_t nvram[ 512 * 1024 ];
0057
0058   /* 0x0c100000 - 0x0c100007 - NVRAM/RTC */
0059   psim_rtc_t RTC;
0060
0061   /* 0x0c100008 - 0x0c10000F - NVRAM/RTC */
0062   uint8_t gap1[8];
0063
0064   /* 0x0c100010 - 0x0c10001b - System V IPC Semaphore */
0065   psim_sysv_sem_t Semaphore;
0066
0067   /* 0x0c10001c - 0x0c10001f - NVRAM/RTC */
0068   uint8_t gap2[4];
0069
0070   /* 0x0c100020 - 0x0c10005F - Ethernet */
0071   volatile uint8_t Ethtap[ 64 ];
0072
0073   /* 0x0c100060 - 0x0c10FFFF - NVRAM/RTC */
0074   uint8_t gap3[65440];
0075
0076   /* 0x0c110000 - 0x0c12FFFF - System V IPC Shared Memory */
0077   uint8_t SharedMemory[ 128 * 1024 ];
0078
0079   /* 0x0c130000 - 0x0c170000 - OpenPIC IRQ Controller */
0080   volatile uint8_t OpenPIC[ 256 * 1024 ];
0081
0082 } psim_registers_t;
0083
0084 /*
0085  *  Data Structure Overlay for Registers.  See linkcmds for placement.
0086  */
0087 extern psim_registers_t PSIM;
0088
0089 #endif
0090 /* end of include file */