mvme5500/start/start.S

0001 /*
0002  *  start.S :     RTEMS entry point
0003  *
0004  *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
0005  *
0006  *  S. Kate Feng <feng1@bnl.gov>, April 2004
0007  *  Mapped the 2nd 256MB of RAM to support the MVME5500/MVME6100 boards
0008  *
0009  *  The license and distribution terms for this file may be
0010  *  found in the file LICENSE in this distribution or at
0011  *  http://www.rtems.org/license/LICENSE.
0012  *
0013  */
0014
0015 #include <rtems/asm.h>
0016 #include <libcpu/powerpc-utility.h>
0017
0018 #include <libcpu/io.h>
0019 #include <libcpu/bat.h>
0020 #include <bspopts.h>
0021
0022 #define SYNC \
0023     sync; \
0024     isync
0025
0026 #define KERNELBASE  0x0
0027 #define MEM256MB        0x10000000
0028
0029 #define MONITOR_ENTER           \
0030     mfmsr   r10     ;   \
0031     ori r10,r10,MSR_IP  ;   \
0032     mtmsr   r10     ;   \
0033     li  r10,0x63    ;   \
0034     sc
0035
0036     .text
0037     .globl  __rtems_entry_point
0038     .type   __rtems_entry_point,@function
0039 __rtems_entry_point:
0040 #ifdef DEBUG_EARLY_START
0041     MONITOR_ENTER
0042 #endif
0043
0044 /*
0045  * PREP
0046  * This is jumped to on prep systems right after the kernel is relocated
0047  * to its proper place in memory by the boot loader.  The expected layout
0048  * of the regs is:
0049  *   r3: ptr to residual data
0050  *   r4: initrd_start or if no initrd then 0
0051  *   r5: initrd_end - unused if r4 is 0
0052  *   r6: Start of command line string
0053  *   r7: End of command line string
0054  *
0055  *   The Prep boot loader insure that the MMU is currently off...
0056  *
0057  */
0058
0059     mr  r31,r3          /* save parameters */
0060     mr  r30,r4
0061     mr  r29,r5
0062     mr  r28,r6
0063     mr  r27,r7
0064
0065 #ifdef __ALTIVEC__
0066     /* enable altivec; gcc may use it! */
0067     mfmsr r0
0068     oris  r0, r0, (1<<(31-16-6))
0069     mtmsr r0
0070     isync
0071     /*
0072      * set vscr and vrsave to known values
0073      */
0074     li    r0, 0
0075     mtvrsave r0
0076     vxor   0,0,0
0077     mtvscr 0
0078 #endif
0079
0080     /*
0081      * Make sure we have nothing in BATS and TLB
0082      */
0083     bl  CPU_clear_bats_early
0084     bl  flush_tlbs
0085 /*
0086  * Use the first pair of BAT registers to map the 1st 256MB
0087  * of RAM to KERNELBASE.
0088  */
0089     lis r11,KERNELBASE@h
0090 /* set up BAT registers for 604 */
0091     ori r11,r11,0x1ffe
0092     li  r8,2            /* R/W access */
0093     isync
0094     mtspr   DBAT0L,r8       /* N.B. 6xx (not 601) have valid */
0095     mtspr   DBAT0U,r11      /* bit in upper BAT register */
0096     mtspr   IBAT0L,r8
0097     mtspr   IBAT0U,r11
0098     isync
0099 /*
0100  * <skf> Use the 2nd pair of BAT registers to map the 2nd 256MB
0101  * of RAM to 0x10000000.
0102  */
0103     lis r11,MEM256MB@h
0104     ori r11,r11,0x1ffe      /* set up BAT1 registers for 604+ */
0105     lis r8,MEM256MB@h
0106     ori     r8,r8,2
0107     isync
0108     mtspr   DBAT1L,r8       /* N.B. 6xx (not 601) have valid */
0109     mtspr   DBAT1U,r11      /* bit in upper BAT register */
0110     mtspr   IBAT1L,r8
0111     mtspr   IBAT1U,r11
0112     isync
0113
0114 /*
0115  * we now have the two 256M of ram mapped with the bats. We are still
0116  * running on the bootloader stack and cannot switch to an RTEMS allocated
0117  * init stack before copying the residual data that may have been set just
0118  * after rtems_end address. This bug has been experienced on MVME2304. Thank
0119  * to Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and
0120  * suggesting the appropriate code.
0121  */
0122
0123 enter_C_code:
0124     bl  MMUon
0125     bl      __eabi  /* setup EABI and SYSV environment */
0126     bl  zero_bss
0127     /*
0128      * restore prep boot params
0129      */
0130     mr  r3,r31
0131     mr  r4,r30
0132     mr  r5,r29
0133     mr  r6,r28
0134     mr  r7,r27
0135     bl  save_boot_params
0136
0137     /*
0138      * Initialize start stack.  The stacks are statically allocated and
0139      * properly aligned.
0140      */
0141     LA  r1, _ISR_Stack_area_end
0142     subi    r1, r1, PPC_DEFAULT_CACHE_LINE_SIZE
0143     li  r0, 0
0144     stw r0, 0(r1)
0145
0146     /*
0147      * We are now in a environment that is totally independent from
0148      * bootloader setup.
0149      */
0150     /* pass result of 'save_boot_params' to 'boot_card' in R3 */
0151     bl  boot_card
0152     bl  _return_to_ppcbug
0153
0154     .globl  MMUon
0155     .type   MMUon,@function
0156 MMUon:
0157     mfmsr   r0
0158     ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
0159 #if (PPC_HAS_FPU == 0)
0160     xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
0161 #else
0162     xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
0163 #endif
0164     mflr    r11
0165     mtsrr0  r11
0166     mtsrr1  r0
0167     SYNC
0168     rfi
0169
0170     .globl  MMUoff
0171     .type   MMUoff,@function
0172 MMUoff:
0173     mfmsr   r0
0174     ori r0,r0,MSR_IR| MSR_DR | MSR_IP
0175     mflr    r11
0176     xori    r0,r0,MSR_IR|MSR_DR
0177     mtsrr0  r11
0178     mtsrr1  r0
0179     SYNC
0180     rfi
0181
0182     .globl  _return_to_ppcbug
0183     .type   _return_to_ppcbug,@function
0184
0185 _return_to_ppcbug:
0186     mflr    r30
0187     bl  MMUoff
0188     MONITOR_ENTER
0189     bl  MMUon
0190     mtctr   r30
0191     bctr
0192
0193 flush_tlbs:
0194     lis r20, 0x1000
0195 1:  addic.  r20, r20, -0x1000
0196     tlbie   r20, 0
0197     bgt 1b
0198     sync
0199     blr