mvme5500/pci/pci_interface.c

0001 /* pci_interface.c
0002  *
0003  * Copyright 2004, 2006, 2007 All rights reserved. (NDA items)
0004  *      Brookhaven National Laboratory and Shuchen Kate Feng <feng1@bnl.gov>
0005  *
0006  * The license and distribution terms for this file may be
0007  * found in the file LICENSE in this distribution.
0008  *
0009  * 8/17/2006 : S. Kate Feng
0010  *             uses in_le32()/out_le32(), instead of inl()/outl() for compatibility.
0011  *
0012  * 11/2008 : Enable "PCI Read Agressive Prefetch",
0013  *           "PCI Read Line Agressive Prefetch", and
0014  *           "PCI Read Multiple Agressive Prefetch" to improve the
0015  *           performance of the PCI based applications (e.g. 1GHz NIC).
0016  */
0017
0018 #include <libcpu/io.h>
0019 #include <rtems/bspIo.h>        /* printk */
0020
0021 #include <bsp.h>
0022 #include <bsp/pci.h>
0023 #include <bsp/gtreg.h>
0024 #include <bsp/gtpcireg.h>
0025
0026 #include <inttypes.h>
0027
0028 #define PCI_DEBUG     0
0029
0030 #if 0
0031 #define CPU2PCI_ORDER
0032 #define PCI2CPU_ORDER
0033 #endif
0034
0035 /* PCI Read Agressive Prefetch Enable (1<<16 ),
0036  * PCI Read Line Agressive Prefetch Enable( 1<<17),
0037  * PCI Read Multiple Agressive Prefetch Enable (1<<18).
0038  */
0039 #ifdef PCI2CPU_ORDER
0040 #define PCI_ACCCTLBASEL_VALUE          0x01079000
0041 #else
0042 #define PCI_ACCCTLBASEL_VALUE          0x01071000
0043 #endif
0044
0045
0046 #define ConfSBDis     0x10000000  /* 1: disable, 0: enable */
0047 #define IOSBDis       0x20000000  /* 1: disable, 0: enable */
0048 #define ConfIOSBDis   0x30000000
0049 #define CpuPipeline   0x00002000  /* optional, 1:enable, 0:disable */
0050
0051 /* CPU to PCI ordering register */
0052 #define DLOCK_ORDER_REG    0x2D0  /* Deadlock and Ordering register */
0053 #define PCI0OrEn      0x00000001
0054 #define PCI1OrEn      0x00000020
0055 #define PCIOrEn       0x40000000
0056 #define PCIOrEnMASK   0x40000021
0057
0058 #define CNT_SYNC_REG       0x2E0  /* Counters and Sync Barrier register */
0059 #define L0SyncBar     0x00001000
0060 #define L1SyncBar     0x00002000
0061 #define DSyncBar      0x00004000
0062 #define SyncBarMode   0x00008000
0063 #define SyncBarMASK   0x0000f000
0064
0065 #define WRTBK_PRIO_BUFFER  0x2d8  /* writback priority and buffer depth */
0066
0067 #define ADDR_PIPELINE 0x00020000
0068
0069 void  pciAccessInit(void);
0070
0071 void pci_interface(void)
0072 {
0073
0074 #ifdef CPU2PCI_ORDER
0075     /* MOTLOad deafult : 0x07ff8600 */
0076     out_le32((volatile uint32_t *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);
0077 #endif
0078     /* asserts SERR upon various detection */
0079     out_le32((volatile uint32_t *)(GT64x60_REG_BASE+0xc28), 0x3fffff);
0080     pciAccessInit();
0081 }
0082
0083 void pciAccessInit(void)
0084 {
0085   unsigned int PciLocal, data;
0086
0087   for (PciLocal=0; PciLocal < 2; PciLocal++) {
0088     data = in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
0089 #if 0
0090     printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data);
0091 #endif
0092     data |= PCI_ACCCTLBASEL_VALUE;
0093     data &= ~0x300000;
0094     out_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);
0095 #if 0
0096       printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%" PRIx32 "\n",PciLocal,in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))));
0097 #endif
0098   }
0099 }
0100