include/bsp/pcireg.h

0001 /*  $NetBSD: pcireg.h,v 1.44 2003/12/02 16:31:06 briggs Exp $   */
0002
0003 /*
0004  * Copyright (c) 1995, 1996, 1999, 2000
0005  *     Christopher G. Demetriou.  All rights reserved.
0006  * Copyright (c) 1994, 1996 Charles M. Hannum.  All rights reserved.
0007  * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  * 3. All advertising materials mentioning features or use of this software
0018  *    must display the following acknowledgement:
0019  *  This product includes software developed by Charles M. Hannum.
0020  * 4. The name of the author may not be used to endorse or promote products
0021  *    derived from this software without specific prior written permission.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
0024  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
0025  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0026  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0027  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0028  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0029  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0030  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0031  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0032  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0033  */
0034 #include <bsp.h>
0035
0036 /*
0037  * PCI Class and Revision Register; defines type and revision of device.
0038  */
0039 #define PCI_CLASS_REG           0x08
0040
0041 #define PCI_CLASS_SHIFT             24
0042 #define PCI_CLASS_MASK              0xff
0043 #define PCI_CLASS(cr) \
0044         (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
0045
0046 #define PCI_SUBCLASS_SHIFT          16
0047 #define PCI_SUBCLASS_MASK           0xff
0048 #define PCI_SUBCLASS(cr) \
0049         (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
0050
0051 #define PCI_INTERFACE_SHIFT         8
0052 #define PCI_INTERFACE_MASK          0xff
0053 #define PCI_INTERFACE(cr) \
0054         (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
0055
0056 #define PCI_REVISION_SHIFT          0
0057 #define PCI_REVISION_MASK           0xff
0058 #define PCI_REVISION(cr) \
0059         (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
0060
0061 #define PCI_CLASS_CODE(mainclass, subclass, interface) \
0062         ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
0063          (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
0064          (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
0065
0066 /* base classes */
0067 #define PCI_CLASS_PREHISTORIC           0x00
0068 #define PCI_CLASS_MASS_STORAGE          0x01
0069 #define PCI_CLASS_NETWORK           0x02
0070 #define PCI_CLASS_DISPLAY           0x03
0071 #define PCI_CLASS_MULTIMEDIA            0x04
0072 #define PCI_CLASS_MEMORY            0x05
0073 #define PCI_CLASS_BRIDGE            0x06
0074 #define PCI_CLASS_COMMUNICATIONS        0x07
0075 #define PCI_CLASS_SYSTEM            0x08
0076 #define PCI_CLASS_INPUT             0x09
0077 #define PCI_CLASS_DOCK              0x0a
0078 #define PCI_CLASS_PROCESSOR         0x0b
0079 #define PCI_CLASS_SERIALBUS         0x0c
0080 #define PCI_CLASS_WIRELESS          0x0d
0081 #define PCI_CLASS_I2O               0x0e
0082 #define PCI_CLASS_SATCOM            0x0f
0083 #define PCI_CLASS_CRYPTO            0x10
0084 #define PCI_CLASS_DASP              0x11
0085 #define PCI_CLASS_UNDEFINED         0xff
0086
0087 /* 0x00 prehistoric subclasses */
0088 #define PCI_SUBCLASS_PREHISTORIC_MISC       0x00
0089 #define PCI_SUBCLASS_PREHISTORIC_VGA        0x01
0090
0091 /* 0x01 mass storage subclasses */
0092 #define PCI_SUBCLASS_MASS_STORAGE_SCSI      0x00
0093 #define PCI_SUBCLASS_MASS_STORAGE_IDE       0x01
0094 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY    0x02
0095 #define PCI_SUBCLASS_MASS_STORAGE_IPI       0x03
0096 #define PCI_SUBCLASS_MASS_STORAGE_RAID      0x04
0097 #define PCI_SUBCLASS_MASS_STORAGE_ATA       0x05
0098 #define PCI_SUBCLASS_MASS_STORAGE_SATA      0x06
0099 #define PCI_SUBCLASS_MASS_STORAGE_MISC      0x80
0100
0101 /* 0x02 network subclasses */
0102 #define PCI_SUBCLASS_NETWORK_ETHERNET       0x00
0103 #define PCI_SUBCLASS_NETWORK_TOKENRING      0x01
0104 #define PCI_SUBCLASS_NETWORK_FDDI       0x02
0105 #define PCI_SUBCLASS_NETWORK_ATM        0x03
0106 #define PCI_SUBCLASS_NETWORK_ISDN       0x04
0107 #define PCI_SUBCLASS_NETWORK_WORLDFIP       0x05
0108 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
0109 #define PCI_SUBCLASS_NETWORK_MISC       0x80
0110
0111 /* 0x03 display subclasses */
0112 #define PCI_SUBCLASS_DISPLAY_VGA        0x00
0113 #define PCI_SUBCLASS_DISPLAY_XGA        0x01
0114 #define PCI_SUBCLASS_DISPLAY_3D         0x02
0115 #define PCI_SUBCLASS_DISPLAY_MISC       0x80
0116
0117 /* 0x04 multimedia subclasses */
0118 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO       0x00
0119 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO       0x01
0120 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY   0x02
0121 #define PCI_SUBCLASS_MULTIMEDIA_MISC        0x80
0122
0123 /* 0x05 memory subclasses */
0124 #define PCI_SUBCLASS_MEMORY_RAM         0x00
0125 #define PCI_SUBCLASS_MEMORY_FLASH       0x01
0126 #define PCI_SUBCLASS_MEMORY_MISC        0x80
0127
0128 /* 0x06 bridge subclasses */
0129 #define PCI_SUBCLASS_BRIDGE_HOST        0x00
0130 #define PCI_SUBCLASS_BRIDGE_ISA         0x01
0131 #define PCI_SUBCLASS_BRIDGE_EISA        0x02
0132 #define PCI_SUBCLASS_BRIDGE_MC          0x03    /* XXX _MCA? */
0133 #define PCI_SUBCLASS_BRIDGE_PCI         0x04
0134 #define PCI_SUBCLASS_BRIDGE_PCMCIA      0x05
0135 #define PCI_SUBCLASS_BRIDGE_NUBUS       0x06
0136 #define PCI_SUBCLASS_BRIDGE_CARDBUS     0x07
0137 #define PCI_SUBCLASS_BRIDGE_RACEWAY     0x08
0138 #define PCI_SUBCLASS_BRIDGE_STPCI       0x09
0139 #define PCI_SUBCLASS_BRIDGE_INFINIBAND      0x0a
0140 #define PCI_SUBCLASS_BRIDGE_MISC        0x80
0141
0142 /* 0x07 communications subclasses */
0143 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL  0x00
0144 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL    0x01
0145 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL    0x02
0146 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM   0x03
0147 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB    0x04
0148 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD   0x05
0149 #define PCI_SUBCLASS_COMMUNICATIONS_MISC    0x80
0150
0151 /* 0x08 system subclasses */
0152 #define PCI_SUBCLASS_SYSTEM_PIC         0x00
0153 #define PCI_SUBCLASS_SYSTEM_DMA         0x01
0154 #define PCI_SUBCLASS_SYSTEM_TIMER       0x02
0155 #define PCI_SUBCLASS_SYSTEM_RTC         0x03
0156 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG      0x04
0157 #define PCI_SUBCLASS_SYSTEM_MISC        0x80
0158
0159 /* 0x09 input subclasses */
0160 #define PCI_SUBCLASS_INPUT_KEYBOARD     0x00
0161 #define PCI_SUBCLASS_INPUT_DIGITIZER        0x01
0162 #define PCI_SUBCLASS_INPUT_MOUSE        0x02
0163 #define PCI_SUBCLASS_INPUT_SCANNER      0x03
0164 #define PCI_SUBCLASS_INPUT_GAMEPORT     0x04
0165 #define PCI_SUBCLASS_INPUT_MISC         0x80
0166
0167 /* 0x0a dock subclasses */
0168 #define PCI_SUBCLASS_DOCK_GENERIC       0x00
0169 #define PCI_SUBCLASS_DOCK_MISC          0x80
0170
0171 /* 0x0b processor subclasses */
0172 #define PCI_SUBCLASS_PROCESSOR_386      0x00
0173 #define PCI_SUBCLASS_PROCESSOR_486      0x01
0174 #define PCI_SUBCLASS_PROCESSOR_PENTIUM      0x02
0175 #define PCI_SUBCLASS_PROCESSOR_ALPHA        0x10
0176 #define PCI_SUBCLASS_PROCESSOR_POWERPC      0x20
0177 #define PCI_SUBCLASS_PROCESSOR_MIPS     0x30
0178 #define PCI_SUBCLASS_PROCESSOR_COPROC       0x40
0179
0180 /* 0x0c serial bus subclasses */
0181 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE     0x00
0182 #define PCI_SUBCLASS_SERIALBUS_ACCESS       0x01
0183 #define PCI_SUBCLASS_SERIALBUS_SSA      0x02
0184 #define PCI_SUBCLASS_SERIALBUS_USB      0x03
0185 #define PCI_SUBCLASS_SERIALBUS_FIBER        0x04    /* XXX _FIBRECHANNEL */
0186 #define PCI_SUBCLASS_SERIALBUS_SMBUS        0x05
0187 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND   0x06
0188 #define PCI_SUBCLASS_SERIALBUS_IPMI     0x07
0189 #define PCI_SUBCLASS_SERIALBUS_SERCOS       0x08
0190 #define PCI_SUBCLASS_SERIALBUS_CANBUS       0x09
0191
0192 /* 0x0d wireless subclasses */
0193 #define PCI_SUBCLASS_WIRELESS_IRDA      0x00
0194 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR    0x01
0195 #define PCI_SUBCLASS_WIRELESS_RF        0x10
0196 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH     0x11
0197 #define PCI_SUBCLASS_WIRELESS_BROADBAND     0x12
0198 #define PCI_SUBCLASS_WIRELESS_802_11A       0x20
0199 #define PCI_SUBCLASS_WIRELESS_802_11B       0x21
0200 #define PCI_SUBCLASS_WIRELESS_MISC      0x80
0201
0202 /* 0x0e I2O (Intelligent I/O) subclasses */
0203 #define PCI_SUBCLASS_I2O_STANDARD       0x00
0204
0205 /* 0x0f satellite communication subclasses */
0206 /*  PCI_SUBCLASS_SATCOM_???         0x00    / * XXX ??? */
0207 #define PCI_SUBCLASS_SATCOM_TV          0x01
0208 #define PCI_SUBCLASS_SATCOM_AUDIO       0x02
0209 #define PCI_SUBCLASS_SATCOM_VOICE       0x03
0210 #define PCI_SUBCLASS_SATCOM_DATA        0x04
0211
0212 /* 0x10 encryption/decryption subclasses */
0213 #define PCI_SUBCLASS_CRYPTO_NETCOMP     0x00
0214 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT   0x10
0215 #define PCI_SUBCLASS_CRYPTO_MISC        0x80
0216
0217 /* 0x11 data acquisition and signal processing subclasses */
0218 #define PCI_SUBCLASS_DASP_DPIO          0x00
0219 #define PCI_SUBCLASS_DASP_TIMEFREQ      0x01
0220 #define PCI_SUBCLASS_DASP_SYNC          0x10
0221 #define PCI_SUBCLASS_DASP_MGMT          0x20
0222 #define PCI_SUBCLASS_DASP_MISC          0x80
0223
0224 /*
0225  * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
0226  */
0227 #define PCI_BHLC_REG            0x0c
0228
0229 #define PCI_BIST_SHIFT              24
0230 #define PCI_BIST_MASK               0xff
0231 #define PCI_BIST(bhlcr) \
0232         (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
0233
0234 #define PCI_HDRTYPE_SHIFT           16
0235 #define PCI_HDRTYPE_MASK            0xff
0236 #define PCI_HDRTYPE(bhlcr) \
0237         (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
0238
0239 #define PCI_HDRTYPE_TYPE(bhlcr) \
0240         (PCI_HDRTYPE(bhlcr) & 0x7f)
0241 #define PCI_HDRTYPE_MULTIFN(bhlcr) \
0242         ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
0243
0244 #define PCI_LATTIMER_SHIFT          8
0245 #define PCI_LATTIMER_MASK           0xff
0246 #define PCI_LATTIMER(bhlcr) \
0247         (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
0248
0249 #define PCI_CACHELINE_SHIFT         0
0250 #define PCI_CACHELINE_MASK          0xff
0251 #define PCI_CACHELINE(bhlcr) \
0252         (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
0253
0254 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline)        \
0255         ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) |     \
0256          (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) |   \
0257          (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) |          \
0258          (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) |  \
0259          (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
0260
0261 /*
0262  * PCI header type
0263  */
0264 #define PCI_HDRTYPE_DEVICE  0
0265 #define PCI_HDRTYPE_PPB     1
0266 #define PCI_HDRTYPE_PCB     2
0267
0268 /*
0269  * Mapping registers
0270  */
0271 #define PCI_MAPREG_START        0x10
0272 #define PCI_MAPREG_END          0x28
0273 #define PCI_MAPREG_ROM          0x30
0274 #define PCI_MAPREG_PPB_END      0x18
0275 #define PCI_MAPREG_PCB_END      0x14
0276
0277 #define PCI_MAPREG_TYPE(mr)                     \
0278         ((mr) & PCI_MAPREG_TYPE_MASK)
0279 #define PCI_MAPREG_TYPE_MASK            0x00000001
0280
0281 #define PCI_MAPREG_TYPE_MEM         0x00000000
0282 #define PCI_MAPREG_TYPE_IO          0x00000001
0283 #define PCI_MAPREG_ROM_ENABLE           0x00000001
0284
0285 #define PCI_MAPREG_MEM_TYPE(mr)                     \
0286         ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
0287 #define PCI_MAPREG_MEM_TYPE_MASK        0x00000006
0288
0289 #define PCI_MAPREG_MEM_TYPE_32BIT       0x00000000
0290 #define PCI_MAPREG_MEM_TYPE_32BIT_1M        0x00000002
0291 #define PCI_MAPREG_MEM_TYPE_64BIT       0x00000004
0292
0293 #define PCI_MAPREG_MEM_PREFETCHABLE(mr)             \
0294         (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
0295 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK    0x00000008
0296
0297 #define PCI_MAPREG_MEM_ADDR(mr)                     \
0298         ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
0299 #define PCI_MAPREG_MEM_SIZE(mr)                     \
0300         (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
0301 #define PCI_MAPREG_MEM_ADDR_MASK        0xfffffff0
0302
0303 #define PCI_MAPREG_MEM64_ADDR(mr)                   \
0304         ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
0305 #define PCI_MAPREG_MEM64_SIZE(mr)                   \
0306         (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
0307 #define PCI_MAPREG_MEM64_ADDR_MASK      0xfffffffffffffff0ULL
0308
0309 #define PCI_MAPREG_IO_ADDR(mr)                      \
0310         ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK)
0311 #define PCI_MAPREG_IO_SIZE(mr)                      \
0312         (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
0313 #define PCI_MAPREG_IO_ADDR_MASK         0xfffffffc
0314
0315 #define PCI_MAPREG_SIZE_TO_MASK(size)                   \
0316         (-(size))
0317
0318 #define PCI_MAPREG_NUM(offset)                      \
0319         (((unsigned)(offset)-PCI_MAPREG_START)/4)
0320
0321
0322 /*
0323  * Cardbus CIS pointer (PCI rev. 2.1)
0324  */
0325 #define PCI_CARDBUS_CIS_REG 0x28
0326
0327 /*
0328  * Subsystem identification register; contains a vendor ID and a device ID.
0329  * Types/macros for PCI_ID_REG apply.
0330  * (PCI rev. 2.1)
0331  */
0332 #define PCI_SUBSYS_ID_REG 0x2c
0333
0334 /*
0335  * capabilities link list (PCI rev. 2.2)
0336  */
0337 #define PCI_CAPLISTPTR_REG      0x34    /* header type 0 */
0338 #define PCI_CARDBUS_CAPLISTPTR_REG  0x14    /* header type 2 */
0339 #define PCI_CAPLIST_PTR(cpr)    ((cpr) & 0xff)
0340 #define PCI_CAPLIST_NEXT(cr)    (((cr) >> 8) & 0xff)
0341 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
0342
0343 #define PCI_CAP_RESERVED0   0x00
0344 #define PCI_CAP_PWRMGMT     0x01
0345 #define PCI_CAP_AGP     0x02
0346 #define PCI_CAP_VPD     0x03
0347 #define PCI_CAP_SLOTID      0x04
0348 #define PCI_CAP_MSI     0x05
0349 #define PCI_CAP_CPCI_HOTSWAP    0x06
0350 #define PCI_CAP_PCIX        0x07
0351 #define PCI_CAP_LDT     0x08
0352 #define PCI_CAP_VENDSPEC    0x09
0353 #define PCI_CAP_DEBUGPORT   0x0a
0354 #define PCI_CAP_CPCI_RSRCCTL    0x0b
0355 #define PCI_CAP_HOTPLUG     0x0c
0356 #define PCI_CAP_AGP8        0x0e
0357 #define PCI_CAP_SECURE      0x0f
0358 #define PCI_CAP_PCIEXPRESS      0x10
0359 #define PCI_CAP_MSIX        0x11
0360
0361 /*
0362  * Vital Product Data; access via capability pointer (PCI rev 2.2).
0363  */
0364 #define PCI_VPD_ADDRESS_MASK    0x7fff
0365 #define PCI_VPD_ADDRESS_SHIFT   16
0366 #define PCI_VPD_ADDRESS(ofs)    \
0367     (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
0368 #define PCI_VPD_DATAREG(ofs)    ((ofs) + 4)
0369 #define PCI_VPD_OPFLAG      0x80000000
0370
0371 /*
0372  * Power Management Capability; access via capability pointer.
0373  */
0374
0375 /* Power Management Capability Register */
0376 #define PCI_PMCR        0x02
0377 #define PCI_PMCR_D1SUPP     0x0200
0378 #define PCI_PMCR_D2SUPP     0x0400
0379 /* Power Management Control Status Register */
0380 #define PCI_PMCSR       0x04
0381 #define PCI_PMCSR_STATE_MASK    0x03
0382 #define PCI_PMCSR_STATE_D0      0x00
0383 #define PCI_PMCSR_STATE_D1      0x01
0384 #define PCI_PMCSR_STATE_D2      0x02
0385 #define PCI_PMCSR_STATE_D3      0x03
0386