include/bsp/gtpcireg.h

0001 /*  $NetBSD: gtpcireg.h,v 1.2 2003/03/24 17:03:18 matt Exp $    */
0002
0003 /*
0004  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
0005  * All rights reserved.
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions and the following disclaimer.
0012  * 2. Redistributions in binary form must reproduce the above copyright
0013  *    notice, this list of conditions and the following disclaimer in the
0014  *    documentation and/or other materials provided with the distribution.
0015  * 3. All advertising materials mentioning features or use of this software
0016  *    must display the following acknowledgement:
0017  *      This product includes software developed for the NetBSD Project by
0018  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
0019  * 4. The name of Allegro Networks, Inc. may not be used to endorse
0020  *    or promote products derived from this software without specific prior
0021  *    written permission.
0022  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
0023  *    or promote products derived from this software without specific prior
0024  *    written permission.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
0027  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
0028  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
0029  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0030  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
0031  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0032  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0033  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0034  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0035  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0036  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGE.
0038  */
0039 #define PCI_ARBCTL_EN   (1<<31)
0040
0041 #define  PCI_COMMAND_SB_DIS     0x2000  /* PCI configuration read will stop
0042                                          * acting as sync barrier transactin
0043                                          */
0044
0045 #define PCI_MEM_BASE_ADDR PCI_BASE_ADDRESS_4
0046
0047 #define PCI_IO_BASE_ADDR  PCI_BASE_ADDRESS_5
0048
0049 #define  PCI_STATUS_CLRERR_MASK 0xf9000000 /* <SKF> */
0050
0051 #define PCI_BARE_IntMemEn     0x200
0052
0053 #define PCI_ACCCTLBASEL_PrefetchEn     0x0001000
0054 #define PCI_ACCCTLBASEL_RdPrefetch     0x0010000
0055 #define PCI_ACCCTLBASEL_RdLinePrefetch 0x0020000
0056 #define PCI_ACCCTLBASEL_RdMulPrefetch  0x0040000
0057 #define PCI_ACCCTLBASEL_WBurst_8_QW    0x0100000
0058 #define PCI_ACCCTLBASEL_PCISwap_NoSwap 0x1000000
0059
0060 #define PCI0_P2P_CONFIG                         0x1d14
0061 #define PCI_SNOOP_BASE0_LOW                     0x1f00
0062 #define PCI_SNOOP_BASE0_HIGH                    0x1f04
0063 #define PCI_SNOOP_TOP0                          0x1f08
0064
0065 #define PCI0_SCS0_BAR_SIZE                      0x0c08
0066 #define PCI0_SCS1_BAR_SIZE                      0x0d08
0067 #define PCI0_SCS2_BAR_SIZE                      0x0c0c
0068 #define PCI0_SCS3_BAR_SIZE                      0x0d0c
0069
0070 #define PCI0_BASE_ADDR_REG_ENABLE               0x0c3c
0071 #define PCI0_ARBITER_CNTL                       0x1d00
0072 #define PCI0_ACCESS_CNTL_BASE0_LOW              0x1e00
0073 #define PCI0_ACCESS_CNTL_BASE0_HIGH             0x1e04
0074 #define PCI0_ACCESS_CNTL_BASE0_TOP              0x1e08
0075
0076 #define PCI0_ACCESS_CNTL_BASE1_LOW              0x1e10
0077 #define PCI0_ACCESS_CNTL_BASE1_HIGH             0x1e14
0078 #define PCI0_ACCESS_CNTL_BASE1_TOP              0x1e18
0079
0080 #define PCI1_BASE_ADDR_REG_ENABLE               0x0cbc
0081 #define PCI1_ARBITER_CNTL                       0x1d80
0082 #define PCI1_ACCESS_CNTL_BASE0_LOW              0x1e80
0083 #define PCI1_ACCESS_CNTL_BASE0_HIGH             0x1e84
0084 #define PCI1_ACCESS_CNTL_BASE0_TOP              0x1e88
0085
0086 #define PCI1_ACCESS_CNTL_BASE1_LOW              0x1e90
0087 #define PCI1_ACCESS_CNTL_BASE1_HIGH             0x1e94
0088 #define PCI1_ACCESS_CNTL_BASE1_TOP              0x1e98
0089
0090 #define PCI_SNOOP_BASE1_LOW                     0x1f10
0091 #define PCI_SNOOP_BASE1_HIGH                    0x1f14
0092 #define PCI_SNOOP_TOP1                          0x1f18
0093
0094 #define PCI0_CMD_CNTL                           0xc00
0095
0096 #define PCI1_P2P_CONFIG                         0x1d94
0097 #define PCI1_CMD_CNTL                           0xc80
0098 #define PCI1_CONFIG_ADDR            0xc78
0099 #define PCI1_CONFIG_DATA            0xc7c