include/bsp/GT64260eth.h

0001 /* GT64260eth.h
0002  *
0003  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
0004  * All rights reserved.
0005  *
0006  * RTEMS/Mvme5500 port 2004  by S. Kate Feng, <feng1@bnl.gov>,
0007  * All rights reserved.
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  * 3. All advertising materials mentioning features or use of this software
0018  *    must display the following acknowledgement:
0019  *      This product includes software developed for the NetBSD Project by
0020  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
0021  * 4. The name of Allegro Networks, Inc. may not be used to endorse
0022  *    or promote products derived from this software without specific prior
0023  *    written permission.
0024  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
0025  *    or promote products derived from this software without specific prior
0026  *    written permission.
0027  *
0028  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
0029  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
0030  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
0031  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0032  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
0033  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 /* Keep the ring sizes a power of two for efficiency.
0043    Making the Tx ring too long decreases the effectiveness of channel
0044    bonding and packet priority.
0045    There are no ill effects from too-large receive rings. */
0046 #define TX_RING_SIZE    32
0047 #define GT_NEXTTX(x)    ((x + 1) % TX_RING_SIZE )
0048 #define TX_QUARTER_FULL TX_RING_SIZE/2
0049 #define TX_HALF_FULL    TX_RING_SIZE/2
0050 #define RX_RING_SIZE    16
0051 #define HASH_TABLE_SIZE 16
0052 #define HASH_DRAM_SIZE  HASH_TABLE_SIZE*1024  /* size of DRAM for hash table */
0053 #define INTR_ERR_SIZE   16
0054
0055 enum GTeth_txprio {
0056     GE_TXPRIO_HI=1,
0057     GE_TXPRIO_LO=0,
0058     GE_TXPRIO_NONE=2
0059 };
0060 enum GTeth_rxprio {
0061     GE_RXPRIO_HI=3,
0062     GE_RXPRIO_MEDHI=2,
0063     GE_RXPRIO_MEDLO=1,
0064     GE_RXPRIO_LO=0
0065 };
0066
0067 struct GTeth_softc {
0068   struct GTeth_desc txq_desc[TX_RING_SIZE]; /* transmit descriptor memory */
0069   struct GTeth_desc rxq_desc[RX_RING_SIZE]; /* receive descriptor memory */
0070   struct mbuf* txq_mbuf[TX_RING_SIZE];  /* transmit buffer memory */
0071   struct mbuf* rxq_mbuf[RX_RING_SIZE];  /* receive buffer memory */
0072   struct GTeth_softc *next_module;
0073   volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* capture the right intr_status */
0074   unsigned int intr_err_ptr1;   /* ptr used in GTeth_error() */
0075   unsigned int intr_err_ptr2;   /* ptr used in ISR */
0076   struct ifqueue txq_pendq; /* these are ready to go to the GT */
0077   unsigned int txq_pending;
0078   unsigned int txq_lo;      /* next to be given to GT DMA */
0079   unsigned int txq_fi;      /* next to be free */
0080   unsigned int txq_to_cpu;      /* next to be returned to CPU */
0081   unsigned int txq_ei_gapcount; /* counter until next EI */
0082   unsigned int txq_nactive; /* number of active descriptors */
0083   unsigned int txq_nintr;       /* number of txq desc. send TX_EVENT */
0084   unsigned int txq_outptr;  /* where to put next transmit packet */
0085   unsigned int txq_inptr;       /* start of 1st queued tx packet */
0086   unsigned int txq_free;    /* free Tx queue slots. */
0087   unsigned txq_intrbits;    /* bits to write to EIMR */
0088   unsigned txq_esdcmrbits;  /* bits to write to ESDCMR */
0089   unsigned txq_epsrbits;    /* bits to test with EPSR */
0090
0091   caddr_t txq_ectdp;        /* offset to cur. tx desc ptr reg */
0092   unsigned long txq_desc_busaddr;   /* bus addr of tx descriptors */
0093   caddr_t txq_buf_busaddr;  /* bus addr of tx buffers */
0094
0095   struct mbuf *rxq_curpkt;  /* mbuf for current packet */
0096   struct GTeth_desc *rxq_head_desc;  /* rxq head descriptor */
0097   unsigned int rxq_fi;      /* next to be returned to CPU */
0098   unsigned int rxq_active;  /* # of descriptors given to GT */
0099   unsigned rxq_intrbits;        /* bits to write to EIMR */
0100   unsigned long rxq_desc_busaddr;   /* bus addr of rx descriptors */
0101
0102   struct arpcom arpcom;         /* rtems if structure, contains ifnet */
0103   int sc_macno;         /* which mac? 0, 1, or 2 */
0104
0105   unsigned int sc_tickflags;
0106   #define   GE_TICK_TX_IFSTART  0x0001
0107   #define   GE_TICK_RX_RESTART  0x0002
0108   unsigned int sc_flags;
0109   #define   GE_ALLMULTI 0x0001
0110   #define   GE_PHYSTSCHG    0x0002
0111   #define   GE_RXACTIVE 0x0004
0112   unsigned sc_pcr;      /* current EPCR value */
0113   unsigned sc_pcxr;     /* current EPCXR value */
0114   unsigned sc_intrmask;     /* current EIMR value */
0115   unsigned sc_idlemask;     /* suspended EIMR bits */
0116   unsigned sc_max_frame_length; /* maximum frame length */
0117   unsigned rx_buf_sz;
0118
0119   /* Hash table related members */
0120   unsigned long long *sc_hashtable;
0121   unsigned int sc_hashmask; /* 0x1ff or 0x1fff */
0122
0123   rtems_id  daemonTid;
0124   rtems_id  daemonSync; /* synchronization with the daemon */
0125   /* statistics */
0126   struct {
0127     volatile unsigned long       rxInterrupts;
0128
0129     volatile unsigned long       txInterrupts;
0130     unsigned long   txMultiBuffPacket;
0131     unsigned long       txMultiMaxLen;
0132     unsigned long       txSinglMaxLen;
0133     unsigned long       txMultiMaxLoop;
0134     unsigned long       txBuffMaxLen;
0135     unsigned long   length_errors;
0136     unsigned long   frame_errors;
0137     unsigned long   crc_errors;
0138     unsigned long       or_errors; /* overrun error */
0139   } stats;
0140 };