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0001 mvme5500
0002 ========
0003 Please reference README.booting for the boot/load process.
0004
0005 For the priority setting of the Interrupt Requests (IRQs), please
0006 reference README.irq
0007
0008 The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
0009
0010 I believe in valuable real-time programming, where technical neatness,
0011 performance and truth are. I hope I still believe. Any suggestion,
0012 bug reports, or even bug fixes (great!) would be highly appreciated
0013 so that I still believe what I believe.
0014
0015
0016 ACKNOWLEDGEMENTS
0017 ----------------
0018 Acknowledgements:
0019
0020 Valuable information was obtained from the following:
0021 1) Marvell NDA document for the discovery system controller.
0022 Other related documents are listed at :
0023 http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf
0024 2) netBSD: For the two NICS and some headers :
0025 Allegro Networks, Inc., Wasabi Systems, Inc.
0026 3) RTEMS: This BSP also builds on top of the work of others who have
0027 contributed to similar RTEMS powerpc shared and motorola_powerpc BSPs, most
0028 notably Eric Valette, Till Straumann (SVGM1 BSP, too), Eric Norum and others.
0029
0030 LICENSE
0031 -------
0032 See ./LICENSE file.
0033
0034 ```
0035 BSP NAME: mvme5500
0036 BOARD: MVME5500 by Motorola
0037 BUS: PCI
0038 CPU FAMILY: ppc
0039 CPU: MPC7455 @ 1GHZ
0040 COPROCESSORS: N/A
0041 MODE: 32/64 bit mode (support 32 bit for now)
0042 DEBUG MONITOR: MOTLoad
0043 SYSTEM CONTROLLER: GT64260B
0044 ```
0045
0046 PERIPHERALS
0047 -----------
0048 ```
0049 TIMERS: Eight, 32 bit programmable
0050 SERIAL PORTS: 2 NS 16550 on GT64260B
0051 REAL-TIME CLOCK: MK48T37V
0052 32K NVSRAM: MK48T37V
0053 WATCHDOG TIMER: use the one in GT-64260B
0054 DMA: 8 channel DMA controller (GT-64260B)
0055 VIDEO: none
0056 NETWORKING: Port 1: Intel 82544EI Gigabit Ethernet Controller
0057 10/100/1000Mb/s routed to front panel RJ-45
0058 Port 2: 10/100 Mb ethernet unit integrated on the
0059 Marvell's GT64260 system controller
0060 ```
0061
0062 DRIVER INFORMATION
0063 ------------------
0064 ```
0065 CLOCK DRIVER: PPC internal
0066 IOSUPP DRIVER: N/A
0067 SHMSUPP: N/A
0068 TIMER DRIVER: PPC internal
0069 TTY DRIVER: PPC internal
0070 ```
0071
0072 STDIO
0073 -----
0074 ```
0075 PORT: Console port 0
0076 ELECTRICAL: na
0077 BAUD: na
0078 BITS PER CHARACTER: na
0079 PARITY: na
0080 STOP BITS: na
0081 ```
0082
0083
0084 Jumpers
0085 =======
0086
0087 1) The BSP is tested with the 60x bus mode instead of the MPX bus mode.
0088 ( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode)
0089
0090 2) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is
0091 front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel
0092 Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and
0093 J101 headers.
0094
0095 3) Enable SROM initialization at startup. (No jumper or a jumper across
0096 pins 1-2 on J17)
0097
0098 In fact, (if I did not miss anything) the mvme5500 board should function
0099 properly if one keeps all the jumpers at factory configuration.
0100 One can leave out the jumper on J30 to disable EEPROM programming.
0101
0102
0103 BSP BAT usage
0104 -------------
0105 ```
0106 DBAT0 and IBAT0
0107 0x00000000
0108 0x0fffffff 1st 256M, for MEMORY access (caching enabled)
0109
0110 DBAT1 and IBAT1
0111 0x00000000
0112 0x0fffffff 2nd 256M, for MEMORY access (caching enabled)
0113 ```
0114
0115 UPDATE: (2004/5).
0116 The BSP now uses page tables for mapping the entire 512MB
0117 of RAM. DBAT0 and DBAT1 is hence free for use by the
0118 application. A simple 1:1 (virt<->phys) mapping is employed.
0119 The BSP write-protects the text and read-only data
0120 areas of the application. Special acknowledgement to Till
0121 Straumann <strauman@slac.stanford.edu> for providing inputs in
0122 porting the memory protection software he wrote (BSP_pgtbl_xxx())
0123 to MVME5500.
0124
0125
0126 The default VME configuration uses DBAT0 to map
0127 more PCI memory space for use by the universe VME
0128 bridge:
0129
0130 ```
0131 DBAT0
0132 0x90000000 PCI memory space <-> VME
0133 0x9fffffff
0134
0135 Port VME-Addr Size PCI-Adrs Mode:
0136 0: 0x20000000 0x0F000000 0x90000000 A32, Dat, Sup
0137 1: 0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup
0138 2: 0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup
0139 ```
0140
0141
0142 Booting
0143 =======
0144
0145 Written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 2007
0146
0147 The bootloader is adapted from Till Straumann's Generic Mini-loader,
0148 which he wrote originally for the SVGM powerpc board.
0149 The BSP is built and tested on the 4.7 CVS RTEMS release.
0150
0151 Booting requirement
0152 -------------------
0153
0154 1) One needs to setup BOOTP/DHCP and TFTP servers and /etc/bootptab(BOOTP)
0155 or /etc/dhcpd.conf (DHCP) properly to boot the system.
0156 (Note : EPICS needs a NTP server).
0157
0158 2) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin)
0159 and perhaps others (e.g. misc/st.sys) to the /tftpboot/epics/hostname/bin/
0160 directory or the TFTPBOOT one you specified in the 'tftpGet'
0161 command of the boot script (as shown in the following example).
0162
0163 3) Example of the boot script setup carried out on the MOTLoad
0164 command line :
0165
0166 ```shell
0167 MVME5500> gevEdit mot-script-boot
0168 (Blank line terminates input.)
0169 waitProbe
0170 tftpGet -a4000000 -cxx.xx.xx.xx -sxx.xx.xx.xx -m255.255.254.0 -d/dev/enet0 -fepics/hostname/bin/rtems5500-cexp.bin
0171 netShut
0172 go -a4000000
0173
0174 Update Global Environment Area of NVRAM (Y/N) ? Y
0175 MVME5500>
0176
0177 Note : (cxx.xx.xx.xx is the client IP address and
0178 sxx.xx.xx.xx is the server IP address)
0179
0180 WARNING : It is extremely important that the MOTLoad "waitProbe", "netShut"
0181 sequence be executed before booting RTEMS. Otherwise, network
0182 interface interrupt handlers installed by MOTLoad may cause memory
0183 corruption
0184 ```
0185
0186 4) Other reference web sites for mvme5500 BSP:
0187 http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt
0188 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/
0189 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt
0190
0191 5) When generating code (especially C++) for this system, one should
0192 use at least gcc-3.2 (preferrably a copy downloaded from the RTEMS
0193 site [snapshot area] )
0194
0195 6) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
0196 bsp_reset() command at Cexp> prompt.
0197
0198 7) Please reference http://www.slac.stanford.edu/~strauman/rtems
0199 for the source code and installation guidance of cexp, GeSys and
0200 other useful utilities such as telnet, nfs, and so on.
0201
0202 8) To get started with RTEMS/EPICS and to build development
0203 tools and BSP, I would recommend one to reference
0204 http://www.aps.anl.gov/epics/base/RTEMS/tutorial/
0205 in additional to the RTEMS document.
0206
0207
0208 IRQ
0209 ===
0210 Shuchen Kate Feng <feng1@bnl.gov>, Sept. 2, 2007
0211
0212 As per implementation in shared PPC code,
0213 the BSPirqPrioTable[96] listed in irq_init.c is where the
0214 software developers can change the levels of priority
0215 for all the interrupts based on the need of their
0216 applications. The IRQs can be eanbled dynamically via the
0217 BSP_enable_pic_irq(), or disbaled dynamically via the
0218 BSP_disable_pic_irq().
0219
0220
0221 Support for run-time priority setup could be
0222 added easily, but there is no action taken yet due to concerns
0223 over computer security at VME CPU level.
0224
0225
0226 The software developers are forbidden to setup picIsrTable[],
0227 as it is a powerful engine for the BSP to find the pending
0228 highest priority IRQ at run time. It ensures the fastest/faster
0229 interrupt service to the highest/higher priority IRQ, if pending.
0230
0231
0232 VME
0233 ===
0234 Written by S. Kate Feng <feng1@bnl.gov> , 7/22/04
0235
0236 Some VME modules(e.g. Oms58 motor controller) might require a PCI sync
0237 command following the out_xx() function (e.g. out_be16()) if mvme5500 is
0238 used as the SBC. The mechanism is a hardware hook to help software
0239 synchronize between the CPU and PCI activities. The PCI sync is
0240 implemented in pci/pci_interface.c. For more example of the usage,one
0241 can reference the drvOMS58.cc file that is posted in synAppRTEMS of
0242 http://www.nsls.bnl.gov/organization/UserScience/Detectors/Software/Default.htm.
0243
0244 In spite of the PCI sync overhead for the Oms58 motor controller, I do
0245 not see the runtime performance of RTEMS-mvme5500 being compromised as
0246 compared with that of RTEMS-mvme2307. For example, it takes the same
0247 time to run motor_init() of synAppRTEMS for 48 motor initializations
0248 running either RTEMS-mvme2307 or RTEMS-mvme5500.
