include/bsp/irq.h

0001 /**
0002  *  @file
0003  *
0004  *  @ingroup powerpc_irq
0005  *
0006  *  @brief This include file describe the data structure and the functions
0007  *  implemented by RTEMS to write interrupt handlers.
0008  */
0009
0010 /* irq.h
0011  *
0012  *  This include file describe the data structure and the functions implemented
0013  *  by RTEMS to write interrupt handlers.
0014  *
0015  *  Copyright (C) 1999 valette@crf.canon.fr
0016  *
0017  *  This code is heavilly inspired by the public specification of STREAM V2
0018  *  that can be found at :
0019  *
0020  *      <http://www.chorus.com/Documentation/index.html> by following
0021  *  the STREAM API Specification Document link.
0022  *
0023  *  The license and distribution terms for this file may be
0024  *  found in the file LICENSE in this distribution or at
0025  *  http://www.rtems.org/license/LICENSE.
0026  *
0027  *  Adapted for the mvme3100 BSP by T. Straumann, 2007.
0028  */
0029
0030 #ifndef BSP_POWERPC_IRQ_H
0031 #define BSP_POWERPC_IRQ_H
0032
0033 #define BSP_SHARED_HANDLER_SUPPORT      1
0034 #include <rtems/irq.h>
0035
0036 #ifndef ASM
0037
0038 #include <bsp/irq-default.h>
0039
0040 #ifdef __cplusplus
0041 extern "C" {
0042 #endif
0043
0044 /**
0045  *  @defgroup powerpc_irq Definitions
0046  *
0047  *  @ingroup RTEMSBSPsPowerPCMVME3100
0048  *
0049  *  @brief rtems_irq_number Definitions
0050  */
0051
0052 /* Must pad number of external sources to 16 because
0053  * of the layout of vector/priority registers in the
0054  * 8540's openpic where there is a gap between
0055  * registers corresponding to external and core sources.
0056  */
0057 #define BSP_EXT_IRQ_NUMBER          (16)
0058 #define BSP_CORE_IRQ_NUMBER         (32)
0059
0060 /* openpic glue code from shared/irq assigns priorities and configures
0061  * initial ISRs for BSP_PCI_IRQ_NUMBER entries (plus ISA stuff on legacy
0062  * boards). Hence PCI_IRQ_NUMBER must also cover the internal sources
0063  * even though they have nothing to do with PCI.
0064  */
0065 #define BSP_PCI_IRQ_NUMBER          (BSP_EXT_IRQ_NUMBER + BSP_CORE_IRQ_NUMBER)
0066 #define BSP_PCI_IRQ_LOWEST_OFFSET   (0)
0067 #define BSP_PCI_IRQ_MAX_OFFSET      (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
0068
0069 #define BSP_CORE_IRQ_LOWEST_OFFSET  (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_EXT_IRQ_NUMBER)
0070 #define BSP_CORE_IRQ_MAX_OFFSET     (BSP_CORE_IRQ_LOWEST_OFFSET + BSP_CORE_IRQ_NUMBER - 1)
0071
0072 /*
0073  * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
0074  * handler might be connected
0075  */
0076 #define BSP_PROCESSOR_IRQ_NUMBER    (1)
0077 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CORE_IRQ_MAX_OFFSET + 1)
0078 #define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
0079 /* Misc vectors for OPENPIC irqs (IPI, timers)
0080  */
0081 #define BSP_MISC_IRQ_NUMBER     (8)
0082 #define BSP_MISC_IRQ_LOWEST_OFFSET  (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
0083 #define BSP_MISC_IRQ_MAX_OFFSET     (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
0084 /*
0085  * Summary
0086  */
0087 #define BSP_IRQ_NUMBER          (BSP_MISC_IRQ_MAX_OFFSET + 1)
0088 #define BSP_LOWEST_OFFSET       (BSP_PCI_IRQ_LOWEST_OFFSET)
0089 #define BSP_MAX_OFFSET          (BSP_MISC_IRQ_MAX_OFFSET)
0090
0091 /*
0092  * Some PCI IRQ symbolic name definition
0093  */
0094 #define BSP_PCI_IRQ0            (BSP_PCI_IRQ_LOWEST_OFFSET)
0095
0096 #define BSP_VME0_IRQ            (BSP_PCI_IRQ_LOWEST_OFFSET  +  0)
0097 #define BSP_VME1_IRQ            (BSP_PCI_IRQ_LOWEST_OFFSET  +  1)
0098 #define BSP_VME2_IRQ            (BSP_PCI_IRQ_LOWEST_OFFSET  +  2)
0099 #define BSP_VME3_IRQ            (BSP_PCI_IRQ_LOWEST_OFFSET  +  3)
0100
0101 #define BSP_ABORT_IRQ           (BSP_PCI_IRQ_LOWEST_OFFSET  +  8)
0102 #define BSP_TEMP_IRQ            (BSP_PCI_IRQ_LOWEST_OFFSET  +  9)
0103 #define BSP_PHY_IRQ             (BSP_PCI_IRQ_LOWEST_OFFSET  + 10)
0104 #define BSP_RTC_IRQ             (BSP_PCI_IRQ_LOWEST_OFFSET  + 11)
0105
0106 /* Weird - they provide 3 different IRQ lines per ethernet controller
0107  * but only one shared line for 2 UARTs ???
0108  */
0109 #define BSP_UART_COM1_IRQ       (BSP_CORE_IRQ_LOWEST_OFFSET + 26)
0110 #define BSP_UART_COM2_IRQ       (BSP_CORE_IRQ_LOWEST_OFFSET + 26)
0111 #define BSP_I2C_IRQ             (BSP_CORE_IRQ_LOWEST_OFFSET + 27)
0112
0113 /*
0114  * Some internal (CORE) name definitions
0115  */
0116 /* Ethernet (FEC) */
0117 #define BSP_CORE_IRQ_FEC        (BSP_CORE_IRQ_LOWEST_OFFSET + 25)
0118 /* i2c controller */
0119 #define BSP_CORE_IRQ_I2C        (BSP_CORE_IRQ_LOWEST_OFFSET + 27)
0120
0121 /*
0122  * Some Processor execption handled as RTEMS IRQ symbolic name definition
0123  */
0124 #define BSP_DECREMENTER         (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
0125
0126 /*-------------------------------------------------------------------------+
0127 | Function Prototypes.
0128 +--------------------------------------------------------------------------*/
0129
0130 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
0131
0132 #include <bsp/irq_supp.h>
0133
0134 #ifdef __cplusplus
0135 };
0136 #endif
0137
0138 #endif
0139 #endif