mvme3100/include/bsp.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsPowerPCMVME3100
0005  *
0006  * @brief Global BSP definitions.
0007  */
0008
0009 /*
0010  *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
0011  *
0012  *  The license and distribution terms for this file may be
0013  *  found in the file LICENSE in this distribution or at
0014  *  http://www.rtems.org/license/LICENSE.
0015  *
0016  *  Adapted for the mvme3100 BSP by T. Straumann, 2007.
0017  */
0018 #ifndef LIBBSP_POWERPC_MVME3100_BSP_H
0019 #define LIBBSP_POWERPC_MVME3100_BSP_H
0020
0021 #ifndef ASM
0022
0023 #include <bspopts.h>
0024 #include <bsp/default-initial-extension.h>
0025
0026 #include <rtems.h>
0027 #include <libcpu/io.h>
0028 #include <bsp/vectors.h>
0029
0030 /**
0031  * @defgroup RTEMSBSPsPowerPCMVME3100 MVME3100
0032  *
0033  * @ingroup RTEMSBSPsPowerPC
0034  *
0035  * @brief MVME3100 Board Support Package.
0036  *
0037  * @{
0038  */
0039
0040 #define BSP_INTERRUPT_STACK_SIZE          (16 * 1024)
0041
0042 /*
0043  * diagram illustrating the role of the configuration
0044  * constants
0045  *  PCI_MEM_WIN0:        CPU starting addr where PCI memory space is visible
0046  *  PCI_MEM_BASE:        CPU address of PCI mem addr. zero. (regardless of this
0047  *                       address being 'visible' or not!).
0048  * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME
0049  * _VME_A32_WIN0_ON_VME: VME address of that same window
0050  *
0051  * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between
0052  * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI
0053  * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
0054  * the base address read from PCI config.space in order to translate that
0055  * into a CPU address.
0056  *
0057  * NOTE: VME addresses should NEVER be translated using these constants!
0058  *       they are strictly for BSP internal use. Drivers etc. should use
0059  *       the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
0060  *
0061  *           CPU ADDR                  PCI_ADDR                                VME ADDR
0062  *
0063  *           00000000                  XXXXXXXX                                XXXXXXXX
0064  *    ^  ^   ........
0065  *    |  |
0066  *    |  |  e.g., RAM                  XXXXXXXX
0067  *    |  |                                                                     00000000
0068  *    |  |  .........                                                          ^
0069  *    |  |            (possible offset                                         |
0070  *    |  |             between pci and XXXXXXXX                                | ......
0071  *    |  |             cpu addresses)                                          |
0072  *    |  v                                                                     |
0073  *    |  PCI_MEM_BASE  ------------->  00000000 ---------------                |
0074  *    |     ........                   ........               ^                |
0075  *    |                                invisible              |                |
0076  *    |     ........                   from CPU               |                |
0077  *    v                                                       |                |
0078  *       PCI_MEM_WIN0 =============  first visible PCI addr   |                |
0079  *                                                            |                |
0080  *        pci devices   pci window                            |                |
0081  *       visible here                                         v                v
0082  *                      mapped by   ========== _VME_A32_WIN0_ON_PCI =======  _VME_A32_WIN0_ON_VME
0083  *                                                 vme window
0084  *        VME devices   hostbridge                 mapped by
0085  *       visible here                              universe
0086  *                    =====================================================
0087  *
0088  */
0089
0090 /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
0091 #define _IO_BASE            0xe0000000 /* Motload's PCI IO base */
0092 #define _ISA_MEM_BASE       CHRP_ISA_MEM_BASE
0093 /* address of our ram on the PCI bus   */
0094 #define PCI_DRAM_OFFSET     CHRP_PCI_DRAM_OFFSET
0095 /* offset of pci memory as seen from the CPU */
0096 #define PCI_MEM_BASE        0
0097 /* where (in CPU addr. space) does the PCI window start */
0098 #define PCI_MEM_WIN0        0x80000000
0099
0100 /*
0101  *  Base address definitions for several devices
0102  */
0103
0104 #define BSP_OPEN_PIC_BASE_OFFSET 0x40000
0105 #define BSP_OPEN_PIC_BIG_ENDIAN
0106
0107 #define BSP_8540_CCSR_BASE   (0xe1000000)
0108
0109 #define BSP_UART_IOBASE_COM1 (BSP_8540_CCSR_BASE+0x4500)
0110 #define BSP_UART_IOBASE_COM2 (BSP_8540_CCSR_BASE+0x4600)
0111 #define PCI_CONFIG_ADDR      (BSP_8540_CCSR_BASE+0x8000)
0112 #define PCI_CONFIG_DATA      (BSP_8540_CCSR_BASE+0x8004)
0113 #define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((uint32_t*)(addr), (val))
0114
0115 #define BSP_CONSOLE_PORT    BSP_UART_COM1
0116 #define BSP_UART_BAUD_BASE  (-9600) /* use existing divisor to determine clock rate */
0117 #define BSP_UART_USE_SHARED_IRQS
0118
0119 #define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007)
0120
0121 /* I2C Devices */
0122 /* Note that the i2c addresses stated in the manual are
0123  * left-shifted by one bit.
0124  */
0125 #define BSP_VPD_I2C_ADDR            (0xA8>>1)       /* the VPD EEPROM  */
0126 #define BSP_USR0_I2C_ADDR           (0xA4>>1)       /* the 1st user EEPROM */
0127 #define BSP_USR1_I2C_ADDR           (0xA6>>1)       /* the 2nd user EEPROM */
0128 #define BSP_THM_I2C_ADDR            (0x90>>1)       /* the DS1621 temperature sensor & thermostat */
0129 #define BSP_RTC_I2C_ADDR            (0xD0>>1)       /* the DS1375 wall-clock */
0130
0131 #define BSP_I2C_BUS_DESCRIPTOR      mpc8540_i2c_bus_descriptor
0132
0133 #define BSP_I2C_BUS0_NAME             "/dev/i2c0"
0134
0135 #define BSP_I2C_VPD_EEPROM_NAME       "vpd-eeprom"
0136 #define BSP_I2C_USR_EEPROM_NAME       "usr-eeprom"
0137 #define BSP_I2C_USR1_EEPROM_NAME      "usr1-eeprom"
0138 #define BSP_I2C_DS1621_NAME           "ds1621"
0139 #define BSP_I2C_THM_NAME              BSP_I2C_DS1621_NAME
0140 #define BSP_I2C_DS1621_RAW_NAME       "ds1621-raw"
0141 #define BSP_I2C_DS1375_RAW_NAME       "ds1375-raw"
0142 #define BSP_I2C_RTC_RAW_NAME          BSP_I2C_DS1375_RAW_NAME
0143
0144 #define BSP_I2C_VPD_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME "." BSP_I2C_VPD_EEPROM_NAME)
0145 #define BSP_I2C_USR_EEPROM_DEV_NAME      (BSP_I2C_BUS0_NAME "." BSP_I2C_USR_EEPROM_NAME)
0146 #define BSP_I2C_USR1_EEPROM_DEV_NAME     (BSP_I2C_BUS0_NAME "." BSP_I2C_USR1_EEPROM_NAME)
0147 #define BSP_I2C_DS1621_DEV_NAME          (BSP_I2C_BUS0_NAME "." BSP_I2C_DS1621_NAME)
0148 #define BSP_I2C_THM_DEV_NAME              BSP_I2C_DS1621_DEV_NAME
0149 #define BSP_I2C_DS1621_RAW_DEV_NAME      (BSP_I2C_BUS0_NAME "." BSP_I2C_DS1621_RAW_NAME)
0150 #define BSP_I2C_DS1375_RAW_DEV_NAME      (BSP_I2C_BUS0_NAME "." BSP_I2C_DS1375_RAW_NAME)
0151
0152 /* Definitions useful for bootloader (netboot); where to find
0153  * boot/'environment' parameters.
0154  */
0155 #define BSP_EEPROM_BOOTPARMS_NAME        BSP_I2C_USR1_EEPROM_DEV_NAME
0156 #define BSP_EEPROM_BOOTPARMS_SIZE        1024
0157 #define BSP_EEPROM_BOOTPARMS_OFFSET      0
0158 #define BSP_BOOTPARMS_WRITE_ENABLE()     do { BSP_eeprom_write_enable(); } while (0)
0159 #define BSP_BOOTPARMS_WRITE_DISABLE()    do { BSP_eeprom_write_protect();} while (0)
0160
0161
0162 #ifdef __cplusplus
0163 extern "C" {
0164 #endif
0165 /* Initialize the I2C driver and register all devices
0166  * RETURNS 0 on success, -1 on error.
0167  *
0168  * Access to the VPD and user EEPROMS as well
0169  * as the ds1621 temperature sensor is possible
0170  * by means of file nodes
0171  *
0172  *   /dev/i2c0.vpd-eeprom   (read-only)
0173  *   /dev/i2c0.usr-eeprom   (read-write)
0174  *   /dev/i2c0.usr1-eeprom  (read-write)
0175  *   /dev/i2c0.ds1621       (read-only; one byte: board-temp in degC)
0176  *   /dev/i2c0.ds1621-raw   (read-write; transfer bytes to/from the ds1621)
0177  *   /dev/i2c0.ds1375-raw   (read-write; transfer bytes to/from the ds1375)
0178  *
0179  */
0180 int BSP_i2c_initialize(void);
0181
0182 /* System Control Register */
0183 #define BSP_MVME3100_SYS_CR             ((volatile uint8_t *)0xe2000001)
0184 #define BSP_MVME3100_SYS_CR_RESET_MSK       (7<<5)
0185 #define BSP_MVME3100_SYS_CR_RESET           (5<<5)
0186 #define BSP_MVME3100_SYS_CR_EEPROM_WP       (1<<1)
0187 #define BSP_MVME3100_SYS_CR_TSTAT_MSK       (1<<0)
0188
0189 /* LED support */
0190 #define BSP_MVME3100_SYS_IND_REG        ((volatile uint8_t *)0xe2000002)
0191 #define BSP_LED_BRD_FAIL                    (1<<0)
0192 #define BSP_LED_USR1                        (1<<1)
0193 #define BSP_LED_USR2                        (1<<2)
0194 #define BSP_LED_USR3                        (1<<3)
0195
0196 /* Flash CSR   */
0197 #define BSP_MVME3100_FLASH_CSR          ((volatile uint8_t *)0xe2000003)
0198 #define BSP_MVME3100_FLASH_CSR_FLASH_RDY    (1<<0)
0199 #define BSP_MVME3100_FLASH_CSR_FBT_BLK_SEL  (1<<1)
0200 #define BSP_MVME3100_FLASH_CSR_F_WP_HW      (1<<2)
0201 #define BSP_MVME3100_FLASH_CSR_F_WP_SW      (1<<3)
0202 #define BSP_MVME3100_FLASH_CSR_MAP_SEL      (1<<4)
0203
0204 /* Phy interrupt detect */
0205 #define BSP_MVME3100_IRQ_DETECT_REG     ((volatile uint8_t *)0xe2000007)
0206
0207 /* Atomically set bits in a sys-register; The bits set in 'mask'
0208  * are set in the register others; are left unmodified.
0209  *
0210  * RETURNS: old state.
0211  *
0212  * NOTE   : since BSP_setSysReg( reg, 0 ) does not make
0213  *          any changes this call may be used
0214  *          to read the current status w/o modifying it.
0215  */
0216 uint8_t BSP_setSysReg(volatile uint8_t *r, uint8_t mask);
0217
0218 /* Atomically clear bits in a sys-register; The bits set in 'mask'
0219  * are cleared in the register; others are left unmodified.
0220  *
0221  * RETURNS: old state.
0222  *
0223  * NOTE   : since BSP_clrSysReg( reg, 0 ) does not make
0224  *          any changes this call may be used
0225  *          to read the current status w/o modifying it.
0226  */
0227
0228 uint8_t BSP_clrSysReg(volatile uint8_t *r, uint8_t mask);
0229
0230 /* Convenience wrappers around BSP_setSysReg()/BSP_clrSysReg() */
0231
0232 /* Set write-protection for all EEPROM devices
0233  * RETURNS: old status
0234  */
0235 uint8_t BSP_eeprom_write_protect(void);
0236
0237 /* Disengage write-protection for all EEPROM devices
0238  * RETURNS: old status
0239  */
0240 uint8_t BSP_eeprom_write_enable(void);
0241
0242 /* Set LEDs that have their bit set in the mask
0243  *
0244  * RETURNS: old status.
0245  *
0246  * NOTE   : since BSP_setLEDs( 0 ) does not make
0247  *          any changes this call may be used
0248  *          to read the current status w/o modifying it.
0249  */
0250 uint8_t BSP_setLEDs(uint8_t mask);
0251
0252 /* Clear LEDs that have their bit set in the mask
0253  *
0254  * RETURNS: old status
0255  *
0256  * NOTE:  : see above (BSP_setLEDs)
0257  */
0258 uint8_t BSP_clrLEDs(uint8_t mask);
0259
0260 #if 0
0261 #define outport_byte(port,value) outb(value,port)
0262 #define outport_word(port,value) outw(value,port)
0263 #define outport_long(port,value) outl(value,port)
0264
0265 #define inport_byte(port,value) (value = inb(port))
0266 #define inport_word(port,value) (value = inw(port))
0267 #define inport_long(port,value) (value = inl(port))
0268 #endif
0269
0270 /*
0271  * Total memory using RESIDUAL DATA
0272  */
0273 extern unsigned int BSP_mem_size;
0274 /*
0275  * PCI Bus Frequency
0276  */
0277 extern unsigned int BSP_bus_frequency;
0278 /*
0279  * processor clock frequency
0280  */
0281 extern unsigned int BSP_processor_frequency;
0282 /*
0283  * Time base divisior (how many tick for 1 second).
0284  */
0285 extern unsigned int BSP_time_base_divisor;
0286 /*
0287  * The commandline as passed from the bootloader.
0288  */
0289 extern char *BSP_commandline_string;
0290
0291 #define BSP_Convert_decrementer( _value ) \
0292   ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
0293
0294 extern int BSP_disconnect_clock_handler (void);
0295 extern int BSP_connect_clock_handler (void);
0296
0297 /* clear hostbridge errors
0298  *
0299  * NOTE: The routine returns always (-1) if 'enableMCP==1'
0300  *       [semantics needed by libbspExt] if the MCP input is not wired.
0301  *       It returns and clears the error bits of the PCI status register.
0302  *       MCP support is disabled because:
0303  *         a) the 2100 has no raven chip
0304  *         b) the raven (2300) would raise machine check interrupts
0305  *            on PCI config space access to empty slots.
0306  */
0307 extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
0308 extern void BSP_motload_pci_fixup(void);
0309
0310 struct rtems_bsdnet_ifconfig;
0311
0312 int
0313 rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching);
0314
0315 #define RTEMS_BSP_NETWORK_DRIVER_NAME   "tse1"
0316 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsec_attach
0317
0318 /*
0319  * Prototypes for methods called only from .S for dependency tracking
0320  */
0321 char *save_boot_params(
0322   void *r3,
0323   void *r4,
0324   void *r5,
0325   char *cmdline_start,
0326   char *cmdline_end
0327 );
0328 void zero_bss(void);
0329
0330 /*
0331  * Prototypes for methods in the BSP that cross file boundaries
0332  */
0333 extern void BSP_vme_config(void);
0334 extern void BSP_pciConfigDump_early( void );
0335
0336 #ifdef __cplusplus
0337 }
0338 #endif
0339
0340 #endif /* !ASM */
0341
0342 /** @} */
0343
0344 #endif