mpc8260ads/start/cpuinit.c

0001 /*
0002  *  cpuinit.c - this file contains functions for initializing the CPU
0003  *
0004  *  Written by Jay Monkman (jmonkman@frasca.com)
0005  */
0006
0007 #include <bsp.h>
0008
0009 /* Macros for handling all the MMU SPRs */
0010 #define PUT_IC_CST(r)   __asm__ volatile ("mtspr 0x230,%0\n" ::"r"(r))
0011 #define GET_IC_CST(r)   __asm__ volatile ("mfspr %0,0x230\n" :"=r"(r))
0012 #define PUT_DC_CST(r)   __asm__ volatile ("mtspr 0x238,%0\n" ::"r"(r))
0013 #define GET_DC_CST(r)   __asm__ volatile ("mfspr %0,0x238\n" :"=r"(r))
0014
0015 void cpu_init(void)
0016 {
0017   /* BRGCLK is VCO_OUT/4 */
0018 /*
0019   m8260.sccr = 0;
0020 */
0021
0022 #if 0
0023   register unsigned long t1, t2;
0024
0025   /* Let's clear MSR[IR] and MSR[DR] */
0026   t2 = PPC_MSR_IR | PPC_MSR_DR;
0027   __asm__ volatile (
0028     "mfmsr    %0\n"
0029     "andc     %0, %0, %1\n"
0030     "mtmsr    %0\n" :"=r"(t1), "=r"(t2):
0031     "1"(t2));
0032
0033   t1 = M8xx_CACHE_CMD_UNLOCK;
0034   /*  PUT_DC_CST(t1); */
0035   PUT_IC_CST(t1);
0036
0037   t1 = M8xx_CACHE_CMD_INVALIDATE;
0038   /*  PUT_DC_CST(t1); */
0039   PUT_IC_CST(t1);
0040
0041   t1 = M8xx_CACHE_CMD_ENABLE;
0042   PUT_IC_CST(t1);
0043
0044   t1 = M8xx_CACHE_CMD_SFWT;
0045   /*  PUT_DC_CST(t1); */
0046   t1 = M8xx_CACHE_CMD_ENABLE;
0047   /*  PUT_DC_CST(t1);*/
0048 #endif
0049 }