mpc8260ads/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This routine does the bulk of the system initialization.
0005  */
0006
0007 /*
0008  *  The MPC860 specific stuff was written by Jay Monkman (jmonkman@frasca.com)
0009  *
0010  *  Modified for the MPC8260ADS board by Andy Dachs <a.dachs@sstl.co.uk>
0011  *  Surrey Satellite Technology Limited, 2001
0012  *  A 40MHz system clock is assumed.
0013  *  The PON. RST.CONF. Dip switches (DS1) are
0014  *  1 - Off
0015  *  2 - On
0016  *  3 - Off
0017  *  4 - On
0018  *  5 - Off
0019  *  6 - Off
0020  *  7 - Off
0021  *  8 - Off
0022  *  Dip switches on DS2 and DS3 are all set to ON
0023  *  The LEDs on the board are used to signal panic and fatal_error
0024  *  conditions.
0025  *  The mmu is unused at this time.
0026  *
0027  *  COPYRIGHT (c) 1989-2007.
0028  *  On-Line Applications Research Corporation (OAR).
0029  *
0030  * Redistribution and use in source and binary forms, with or without
0031  * modification, are permitted provided that the following conditions
0032  * are met:
0033  * 1. Redistributions of source code must retain the above copyright
0034  *    notice, this list of conditions and the following disclaimer.
0035  * 2. Redistributions in binary form must reproduce the above copyright
0036  *    notice, this list of conditions and the following disclaimer in the
0037  *    documentation and/or other materials provided with the distribution.
0038  *
0039  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0040  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0041  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0042  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0043  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0044  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0045  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0046  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0047  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0048  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0049  * POSSIBILITY OF SUCH DAMAGE.
0050  */
0051
0052 #include <bsp.h>
0053 #include <bsp/bootcard.h>
0054
0055 /*
0056 #include <mmu.h>
0057 */
0058
0059 #include <mpc8260.h>
0060 #include <rtems/score/thread.h>
0061 #include <rtems/powerpc/powerpc.h>
0062
0063 #include <rtems/bspIo.h>
0064 #include <rtems/counter.h>
0065 #include <bsp/irq.h>
0066 #include <libcpu/cpuIdent.h>
0067 #include <libcpu/spr.h>
0068
0069 #include <string.h>
0070
0071 #define UART1_E 0x02000002      /* bit 6 of BCSR1 */
0072 #define UART2_E 0x01000001      /* bit 7 of BCSR1 */
0073
0074 #define GP0_LED 0x02000002    /*  bit 6 of BCSR0 */
0075 #define GP1_LED 0x01000001    /*  bit 7 of BCSR0 */
0076
0077 SPR_RW(SPRG1)
0078
0079 /*
0080  *  Driver configuration parameters
0081  */
0082 uint32_t   bsp_clock_speed;
0083 uint32_t   bsp_time_base_frequency;
0084 uint32_t   bsp_clicks_per_usec;
0085 uint32_t   bsp_serial_per_sec;         /* Serial clocks per second */
0086 bool       bsp_serial_external_clock;
0087 bool       bsp_serial_xon_xoff;
0088 bool       bsp_serial_cts_rts;
0089 uint32_t   bsp_serial_rate;
0090
0091 /* leave in case needed in future */
0092 #if 0
0093 static void _BSP_GPLED0_on(void)
0094 {
0095   BCSR *csr;
0096   csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
0097   csr->bcsr0 &=  ~GP0_LED;      /* Turn on GP0 LED */
0098 }
0099 #endif
0100
0101 static void _BSP_GPLED0_off(void)
0102 {
0103   BCSR *csr;
0104   csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
0105   csr->bcsr0 |=  GP0_LED;       /* Turn off GP0 LED */
0106 }
0107
0108 /* leave in case needed in future */
0109 #if 0
0110 static void _BSP_GPLED1_on(void)
0111 {
0112   BCSR *csr;
0113   csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
0114   csr->bcsr0 &=  ~GP1_LED;      /* Turn on GP1 LED */
0115 }
0116 #endif
0117
0118 static void _BSP_GPLED1_off(void)
0119 {
0120   BCSR *csr;
0121   csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
0122   csr->bcsr0 |=  GP1_LED;       /* Turn off GP1 LED */
0123 }
0124
0125 static void _BSP_Uart1_enable(void)
0126 {
0127   BCSR *csr;
0128   csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
0129   csr->bcsr1 &= ~UART1_E;       /* Enable Uart1 */
0130 }
0131
0132 static void _BSP_Uart2_enable(void)
0133 {
0134   BCSR *csr;
0135   csr = (BCSR *)(m8260.memc[1].br & 0xFFFF8000);
0136   csr->bcsr1 &= ~UART2_E;       /* Enable Uart2 */
0137 }
0138
0139 uint32_t _CPU_Counter_frequency(void)
0140 {
0141   return bsp_clock_speed;
0142 }
0143
0144 void bsp_start(void)
0145 {
0146   /* Set MPC8260ADS board LEDS and Uart enable lines */
0147   _BSP_GPLED0_off();
0148   _BSP_GPLED1_off();
0149   _BSP_Uart1_enable();
0150   _BSP_Uart2_enable();
0151
0152   /*
0153    * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
0154    * function stores the result in global variables so that it can be used
0155    * later...
0156    */
0157   get_ppc_cpu_type();
0158   get_ppc_cpu_revision();
0159
0160   cpu_init();
0161
0162 /*
0163   mmu_init();
0164 */
0165
0166   ppc_exc_initialize();
0167   bsp_interrupt_initialize();
0168
0169 /*
0170   mmu_init();
0171 */
0172
0173   /*
0174    * Enable instruction and data caches. Do not force writethrough mode.
0175    */
0176 #if BSP_INSTRUCTION_CACHE_ENABLED
0177   rtems_cache_enable_instruction();
0178 #endif
0179 #if BSP_DATA_CACHE_ENABLED
0180   rtems_cache_enable_data();
0181 #endif
0182
0183   /*
0184    *  initialize the device driver parameters
0185    */
0186   bsp_time_base_frequency    = 10000000;
0187   bsp_clicks_per_usec        = 10;  /* for 40MHz extclk */
0188   bsp_serial_per_sec         = 40000000;
0189   bsp_serial_external_clock  = 0;
0190   bsp_serial_xon_xoff        = 0;
0191   bsp_serial_cts_rts         = 0;
0192   bsp_serial_rate        = 9600;
0193   bsp_clock_speed      = 40000000;
0194
0195 #ifdef REV_0_2
0196   /* set up some board specific registers */
0197   m8260.siumcr &= 0xF3FFFFFF;       /* set TBEN ** BUG FIX ** */
0198   m8260.siumcr |= 0x08000000;
0199 #endif
0200
0201   /* use BRG1 to generate 32kHz timebase */
0202 /*
0203   m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0;
0204 */
0205
0206 #ifdef SHOW_MORE_INIT_SETTINGS
0207   printk("Exit from bspstart\n");
0208 #endif
0209
0210 }