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File indexing completed on 2025-05-11 08:23:56 

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /**
0004  * @file
0005  *
0006  * @ingroup mpc55xx_asm
0007  *
0008  * @brief Boot and system start code.
0009  */
0010 
0011 /*
0012  * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035 
0036 #include <bspopts.h>
0037 #include <bsp/linker-symbols.h>
0038 #include <libcpu/powerpc-utility.h>
0039 
0040 #if MPC55XX_CHIP_FAMILY != 551
0041   #define HAS_SPE
0042 #endif
0043 
0044 #if MPC55XX_CHIP_FAMILY == 564
0045   #define INIT_REGISTERS_FOR_LSM
0046 #endif
0047 
0048 #ifdef HAS_SPE
0049   #define ZERO_GPR(reg) evxor   reg, reg, reg
0050 #else
0051   #define ZERO_GPR(reg) xor reg, reg, reg
0052 #endif
0053 
0054     .extern __eabi
0055     .extern boot_card
0056     .extern bsp_ram_start
0057     .extern mpc55xx_start_config_mmu_early
0058     .extern mpc55xx_start_config_mmu_early_count
0059     .extern mpc55xx_start_early
0060 
0061     .globl  _start
0062     .globl  mpc55xx_start_load_section
0063     .globl  mpc55xx_start_mmu_apply_config
0064 
0065 #ifdef MPC55XX_BOOTFLAGS
0066     .globl  mpc55xx_bootflag_0
0067     .globl  mpc55xx_bootflag_1
0068 #endif
0069 
0070     .section    ".bsp_start_text", "ax"
0071 
0072     /* BAM: RCHW */
0073     .int    0x005a0000
0074 
0075     /* BAM: Address of start instruction */
0076     .int    _start
0077 
0078 #ifdef MPC55XX_BOOTFLAGS
0079     /*
0080      * We skip over the next two boot flag words to the next 64-bit
0081      * aligned start address. It is 64-bit aligned to play well with
0082      * FLASH programming.  These boot flags can be set by debuggers
0083      * and emulators to customize boot.  Currently bit0 of
0084      * bootflag_0 means to "skip setting up the MMU", allowing
0085      * external MMU setup in a debugger before branching to 0x10.
0086      * This can be used e.g., to map FLASH into RAM.
0087      */
0088 mpc55xx_bootflag_0:
0089     .int    0xffffffff
0090 mpc55xx_bootflag_1:
0091     .int    0xffffffff
0092 #endif
0093 
0094 _start:
0095 
0096 #ifdef MPC55XX_ENABLE_START_PROLOGUE
0097     bl  mpc55xx_start_prologue
0098 #endif
0099 
0100 #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
0101 
0102     /* Enable SPE */
0103 #ifdef HAS_SPE
0104     mfmsr   r3
0105     oris    r3, r3, MSR_SPE >> 16
0106     mtmsr   r3
0107     isync
0108 #endif
0109 
0110     /*
0111      * Initialization of core registers according to "e200z4 Power
0112      * Architecture Core Reference Manual" section 2.6 "Reset Settings"
0113      * table 2-16 "Reset Settings of e200 Resources".  This is necessary
0114      * for lock step mode (LSM).
0115      */
0116     ZERO_GPR(r0)
0117 #ifdef INIT_REGISTERS_FOR_LSM
0118     ZERO_GPR(r1)
0119     ZERO_GPR(r2)
0120     ZERO_GPR(r4)
0121     ZERO_GPR(r5)
0122     ZERO_GPR(r6)
0123     ZERO_GPR(r7)
0124     ZERO_GPR(r8)
0125     ZERO_GPR(r9)
0126     ZERO_GPR(r10)
0127     ZERO_GPR(r11)
0128     ZERO_GPR(r12)
0129     ZERO_GPR(r13)
0130     ZERO_GPR(r14)
0131     ZERO_GPR(r15)
0132     ZERO_GPR(r16)
0133     ZERO_GPR(r17)
0134     ZERO_GPR(r18)
0135     ZERO_GPR(r19)
0136     ZERO_GPR(r20)
0137     ZERO_GPR(r21)
0138     ZERO_GPR(r22)
0139     ZERO_GPR(r23)
0140     ZERO_GPR(r24)
0141     ZERO_GPR(r25)
0142     ZERO_GPR(r26)
0143     ZERO_GPR(r27)
0144     ZERO_GPR(r28)
0145     ZERO_GPR(r29)
0146     ZERO_GPR(r30)
0147     ZERO_GPR(r31)
0148     mtcrf   0xff, r0
0149     mtcsrr0 r0
0150     mtcsrr1 r0
0151     mtctr   r0
0152     mtspr   FSL_EIS_DBCNT, r0
0153     mtspr   DEAR_BOOKE, r0
0154     mtdec   r0
0155     mtspr   BOOKE_DECAR, r0
0156     mtspr   FSL_EIS_DSRR0, r0
0157     mtspr   FSL_EIS_DSRR1, r0
0158     mtspr   BOOKE_DVC1, r0
0159     mtspr   BOOKE_DVC2, r0
0160     mtspr   BOOKE_IVPR, r0
0161     mtlr    r0
0162     mtspr   FSL_EIS_MCAR, r0
0163     mtmcsrr0    r0
0164     mtmcsrr1    r0
0165     mtspr   SPRG0, r0
0166     mtspr   SPRG1, r0
0167     mtspr   SPRG2, r0
0168     mtspr   SPRG3, r0
0169     mtspr   SPRG4, r0
0170     mtspr   SPRG5, r0
0171     mtspr   SPRG6, r0
0172     mtspr   SPRG7, r0
0173     mtspr   FSL_EIS_SPRG8, r0
0174     mtspr   FSL_EIS_SPRG9, r0
0175     mtsrr0  r0
0176     mtsrr1  r0
0177     mtspr   USPRG0, r0
0178 #ifdef HAS_SPE
0179     evmra   r0, r0
0180 #endif
0181 #endif /* INIT_REGISTERS_FOR_LSM */
0182     mtspr   TBWL, r0
0183     mtspr   TBWU, r0
0184 
0185     /* Enable time base */
0186     mfspr   r3, HID0
0187     ori r3, r3, 0x4000
0188     mtspr   HID0, r3
0189 
0190     /*
0191      * Enable branch prediction.
0192      *
0193      * Errata e4396: e200z7: Erroneous Address Fetch
0194      *
0195      * The propose workaround does not work.
0196      */
0197 #if MPC55XX_CHIP_FAMILY != 567
0198     LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BALLOC_ALL | FSL_EIS_BUCSR_BPRED_NOT_TAKEN | FSL_EIS_BUCSR_BPEN
0199     mtspr   FSL_EIS_BUCSR, r3
0200 #endif
0201 
0202 #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
0203 
0204     /* MMU early initialization */
0205     LA  r3, mpc55xx_start_config_mmu_early
0206     LW  r4, mpc55xx_start_config_mmu_early_count
0207     bl  mpc55xx_start_mmu_apply_config
0208 
0209 #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
0210 
0211     /* Initialize intermediate stack (ECC) */
0212 
0213     LA  r3, bsp_ram_start
0214     addi    r4, r3, MPC55XX_EARLY_STACK_SIZE
0215 
0216 zero_intermediate_stack_loop:
0217 
0218 #ifdef HAS_SPE
0219     evstdd  r0, 0(r3)
0220     evstdd  r0, 8(r3)
0221     evstdd  r0, 16(r3)
0222     evstdd  r0, 24(r3)
0223 #else
0224     stw r0, 0(r3)
0225     stw r0, 4(r3)
0226     stw r0, 8(r3)
0227     stw r0, 12(r3)
0228     stw r0, 16(r3)
0229     stw r0, 20(r3)
0230     stw r0, 24(r3)
0231     stw r0, 28(r3)
0232 #endif
0233     addi    r3, r3, 32
0234     cmpw    cr7, r3, r4
0235     bne cr7, zero_intermediate_stack_loop
0236     subi    r1, r3, 16
0237 
0238 #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
0239 
0240     /* Next steps in C */
0241     bl  mpc55xx_start_early
0242 
0243     /* Initialize start stack */
0244     LA  r1, _ISR_Stack_area_end
0245     subi    r1, r1, 16
0246     li  r0, 0
0247     stw r0, 0(r1)
0248 
0249     /*
0250      * Load sections.  This must be performed after the stack switch
0251      * because it may overwrite the initial stack.
0252      */
0253     LA  r3, bsp_section_fast_text_begin
0254     LA  r4, bsp_section_fast_text_load_begin
0255     LA  r5, bsp_section_fast_text_size
0256     bl  mpc55xx_start_load_section
0257     LA  r3, bsp_section_fast_data_begin
0258     LA  r4, bsp_section_fast_data_load_begin
0259     LA  r5, bsp_section_fast_data_size
0260     bl  mpc55xx_start_load_section
0261     LA  r3, bsp_section_data_begin
0262     LA  r4, bsp_section_data_load_begin
0263     LA  r5, bsp_section_data_size
0264     bl  mpc55xx_start_load_section
0265 
0266     /* Set up EABI and SYSV environment */
0267     bl  __eabi
0268 
0269     /* Clear command line */
0270     li  r3, 0
0271 
0272     /* Start RTEMS */
0273     bl  boot_card
0274 
0275     /* Spin around */
0276 twiddle:
0277 
0278     b   twiddle
0279 
0280 mpc55xx_start_mmu_apply_config:
0281 
0282     cmpwi   cr7, r4, r0
0283     beqlr   cr7
0284     mtctr   r4
0285 
0286 mmu_init_loop:
0287 
0288     lwz r4, 0(r3)
0289     lwz r5, 4(r3)
0290     lwz r6, 8(r3)
0291     lwz r7, 12(r3)
0292     mtspr   FSL_EIS_MAS0, r4
0293     mtspr   FSL_EIS_MAS1, r5
0294     mtspr   FSL_EIS_MAS2, r6
0295     mtspr   FSL_EIS_MAS3, r7
0296     tlbwe
0297     addi    r3, r3, 16
0298     bdnz    mmu_init_loop
0299     blr
0300 
0301 mpc55xx_start_load_section:
0302     cmpw    cr7, r3, r4
0303     beqlr   cr7
0304     b   memcpy
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