mpc55xxevb/start/start-flash.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup mpc55xx_asm
0007  *
0008  * @brief Flash configuration.
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2015 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <libcpu/powerpc-utility.h>
0037 #include <mpc55xx/reg-defs.h>
0038
0039     .section    ".bsp_start_text", "ax"
0040
0041 #if MPC55XX_CHIP_FAMILY == 551
0042
0043 /* MPC5510 Microcontroller Family Data Sheet, Rev. 3, Table 16, Num 7 */
0044 .equ FLASH_CLOCK_0, 25000000
0045 .equ FLASH_CLOCK_1, 50000000
0046 .equ FLASH_CLOCK_2, 80000000
0047 .equ FLASH_CLOCK_3, FLASH_CLOCK_2
0048 .equ FLASH_SETTINGS_0, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_0 | FLASH_BUICR_RWSC_0 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_1 | FLASH_BUICR_IPFEN_1 | FLASH_BUICR_PFLIM_2 | FLASH_BUICR_BFEN
0049 .equ FLASH_SETTINGS_1, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_1 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_1 | FLASH_BUICR_IPFEN_1 | FLASH_BUICR_PFLIM_2 | FLASH_BUICR_BFEN
0050 .equ FLASH_SETTINGS_2, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_2 | FLASH_BUICR_RWSC_2 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_1 | FLASH_BUICR_IPFEN_1 | FLASH_BUICR_PFLIM_2 | FLASH_BUICR_BFEN
0051 .equ FLASH_SETTINGS_3, FLASH_SETTINGS_2
0052
0053 #else
0054
0055 /* Optimized flash configurations (Table 13-15 [MPC5567 Microcontroller Reference Manual]) */
0056 .equ FLASH_CLOCK_0, 82000000
0057 .equ FLASH_CLOCK_1, 102000000
0058 .equ FLASH_CLOCK_2, 132000000
0059 .equ FLASH_CLOCK_3, 264000000
0060 .equ FLASH_SETTINGS_0, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_1 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
0061 .equ FLASH_SETTINGS_1, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_2 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
0062 .equ FLASH_SETTINGS_2, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_2 | FLASH_BUICR_RWSC_3 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
0063 .equ FLASH_SETTINGS_3, 0x01716B15
0064
0065 #endif
0066
0067 /**
0068  * @fn void mpc55xx_start_flash()
0069  * @brief Optimized flash configuration.
0070  * @warning Code will be copied and executed on the stack.
0071  */
0072 GLOBAL_FUNCTION mpc55xx_start_flash
0073 #if !defined(MPC55XX_NEEDS_LOW_LEVEL_INIT) \
0074   || MPC55XX_CHIP_FAMILY == 564 \
0075   || MPC55XX_CHIP_FAMILY == 566
0076     blr
0077 #else
0078     .equ    stack_size, 20
0079     .equ    lr_offset, 28
0080
0081     /* Reserve stack frame */
0082     stwu    r1, -stack_size(r1)
0083     mflr    r0
0084     stw r0, lr_offset(r1)
0085
0086     /* Flash settings dependent on system clock */
0087     bl  mpc55xx_get_system_clock
0088     LWI r4, FLASH_CLOCK_0
0089     cmpw    r3, r4
0090     ble clock_0
0091     LWI r4, FLASH_CLOCK_1
0092     cmpw    r3, r4
0093     ble clock_1
0094     LWI r4, FLASH_CLOCK_2
0095     cmpw    r3, r4
0096     ble clock_2
0097     LWI r4, FLASH_CLOCK_3
0098     cmpw    r3, r4
0099     ble clock_3
0100
0101     /*
0102      * In case we don't have the right flash settings for the system clock
0103      * value, then rely on the BAM settings.
0104      */
0105     blr
0106
0107 clock_0:
0108     LWI r3, FLASH_SETTINGS_0
0109     b   settings_done
0110 clock_1:
0111     LWI r3, FLASH_SETTINGS_1
0112     b   settings_done
0113 clock_2:
0114     LWI r3, FLASH_SETTINGS_2
0115     b settings_done
0116 clock_3:
0117     LWI r3, FLASH_SETTINGS_3
0118     b   settings_done
0119 settings_done:
0120
0121     /* Copy store code on the stack */
0122     LA  r4, store_start
0123     lwz r6, 0(r4)
0124     lwz r7, 4(r4)
0125     lwz r8, 8(r4)
0126     stw r6, 8(r1)
0127     stw r7, 12(r1)
0128     stw r8, 16(r1)
0129
0130     /* Execute store code */
0131     LA  r4, FLASH_BIUCR
0132     addi    r5, r1, 8
0133     mtctr   r5
0134     bctrl
0135
0136     /* Return */
0137     lwz r0, lr_offset(r1)
0138     addi    r1, r1, stack_size
0139     mtlr    r0
0140     blr
0141
0142 /*
0143  * Store flash settings
0144  */
0145
0146 store_start:
0147
0148     stw r3, 0(r4)
0149     isync
0150     blr
0151
0152 #endif