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0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief MMU configuration.
0009  */
0010 
0011 /*
0012  * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035 
0036 #include <bsp/mpc55xx-config.h>
0037 
0038 const struct MMU_tag mpc55xx_start_config_mmu [] = {
0039 #if defined(MPC55XX_BOARD_GWLCFM)
0040   /* External Ethernet Controller 64k */
0041   MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
0042 #elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
0043   /* Arguments macro:       idx,  addr,      size,              x, w, r, io */
0044   MPC55XX_MMU_TAG_INITIALIZER(8, 0x20000000, MPC55XX_MMU_8M,    1, 0, 1, 0), /* External FLASH 8M */
0045   MPC55XX_MMU_TAG_INITIALIZER(2, 0x21000000, MPC55XX_MMU_4M,    0, 1, 1, 0), /* Lower half SRAM */
0046   MPC55XX_MMU_TAG_INITIALIZER(5, 0x21400000, MPC55XX_MMU_4M,    1, 1, 1, 0), /* Upper half SRAM ("debug") */
0047   MPC55XX_MMU_TAG_INITIALIZER(6, 0x22000000, MPC55XX_MMU_16M,   0, 1, 1, 1), /* LAN91C111 */
0048   MPC55XX_MMU_TAG_INITIALIZER(7, 0x23000000, MPC55XX_MMU_16M,   0, 1, 1, 1), /* FPGA */
0049 #elif defined(MPC55XX_BOARD_MPC5566EVB)
0050   /* Internal flash 3M */
0051   MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
0052   MPC55XX_MMU_TAG_INITIALIZER(6, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
0053   MPC55XX_MMU_TAG_INITIALIZER(7, 0x00020000, MPC55XX_MMU_64K, 1, 0, 1, 0),
0054   MPC55XX_MMU_TAG_INITIALIZER(8, 0x00030000, MPC55XX_MMU_64K, 1, 0, 1, 0),
0055   MPC55XX_MMU_TAG_INITIALIZER(9, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
0056   MPC55XX_MMU_TAG_INITIALIZER(10, 0x00080000, MPC55XX_MMU_256K, 1, 0, 1, 0),
0057   MPC55XX_MMU_TAG_INITIALIZER(11, 0x000c0000, MPC55XX_MMU_256K, 1, 0, 1, 0),
0058   MPC55XX_MMU_TAG_INITIALIZER(12, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
0059   MPC55XX_MMU_TAG_INITIALIZER(13, 0x00200000, MPC55XX_MMU_1M, 1, 0, 1, 0),
0060   /* External SRAM 512k */
0061   MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
0062   MPC55XX_MMU_TAG_INITIALIZER(14, 0x20040000, MPC55XX_MMU_256K, 0, 1, 1, 0),
0063   /* Internal SRAM 128k */
0064   MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
0065   MPC55XX_MMU_TAG_INITIALIZER(5, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0),
0066   /* External Ethernet Controller 64k */
0067   MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
0068 #elif defined(MPC55XX_BOARD_MPC5674FEVB)
0069   /* Internal flash 4M */
0070   MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
0071   MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
0072   MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
0073   MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
0074   MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
0075   MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
0076   MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
0077   /* External SRAM 512k */
0078   MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_512K, 0, 1, 1, 0),
0079   /* Internal SRAM 256k */
0080   MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_128K, 0, 1, 1, 0),
0081   MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0),
0082   MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K, 0, 1, 1, 0),
0083   MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K, 0, 1, 1, 0),
0084   MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1),
0085   /* External Ethernet controller */
0086   MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
0087 #elif defined(MPC55XX_BOARD_MPC5674F_ECU508)
0088   #if defined(MPC55XX_NEEDS_LOW_LEVEL_INIT)
0089     /* Arguments macro:       idx,  addr,       size,             x, w, r, io */
0090 
0091     /* Internal flash 4M */
0092     /* First 64k unused, to detect NULL pointer access */
0093     MPC55XX_MMU_TAG_INITIALIZER(1,  0x00000000, MPC55XX_MMU_64K,  1, 0, 1, 0),
0094     MPC55XX_MMU_TAG_INITIALIZER(5,  0x00010000, MPC55XX_MMU_64K,  1, 0, 1, 0),
0095     MPC55XX_MMU_TAG_INITIALIZER(6,  0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
0096     MPC55XX_MMU_TAG_INITIALIZER(7,  0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
0097     MPC55XX_MMU_TAG_INITIALIZER(8,  0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
0098     MPC55XX_MMU_TAG_INITIALIZER(9,  0x00100000, MPC55XX_MMU_1M,   1, 0, 1, 0),
0099     MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M,   1, 0, 1, 0),
0100     /* External SRAM 2M */
0101     #ifndef BSP_DATA_CACHE_USE_WRITE_THROUGH
0102       MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M,  0, 1, 1, 0),
0103     #else
0104       MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M,  0, 1, 1, 2),
0105     #endif
0106     /* Internal SRAM 256k */
0107     MPC55XX_MMU_TAG_INITIALIZER(3,  0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
0108     MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K,  0, 1, 1, 0),
0109     MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K,  0, 1, 1, 0),
0110     MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K,  0, 1, 1, 0),
0111     /* Used as cache-inhibited area (ADC, DSPI queues) */
0112     MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K,  0, 1, 1, 1),
0113     /* External Ethernet controller */
0114     MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_1K,   0, 1, 1, 1),
0115     /* External MRAM 128k */
0116     MPC55XX_MMU_TAG_INITIALIZER(16, 0x3ffa0000, MPC55XX_MMU_128K, 0, 1, 1, 0),
0117     /* External ARCNET controller */
0118     MPC55XX_MMU_TAG_INITIALIZER(17, 0x3ffc0000, MPC55XX_MMU_1K,   0, 1, 1, 1)
0119     /* Peripheral Bridge A-Registers on MMU-table pos 4 */
0120     /* Peripheral Bridge B-Registers on MMU-table pos 0 */
0121   #else
0122     /* Used as cache-inhibited area (ADC, DSPI queues) */
0123     MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K,  0, 1, 1, 1)
0124   #endif
0125 #elif defined(MPC55XX_BOARD_MPC5674F_RSM6)
0126   /* Arguments macro:        idx, addr,       size,             x, w, r, io */
0127 
0128   /* Internal flash 4M */
0129   /* First 64k unused, to detect NULL pointer access */
0130   MPC55XX_MMU_TAG_INITIALIZER(1,  0x00000000, MPC55XX_MMU_64K,  1, 0, 1, 0),
0131   MPC55XX_MMU_TAG_INITIALIZER(5,  0x00010000, MPC55XX_MMU_64K,  1, 0, 1, 0),
0132   MPC55XX_MMU_TAG_INITIALIZER(6,  0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
0133   MPC55XX_MMU_TAG_INITIALIZER(7,  0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
0134   MPC55XX_MMU_TAG_INITIALIZER(8,  0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
0135   MPC55XX_MMU_TAG_INITIALIZER(9,  0x00100000, MPC55XX_MMU_1M,   1, 0, 1, 0),
0136   MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M,   1, 0, 1, 0),
0137   /* External MRAM 4M */
0138   MPC55XX_MMU_TAG_INITIALIZER(2,  0x20000000, MPC55XX_MMU_4M,   0, 1, 1, 0),
0139   /* Internal SRAM 256k */
0140   MPC55XX_MMU_TAG_INITIALIZER(3,  0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
0141   MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K,  0, 1, 1, 0),
0142   MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K,  0, 1, 1, 0),
0143   MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K,  0, 1, 1, 0),
0144   /* Used as cache-inhibited area (ADC, DSPI queues) */
0145   MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K,  0, 1, 1, 1),
0146   /* External FPGA */
0147   MPC55XX_MMU_TAG_INITIALIZER(15, 0x21000000, MPC55XX_MMU_8M,   0, 1, 1, 1),
0148   /* External Ethernet controller */
0149   MPC55XX_MMU_TAG_INITIALIZER(16, 0x23000000, MPC55XX_MMU_1K,   0, 1, 1, 1)
0150 #elif MPC55XX_CHIP_FAMILY == 564
0151   /* Internal flash 1M */
0152   MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 0),
0153   /* IO */
0154   MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1),
0155   MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1),
0156   /* Internal SRAM 64k + 64k */
0157   MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
0158   MPC55XX_MMU_TAG_INITIALIZER(4, 0x50000000, MPC55XX_MMU_64K, 0, 1, 1, 0)
0159 #endif
0160 };
0161 
0162 const size_t mpc55xx_start_config_mmu_count [] = {
0163   RTEMS_ARRAY_SIZE(mpc55xx_start_config_mmu)
0164 };
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