mpc55xxevb/start/start-config-ebi-cs.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief EBI chip-select configuration.
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp/mpc55xx-config.h>
0037
0038 #ifdef MPC55XX_HAS_EBI
0039
0040 const struct EBI_CS_tag mpc55xx_start_config_ebi_cs [] = {
0041 #if defined(MPC55XX_BOARD_GWLCFM)
0042     /* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
0043     {
0044         {
0045             .B.BA = 0x20000000>>15,
0046             .B.PS = 1,
0047             .B.AD_MUX = 1,
0048             .B.WEBS = 1,
0049             .B.TBDIP = 0,
0050             .B.BI = 1,
0051             .B.V = 1
0052         },
0053         {
0054             .B.AM = 0x1fff0,
0055             .B.SCY = 1,
0056             .B.BSCY = 0
0057         }
0058     },
0059     /* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */
0060     {
0061         {
0062             .B.BA = 0x22000000>>15,
0063             .B.PS = 1,
0064             .B.AD_MUX = 1,
0065             .B.WEBS = 0,
0066             .B.TBDIP = 0,
0067             .B.BI = 1,
0068             .B.V = 1
0069         },
0070         {
0071             .B.AM = 0x1ffff,
0072             .B.SCY = 3,
0073             .B.BSCY = 0
0074         }
0075     },
0076     /* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */
0077     {
0078         {
0079             .B.BA = 0x22800000>>15,
0080             .B.PS = 1,
0081             .B.AD_MUX = 1,
0082             .B.WEBS = 1,
0083             .B.TBDIP = 0,
0084             .B.BI = 1,
0085             .B.V = 1
0086         },
0087         {
0088             .B.AM = 0x1ffff,
0089             .B.SCY = 1,
0090             .B.BSCY = 0
0091         }
0092     },
0093     {               /* CS3: MOST Companion. */
0094         {
0095             .B.BA = 0x23000000>>15,
0096             .B.PS = 1,
0097             .B.AD_MUX = 1,
0098             .B.WEBS = 0,
0099             .B.TBDIP = 0,
0100             .B.BI = 1,
0101             .B.V = 1
0102         },
0103
0104         {
0105             .B.AM = 0x1fff0,
0106             .B.SCY = 1,
0107             .B.BSCY = 0
0108         }
0109     }
0110 #elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
0111     /* CS0: External flash. */
0112     {
0113         { .R = 0x20000003 },   /* Base 0x2000000, Burst Inhibit, Valid */
0114         { .R = 0xff000050 }
0115     },
0116     /* CS1: External synchronous burst mode SRAM. */
0117     {
0118         { .R = 0x21000051 },   /* Base 0x2100000, 4-word Burst Enabled, Valid */
0119         { .R = 0xff000000 }    /* No wait states. */
0120     },
0121     /* CS2: External LAN91C111 */
0122     {
0123         { .R = 0x22000003 },   /* Base 0x22000000, Burst inhibit, valid */
0124         { .R = 0xff000010 }
0125     },
0126
0127     /* CS3: External FPGA */
0128     {
0129         { .R = 0x23000003 },   /* Base 0x23000000, Burst inhibit, valid. */
0130         { .R = 0xff000020 }
0131     }
0132 #elif defined(MPC55XX_BOARD_MPC5566EVB)
0133     /* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */
0134     {
0135         {
0136             .B.BA = 0,
0137             .B.PS = 1,
0138             .B.BL = 1,
0139             .B.WEBS = 0,
0140             .B.TBDIP = 0,
0141             .B.BI = 1, /* TODO: Enable burst */
0142             .B.V = 1
0143         },
0144
0145         {
0146             .B.AM = 0x1fff0,
0147             .B.SCY = 0,
0148             .B.BSCY = 0
0149         }
0150     },
0151     { { .R = 0 }, { .R = 0 } },   /* CS1: Unused. */
0152     { { .R = 0 }, { .R = 0 } },   /* CS2: Unused. */
0153     {   /* CS3: ethernet? */
0154         {
0155             .B.BA = 0x7fff,
0156             .B.PS = 1,
0157             .B.BL = 0,
0158             .B.WEBS = 0,
0159             .B.TBDIP = 0,
0160             .B.BI = 1,
0161             .B.V = 1
0162         },
0163
0164         {
0165             .B.AM = 0x1ffff,
0166             .B.SCY = 1,
0167             .B.BSCY = 0
0168         }
0169     }
0170 #endif
0171 };
0172
0173 const size_t mpc55xx_start_config_ebi_cs_count [] = {
0174   RTEMS_ARRAY_SIZE(mpc55xx_start_config_ebi_cs)
0175 };
0176
0177 #endif /* MPC55XX_HAS_EBI */