mpc55xxevb/start/start-config-clock.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief Clock and FMPLL configuration.
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp/mpc55xx-config.h>
0037
0038 const mpc55xx_clock_config mpc55xx_start_config_clock [1] = { {
0039   #ifdef MPC55XX_HAS_FMPLL
0040     .syncr_tmp = {
0041       .B = {
0042         .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
0043         .MFD = MPC55XX_FMPLL_MFD,
0044         .RFD = 2,
0045         .LOCEN = 1
0046       }
0047     },
0048     .syncr_final = {
0049       .B = {
0050         .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
0051         .MFD = MPC55XX_FMPLL_MFD,
0052         .RFD = 0,
0053         .LOCEN = 1,
0054         .LOLIRQ = 1,
0055         .LOCIRQ = 1
0056       }
0057     }
0058   #endif
0059   #ifdef MPC55XX_HAS_FMPLL_ENHANCED
0060     #define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
0061     #define EMFD_VAL    (MPC55XX_FMPLL_MFD-16)
0062     #define VCO_CLK_REF (MPC55XX_REFERENCE_CLOCK/(EPREDIV_VAL+1))
0063     #define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
0064     #define ERFD_VAL \
0065       (((VCO_CLK_OUT + MPC55XX_SYSTEM_CLOCK - 1) / MPC55XX_SYSTEM_CLOCK)-1)
0066
0067     .esyncr2_tmp = {
0068       .B = {
0069         .LOCEN = 0,
0070         .LOLRE = 0,
0071         .LOCRE = 0,
0072         .LOLIRQ = 0,
0073         .LOCIRQ = 0,
0074         .ERATE = 0,
0075         .EDEPTH = 0,
0076         .ERFD = ERFD_VAL + 2 /* reduce output clock during init */
0077       }
0078     },
0079     .esyncr2_final = {
0080       .B = {
0081         .LOCEN = 0,
0082         .LOLRE = 0,
0083         .LOCRE = 0,
0084         .LOLIRQ = 0,
0085         .LOCIRQ = 0,
0086         .ERATE = 0,
0087         #if MPC55XX_CHIP_FAMILY  == 567
0088           .CLKCFG_DIS = 1,
0089         #endif
0090         .EDEPTH = 0,
0091         .ERFD = ERFD_VAL /* nominal output clock after init */
0092       }
0093     },
0094     .esyncr1_final = {
0095       .B = {
0096         .CLKCFG = MPC55XX_FMPLL_ESYNCR1_CLKCFG,
0097         .EPREDIV = EPREDIV_VAL,
0098         .EMFD = EMFD_VAL
0099       }
0100     }
0101   #endif
0102   #ifdef MPC55XX_HAS_MODE_CONTROL
0103     .fmpll = {
0104       {
0105         .cr = {
0106           #if MPC55XX_REFERENCE_CLOCK == 8000000
0107             .B = { .IDF = 0, .ODF = 1, .NDIV = 60, .I_LOCK = 1, .PLL_ON = 1 }
0108           #elif MPC55XX_REFERENCE_CLOCK == 40000000
0109             .B = { .IDF = 3, .ODF = 1, .NDIV = 48, .I_LOCK = 1, .PLL_ON = 1 }
0110           #else
0111             #error "unexpected reference clock"
0112           #endif
0113         }
0114       },
0115       {
0116         .cr = {
0117           .B = { .IDF = 3, .ODF = 2, .NDIV = 32, .I_LOCK = 1, .PLL_ON = 1 }
0118         }
0119       }
0120     },
0121     .ocds_sc = {
0122       .B = { .SELDIV = 2, .SELCTL = 2 }
0123     },
0124     .auxclk = {
0125       [0] = {
0126         .AC_SC = { .B = { .SELCTL = 4 } },
0127         .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 0 } }
0128       },
0129       [1] = {
0130         .AC_SC = { .B = { .SELCTL = 4 } },
0131         .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
0132       },
0133       [2] = {
0134         .AC_SC = { .B = { .SELCTL = 4 } },
0135         .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
0136       },
0137       [3] = {
0138         .AC_SC = { .B = { .SELCTL = 1 } }
0139       },
0140       [4] = {
0141         .AC_SC = { .B = { .SELCTL = 1 } }
0142       }
0143     }
0144   #endif
0145 } };