mpc55xxevb/start/start-clock.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief Clock and FMPLL initialization code.
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp.h>
0037 #include <bsp/fatal.h>
0038 #include <bsp/start.h>
0039 #include <bsp/bootcard.h>
0040 #include <bsp/mpc55xx-config.h>
0041
0042 #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
0043   #if defined(MPC55XX_HAS_FMPLL) || defined(MPC55XX_HAS_FMPLL_ENHANCED)
0044     static BSP_START_TEXT_SECTION void fmpll_wait_for_lock(void)
0045     {
0046       int i = 0;
0047       bool lock = false;
0048
0049       while (!lock && i < 6000) {
0050         lock = FMPLL.SYNSR.B.LOCK != 0;
0051         ++i;
0052       }
0053
0054       if (!lock) {
0055         bsp_fatal(MPC55XX_FATAL_FMPLL_LOCK);
0056       }
0057     }
0058   #endif
0059 #endif
0060
0061 BSP_START_TEXT_SECTION void mpc55xx_start_clock(void)
0062 {
0063   #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
0064     const mpc55xx_clock_config *cfg = mpc55xx_start_config_clock;
0065
0066     #ifdef MPC55XX_HAS_FMPLL
0067       volatile struct FMPLL_tag *fmpll = &FMPLL;
0068
0069       fmpll->SYNCR.R = cfg->syncr_tmp.R;
0070       fmpll->SYNCR.R;
0071       fmpll_wait_for_lock();
0072
0073       fmpll->SYNCR.R = cfg->syncr_final.R;
0074       fmpll->SYNCR.R;
0075       fmpll_wait_for_lock();
0076     #endif
0077
0078     #ifdef MPC55XX_HAS_FMPLL_ENHANCED
0079       volatile struct FMPLL_tag *fmpll = &FMPLL;
0080
0081       fmpll->ESYNCR2.R = cfg->esyncr2_tmp.R;
0082       fmpll->ESYNCR2.R;
0083       fmpll->ESYNCR1.R = cfg->esyncr1_final.R;
0084       fmpll->ESYNCR1.R;
0085       fmpll_wait_for_lock();
0086
0087       fmpll->ESYNCR2.R = cfg->esyncr2_final.R;
0088       fmpll->ESYNCR2.R;
0089       fmpll_wait_for_lock();
0090
0091       #if MPC55XX_CHIP_FAMILY == 551 || MPC55XX_CHIP_FAMILY == 566
0092         /* System clock supplied by PLL */
0093         SIU.SYSCLK.B.SYSCLKSEL = 2;
0094       #endif
0095     #endif
0096
0097     #ifdef MPC55XX_HAS_MODE_CONTROL
0098       volatile CGM_tag *cgm = &CGM;
0099       size_t fmpll_count = sizeof(cfg->fmpll) / sizeof(cfg->fmpll [0]);
0100       size_t auxclk_count = sizeof(cfg->auxclk) / sizeof(cfg->auxclk [0]);
0101       size_t i = 0;
0102
0103       for (i = 0; i < auxclk_count; ++i) {
0104         cgm->AUXCLK [i].AC_SC.R = cfg->auxclk [i].AC_SC.R;
0105         cgm->AUXCLK [i].AC_DC0_3.R = cfg->auxclk [i].AC_DC0_3.R;
0106       }
0107
0108       for (i = 0; i < fmpll_count; ++i) {
0109         cgm->FMPLL [i].CR.R = cfg->fmpll [i].cr.R;
0110         cgm->FMPLL [i].MR.R = cfg->fmpll [i].mr.R;
0111       }
0112
0113       cgm->OC_EN.R = cfg->oc_en.R;
0114       cgm->OCDS_SC.R = cfg->ocds_sc.R;
0115     #endif
0116   #endif
0117 }