mpc55xxevb/start/get-system-clock.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief System clock calculation.
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp.h>
0037 #include <bsp/start.h>
0038 #include <bsp/mpc55xx-config.h>
0039
0040 uint32_t mpc55xx_get_system_clock(void)
0041 {
0042   uint32_t system_clock = 0;
0043
0044   #ifdef MPC55XX_HAS_FMPLL
0045     volatile struct FMPLL_tag *fmpll = &FMPLL;
0046     union FMPLL_SYNSR_tag synsr = { .R = fmpll->SYNSR.R };
0047     uint32_t reference_clock = MPC55XX_REFERENCE_CLOCK;
0048     bool pll_clock_mode = synsr.B.MODE != 0;
0049     bool crystal_or_external_reference_mode = synsr.B.PLLSEL != 0;
0050
0051     if (pll_clock_mode) {
0052       if (crystal_or_external_reference_mode) {
0053         union FMPLL_SYNCR_tag syncr = { .R = fmpll->SYNCR.R };
0054         uint32_t prediv = syncr.B.PREDIV;
0055         uint32_t mfd = syncr.B.MFD;
0056         uint32_t rfd = syncr.B.RFD;
0057
0058         system_clock = ((reference_clock * (mfd + 4)) >> rfd) / (prediv + 1);
0059       } else {
0060         system_clock = 2 * reference_clock;
0061       }
0062     } else {
0063       system_clock = reference_clock;
0064     }
0065   #endif
0066
0067   #ifdef MPC55XX_HAS_FMPLL_ENHANCED
0068     volatile struct FMPLL_tag *fmpll = &FMPLL;
0069     union FMPLL_ESYNCR1_tag esyncr1 = { .R = fmpll->ESYNCR1.R };
0070     uint32_t reference_clock = MPC55XX_REFERENCE_CLOCK;
0071     bool normal_mode = (esyncr1.B.CLKCFG & 0x4U) != 0;
0072
0073     if (normal_mode) {
0074       union FMPLL_ESYNCR2_tag esyncr2 = { .R = fmpll->ESYNCR2.R };
0075       uint32_t eprediv = esyncr1.B.EPREDIV;
0076       uint32_t emfd = esyncr1.B.EMFD;
0077       uint32_t erfd = esyncr2.B.ERFD;
0078
0079       system_clock = ((reference_clock / (eprediv + 1)) * (emfd + 16))
0080         / (erfd + 1);
0081     } else {
0082       system_clock = reference_clock;
0083     }
0084   #endif
0085
0086   #ifdef MPC55XX_HAS_MODE_CONTROL
0087     /* FIXME: Assumes normal mode and external oscillator */
0088     PLLD_CR_32B_tag cr = { . R = CGM.FMPLL [0].CR.R };
0089     uint32_t xosc = MPC55XX_REFERENCE_CLOCK;
0090     uint32_t ldf = cr.B.NDIV;
0091     uint32_t idf = cr.B.IDF + 1;
0092     uint32_t odf = 2U << cr.B.ODF;
0093
0094     system_clock = (xosc * ldf) / (idf * odf);
0095   #endif
0096
0097   return system_clock;
0098 }