mpc55xxevb/start/exc-vector-base.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup mpc55xx_asm
0007  *
0008  * @brief Exception minimum prologues.
0009  */
0010
0011 /*
0012  * Copyright (C) 2011, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 /**
0037  * @defgroup mpc55xx_asm Assembler files
0038  *
0039  * @ingroup RTEMSBSPsPowerPCMPC55XX
0040  */
0041
0042 #include <bspopts.h>
0043
0044 #include <bsp/vectors.h>
0045
0046     .globl mpc55xx_exc_vector_base
0047
0048     .section ".bsp_text", "ax"
0049
0050 #if 5510 <= MPC55XX_CHIP_TYPE && MPC55XX_CHIP_TYPE <= 5517
0051     .align 12
0052 #else
0053     .align 16
0054 #endif
0055
0056 mpc55xx_exc_vector_base:
0057
0058     stw r1, ppc_exc_lock_crit@sdarel(r13)
0059     stw r4, ppc_exc_vector_register_crit@sdarel(r13)
0060     li  r4, -32767
0061     b   ppc_exc_wrap_bookE_crit
0062     stwu    r1, -EXC_GENERIC_SIZE(r1)
0063     stw r4, GPR4_OFFSET(r1)
0064     li  r4, 2
0065     b   ppc_exc_wrap_nopush_bookE_crit
0066     stwu    r1, -EXC_GENERIC_SIZE(r1)
0067     stw r4, GPR4_OFFSET(r1)
0068     li  r4, 3
0069     b   ppc_exc_wrap_nopush_std
0070     stwu    r1, -EXC_GENERIC_SIZE(r1)
0071     stw r4, GPR4_OFFSET(r1)
0072     li  r4, 4
0073     b   ppc_exc_wrap_nopush_std
0074     stwu    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0075     stw r3, GPR3_OFFSET(r1)
0076     li  r3, -32763
0077     b   ppc_exc_interrupt
0078     stwu    r1, -EXC_GENERIC_SIZE(r1)
0079     stw r4, GPR4_OFFSET(r1)
0080     li  r4, 6
0081     b   ppc_exc_wrap_nopush_std
0082     stwu    r1, -EXC_GENERIC_SIZE(r1)
0083     stw r4, GPR4_OFFSET(r1)
0084     li  r4, 7
0085     b   ppc_exc_wrap_nopush_std
0086     stwu    r1, -EXC_GENERIC_SIZE(r1)
0087     stw r4, GPR4_OFFSET(r1)
0088     li  r4, 8
0089     b   ppc_exc_wrap_nopush_std
0090     stwu    r1, -EXC_GENERIC_SIZE(r1)
0091     stw r4, GPR4_OFFSET(r1)
0092     li  r4, 12
0093     b   ppc_exc_wrap_nopush_std
0094     stwu    r1, -EXC_GENERIC_SIZE(r1)
0095     stw r4, GPR4_OFFSET(r1)
0096     li  r4, 24
0097     b   ppc_exc_wrap_nopush_std
0098     stwu    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0099     stw r3, GPR3_OFFSET(r1)
0100     li  r3, -32752
0101     b   ppc_exc_interrupt
0102     stwu    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
0103     stw r3, GPR3_OFFSET(r1)
0104     li  r3, -32749
0105     b   ppc_exc_interrupt
0106     stw r1, ppc_exc_lock_crit@sdarel(r13)
0107     stw r4, ppc_exc_vector_register_crit@sdarel(r13)
0108     li  r4, -32748
0109     b   ppc_exc_wrap_bookE_crit
0110     stwu    r1, -EXC_GENERIC_SIZE(r1)
0111     stw r4, GPR4_OFFSET(r1)
0112     li  r4, 18
0113     b   ppc_exc_wrap_nopush_std
0114     stwu    r1, -EXC_GENERIC_SIZE(r1)
0115     stw r4, GPR4_OFFSET(r1)
0116     li  r4, 17
0117     b   ppc_exc_wrap_nopush_std
0118     stwu    r1, -EXC_GENERIC_SIZE(r1)
0119     stw r4, GPR4_OFFSET(r1)
0120     li  r4, 13
0121     b   ppc_exc_wrap_nopush_bookE_crit
0122     stwu    r1, -EXC_GENERIC_SIZE(r1)
0123     stw r4, GPR4_OFFSET(r1)
0124     li  r4, 10
0125     b   ppc_exc_wrap_nopush_std
0126     stwu    r1, -EXC_GENERIC_SIZE(r1)
0127     stw r4, GPR4_OFFSET(r1)
0128     li  r4, 25
0129     b   ppc_exc_wrap_nopush_std
0130     stwu    r1, -EXC_GENERIC_SIZE(r1)
0131     stw r4, GPR4_OFFSET(r1)
0132     li  r4, 26
0133     b   ppc_exc_wrap_nopush_std
0134     stwu    r1, -EXC_GENERIC_SIZE(r1)
0135     stw r4, GPR4_OFFSET(r1)
0136     li  r4, 15
0137     b   ppc_exc_wrap_nopush_std