include/mpc55xx/regs-mmu.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsPowerPCMPC55XX
0005  */
0006
0007 /*
0008  * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
0009  *
0010  * The license and distribution terms for this file may be
0011  * found in the file LICENSE in this distribution or at
0012  * http://www.rtems.org/license/LICENSE.
0013  */
0014
0015 /*********************************************************************
0016  *
0017  * Copyright:
0018  *  Freescale Semiconductor, INC. All Rights Reserved.
0019  *  You are hereby granted a copyright license to use, modify, and
0020  *  distribute the SOFTWARE so long as this entire notice is
0021  *  retained without alteration in any modified and/or redistributed
0022  *  versions, and that such modified versions are clearly identified
0023  *  as such. No licenses are granted by implication, estoppel or
0024  *  otherwise under any patents or trademarks of Freescale
0025  *  Semiconductor, Inc. This software is provided on an "AS IS"
0026  *  basis and without warranty.
0027  *
0028  *  To the maximum extent permitted by applicable law, Freescale
0029  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
0030  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
0031  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
0032  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
0033  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
0034  *
0035  *  To the maximum extent permitted by applicable law, IN NO EVENT
0036  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
0037  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
0038  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
0039  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
0040  *
0041  *  Freescale Semiconductor assumes no responsibility for the
0042  *  maintenance and support of this software
0043  *
0044  ********************************************************************/
0045
0046 #ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
0047 #define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
0048
0049 #include <stdint.h>
0050
0051 #include <bspopts.h>
0052
0053 #ifdef  __cplusplus
0054 extern "C" {
0055 #endif
0056
0057 /****************************************************************************/
0058 /*                          MMU                                             */
0059 /****************************************************************************/
0060     struct MMU_tag {
0061         union {
0062             uint32_t R;
0063             struct {
0064                 uint32_t : 2;
0065                 uint32_t TLBSEL : 2;
0066                 uint32_t : 7;
0067                 uint32_t ESEL : 5;
0068                 uint32_t : 11;
0069                 uint32_t NV : 5;
0070             } B;
0071         } MAS0;
0072
0073         union {
0074             uint32_t R;
0075             struct {
0076                 uint32_t VALID : 1;
0077                 uint32_t IPROT : 1;
0078                 uint32_t : 6;
0079                 uint32_t TID : 8;
0080                 uint32_t : 3;
0081                 uint32_t TS : 1;
0082                 uint32_t TSIZE : 5;
0083                 uint32_t : 7;
0084             } B;
0085         } MAS1;
0086
0087         union {
0088             uint32_t R;
0089             struct {
0090                 uint32_t EPN : 22;
0091                 uint32_t : 4;
0092                 uint32_t VLE : 1;
0093                 uint32_t W : 1;
0094                 uint32_t I : 1;
0095                 uint32_t M : 1;
0096                 uint32_t G : 1;
0097                 uint32_t E : 1;
0098             } B;
0099         } MAS2;
0100
0101         union {
0102             uint32_t R;
0103             struct {
0104                 uint32_t RPN : 22;
0105                 uint32_t U0 : 1;
0106                 uint32_t U1 : 1;
0107                 uint32_t U2 : 1;
0108                 uint32_t U3 : 1;
0109                 uint32_t UX : 1;
0110                 uint32_t SX : 1;
0111                 uint32_t UW : 1;
0112                 uint32_t SW : 1;
0113                 uint32_t UR : 1;
0114                 uint32_t SR : 1;
0115             } B;
0116         } MAS3;
0117     };
0118
0119         union MMU_MAS4_tag {
0120             uint32_t R;
0121             struct {
0122                 uint32_t : 2;
0123                 uint32_t TLBSELD : 2;
0124                 uint32_t : 10;
0125                 uint32_t TIDSELD : 2;
0126                 uint32_t : 4;
0127                 uint32_t TSIZED : 4;
0128                 uint32_t : 3;
0129                 uint32_t WD : 1;
0130                 uint32_t ID : 1;
0131                 uint32_t MD : 1;
0132                 uint32_t GD : 1;
0133                 uint32_t ED : 1;
0134             } B;
0135         };
0136
0137         union MMU_MAS6_tag {
0138             uint32_t R;
0139             struct {
0140                 uint32_t : 8;
0141                 uint32_t SPID : 8;
0142                 uint32_t : 15;
0143                 uint32_t SAS : 1;
0144             } B;
0145         };
0146
0147 #define MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addreff, addrreal, size, x, w, r, io) \
0148   { \
0149     .MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \
0150     .MAS1 = { .B = { \
0151       .VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \
0152     }, \
0153     .MAS2 = { .B = { \
0154       .EPN = (addreff) >> 10, .VLE = 0, \
0155       .W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \
0156     }, \
0157     .MAS3 = { .B = { \
0158       .RPN = (addrreal) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \
0159       .SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \
0160     } \
0161   }
0162
0163 #define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \
0164   MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addr, addr, size, x, w, r, io)
0165
0166 #define MPC55XX_MMU_1K 0
0167 #define MPC55XX_MMU_2K 1
0168 #define MPC55XX_MMU_4K 2
0169 #define MPC55XX_MMU_8K 3
0170 #define MPC55XX_MMU_16K 4
0171 #define MPC55XX_MMU_32K 5
0172 #define MPC55XX_MMU_64K 6
0173 #define MPC55XX_MMU_128K 7
0174 #define MPC55XX_MMU_256K 8
0175 #define MPC55XX_MMU_512K 9
0176 #define MPC55XX_MMU_1M 10
0177 #define MPC55XX_MMU_2M 11
0178 #define MPC55XX_MMU_4M 12
0179 #define MPC55XX_MMU_8M 13
0180 #define MPC55XX_MMU_16M 14
0181 #define MPC55XX_MMU_32M 15
0182 #define MPC55XX_MMU_64M 16
0183 #define MPC55XX_MMU_128M 17
0184 #define MPC55XX_MMU_256M 18
0185 #define MPC55XX_MMU_512M 19
0186 #define MPC55XX_MMU_1G 20
0187 #define MPC55XX_MMU_2G 21
0188 #define MPC55XX_MMU_4G 22
0189
0190 #ifdef  __cplusplus
0191 }
0192 #endif /* __cplusplus */
0193
0194 #endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */