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0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsPowerPCMPC55XX
0005  */
0006 
0007 /*
0008  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0009  *
0010  * The license and distribution terms for this file may be
0011  * found in the file LICENSE in this distribution or at
0012  * http://www.rtems.org/license/LICENSE.
0013  */
0014 
0015 /*********************************************************************
0016  *
0017  * Copyright:
0018  *  Freescale Semiconductor, INC. All Rights Reserved.
0019  *  You are hereby granted a copyright license to use, modify, and
0020  *  distribute the SOFTWARE so long as this entire notice is
0021  *  retained without alteration in any modified and/or redistributed
0022  *  versions, and that such modified versions are clearly identified
0023  *  as such. No licenses are granted by implication, estoppel or
0024  *  otherwise under any patents or trademarks of Freescale
0025  *  Semiconductor, Inc. This software is provided on an "AS IS"
0026  *  basis and without warranty.
0027  *
0028  *  To the maximum extent permitted by applicable law, Freescale
0029  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
0030  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
0031  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
0032  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
0033  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
0034  *
0035  *  To the maximum extent permitted by applicable law, IN NO EVENT
0036  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
0037  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
0038  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
0039  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
0040  *
0041  *  Freescale Semiconductor assumes no responsibility for the
0042  *  maintenance and support of this software
0043  *
0044  ********************************************************************/
0045 
0046 #ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
0047 #define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
0048 
0049 #include <stdint.h>
0050 
0051 #include <bspopts.h>
0052 
0053 #ifdef  __cplusplus
0054 extern "C" {
0055 #endif
0056 
0057 /****************************************************************************/
0058 /*                          MODULE : eDMA                                   */
0059 /****************************************************************************/
0060     struct EDMA_tag {
0061         union EDMA_CR_tag {
0062             uint32_t R;
0063             struct {
0064 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
0065                 uint32_t:14;
0066                 uint32_t CX:1;
0067                 uint32_t ECX:1;
0068 #else
0069                 uint32_t:16;
0070 #endif
0071                 uint32_t GRP3PRI:2;
0072                 uint32_t GRP2PRI:2;
0073                 uint32_t GRP1PRI:2;
0074                 uint32_t GRP0PRI:2;
0075 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
0076                 uint32_t EMLM:1;
0077                 uint32_t CLM:1;
0078                 uint32_t HALT:1;
0079                 uint32_t HOE:1;
0080 #else
0081                   uint32_t:4;
0082 #endif
0083                 uint32_t ERGA:1;
0084                 uint32_t ERCA:1;
0085                 uint32_t EDBG:1;
0086                 uint32_t EBW:1;
0087             } B;
0088         } CR;                   /* Control Register */
0089 
0090         union {
0091             uint32_t R;
0092             struct {
0093                 uint32_t VLD:1;
0094 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
0095                 uint32_t:14;
0096                 uint32_t ECX:1;
0097 #else
0098                   uint32_t:15;
0099 #endif
0100                 uint32_t GPE:1;
0101                 uint32_t CPE:1;
0102                 uint32_t ERRCHN:6;
0103                 uint32_t SAE:1;
0104                 uint32_t SOE:1;
0105                 uint32_t DAE:1;
0106                 uint32_t DOE:1;
0107                 uint32_t NCE:1;
0108                 uint32_t SGE:1;
0109                 uint32_t SBE:1;
0110                 uint32_t DBE:1;
0111             } B;
0112         } ESR;                  /* Error Status Register */
0113 
0114         union {
0115             uint32_t R;
0116             struct {
0117                 uint32_t ERQ63:1;
0118                 uint32_t ERQ62:1;
0119                 uint32_t ERQ61:1;
0120                 uint32_t ERQ60:1;
0121                 uint32_t ERQ59:1;
0122                 uint32_t ERQ58:1;
0123                 uint32_t ERQ57:1;
0124                 uint32_t ERQ56:1;
0125                 uint32_t ERQ55:1;
0126                 uint32_t ERQ54:1;
0127                 uint32_t ERQ53:1;
0128                 uint32_t ERQ52:1;
0129                 uint32_t ERQ51:1;
0130                 uint32_t ERQ50:1;
0131                 uint32_t ERQ49:1;
0132                 uint32_t ERQ48:1;
0133                 uint32_t ERQ47:1;
0134                 uint32_t ERQ46:1;
0135                 uint32_t ERQ45:1;
0136                 uint32_t ERQ44:1;
0137                 uint32_t ERQ43:1;
0138                 uint32_t ERQ42:1;
0139                 uint32_t ERQ41:1;
0140                 uint32_t ERQ40:1;
0141                 uint32_t ERQ39:1;
0142                 uint32_t ERQ38:1;
0143                 uint32_t ERQ37:1;
0144                 uint32_t ERQ36:1;
0145                 uint32_t ERQ35:1;
0146                 uint32_t ERQ34:1;
0147                 uint32_t ERQ33:1;
0148                 uint32_t ERQ32:1;
0149             } B;
0150         } ERQRH;                /* DMA Enable Request Register High */
0151 
0152         union {
0153             uint32_t R;
0154             struct {
0155                 uint32_t ERQ31:1;
0156                 uint32_t ERQ30:1;
0157                 uint32_t ERQ29:1;
0158                 uint32_t ERQ28:1;
0159                 uint32_t ERQ27:1;
0160                 uint32_t ERQ26:1;
0161                 uint32_t ERQ25:1;
0162                 uint32_t ERQ24:1;
0163                 uint32_t ERQ23:1;
0164                 uint32_t ERQ22:1;
0165                 uint32_t ERQ21:1;
0166                 uint32_t ERQ20:1;
0167                 uint32_t ERQ19:1;
0168                 uint32_t ERQ18:1;
0169                 uint32_t ERQ17:1;
0170                 uint32_t ERQ16:1;
0171                 uint32_t ERQ15:1;
0172                 uint32_t ERQ14:1;
0173                 uint32_t ERQ13:1;
0174                 uint32_t ERQ12:1;
0175                 uint32_t ERQ11:1;
0176                 uint32_t ERQ10:1;
0177                 uint32_t ERQ09:1;
0178                 uint32_t ERQ08:1;
0179                 uint32_t ERQ07:1;
0180                 uint32_t ERQ06:1;
0181                 uint32_t ERQ05:1;
0182                 uint32_t ERQ04:1;
0183                 uint32_t ERQ03:1;
0184                 uint32_t ERQ02:1;
0185                 uint32_t ERQ01:1;
0186                 uint32_t ERQ00:1;
0187             } B;
0188         } ERQRL;                /* DMA Enable Request Register Low */
0189 
0190         union {
0191             uint32_t R;
0192             struct {
0193                 uint32_t EEI63:1;
0194                 uint32_t EEI62:1;
0195                 uint32_t EEI61:1;
0196                 uint32_t EEI60:1;
0197                 uint32_t EEI59:1;
0198                 uint32_t EEI58:1;
0199                 uint32_t EEI57:1;
0200                 uint32_t EEI56:1;
0201                 uint32_t EEI55:1;
0202                 uint32_t EEI54:1;
0203                 uint32_t EEI53:1;
0204                 uint32_t EEI52:1;
0205                 uint32_t EEI51:1;
0206                 uint32_t EEI50:1;
0207                 uint32_t EEI49:1;
0208                 uint32_t EEI48:1;
0209                 uint32_t EEI47:1;
0210                 uint32_t EEI46:1;
0211                 uint32_t EEI45:1;
0212                 uint32_t EEI44:1;
0213                 uint32_t EEI43:1;
0214                 uint32_t EEI42:1;
0215                 uint32_t EEI41:1;
0216                 uint32_t EEI40:1;
0217                 uint32_t EEI39:1;
0218                 uint32_t EEI38:1;
0219                 uint32_t EEI37:1;
0220                 uint32_t EEI36:1;
0221                 uint32_t EEI35:1;
0222                 uint32_t EEI34:1;
0223                 uint32_t EEI33:1;
0224                 uint32_t EEI32:1;
0225             } B;
0226         } EEIRH;                /* DMA Enable Error Interrupt Register High */
0227 
0228         union {
0229             uint32_t R;
0230             struct {
0231                 uint32_t EEI31:1;
0232                 uint32_t EEI30:1;
0233                 uint32_t EEI29:1;
0234                 uint32_t EEI28:1;
0235                 uint32_t EEI27:1;
0236                 uint32_t EEI26:1;
0237                 uint32_t EEI25:1;
0238                 uint32_t EEI24:1;
0239                 uint32_t EEI23:1;
0240                 uint32_t EEI22:1;
0241                 uint32_t EEI21:1;
0242                 uint32_t EEI20:1;
0243                 uint32_t EEI19:1;
0244                 uint32_t EEI18:1;
0245                 uint32_t EEI17:1;
0246                 uint32_t EEI16:1;
0247                 uint32_t EEI15:1;
0248                 uint32_t EEI14:1;
0249                 uint32_t EEI13:1;
0250                 uint32_t EEI12:1;
0251                 uint32_t EEI11:1;
0252                 uint32_t EEI10:1;
0253                 uint32_t EEI09:1;
0254                 uint32_t EEI08:1;
0255                 uint32_t EEI07:1;
0256                 uint32_t EEI06:1;
0257                 uint32_t EEI05:1;
0258                 uint32_t EEI04:1;
0259                 uint32_t EEI03:1;
0260                 uint32_t EEI02:1;
0261                 uint32_t EEI01:1;
0262                 uint32_t EEI00:1;
0263             } B;
0264         } EEIRL;                /* DMA Enable Error Interrupt Register Low */
0265 
0266         union {                /* DMA Set Enable Request Register */
0267             uint8_t R;
0268             struct {
0269                 uint8_t NOP:1;
0270                 uint8_t SERQ:7;
0271             } B;
0272         } SERQR;
0273 
0274         union {                /* DMA Clear Enable Request Register */
0275             uint8_t R;
0276             struct {
0277                 uint8_t NOP:1;
0278                 uint8_t CERQ:7;
0279             } B;
0280         } CERQR;
0281 
0282         union {                /* DMA Set Enable Error Interrupt Register */
0283             uint8_t R;
0284             struct {
0285                 uint8_t NOP:1;
0286                 uint8_t SEEI:7;
0287             } B;
0288         } SEEIR;
0289 
0290         union {                /* DMA Clear Enable Error Interrupt Register */
0291             uint8_t R;
0292             struct {
0293                 uint8_t NOP:1;
0294                 uint8_t CEEI:7;
0295             } B;
0296         } CEEIR;
0297 
0298         union {                /* DMA Clear Interrupt Request Register */
0299             uint8_t R;
0300             struct {
0301                 uint8_t NOP:1;
0302                 uint8_t CINT:7;
0303             } B;
0304         } CIRQR;
0305 
0306         union {                  /* DMA Clear error Register */
0307             uint8_t R;
0308             struct {
0309                 uint8_t NOP:1;
0310                 uint8_t CERR:7;
0311             } B;
0312         } CER;
0313 
0314         union {                 /* Set Start Bit Register */
0315             uint8_t R;
0316             struct {
0317                 uint8_t NOP:1;
0318                 uint8_t SSB:7;
0319             } B;
0320         } SSBR;
0321 
0322         union {                /* Clear Done Status Bit Register */
0323             uint8_t R;
0324             struct {
0325                 uint8_t NOP:1;
0326                 uint8_t CDSB:7;
0327             } B;
0328         } CDSBR;
0329 
0330         union {
0331             uint32_t R;
0332             struct {
0333                 uint32_t INT63:1;
0334                 uint32_t INT62:1;
0335                 uint32_t INT61:1;
0336                 uint32_t INT60:1;
0337                 uint32_t INT59:1;
0338                 uint32_t INT58:1;
0339                 uint32_t INT57:1;
0340                 uint32_t INT56:1;
0341                 uint32_t INT55:1;
0342                 uint32_t INT54:1;
0343                 uint32_t INT53:1;
0344                 uint32_t INT52:1;
0345                 uint32_t INT51:1;
0346                 uint32_t INT50:1;
0347                 uint32_t INT49:1;
0348                 uint32_t INT48:1;
0349                 uint32_t INT47:1;
0350                 uint32_t INT46:1;
0351                 uint32_t INT45:1;
0352                 uint32_t INT44:1;
0353                 uint32_t INT43:1;
0354                 uint32_t INT42:1;
0355                 uint32_t INT41:1;
0356                 uint32_t INT40:1;
0357                 uint32_t INT39:1;
0358                 uint32_t INT38:1;
0359                 uint32_t INT37:1;
0360                 uint32_t INT36:1;
0361                 uint32_t INT35:1;
0362                 uint32_t INT34:1;
0363                 uint32_t INT33:1;
0364                 uint32_t INT32:1;
0365             } B;
0366         } IRQRH;                /* DMA Interrupt Request High */
0367 
0368         union {
0369             uint32_t R;
0370             struct {
0371                 uint32_t INT31:1;
0372                 uint32_t INT30:1;
0373                 uint32_t INT29:1;
0374                 uint32_t INT28:1;
0375                 uint32_t INT27:1;
0376                 uint32_t INT26:1;
0377                 uint32_t INT25:1;
0378                 uint32_t INT24:1;
0379                 uint32_t INT23:1;
0380                 uint32_t INT22:1;
0381                 uint32_t INT21:1;
0382                 uint32_t INT20:1;
0383                 uint32_t INT19:1;
0384                 uint32_t INT18:1;
0385                 uint32_t INT17:1;
0386                 uint32_t INT16:1;
0387                 uint32_t INT15:1;
0388                 uint32_t INT14:1;
0389                 uint32_t INT13:1;
0390                 uint32_t INT12:1;
0391                 uint32_t INT11:1;
0392                 uint32_t INT10:1;
0393                 uint32_t INT09:1;
0394                 uint32_t INT08:1;
0395                 uint32_t INT07:1;
0396                 uint32_t INT06:1;
0397                 uint32_t INT05:1;
0398                 uint32_t INT04:1;
0399                 uint32_t INT03:1;
0400                 uint32_t INT02:1;
0401                 uint32_t INT01:1;
0402                 uint32_t INT00:1;
0403             } B;
0404         } IRQRL;                /* DMA Interrupt Request Low */
0405 
0406         union {
0407             uint32_t R;
0408             struct {
0409                 uint32_t ERR63:1;
0410                 uint32_t ERR62:1;
0411                 uint32_t ERR61:1;
0412                 uint32_t ERR60:1;
0413                 uint32_t ERR59:1;
0414                 uint32_t ERR58:1;
0415                 uint32_t ERR57:1;
0416                 uint32_t ERR56:1;
0417                 uint32_t ERR55:1;
0418                 uint32_t ERR54:1;
0419                 uint32_t ERR53:1;
0420                 uint32_t ERR52:1;
0421                 uint32_t ERR51:1;
0422                 uint32_t ERR50:1;
0423                 uint32_t ERR49:1;
0424                 uint32_t ERR48:1;
0425                 uint32_t ERR47:1;
0426                 uint32_t ERR46:1;
0427                 uint32_t ERR45:1;
0428                 uint32_t ERR44:1;
0429                 uint32_t ERR43:1;
0430                 uint32_t ERR42:1;
0431                 uint32_t ERR41:1;
0432                 uint32_t ERR40:1;
0433                 uint32_t ERR39:1;
0434                 uint32_t ERR38:1;
0435                 uint32_t ERR37:1;
0436                 uint32_t ERR36:1;
0437                 uint32_t ERR35:1;
0438                 uint32_t ERR34:1;
0439                 uint32_t ERR33:1;
0440                 uint32_t ERR32:1;
0441             } B;
0442         } ERH;                  /* DMA Error High */
0443 
0444         union {
0445             uint32_t R;
0446             struct {
0447                 uint32_t ERR31:1;
0448                 uint32_t ERR30:1;
0449                 uint32_t ERR29:1;
0450                 uint32_t ERR28:1;
0451                 uint32_t ERR27:1;
0452                 uint32_t ERR26:1;
0453                 uint32_t ERR25:1;
0454                 uint32_t ERR24:1;
0455                 uint32_t ERR23:1;
0456                 uint32_t ERR22:1;
0457                 uint32_t ERR21:1;
0458                 uint32_t ERR20:1;
0459                 uint32_t ERR19:1;
0460                 uint32_t ERR18:1;
0461                 uint32_t ERR17:1;
0462                 uint32_t ERR16:1;
0463                 uint32_t ERR15:1;
0464                 uint32_t ERR14:1;
0465                 uint32_t ERR13:1;
0466                 uint32_t ERR12:1;
0467                 uint32_t ERR11:1;
0468                 uint32_t ERR10:1;
0469                 uint32_t ERR09:1;
0470                 uint32_t ERR08:1;
0471                 uint32_t ERR07:1;
0472                 uint32_t ERR06:1;
0473                 uint32_t ERR05:1;
0474                 uint32_t ERR04:1;
0475                 uint32_t ERR03:1;
0476                 uint32_t ERR02:1;
0477                 uint32_t ERR01:1;
0478                 uint32_t ERR00:1;
0479             } B;
0480         } ERL;                  /* DMA Error Low */
0481 
0482 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
0483         union {                  /* hardware request status high */
0484             uint32_t R;
0485             struct {
0486                 uint32_t HRS63:1;
0487                 uint32_t HRS62:1;
0488                 uint32_t HRS61:1;
0489                 uint32_t HRS60:1;
0490                 uint32_t HRS59:1;
0491                 uint32_t HRS58:1;
0492                 uint32_t HRS57:1;
0493                 uint32_t HRS56:1;
0494                 uint32_t HRS55:1;
0495                 uint32_t HRS54:1;
0496                 uint32_t HRS53:1;
0497                 uint32_t HRS52:1;
0498                 uint32_t HRS51:1;
0499                 uint32_t HRS50:1;
0500                 uint32_t HRS49:1;
0501                 uint32_t HRS48:1;
0502                 uint32_t HRS47:1;
0503                 uint32_t HRS46:1;
0504                 uint32_t HRS45:1;
0505                 uint32_t HRS44:1;
0506                 uint32_t HRS43:1;
0507                 uint32_t HRS42:1;
0508                 uint32_t HRS41:1;
0509                 uint32_t HRS40:1;
0510                 uint32_t HRS39:1;
0511                 uint32_t HRS38:1;
0512                 uint32_t HRS37:1;
0513                 uint32_t HRS36:1;
0514                 uint32_t HRS35:1;
0515                 uint32_t HRS34:1;
0516                 uint32_t HRS33:1;
0517                 uint32_t HRS32:1;
0518             } B;
0519         } HRSH;
0520 
0521         union {                  /* hardware request status low */
0522             uint32_t R;
0523             struct {
0524                 uint32_t HRS31:1;
0525                 uint32_t HRS30:1;
0526                 uint32_t HRS29:1;
0527                 uint32_t HRS28:1;
0528                 uint32_t HRS27:1;
0529                 uint32_t HRS26:1;
0530                 uint32_t HRS25:1;
0531                 uint32_t HRS24:1;
0532                 uint32_t HRS23:1;
0533                 uint32_t HRS22:1;
0534                 uint32_t HRS21:1;
0535                 uint32_t HRS20:1;
0536                 uint32_t HRS19:1;
0537                 uint32_t HRS18:1;
0538                 uint32_t HRS17:1;
0539                 uint32_t HRS16:1;
0540                 uint32_t HRS15:1;
0541                 uint32_t HRS14:1;
0542                 uint32_t HRS13:1;
0543                 uint32_t HRS12:1;
0544                 uint32_t HRS11:1;
0545                 uint32_t HRS10:1;
0546                 uint32_t HRS09:1;
0547                 uint32_t HRS08:1;
0548                 uint32_t HRS07:1;
0549                 uint32_t HRS06:1;
0550                 uint32_t HRS05:1;
0551                 uint32_t HRS04:1;
0552                 uint32_t HRS03:1;
0553                 uint32_t HRS02:1;
0554                 uint32_t HRS01:1;
0555                 uint32_t HRS00:1;
0556             } B;
0557         } HRSL;
0558 
0559         uint32_t eDMA_reserved0038[50];  /* 0x0038-0x00FF */
0560 #else
0561         uint32_t edma_reserved1[52];
0562 #endif
0563 
0564         union {
0565             uint8_t R;
0566             struct {
0567                 uint8_t ECP:1;
0568 #if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567
0569                 uint8_t DPA:1;
0570 #else
0571                   uint8_t:1;
0572 #endif
0573                 uint8_t GRPPRI:2;
0574                 uint8_t CHPRI:4;
0575             } B;
0576         } CPR[64];
0577 
0578         uint32_t edma_reserved2[944];
0579 
0580 /****************************************************************************/
0581 /*       DMA2 Transfer Control Descriptor                                   */
0582 /****************************************************************************/
0583         struct tcd_t {
0584             uint32_t SADDR;    /* source address */
0585 
0586             /* Source and destination fields */
0587             union tcd_SDF_tag {
0588                 uint32_t R;
0589                 struct {
0590                     uint16_t SMOD:5;   /* source address modulo */
0591                     uint16_t SSIZE:3;  /* source transfer size */
0592                     uint16_t DMOD:5;   /* destination address modulo */
0593                     uint16_t DSIZE:3;  /* destination transfer size */
0594                     int16_t SOFF;      /* signed source address offset */
0595                 } B;
0596             } SDF;
0597 
0598             uint32_t NBYTES;   /* inner (“minor”) byte count */
0599 
0600             int32_t SLAST;     /* last destination address adjustment, or
0601                                    scatter/gather address (if e_sg = 1) */
0602 
0603             uint32_t DADDR;    /* destination address */
0604 
0605             /* CITER and destination fields */
0606             union tcd_CDF_tag {
0607                 uint32_t R;
0608                 struct {
0609                     uint16_t CITERE_LINK:1;
0610                     uint16_t CITER:15;
0611                     int16_t DOFF;      /* signed destination address offset */
0612                 } B;
0613                 struct {
0614             uint16_t CITERE_LINK:1;
0615             uint16_t CITERLINKCH:6;
0616             uint16_t CITER:9;
0617                     int16_t DOFF;
0618                 } B_ALT;
0619                 struct {
0620                     uint16_t CITER;
0621                     int16_t DOFF;
0622                 } B_NOLINK;
0623             } CDF;
0624 
0625             int32_t DLAST_SGA;
0626 
0627             /* BITER and misc fields */
0628             union tcd_BMF_tag {
0629                 uint32_t R;
0630                 struct {
0631                     uint32_t BITERE_LINK:1;    /* beginning ("major") iteration count */
0632                     uint32_t BITER:15;
0633                     uint32_t BWC:2;    /* bandwidth control */
0634                     uint32_t MAJORLINKCH:6;    /* enable channel-to-channel link */
0635                     uint32_t DONE:1;   /* channel done */
0636                     uint32_t ACTIVE:1; /* channel active */
0637                     uint32_t MAJORE_LINK:1;    /* enable channel-to-channel link */
0638                     uint32_t E_SG:1;   /* enable scatter/gather descriptor */
0639                     uint32_t D_REQ:1;  /* disable ipd_req when done */
0640                     uint32_t INT_HALF:1;       /* interrupt on citer = (biter >> 1) */
0641                     uint32_t INT_MAJ:1;        /* interrupt on major loop completion */
0642                     uint32_t START:1;  /* explicit channel start */
0643                 } B;
0644                 struct {
0645                     uint32_t BITERE_LINK:1;
0646                     uint32_t BITERLINKCH:6;
0647                     uint32_t BITER:9;
0648                     uint32_t BWC:2;
0649                     uint32_t MAJORLINKCH:6;
0650                     uint32_t DONE:1;
0651                     uint32_t ACTIVE:1;
0652                     uint32_t MAJORE_LINK:1;
0653                     uint32_t E_SG:1;
0654                     uint32_t D_REQ:1;
0655                     uint32_t INT_HALF:1;
0656                     uint32_t INT_MAJ:1;
0657                     uint32_t START:1;
0658                 } B_ALT;
0659                 struct {
0660                     uint16_t BITER;
0661                     uint16_t BWC:2;
0662                     uint16_t MAJORLINKCH:6;
0663                     uint16_t DONE:1;
0664                     uint16_t ACTIVE:1;
0665                     uint16_t MAJORE_LINK:1;
0666                     uint16_t E_SG:1;
0667                     uint16_t D_REQ:1;
0668                     uint16_t INT_HALF:1;
0669                     uint16_t INT_MAJ:1;
0670                     uint16_t START:1;
0671                 } B_NOLINK;
0672             } BMF;
0673         } TCD[64];              /* transfer_control_descriptor */
0674     };
0675 
0676 #ifndef  __cplusplus
0677     static const struct tcd_t EDMA_TCD_DEFAULT = {
0678         .SADDR = 0,
0679         .SDF = { .R = 0 },
0680         .NBYTES = 0,
0681         .SLAST = 0,
0682         .DADDR = 0,
0683         .CDF = { .R = 0 },
0684         .DLAST_SGA = 0,
0685         .BMF = { .R = 0 }
0686     };
0687 #endif /* __cplusplus */
0688 
0689 #define EDMA_TCD_BITER_MASK 0x7fff
0690 
0691 #define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1)
0692 
0693 #define EDMA_TCD_BITER_LINKED_MASK 0x1ff
0694 
0695 #define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1)
0696 
0697 #define EDMA_TCD_LINK_AND_BITER(link, biter) \
0698   (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK))
0699 
0700 #ifdef  __cplusplus
0701 }
0702 #endif /* __cplusplus */
0703 
0704 #endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */
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