include/mpc55xx/reg-defs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief Register definitions.
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2014 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
0037 #define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
0038
0039 #include <bspopts.h>
0040
0041 #if MPC55XX_CHIP_FAMILY == 551
0042   #define FLASH_BIUCR   0xFFFF801C
0043 #else
0044   #define FLASH_BIUCR 0xC3F8801C
0045 #endif
0046
0047 /*
0048  * Definitions for FLASH_BIUCR (Flash BIU Control Register)
0049  */
0050
0051 /* Fields for Flash Bus Interface Control */
0052 /* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */
0053
0054 /* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */
0055 #define FLASH_BUICR_EBI_PREFTCH 0x00080000
0056
0057 /* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */
0058 #define FLASH_BUICR_EDMA_PREFTCH 0x00040000
0059
0060 /* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */
0061 #define FLASH_BUICR_NEX_PREFTCH 0x00020000
0062
0063 /* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */
0064 #define FLASH_BUICR_CPU_PREFTCH 0x00010000
0065
0066 /* Fields for APC (access pipelining control bits [16:18]) */
0067 #define FLASH_BUICR_APC_0 0x00000000
0068 #define FLASH_BUICR_APC_1 0x00002000
0069 #define FLASH_BUICR_APC_2 0x00004000
0070 #define FLASH_BUICR_APC_3 0x00006000
0071 #define FLASH_BUICR_APC_4 0x00008000
0072 #define FLASH_BUICR_APC_5 0x0000A000
0073 #define FLASH_BUICR_APC_6 0x0000C000
0074 #define FLASH_BUICR_APC_NO 0x0000E000
0075
0076 /* Fields for WWSC (write wait state control bits [19:20]) */
0077 #define FLASH_BUICR_WWSC_1 0x00000800
0078 #define FLASH_BUICR_WWSC_2 0x00001000
0079 #define FLASH_BUICR_WWSC_3 0x00001800
0080
0081 /* Fields for RWSC (read wait state control bits [21:23]) */
0082 #define FLASH_BUICR_RWSC_0 0x00000000
0083 #define FLASH_BUICR_RWSC_1 0x00000100
0084 #define FLASH_BUICR_RWSC_2 0x00000200
0085 #define FLASH_BUICR_RWSC_3 0x00000300
0086 #define FLASH_BUICR_RWSC_4 0x00000400
0087 #define FLASH_BUICR_RWSC_5 0x00000500
0088 #define FLASH_BUICR_RWSC_6 0x00000600
0089 #define FLASH_BUICR_RWSC_7 0x00000700
0090
0091 /* Fields for DPFEN (data prefetch enable bits [24:25]) */
0092 #define FLASH_BUICR_DPFEN_0 0x00000000
0093 #define FLASH_BUICR_DPFEN_1 0x00000040
0094 #define FLASH_BUICR_DPFEN_3 0x000000C0
0095
0096 /* Fields for IPFEN (instruction prefetch enable bits [26:27]) */
0097 #define FLASH_BUICR_IPFEN_0 0x00000000
0098 #define FLASH_BUICR_IPFEN_1 0x00000010
0099 #define FLASH_BUICR_IPFEN_3 0x00000030
0100
0101 /* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */
0102 #define FLASH_BUICR_PFLIM_0 0x00000000
0103 #define FLASH_BUICR_PFLIM_1 0x00000002
0104 #define FLASH_BUICR_PFLIM_2 0x00000004
0105 #define FLASH_BUICR_PFLIM_3 0x00000006
0106 #define FLASH_BUICR_PFLIM_4 0x00000008
0107 #define FLASH_BUICR_PFLIM_5 0x0000000A
0108 #define FLASH_BUICR_PFLIM_6 0x0000000C
0109
0110 /* Fields for BFEN (enable line read buffer hits bit [31]) */
0111 #define FLASH_BUICR_BFEN 0x00000001
0112
0113 #endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */