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File indexing completed on 2025-05-11 08:23:56 

0001 /*
0002  * Modifications of the original file provided by Freescale are:
0003  *
0004  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0016  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0017  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0018  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0019  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0020  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0021  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0022  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0023  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0024  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0025  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0026  */
0027 
0028 /**************************************************************************/
0029 /* FILE NAME: mpc5674f.h                     COPYRIGHT (c) Freescale 2009 */
0030 /* VERSION:  1.04                                 All Rights Reserved     */
0031 /*                                                                        */
0032 /* DESCRIPTION:                                                           */
0033 /* This file contains all of the register and bit field definitions for   */
0034 /* MPC5674F.                                                              */
0035 /*========================================================================*/
0036 /* UPDATE HISTORY                                                         */
0037 /* REV      AUTHOR      DATE       DESCRIPTION OF CHANGE                  */
0038 /* ---   -----------  ---------    ---------------------                  */
0039 /* NOTE: Branch pulled at version 0.87 for mpc5674_c.h version 1.00       */
0040 /* 1.00  B. Terry                  Corrected DECFILT addresses and added  */
0041 /*                                 4 additional filters for Rev. 2        */
0042 /* 1.01  B. Terry     16/Nov/09    Corrected bit definitions in SIUDIV    */
0043 /*                                 register.                              */
0044 /* 1.02  B. Terry     19/Nov/09    Added ISEL8, ISEL9, ISEL10, and ISEL11 */
0045 /*                                 regs to SIU tag. (Mamba 2 features)    */
0046 /* 1.03  B. Terry     19/Nov/09    Renamed ISEL10 and ISEL11 to DECFIL1   */
0047 /*                                 and DECFIL2 to match RM.               */
0048 /* 1.04  B. Terry     22/Jan/10    Updated bitfields of MPU RGDx Word2    */
0049 /*                                 register to reflect Mamba 2. Added     */
0050 /*                                 MXCR and MXSR registers to DecFilt.    */
0051 /*                                 Removed pre-release rev history.       */
0052 /**************************************************************************/
0053 
0054 #ifndef _MPC5674F_H_
0055 #define _MPC5674F_H_
0056 
0057 #ifndef ASM
0058 
0059 #include <stdint.h>
0060 
0061 #include <mpc55xx/regs-edma.h>
0062 
0063 #ifdef  __cplusplus
0064 extern "C" {
0065 #endif
0066 
0067 #ifdef __MWERKS__
0068 #pragma push
0069 #pragma ANSI_strict off
0070 #endif
0071 
0072 /****************************************************************************/
0073 /*                          MODULE : PBRIDGE_A Peripheral Bridge            */
0074 /****************************************************************************/
0075 
0076     struct PBRIDGE_A_tag {
0077 
0078         union {                 /* Master Privilege Control Register 0*/
0079             uint32_t R;
0080             struct {
0081                 uint32_t MBW0:1;      /* z7 Core */
0082                 uint32_t MTR0:1;
0083                 uint32_t MTW0:1;
0084                 uint32_t MPL0:1;
0085                 uint32_t MBW1:1;      /* Nexus */
0086                 uint32_t MTR1:1;
0087                 uint32_t MTW1:1;
0088                 uint32_t MPL1:1;
0089                 uint32_t MBW2:1;      /* Reserved */
0090                 uint32_t MTR2:1;
0091                 uint32_t MTW2:1;
0092                 uint32_t MPL2:1;
0093                 uint32_t MBW3:1;      /* Reserved */
0094                 uint32_t MTR3:1;
0095                 uint32_t MTW3:1;
0096                 uint32_t MPL3:1;
0097                 uint32_t MBW4:1;       /* eDMA A */
0098                 uint32_t MTR4:1;
0099                 uint32_t MTW4:1;
0100                 uint32_t MPL4:1;
0101                 uint32_t MBW5:1;       /* eDMA B */
0102                 uint32_t MTR5:1;
0103                 uint32_t MTW5:1;
0104                 uint32_t MPL5:1;
0105                 uint32_t MBW6:1;       /* FLEXRAY */
0106                 uint32_t MTR6:1;
0107                 uint32_t MTW6:1;
0108                 uint32_t MPL6:1;
0109                 uint32_t MBW7:1;       /* EBI */
0110                 uint32_t MTR7:1;
0111                 uint32_t MTW7:1;
0112                 uint32_t MPL7:1;
0113             } B;
0114         } MPCR;
0115 
0116         union {                 /* Master Privilege Control Register 1 */
0117             uint32_t R;
0118             struct {
0119                 uint32_t:32;      /* reserved */
0120             } B;
0121         } MPCR1;
0122 
0123         uint32_t PBRIDGE_A_reserved0008[6];  /* 0x0008-0x001F */
0124 
0125         union {                 /* Peripheral Access Control Register 0 */
0126             uint32_t R;
0127             struct {
0128                 uint32_t BW0:1;  /* PBRIDGE_A */
0129                 uint32_t SP0:1;
0130                 uint32_t WP0:1;
0131                 uint32_t TP0:1;
0132                 uint32_t:4;      /* Reserved */
0133                 uint32_t:4;      /* Reserved */
0134                 uint32_t:4;      /* Reserved */
0135                 uint32_t:4;      /* Reserved */
0136                 uint32_t:4;      /* Reserved */
0137                 uint32_t:4;      /* Reserved */
0138                 uint32_t:4;      /* Reserved */
0139             } B;
0140         } PACR0;
0141 
0142         uint32_t PBRIDGE_A_reserved0024[7];  /* 0x0024-0x003F */
0143 
0144         union {                 /* Off-Platform Peripheral Access Control Register 0 */
0145             uint32_t R;
0146             struct {
0147                 uint32_t BW0:1;  /* FMPLL */
0148                 uint32_t SP0:1;
0149                 uint32_t WP0:1;
0150                 uint32_t TP0:1;
0151                 uint32_t BW1:1;  /* EBI control */
0152                 uint32_t SP1:1;
0153                 uint32_t WP1:1;
0154                 uint32_t TP1:1;
0155                 uint32_t BW2:1;  /* Flash A control */
0156                 uint32_t SP2:1;
0157                 uint32_t WP2:1;
0158                 uint32_t TP2:1;
0159                 uint32_t BW3:1;  /* Flash B control */
0160                 uint32_t SP3:1;
0161                 uint32_t WP3:1;
0162                 uint32_t TP3:1;
0163                 uint32_t BW4:1;  /* SIU */
0164                 uint32_t SP4:1;
0165                 uint32_t WP4:1;
0166                 uint32_t TP4:1;
0167                 uint32_t:4;      /* Reserved */
0168                 uint32_t:4;      /* Reserved */
0169                 uint32_t:4;      /* Reserved */
0170             } B;
0171         } OPACR0;
0172 
0173         union {                 /* Off-Platform Peripheral Access Control Register 1 */
0174             uint32_t R;
0175             struct {
0176                 uint32_t BW0:1;  /* EMIOS */
0177                 uint32_t SP0:1;
0178                 uint32_t WP0:1;
0179                 uint32_t TP0:1;
0180                 uint32_t:4;      /* Reserved */
0181                 uint32_t:4;      /* Reserved */
0182                 uint32_t:4;      /* Reserved */
0183                 uint32_t:4;      /* Reserved */
0184                 uint32_t:4;      /* Reserved */
0185                 uint32_t:4;      /* Reserved */
0186                 uint32_t BW7:1;  /* PMC */
0187                 uint32_t SP7:1;
0188                 uint32_t WP7:1;
0189                 uint32_t TP7:1;
0190             } B;
0191         } OPACR1;
0192 
0193         union {                 /* Off-Platform Peripheral Access Control Register 2 */
0194             uint32_t R;
0195             struct {
0196                 uint32_t BW0:1;  /* eTPU */
0197                 uint32_t SP0:1;
0198                 uint32_t WP0:1;
0199                 uint32_t TP0:1;
0200                 uint32_t:4;      /* Reserved */
0201                 uint32_t BW2:1;  /* eTPU PRAM */
0202                 uint32_t SP2:1;
0203                 uint32_t WP2:1;
0204                 uint32_t TP2:1;
0205                 uint32_t BW3:1;  /* eTPU PRAM mirror */
0206                 uint32_t SP3:1;
0207                 uint32_t WP3:1;
0208                 uint32_t TP3:1;
0209                 uint32_t BW4:1;  /* eTPU SCM */
0210                 uint32_t SP4:1;
0211                 uint32_t WP4:1;
0212                 uint32_t TP4:1;
0213                 uint32_t BW5:1;  /* eTPU SCM */
0214                 uint32_t SP5:1;
0215                 uint32_t WP5:1;
0216                 uint32_t TP5:1;
0217                 uint32_t:4;      /* Reserved */
0218                 uint32_t:4;      /* Reserved */
0219             } B;
0220         } OPACR2;
0221 
0222         union {                 /* Off-Platform Peripheral Access Control Register 3 */
0223             uint32_t R;
0224             struct {
0225                 uint32_t:4;      /* Reserved */
0226                 uint32_t:4;      /* Reserved */
0227                 uint32_t:4;      /* Reserved */
0228                 uint32_t:4;      /* Reserved */
0229                 uint32_t BW4:1;  /* PIT/RTI  */
0230                 uint32_t SP4:1;
0231                 uint32_t WP4:1;
0232                 uint32_t TP4:1;
0233                 uint32_t:4;      /* Reserved */
0234                 uint32_t:4;      /* Reserved */
0235                 uint32_t:4;      /* Reserved */
0236             } B;
0237         } OPACR3;
0238 
0239         uint32_t PBRIDGE_A_reserved0050[4076];  /* 0x0050-0x3FFF */
0240 
0241     };
0242 
0243 /****************************************************************************/
0244 /*                          MODULE : PBRIDGE_B Peripheral Bridge            */
0245 /****************************************************************************/
0246 
0247     struct PBRIDGE_B_tag {
0248 
0249         union {                 /* Master Privilege Control Register 0 */
0250             uint32_t R;
0251             struct {
0252                 uint32_t MBW0:1;      /* z7 Core */
0253                 uint32_t MTR0:1;
0254                 uint32_t MTW0:1;
0255                 uint32_t MPL0:1;
0256                 uint32_t MBW1:1;      /* Nexus */
0257                 uint32_t MTR1:1;
0258                 uint32_t MTW1:1;
0259                 uint32_t MPL1:1;
0260                 uint32_t MBW2:1;      /* Reserved */
0261                 uint32_t MTR2:1;
0262                 uint32_t MTW2:1;
0263                 uint32_t MPL2:1;
0264                 uint32_t MBW3:1;      /* Reserved */
0265                 uint32_t MTR3:1;
0266                 uint32_t MTW3:1;
0267                 uint32_t MPL3:1;
0268                 uint32_t MBW4:1;      /* eDMA A */
0269                 uint32_t MTR4:1;
0270                 uint32_t MTW4:1;
0271                 uint32_t MPL4:1;
0272                 uint32_t MBW5:1;      /* eDMA B */
0273                 uint32_t MTR5:1;
0274                 uint32_t MTW5:1;
0275                 uint32_t MPL5:1;
0276                 uint32_t MBW6:1;      /* FLEXRAY */
0277                 uint32_t MTR6:1;
0278                 uint32_t MTW6:1;
0279                 uint32_t MPL6:1;
0280                 uint32_t MBW7:1;      /* EBI */
0281                 uint32_t MTR7:1;
0282                 uint32_t MTW7:1;
0283                 uint32_t MPL7:1;
0284             } B;
0285         } MPCR;
0286 
0287         union {                 /* Master Privilege Control Register 1 */
0288             uint32_t R;
0289             struct {
0290                uint32_t:32;     /* Reserved */
0291 
0292             } B;
0293         } MPCR1;
0294 
0295         uint32_t PBRIDGE_B_reserved0008[6];  /* 0x0008-0x001F */
0296 
0297         union {                 /* Peripheral Access Control Register 0 */
0298             uint32_t R;
0299             struct {
0300                 uint32_t BW0:1;  /* PBRIDGE B */
0301                 uint32_t SP0:1;
0302                 uint32_t WP0:1;
0303                 uint32_t TP0:1;
0304                 uint32_t BW1:1;  /* XBAR  */
0305                 uint32_t SP1:1;
0306                 uint32_t WP1:1;
0307                 uint32_t TP1:1;
0308                 uint32_t:4;      /* Reserved */
0309                 uint32_t:4;      /* Reserved */
0310                 uint32_t BW4:1;  /* MPU */
0311                 uint32_t SP4:1;
0312                 uint32_t WP4:1;
0313                 uint32_t TP4:1;
0314                 uint32_t:4;      /* Reserved */
0315                 uint32_t:4;      /* Reserved */
0316                 uint32_t:4;      /* Reserved */
0317             } B;
0318         } PACR0;
0319 
0320         union {                 /* Peripheral Access Control Register 1 */
0321             uint32_t R;
0322             struct {
0323                 uint32_t:4;      /* Reserved */
0324                 uint32_t:4;      /* Reserved */
0325                 uint32_t:4;      /* Reserved */
0326                 uint32_t:4;      /* Reserved */
0327                 uint32_t:4;      /* Reserved */
0328                 uint32_t:4;      /* Reserved */
0329                 uint32_t BW6:1;  /* SWT */
0330                 uint32_t SP6:1;
0331                 uint32_t WP6:1;
0332                 uint32_t TP6:1;
0333                 uint32_t BW7:1;  /* STM */
0334                 uint32_t SP7:1;
0335                 uint32_t WP7:1;
0336                 uint32_t TP7:1;
0337             } B;
0338         } PACR1;
0339 
0340         union {                 /* Peripheral Access Control Register 2 */
0341             uint32_t R;
0342             struct {
0343                 uint32_t BW0:1;  /* ECSM */
0344                 uint32_t SP0:1;
0345                 uint32_t WP0:1;
0346                 uint32_t TP0:1;
0347                 uint32_t BW1:1;  /* eDMA A */
0348                 uint32_t SP1:1;
0349                 uint32_t WP1:1;
0350                 uint32_t TP1:1;
0351                 uint32_t BW2:1;  /* INTC */
0352                 uint32_t SP2:1;
0353                 uint32_t WP2:1;
0354                 uint32_t TP2:1;
0355                 uint32_t:4;      /* Reserved */
0356                 uint32_t:4;      /* Reserved */
0357                 uint32_t BW5:1;  /* eDMA B */
0358                 uint32_t SP5:1;
0359                 uint32_t WP5:1;
0360                 uint32_t TP5:1;
0361                 uint32_t:4;      /* Reserved */
0362                 uint32_t:4;      /* Reserved */
0363             } B;
0364         } PACR2;
0365 
0366         uint32_t PBRIDGE_B_reserved002C[5];  /* 0x002C-0x003F */
0367 
0368         union {                 /* Off-Platform Peripheral Access Control Register 0 */
0369             uint32_t R;
0370             struct {
0371                 uint32_t BW0:1;  /* eQADC A */
0372                 uint32_t SP0:1;
0373                 uint32_t WP0:1;
0374                 uint32_t TP0:1;
0375                 uint32_t BW1:1;  /* eQADC B */
0376                 uint32_t SP1:1;
0377                 uint32_t WP1:1;
0378                 uint32_t TP1:1;
0379                 uint32_t BW2:1;  /* Decimation Filters A, B, C, D */
0380                 uint32_t SP2:1;
0381                 uint32_t WP2:1;
0382                 uint32_t TP2:1;
0383                 uint32_t:4;      /* Reserved */
0384                 uint32_t BW4:1;  /* DSPI_A */
0385                 uint32_t SP4:1;
0386                 uint32_t WP4:1;
0387                 uint32_t TP4:1;
0388                 uint32_t BW5:1;  /* DSPI_B */
0389                 uint32_t SP5:1;
0390                 uint32_t WP5:1;
0391                 uint32_t TP5:1;
0392                 uint32_t BW6:1;  /* DSPI_C */
0393                 uint32_t SP6:1;
0394                 uint32_t WP6:1;
0395                 uint32_t TP6:1;
0396                 uint32_t BW7:1;  /* DSPI_D */
0397                 uint32_t SP7:1;
0398                 uint32_t WP7:1;
0399                 uint32_t TP7:1;
0400             } B;
0401         } OPACR0;
0402 
0403         union {                 /* Off-Platform Peripheral Access Control Register 1 */
0404             uint32_t R;
0405             struct {
0406                 uint32_t:4;      /* Reserved */
0407                 uint32_t:4;      /* Reserved */
0408                 uint32_t:4;      /* Reserved */
0409                 uint32_t:4;      /* Reserved */
0410                 uint32_t BW4:1;  /* ESCI_A */
0411                 uint32_t SP4:1;
0412                 uint32_t WP4:1;
0413                 uint32_t TP4:1;
0414                 uint32_t BW5:1;  /* ESCI_B */
0415                 uint32_t SP5:1;
0416                 uint32_t WP5:1;
0417                 uint32_t TP5:1;
0418                 uint32_t BW6:1;  /* ESCI_C */
0419                 uint32_t SP6:1;
0420                 uint32_t WP6:1;
0421                 uint32_t TP6:1;
0422                 uint32_t:4;      /* Reserved */
0423             } B;
0424         } OPACR1;
0425 
0426         union {                 /* Off-Platform Peripheral Access Control Register 2 */
0427             uint32_t R;
0428             struct {
0429                 uint32_t BW0:1;  /* FlexCAN_A */
0430                 uint32_t SP0:1;
0431                 uint32_t WP0:1;
0432                 uint32_t TP0:1;
0433                 uint32_t BW1:1;  /* FlexCAN_B */
0434                 uint32_t SP1:1;
0435                 uint32_t WP1:1;
0436                 uint32_t TP1:1;
0437                 uint32_t BW2:1;  /* FlexCAN_C */
0438                 uint32_t SP2:1;
0439                 uint32_t WP2:1;
0440                 uint32_t TP2:1;
0441                 uint32_t BW3:1;  /* FlexCAN_D */
0442                 uint32_t SP3:1;
0443                 uint32_t WP3:1;
0444                 uint32_t TP3:1;
0445                 uint32_t:4;      /* Reserved */
0446                 uint32_t:4;      /* Reserved */
0447                 uint32_t:4;      /* Reserved */
0448                 uint32_t:4;      /* Reserved */
0449             } B;
0450         } OPACR2;
0451 
0452         union {                 /* Off-Platform Peripheral Access Control Register 3 */
0453             uint32_t R;
0454             struct {
0455                 uint32_t BW0:1;  /* FlexRAY */
0456                 uint32_t SP0:1;
0457                 uint32_t WP0:1;
0458                 uint32_t TP0:1;
0459                 uint32_t:4;      /* Reserved */
0460                 uint32_t:4;      /* Reserved */
0461                 uint32_t BW3:1;  /* Temp Sensor */
0462                 uint32_t SP3:1;
0463                 uint32_t WP3:1;
0464                 uint32_t TP3:1;
0465                 uint32_t:4;      /* Reserved */
0466                 uint32_t:4;      /* Reserved */
0467                 uint32_t:4;      /* Reserved */
0468                 uint32_t BW7:1;  /* BAM */
0469                 uint32_t SP7:1;
0470                 uint32_t WP7:1;
0471                 uint32_t TP7:1;
0472             } B;
0473         } OPACR3;
0474 
0475         uint32_t PBRIDGE_B_reserved0050[4076];  /* 0x0050-0x3FFF */
0476 
0477     };
0478 
0479 /****************************************************************************/
0480 /*                     MODULE : FMPLL                                       */
0481 /****************************************************************************/
0482 
0483     struct FMPLL_tag {
0484 
0485         uint32_t FMPLL_reserved0000;  /* 0x0000-0x0003 */
0486 
0487         union FMPLL_SYNSR_tag { /* FMPLL Synthesizer Status Register */
0488             uint32_t R;
0489             struct {
0490                 uint32_t:22;
0491                 uint32_t LOLF:1;
0492                 uint32_t LOC:1;
0493                 uint32_t MODE:1;
0494                 uint32_t PLLSEL:1;
0495                 uint32_t PLLREF:1;
0496                 uint32_t LOCKS:1;
0497                 uint32_t LOCK:1;
0498                 uint32_t LOCF:1;
0499                 uint32_t CALDONE:1;
0500                 uint32_t CALPASS:1;
0501             } B;
0502         } SYNSR;
0503 
0504         union FMPLL_ESYNCR1_tag {/* FMPLL Enhanced Synthesizer Control Register 1 */
0505             uint32_t R;
0506             struct {
0507                 uint32_t:1;
0508                 uint32_t CLKCFG:3;
0509                 uint32_t:8;
0510                 uint32_t EPREDIV:4;
0511                 uint32_t :8;
0512                 uint32_t EMFD:8;
0513             } B;
0514         } ESYNCR1;
0515 
0516         union FMPLL_ESYNCR2_tag {/* FMPLL Enhanced Synthesizer Control Register 2 */
0517             uint32_t R;
0518             struct {
0519                 uint32_t:8;
0520                 uint32_t LOCEN:1;
0521                 uint32_t LOLRE:1;
0522                 uint32_t LOCRE:1;
0523                 uint32_t LOLIRQ:1;
0524                 uint32_t LOCIRQ:1;
0525                 uint32_t:1;
0526                 uint32_t ERATE:2;
0527                 uint32_t CLKCFG_DIS:1;
0528                 uint32_t:4;
0529                 uint32_t EDEPTH:3;
0530                 uint32_t:2;
0531                 uint32_t ERFD:6;
0532             } B;
0533         } ESYNCR2;
0534 
0535         uint32_t FMPLL_reserved0010[4092];  /* 0x0010-0x3FFF */
0536 
0537     };
0538 
0539 /****************************************************************************/
0540 /*                     MODULE : External Bus Interface (EBI)                */
0541 /****************************************************************************/
0542 
0543     struct EBI_CS_tag {
0544         uint32_t ebi_cs_reserved [2];
0545     };
0546     
0547     struct EBI_CAL_CS_tag {
0548         union {                 /* Calibration Base Register Bank */
0549             uint32_t R;
0550             struct {
0551                 uint32_t BA:17;
0552                 uint32_t:3;
0553                 uint32_t PS:1;
0554                 uint32_t:3;
0555                 uint32_t AD_MUX:1;
0556                 uint32_t BL:1;
0557                 uint32_t WEBS:1;
0558                 uint32_t TBDIP:1;
0559                 uint32_t:1;
0560                 uint32_t SETA:1;
0561                 uint32_t BI:1;
0562                 uint32_t V:1;
0563             } B;
0564         } BR;
0565 
0566         union {                 /* Calibration Option Register Bank */
0567             uint32_t R;
0568             struct {
0569                 uint32_t AM:17;
0570                 uint32_t:7;
0571                 uint32_t SCY:4;
0572                 uint32_t:1;
0573                 uint32_t BSCY:2;
0574                 uint32_t:1;
0575             } B;
0576         } OR;
0577     };
0578 
0579     struct EBI_tag {
0580 
0581         union EBI_MCR_tag {     /* Module Configuration Register */
0582             uint32_t R;
0583             struct {
0584                 uint32_t:16;
0585                 uint32_t ACGE:1;
0586                 uint32_t:8;
0587                 uint32_t MDIS:1;
0588                 uint32_t:3;
0589                 uint32_t D16_31:1;
0590                 uint32_t AD_MUX:1;
0591                 uint32_t DBM:1;
0592             } B;
0593         } MCR;
0594 
0595         uint32_t EBI_reserved0004;  /* 0x0004-0x0007 */
0596 
0597         union {                 /* Transfer Error Status Register */
0598             uint32_t R;
0599             struct {
0600                 uint32_t:30;
0601                 uint32_t TEAF:1;
0602                 uint32_t BMTF:1;
0603             } B;
0604         } TESR;
0605 
0606         union {                 /* Bus Monitor Control Register */
0607             uint32_t R;
0608             struct {
0609                 uint32_t:16;
0610                 uint32_t BMT:8;
0611                 uint32_t BME:1;
0612                   uint32_t:7;
0613             } B;
0614         } BMCR;
0615 
0616         /* Base/Option registers */
0617         struct EBI_CS_tag CS[4];
0618 
0619         uint32_t EBI_reserved0030[4];  /* 0x0030-0x003F */
0620 
0621         /* Calibration registers */
0622         struct EBI_CAL_CS_tag CAL_CS[4];
0623 
0624         uint32_t EBI_reserved0060[4000];  /* 0x0060-0x3FFF */
0625 
0626     };
0627 
0628 /****************************************************************************/
0629 /*                     MODULE : FLASH                                       */
0630 /****************************************************************************/
0631 
0632     struct FLASH_tag {
0633 
0634         union {                 /* Module Configuration Register */
0635             uint32_t R;
0636             struct {
0637                 uint32_t:5;
0638                 uint32_t SIZE:3;
0639                 uint32_t:1;
0640                 uint32_t LAS:3;
0641                 uint32_t:3;
0642                 uint32_t MAS:1;
0643                 uint32_t EER:1;
0644                 uint32_t RWE:1;
0645                 uint32_t SBC:1;
0646                 uint32_t:1;
0647                 uint32_t PEAS:1;
0648                 uint32_t DONE:1;
0649                 uint32_t PEG:1;
0650                 uint32_t:4;
0651                 uint32_t PGM:1;
0652                 uint32_t PSUS:1;
0653                 uint32_t ERS:1;
0654                 uint32_t ESUS:1;
0655                 uint32_t EHV:1;
0656             } B;
0657         } MCR;
0658 
0659         union LMLR_tag {        /* Low/Mid Address Space Block Locking Register */
0660             uint32_t R;
0661             struct {
0662                 uint32_t LME:1;
0663                 uint32_t:10;
0664                 uint32_t SLOCK:1;
0665                 uint32_t:2;
0666                 uint32_t MLOCK:2;
0667                 uint32_t:6;
0668                 uint32_t LLOCK:10;
0669             } B;
0670         } LMLR; /* Legacy naming - refer to LML in Reference Manual */
0671 
0672         union HLR_tag {         /* High Address Space Block Locking Register */
0673             uint32_t R;
0674             struct {
0675                 uint32_t HBE:1;
0676                 uint32_t:25;
0677                 uint32_t HBLOCK:6; /* Legacy naming - refer to HLOCK in Reference Manual */
0678             } B;
0679         } HLR; /* Legacy naming - refer to HBL in Reference Manual */
0680 
0681         union SLMLR_tag {       /* Secondary Low/Mid Block Locking Register */
0682             uint32_t R;
0683             struct {
0684                 uint32_t SLE:1;
0685                 uint32_t:10;
0686                 uint32_t SSLOCK:1;
0687                 uint32_t:2;
0688                 uint32_t SMLOCK:2;
0689                 uint32_t:6;
0690                 uint32_t SLLOCK:10;
0691             } B;
0692         } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */
0693 
0694         union {                 /* Low/Mid Address Space Block Select Register */
0695             uint32_t R;
0696             struct {
0697                 uint32_t:14;
0698                 uint32_t MSEL:2;
0699                 uint32_t:6;
0700                 uint32_t LSEL:10;
0701             } B;
0702         } LMSR; /* Legacy naming - refer to LMS in Reference Manual */
0703 
0704         union {                 /* High Address Space Block Select Register */
0705             uint32_t R;
0706             struct {
0707                 uint32_t:26;
0708                 uint32_t HBSEL:6; /* Legacy naming - refer to HSEL in Reference Manual */
0709             } B;
0710         } HSR; /* Legacy naming - refer to HBS in Reference Manual */
0711 
0712         union {                 /* Address Register */
0713             uint32_t R;
0714             struct {
0715                 uint32_t SAD:1;
0716                 uint32_t:13;
0717                 uint32_t ADDR:15;
0718                 uint32_t:3;
0719             } B;
0720         } AR; /* Legacy naming - refer to ADR in Reference Manual */
0721 
0722         union {                 /* Platform Flash Configuration Register 1 */
0723             uint32_t R;
0724             struct {
0725                 uint32_t:7;
0726                 uint32_t M8PFE:1;     /* z7 Nexus */
0727                 uint32_t:1;           /* EBI Testing - Reserved */
0728                 uint32_t M6PFE:1;     /* FlexRay  */
0729                 uint32_t M5PFE:1;     /* eDMA_B   */
0730                 uint32_t M4PFE:1;     /* eDMA_A   */
0731                 uint32_t:1;           /* Reserved */
0732                 uint32_t:1;           /* Reserved */
0733                 uint32_t:1;           /* Reserved */
0734                 uint32_t M0PFE:1;     /* z7 Core  */
0735                 uint32_t APC:3;
0736                 uint32_t WWSC:2;
0737                 uint32_t RWSC:3;
0738                 uint32_t:1;
0739                 uint32_t DPFEN:1;
0740                 uint32_t:1;
0741                 uint32_t IPFEN:1;
0742                 uint32_t:1;
0743                 uint32_t PFLIM:2;
0744                 uint32_t BFEN:1;
0745             } B;
0746         } BIUCR; /* Legacy naming - PFCR1 */
0747 
0748         union {                 /*Platform Flash Access Protection Register */
0749             uint32_t R;
0750             struct {
0751                 uint32_t:14;
0752                 uint32_t M8AP:2;     /* z7 Nexus */
0753                 uint32_t:2;          /* EBI Testing - Reserved */
0754                 uint32_t M6AP:2;     /* FlexRay  */
0755                 uint32_t M5AP:2;     /* eDMA_B   */
0756                 uint32_t M4AP:2;     /* eDMA_A   */
0757                 uint32_t:2;          /* Reserved */
0758                 uint32_t:2;          /* Reserved */
0759                 uint32_t:2;          /* Reserved */
0760                 uint32_t M0AP:2;     /* z7 Core  */
0761             } B;
0762         } BIUAPR; /* Legacy naming - refer to PFAPR in Reference Manual */
0763 
0764         union {                 /* Platform Flash Configuration Register 2 */
0765             uint32_t R;
0766             struct {
0767                 uint32_t LBCFG:2;
0768                 uint32_t:30;
0769             } B;
0770         } BIUCR2;
0771 
0772         uint32_t FLASH_reserved0028[4086];  /* 0x0028-0x3FFF */
0773     };
0774 
0775 /****************************************************************************/
0776 /*                     MODULE : SIU                                         */
0777 /****************************************************************************/
0778     struct SIU_tag {
0779         int32_t SIU_reserved0000  /* 0x0000-0x0003 */;
0780 
0781         union {                 /* MCU ID Register */
0782             uint32_t R;
0783             struct {
0784                 uint32_t PARTNUM:16;
0785                 uint32_t PKG:4;
0786                 uint32_t:4;
0787                 uint32_t MAJOR_REV:4;
0788                 uint32_t MINOR_REV:4;
0789             } B;
0790         } MIDR;
0791 
0792         int32_t SIU_reserved0008;  /* 0x0008-0x000B */
0793 
0794         union {                 /* Reset Status Register */
0795             uint32_t R;
0796             struct {
0797                 uint32_t PORS:1;
0798                 uint32_t ERS:1;
0799                 uint32_t LLRS:1;
0800                 uint32_t LCRS:1;
0801                 uint32_t WDRS:1;
0802                 uint32_t CRS:1;
0803                 uint32_t SWTRS:1;
0804                 uint32_t:7;
0805                 uint32_t SSRS:1;
0806                 uint32_t SERF:1;
0807                 uint32_t WKPCFG:1;
0808                 uint32_t:11;
0809                 uint32_t ABR:1;
0810                 uint32_t BOOTCFG:2;
0811                 uint32_t RGF:1;
0812             } B;
0813         } RSR;
0814 
0815         union {                 /* System Reset Control Register */
0816             uint32_t R;
0817             struct {
0818                 uint32_t SSR:1;
0819                 uint32_t SER:1;
0820                 uint32_t:30;   // Removed CRE bit
0821             } B;
0822         } SRCR;
0823 
0824         union SIU_EISR_tag {    /* External Interrupt Status Register */
0825             uint32_t R;
0826             struct {
0827                 uint32_t NMI:1;
0828                 uint32_t:15;
0829                 uint32_t EIF15:1;
0830                 uint32_t EIF14:1;
0831                 uint32_t EIF13:1;
0832                 uint32_t EIF12:1;
0833                 uint32_t EIF11:1;
0834                 uint32_t EIF10:1;
0835                 uint32_t EIF9:1;
0836                 uint32_t EIF8:1;
0837                 uint32_t EIF7:1;
0838                 uint32_t EIF6:1;
0839                 uint32_t EIF5:1;
0840                 uint32_t EIF4:1;
0841                 uint32_t EIF3:1;
0842                 uint32_t EIF2:1;
0843                 uint32_t EIF1:1;
0844                 uint32_t EIF0:1;
0845             } B;
0846         } EISR;
0847 
0848         union SIU_DIRER_tag {   /* DMA/Interrupt Request Enable Register */
0849             uint32_t R;
0850             struct {
0851                 uint32_t NMISEL8:1;
0852                 uint32_t:7;
0853                 uint32_t NMISEL0:1;
0854                 uint32_t:7;
0855                 uint32_t EIRE15:1;
0856                 uint32_t EIRE14:1;
0857                 uint32_t EIRE13:1;
0858                 uint32_t EIRE12:1;
0859                 uint32_t EIRE11:1;
0860                 uint32_t EIRE10:1;
0861                 uint32_t EIRE9:1;
0862                 uint32_t EIRE8:1;
0863                 uint32_t EIRE7:1;
0864                 uint32_t EIRE6:1;
0865                 uint32_t EIRE5:1;
0866                 uint32_t EIRE4:1;
0867                 uint32_t EIRE3:1;
0868                 uint32_t EIRE2:1;
0869                 uint32_t EIRE1:1;
0870                 uint32_t EIRE0:1;
0871             } B;
0872         } DIRER;
0873 
0874         union SIU_DIRSR_tag {   /* DMA/Interrupt Request Select Register */
0875             uint32_t R;
0876             struct {
0877                 uint32_t:28;
0878                 uint32_t DIRS3:1;
0879                 uint32_t DIRS2:1;
0880                 uint32_t DIRS1:1;
0881                 uint32_t DIRS0:1;
0882             } B;
0883         } DIRSR;
0884 
0885         union {                 /* Overrun Status Register */
0886             uint32_t R;
0887             struct {
0888                 uint32_t:16;
0889                 uint32_t OVF15:1;
0890                 uint32_t OVF14:1;
0891                 uint32_t OVF13:1;
0892                 uint32_t OVF12:1;
0893                 uint32_t OVF11:1;
0894                 uint32_t OVF10:1;
0895                 uint32_t OVF9:1;
0896                 uint32_t OVF8:1;
0897                 uint32_t OVF7:1;
0898                 uint32_t OVF6:1;
0899                 uint32_t OVF5:1;
0900                 uint32_t OVF4:1;
0901                 uint32_t OVF3:1;
0902                 uint32_t OVF2:1;
0903                 uint32_t OVF1:1;
0904                 uint32_t OVF0:1;
0905             } B;
0906         } OSR;
0907 
0908         union SIU_ORER_tag {    /* Overrun Request Enable Register */
0909             uint32_t R;
0910             struct {
0911                 uint32_t:16;
0912                 uint32_t ORE15:1;
0913                 uint32_t ORE14:1;
0914                 uint32_t ORE13:1;
0915                 uint32_t ORE12:1;
0916                 uint32_t ORE11:1;
0917                 uint32_t ORE10:1;
0918                 uint32_t ORE9:1;
0919                 uint32_t ORE8:1;
0920                 uint32_t ORE7:1;
0921                 uint32_t ORE6:1;
0922                 uint32_t ORE5:1;
0923                 uint32_t ORE4:1;
0924                 uint32_t ORE3:1;
0925                 uint32_t ORE2:1;
0926                 uint32_t ORE1:1;
0927                 uint32_t ORE0:1;
0928             } B;
0929         } ORER;
0930 
0931         union SIU_IREER_tag {   /* External IRQ Rising-Edge Event Enable Register */
0932             uint32_t R;
0933             struct {
0934                 uint32_t IREE_NMI8:1;
0935                 uint32_t:7;
0936                 uint32_t IREE_NMI0:1;
0937                 uint32_t:7;
0938                 uint32_t IREE15:1;
0939                 uint32_t IREE14:1;
0940                 uint32_t IREE13:1;
0941                 uint32_t IREE12:1;
0942                 uint32_t IREE11:1;
0943                 uint32_t IREE10:1;
0944                 uint32_t IREE9:1;
0945                 uint32_t IREE8:1;
0946                 uint32_t IREE7:1;
0947                 uint32_t IREE6:1;
0948                 uint32_t IREE5:1;
0949                 uint32_t IREE4:1;
0950                 uint32_t IREE3:1;
0951                 uint32_t IREE2:1;
0952                 uint32_t IREE1:1;
0953                 uint32_t IREE0:1;
0954             } B;
0955         } IREER;
0956 
0957         union SIU_IFEER_tag {   /* External IRQ Falling-Edge Event Enable Register */
0958             uint32_t R;
0959             struct {
0960                 uint32_t IFEE_NMI8:1;
0961                 uint32_t:7;
0962                 uint32_t IFEE_NMI0:1;
0963                 uint32_t:7;
0964                 uint32_t IFEE15:1;
0965                 uint32_t IFEE14:1;
0966                 uint32_t IFEE13:1;
0967                 uint32_t IFEE12:1;
0968                 uint32_t IFEE11:1;
0969                 uint32_t IFEE10:1;
0970                 uint32_t IFEE9:1;
0971                 uint32_t IFEE8:1;
0972                 uint32_t IFEE7:1;
0973                 uint32_t IFEE6:1;
0974                 uint32_t IFEE5:1;
0975                 uint32_t IFEE4:1;
0976                 uint32_t IFEE3:1;
0977                 uint32_t IFEE2:1;
0978                 uint32_t IFEE1:1;
0979                 uint32_t IFEE0:1;
0980             } B;
0981         } IFEER;
0982 
0983         union SIU_IDFR_tag {    /* External IRQ Digital Filter Register */
0984             uint32_t R;
0985             struct {
0986                 uint32_t:28;
0987                 uint32_t DFL:4;
0988             } B;
0989         } IDFR;
0990 
0991         union {                 /* External IRQ Filtered Input Register */
0992             uint32_t R;
0993             struct {
0994                 uint32_t FI31:1;
0995                 uint32_t FI30:1;
0996                 uint32_t FI29:1;
0997                 uint32_t FI28:1;
0998                 uint32_t FI27:1;
0999                 uint32_t FI26:1;
1000                 uint32_t FI25:1;
1001                 uint32_t FI24:1;
1002                 uint32_t FI23:1;
1003                 uint32_t FI22:1;
1004                 uint32_t FI21:1;
1005                 uint32_t FI20:1;
1006                 uint32_t FI19:1;
1007                 uint32_t FI18:1;
1008                 uint32_t FI17:1;
1009                 uint32_t FI16:1;
1010                 uint32_t FI15:1;
1011                 uint32_t FI14:1;
1012                 uint32_t FI13:1;
1013                 uint32_t FI12:1;
1014                 uint32_t FI11:1;
1015                 uint32_t FI10:1;
1016                 uint32_t FI9:1;
1017                 uint32_t FI8:1;
1018                 uint32_t FI7:1;
1019                 uint32_t FI6:1;
1020                 uint32_t FI5:1;
1021                 uint32_t FI4:1;
1022                 uint32_t FI3:1;
1023                 uint32_t FI2:1;
1024                 uint32_t FI1:1;
1025                 uint32_t FI0:1;
1026             } B;
1027         } IFIR;
1028 
1029         int32_t SIU_reserved0038[2]; /* 0x0038-0x003F */
1030 
1031         union SIU_PCR_tag {     /* Pad Configuration Registers */
1032             uint16_t R;
1033             struct {
1034                 uint16_t:3;
1035                 uint16_t PA:3;
1036                 uint16_t OBE:1;
1037                 uint16_t IBE:1;
1038                 uint16_t DSC:2;
1039                 uint16_t ODE:1;
1040                 uint16_t HYS:1;
1041                 uint16_t SRC:2;
1042                 uint16_t WPE:1;
1043                 uint16_t WPS:1;
1044             } B;
1045         } PCR[512];
1046 
1047         int16_t SIU_reserved0440[224];  /* 0x0440-0x05FF */
1048 
1049         union {                 /* GPIO Pin Data Output Registers */
1050             uint8_t R;
1051             struct {
1052                 uint8_t:7;
1053                 uint8_t PDO:1;
1054             } B;
1055         } GPDO[512];
1056 
1057         union {                 /* GPIO Pin Data Input Registers */
1058             uint8_t R;
1059             struct {
1060                 uint8_t:7;
1061                 uint8_t PDI:1;
1062             } B;
1063         } GPDI[256];
1064 
1065         uint32_t SIU_reserved0900;  /* 0x0900-0x0903 */
1066 
1067         union {                 /* External IRQ Input Select Register */
1068             uint32_t R;
1069             struct {
1070                 uint32_t ESEL15:2;
1071                 uint32_t ESEL14:2;
1072                 uint32_t ESEL13:2;
1073                 uint32_t ESEL12:2;
1074                 uint32_t ESEL11:2;
1075                 uint32_t ESEL10:2;
1076                 uint32_t ESEL9:2;
1077                 uint32_t ESEL8:2;
1078                 uint32_t ESEL7:2;
1079                 uint32_t ESEL6:2;
1080                 uint32_t ESEL5:2;
1081                 uint32_t ESEL4:2;
1082                 uint32_t ESEL3:2;
1083                 uint32_t ESEL2:2;
1084                 uint32_t ESEL1:2;
1085                 uint32_t ESEL0:2;
1086             } B;
1087         } EIISR;
1088 
1089         union {                 /* DSPI Input Select Register */
1090             uint32_t R;
1091             struct {
1092                 uint32_t SINSELA:2;
1093                 uint32_t SSSELA:2;
1094                 uint32_t SCKSELA:2;
1095                 uint32_t TRIGSELA:2;
1096                 uint32_t SINSELB:2;
1097                 uint32_t SSSELB:2;
1098                 uint32_t SCKSELB:2;
1099                 uint32_t TRIGSELB:2;
1100                 uint32_t SINSELC:2;
1101                 uint32_t SSSELC:2;
1102                 uint32_t SCKSELC:2;
1103                 uint32_t TRIGSELC:2;
1104                 uint32_t SINSELD:2;
1105                 uint32_t SSSELD:2;
1106                 uint32_t SCKSELD:2;
1107                 uint32_t TRIGSELD:2;
1108             } B;
1109         } DISR;
1110 
1111         int32_t SIU_reserved090C;  /* 0x090C-0x090F */
1112 
1113         union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1114             uint32_t R;
1115             struct {
1116                 uint32_t:1;
1117                 uint32_t CTSEL5_0:7;
1118                 uint32_t:1;
1119                 uint32_t CTSEL4_0:7;
1120                 uint32_t:1;
1121                 uint32_t CTSEL3_0:7;
1122                 uint32_t:1;
1123                 uint32_t CTSEL2_0:7;
1124             } B;
1125         } ISEL4;
1126 
1127         union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1128             uint32_t R;
1129             struct {
1130                 uint32_t:1;
1131                 uint32_t CTSEL1_0:7;
1132                 uint32_t:1;
1133                 uint32_t CTSEL0_0:7;
1134                 uint32_t:16;
1135             } B;
1136         } ISEL5;
1137 
1138         union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1139             uint32_t R;
1140             struct {
1141                 uint32_t:1;
1142                 uint32_t CTSEL5_1:7;
1143                 uint32_t:1;
1144                 uint32_t CTSEL4_1:7;
1145                 uint32_t:1;
1146                 uint32_t CTSEL3_1:7;
1147                 uint32_t:1;
1148                 uint32_t CTSEL2_1:7;
1149             } B;
1150         } ISEL6;
1151 
1152         union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1153             uint32_t R;
1154             struct {
1155                 uint32_t:1;
1156                 uint32_t CTSEL1_1:7;
1157                 uint32_t:1;
1158                 uint32_t CTSEL0_1:7;
1159                 uint32_t:16;
1160             } B;
1161         } ISEL7;
1162 
1163         union {                 /* eTPU Input Select Register */
1164             uint32_t R;
1165             struct {
1166                 uint32_t:11;
1167                 uint32_t ETPU29:1;
1168                 uint32_t:3;
1169                 uint32_t ETPU28:1;
1170                 uint32_t:3;
1171                 uint32_t ETPU27:1;
1172                 uint32_t:3;
1173                 uint32_t ETPU26:1;
1174                 uint32_t:3;
1175                 uint32_t ETPU25:1;
1176                 uint32_t:3;
1177                 uint32_t ETPU24:1;
1178              } B;
1179         } ISEL8;
1180 
1181         union {                 /* eQADC Advanced Trigger Select  */
1182             uint32_t R;
1183             struct {
1184                 uint32_t:27;
1185                 uint32_t ETSEL0A:5;
1186             } B;
1187         } ISEL9;
1188 
1189         union {                 /* DecFilter Integrator Control  */
1190             uint32_t R;
1191             struct {
1192                 uint32_t ZSELA:4;
1193                 uint32_t HSELA:4;
1194                 uint32_t ZSELB:4;
1195                 uint32_t HSELB:4;
1196                 uint32_t ZSELC:4;
1197                 uint32_t HSELC:4;
1198                 uint32_t ZSELD:4;
1199                 uint32_t HSELD:4;
1200             } B;
1201         } DECFIL1;
1202 
1203         union {                 /* DecFilter Integrator Control */
1204             uint32_t R;
1205             struct {
1206                 uint32_t ZSELE:4;
1207                 uint32_t HSELE:4;
1208                 uint32_t ZSELF:4;
1209                 uint32_t HSELF:4;
1210                 uint32_t ZSELG:4;
1211                 uint32_t HSELG:4;
1212                 uint32_t ZSELH:4;
1213                 uint32_t HSELH:4;
1214             } B;
1215         } DECFIL2;
1216 
1217 
1218         int32_t SIU_reserved0920[20]; /* 0x0930-0x097F */
1219 
1220         union {                 /* Chip Configuration Register Register */
1221             uint32_t R;
1222             struct {
1223                 uint32_t:14;
1224                 uint32_t MATCH:1;
1225                 uint32_t DISNEX:1;
1226                 uint32_t:16;
1227             } B;
1228         } CCR;
1229 
1230         union {                 /* External Clock Configuration Register Register */
1231             uint32_t R;
1232             struct {
1233                 uint32_t:16;
1234                 uint32_t ENGDIV:8;
1235                 uint32_t ECSS:1;
1236                 uint32_t:3;
1237                 uint32_t EBTS:1;
1238                 uint32_t:1;
1239                 uint32_t EBDF:2;
1240             } B;
1241         } ECCR;
1242 
1243         union {                 /* Compare A Register High */
1244             uint32_t R;
1245             struct {
1246                 uint32_t CMPAH:32;
1247             } B;
1248         } CARH;
1249 
1250         union {                 /* Compare A Register Low */
1251             uint32_t R;
1252             struct {
1253                 uint32_t CMPAL:32;
1254             } B;
1255         } CARL;
1256 
1257         union {                 /* Compare B Register High */
1258             uint32_t R;
1259             struct {
1260                 uint32_t CMPBH:32;
1261             } B;
1262         } CBRH;
1263 
1264         union {                 /* Compare B Register Low */
1265             uint32_t R;
1266             struct {
1267                 uint32_t CMPBL:32;
1268             } B;
1269         } CBRL;
1270 
1271         int32_t SIU_reserved0998[2];  /* 0x0998-0x099F */
1272 
1273         union {                 /* System Clock Register */
1274             uint32_t R;
1275             struct {
1276                 uint32_t:22;
1277                 uint32_t IPCLKDIV:2;
1278                 uint32_t:3;
1279                 uint32_t BYPASS:1;
1280                 uint32_t SYSCLKDIV:2;
1281                 uint32_t:2;
1282             } B;
1283         } SYSDIV;
1284 
1285         union {                 /* Halt Register */
1286             uint32_t R;
1287             struct {
1288                 uint32_t CPUSTP:1;     /* CPU and Platform stop request  */
1289                 uint32_t:4;            /* Reserved */
1290                 uint32_t TPUSTP:1;     /* eTPU_A stop request */
1291                 uint32_t NPCSTP:1;     /* Nexus stop request */
1292                 uint32_t EBISTP:1;     /* EBI stop request*/
1293                 uint32_t ADCSTP:1;     /* eQADC stop request */
1294                 uint32_t:1;            /* Reserved */
1295                 uint32_t MIOSSTP:1;    /* eMIOS stop request */
1296                 uint32_t DFILSTP:1;    /* Decimation filter stop request */
1297                 uint32_t:1;            /* Reserved */
1298                 uint32_t PITSTP:1;     /* PIT stop request */
1299                 uint32_t:2;            /* Reserved */
1300                 uint32_t CNDSTP:1;     /* FlexCAN D stop request */
1301                 uint32_t CNCSTP:1;     /* FlexCAN C stop request */
1302                 uint32_t CNBSTP:1;     /* FlexCAN B stop request */
1303                 uint32_t CNASTP:1;     /* FlexCAN A stop request */
1304                 uint32_t SPIDSTP:1;    /* DSPI D stop request */
1305                 uint32_t SPICSTP:1;    /* DSPI C stop request */
1306                 uint32_t SPIBSTP:1;    /* DSPI B stop request */
1307                 uint32_t SPIASTP:1;    /* DSPI C stop request */
1308                 uint32_t:5;            /* Reserved */
1309                 uint32_t SCICSTP:1;    /* eSCI C stop request */
1310                 uint32_t SCIBSTP:1;    /* eSCI B stop request */
1311                 uint32_t SCIASTP:1;    /* eSCI A stop request */
1312             } B;
1313         } HLT;
1314 
1315         union {                 /* Halt Acknowledge Register */
1316             uint32_t R;
1317             struct {
1318                 uint32_t CPUACK:1;     /* CPU and Platform stop acknowledge  */
1319                 uint32_t:4;            /* Reserved */
1320                 uint32_t TPUACK:1;     /* eTPU_A stop acknowledge */
1321                 uint32_t NPCACK:1;     /* Nexus stop acknowledge */
1322                 uint32_t EBIACK:1;     /* EBI stop acknowledge*/
1323                 uint32_t ADCACK:1;     /* eQADC stop acknowledge */
1324                 uint32_t:1;            /* Reserved */
1325                 uint32_t MIOSACK:1;    /* eMIOS stop acknowledge */
1326                 uint32_t DFILACK:1;    /* Decimation filter stop acknowledge */
1327                 uint32_t:1;            /* Reserved */
1328                 uint32_t PITACK:1;     /* PIT stop acknowledge */
1329                 uint32_t:2;            /* Reserved */
1330                 uint32_t CNDACK:1;     /* FlexCAN D stop acknowledge */
1331                 uint32_t CNCACK:1;     /* FlexCAN C stop acknowledge */
1332                 uint32_t CNBACK:1;     /* FlexCAN B stop acknowledge */
1333                 uint32_t CNAACK:1;     /* FlexCAN A stop acknowledge */
1334                 uint32_t SPIDACK:1;    /* DSPI D stop acknowledge */
1335                 uint32_t SPICACK:1;    /* DSPI C stop acknowledge */
1336                 uint32_t SPIBACK:1;    /* DSPI B stop acknowledge */
1337                 uint32_t SPIAACK:1;    /* DSPI C stop acknowledge */
1338                 uint32_t:5;            /* Reserved */
1339                 uint32_t SCICACK:1;    /* eSCI C stop acknowledge */
1340                 uint32_t SCIBACK:1;    /* eSCI B stop acknowledge */
1341                 uint32_t SCIAACK:1;    /* eSCI A stop acknowledge */
1342             } B;
1343         } HLTACK;
1344 
1345         int32_t SIU_reserved09AC[21]; /* 0x09AC-0x09FF */
1346 
1347         int32_t SIU_reserved0A00[128]; /* 0x0A00-0x0BFF */
1348 
1349         union {               /* Parallel GPIO Pin Data Output Register */
1350             uint32_t R;
1351             struct {
1352                 uint32_t PGPDO0:1;
1353                 uint32_t PGPDO1:1;
1354                 uint32_t PGPDO2:1;
1355                 uint32_t PGPDO3:1;
1356                 uint32_t PGPDO4:1;
1357                 uint32_t PGPDO5:1;
1358                 uint32_t PGPDO6:1;
1359                 uint32_t PGPDO7:1;
1360                 uint32_t PGPDO8:1;
1361                 uint32_t PGPDO9:1;
1362                 uint32_t PGPDO10:1;
1363                 uint32_t PGPDO11:1;
1364                 uint32_t PGPDO12:1;
1365                 uint32_t PGPDO13:1;
1366                 uint32_t PGPDO14:1;
1367                 uint32_t PGPDO15:1;
1368                 uint32_t PGPDO16:1;
1369                 uint32_t PGPDO17:1;
1370                 uint32_t PGPDO18:1;
1371                 uint32_t PGPDO19:1;
1372                 uint32_t PGPDO20:1;
1373                 uint32_t PGPDO21:1;
1374                 uint32_t PGPDO22:1;
1375                 uint32_t PGPDO23:1;
1376                 uint32_t PGPDO24:1;
1377                 uint32_t PGPDO25:1;
1378                 uint32_t PGPDO26:1;
1379                 uint32_t PGPDO27:1;
1380                 uint32_t PGPDO28:1;
1381                 uint32_t PGPDO29:1;
1382                 uint32_t PGPDO30:1;
1383                 uint32_t PGPDO31:1;
1384             } B;
1385         } PGPDO[16];
1386 
1387         union {               /* Parallel GPIO Pin Data Input Register */
1388             uint32_t R;
1389             struct {
1390                 uint32_t PGPDI0:1;
1391                 uint32_t PGPDI1:1;
1392                 uint32_t PGPDI2:1;
1393                 uint32_t PGPDI3:1;
1394                 uint32_t PGPDI4:1;
1395                 uint32_t PGPDI5:1;
1396                 uint32_t PGPDI6:1;
1397                 uint32_t PGPDI7:1;
1398                 uint32_t PGPDI8:1;
1399                 uint32_t PGPDI9:1;
1400                 uint32_t PGPDI10:1;
1401                 uint32_t PGPDI11:1;
1402                 uint32_t PGPDI12:1;
1403                 uint32_t PGPDI13:1;
1404                 uint32_t PGPDI14:1;
1405                 uint32_t PGPDI15:1;
1406                 uint32_t PGPDI16:1;
1407                 uint32_t PGPDI17:1;
1408                 uint32_t PGPDI18:1;
1409                 uint32_t PGPDI19:1;
1410                 uint32_t PGPDI20:1;
1411                 uint32_t PGPDI21:1;
1412                 uint32_t PGPDI22:1;
1413                 uint32_t PGPDI23:1;
1414                 uint32_t PGPDI24:1;
1415                 uint32_t PGPDI25:1;
1416                 uint32_t PGPDI26:1;
1417                 uint32_t PGPDI27:1;
1418                 uint32_t PGPDI28:1;
1419                 uint32_t PGPDI29:1;
1420                 uint32_t PGPDI30:1;
1421                 uint32_t PGPDI31:1;
1422             } B;
1423         } PGPDI[16];
1424 
1425         union {              /* Masked Parallel GPIO Pin Data Input Register */
1426             uint32_t R;
1427             struct {
1428                 uint32_t MASK0:1;
1429                 uint32_t MASK1:1;
1430                 uint32_t MASK2:1;
1431                 uint32_t MASK3:1;
1432                 uint32_t MASK4:1;
1433                 uint32_t MASK5:1;
1434                 uint32_t MASK6:1;
1435                 uint32_t MASK7:1;
1436                 uint32_t MASK8:1;
1437                 uint32_t MASK9:1;
1438                 uint32_t MASK10:1;
1439                 uint32_t MASK11:1;
1440                 uint32_t MASK12:1;
1441                 uint32_t MASK13:1;
1442                 uint32_t MASK14:1;
1443                 uint32_t MASK15:1;
1444                 uint32_t DATA0:1;
1445                 uint32_t DATA1:1;
1446                 uint32_t DATA2:1;
1447                 uint32_t DATA3:1;
1448                 uint32_t DATA4:1;
1449                 uint32_t DATA5:1;
1450                 uint32_t DATA6:1;
1451                 uint32_t DATA7:1;
1452                 uint32_t DATA8:1;
1453                 uint32_t DATA9:1;
1454                 uint32_t DATA10:1;
1455                 uint32_t DATA11:1;
1456                 uint32_t DATA12:1;
1457                 uint32_t DATA13:1;
1458                 uint32_t DATA14:1;
1459                 uint32_t DATA15:1;
1460             } B;
1461         } MPGPDO[32];
1462 
1463         union {              /* DSPI_A Mask Output High Register */
1464             uint32_t R;
1465             struct {
1466                 uint32_t MASK0:1;
1467                 uint32_t MASK1:1;
1468                 uint32_t MASK2:1;
1469                 uint32_t MASK3:1;
1470                 uint32_t MASK4:1;
1471                 uint32_t MASK5:1;
1472                 uint32_t MASK6:1;
1473                 uint32_t MASK7:1;
1474                 uint32_t MASK8:1;
1475                 uint32_t MASK9:1;
1476                 uint32_t MASK10:1;
1477                 uint32_t MASK11:1;
1478                 uint32_t MASK12:1;
1479                 uint32_t MASK13:1;
1480                 uint32_t MASK14:1;
1481                 uint32_t MASK15:1;
1482                 uint32_t DATA0:1;
1483                 uint32_t DATA1:1;
1484                 uint32_t DATA2:1;
1485                 uint32_t DATA3:1;
1486                 uint32_t DATA4:1;
1487                 uint32_t DATA5:1;
1488                 uint32_t DATA6:1;
1489                 uint32_t DATA7:1;
1490                 uint32_t DATA8:1;
1491                 uint32_t DATA9:1;
1492                 uint32_t DATA10:1;
1493                 uint32_t DATA11:1;
1494                 uint32_t DATA12:1;
1495                 uint32_t DATA13:1;
1496                 uint32_t DATA14:1;
1497                 uint32_t DATA15:1;
1498             } B;
1499         } DSPIAH;
1500 
1501         union {              /* DSPI_A Mask Output Low Register */
1502             uint32_t R;
1503             struct {
1504                 uint32_t MASK16:1;
1505                 uint32_t MASK17:1;
1506                 uint32_t MASK18:1;
1507                 uint32_t MASK19:1;
1508                 uint32_t MASK20:1;
1509                 uint32_t MASK21:1;
1510                 uint32_t MASK22:1;
1511                 uint32_t MASK23:1;
1512                 uint32_t MASK24:1;
1513                 uint32_t MASK25:1;
1514                 uint32_t MASK26:1;
1515                 uint32_t MASK27:1;
1516                 uint32_t MASK28:1;
1517                 uint32_t MASK29:1;
1518                 uint32_t MASK30:1;
1519                 uint32_t MASK31:1;
1520                 uint32_t DATA16:1;
1521                 uint32_t DATA17:1;
1522                 uint32_t DATA18:1;
1523                 uint32_t DATA19:1;
1524                 uint32_t DATA20:1;
1525                 uint32_t DATA21:1;
1526                 uint32_t DATA22:1;
1527                 uint32_t DATA23:1;
1528                 uint32_t DATA24:1;
1529                 uint32_t DATA25:1;
1530                 uint32_t DATA26:1;
1531                 uint32_t DATA27:1;
1532                 uint32_t DATA28:1;
1533                 uint32_t DATA29:1;
1534                 uint32_t DATA30:1;
1535                 uint32_t DATA31:1;
1536             } B;
1537         } DSPIAL;
1538 
1539         union {              /* DSPI_B Mask Output High Register */
1540             uint32_t R;
1541             struct {
1542                 uint32_t MASK0:1;
1543                 uint32_t MASK1:1;
1544                 uint32_t MASK2:1;
1545                 uint32_t MASK3:1;
1546                 uint32_t MASK4:1;
1547                 uint32_t MASK5:1;
1548                 uint32_t MASK6:1;
1549                 uint32_t MASK7:1;
1550                 uint32_t MASK8:1;
1551                 uint32_t MASK9:1;
1552                 uint32_t MASK10:1;
1553                 uint32_t MASK11:1;
1554                 uint32_t MASK12:1;
1555                 uint32_t MASK13:1;
1556                 uint32_t MASK14:1;
1557                 uint32_t MASK15:1;
1558                 uint32_t DATA0:1;
1559                 uint32_t DATA1:1;
1560                 uint32_t DATA2:1;
1561                 uint32_t DATA3:1;
1562                 uint32_t DATA4:1;
1563                 uint32_t DATA5:1;
1564                 uint32_t DATA6:1;
1565                 uint32_t DATA7:1;
1566                 uint32_t DATA8:1;
1567                 uint32_t DATA9:1;
1568                 uint32_t DATA10:1;
1569                 uint32_t DATA11:1;
1570                 uint32_t DATA12:1;
1571                 uint32_t DATA13:1;
1572                 uint32_t DATA14:1;
1573                 uint32_t DATA15:1;
1574             } B;
1575         } DSPIBH;
1576 
1577         union {              /* DSPI_B Mask Output Low Register */
1578             uint32_t R;
1579             struct {
1580                 uint32_t MASK16:1;
1581                 uint32_t MASK17:1;
1582                 uint32_t MASK18:1;
1583                 uint32_t MASK19:1;
1584                 uint32_t MASK20:1;
1585                 uint32_t MASK21:1;
1586                 uint32_t MASK22:1;
1587                 uint32_t MASK23:1;
1588                 uint32_t MASK24:1;
1589                 uint32_t MASK25:1;
1590                 uint32_t MASK26:1;
1591                 uint32_t MASK27:1;
1592                 uint32_t MASK28:1;
1593                 uint32_t MASK29:1;
1594                 uint32_t MASK30:1;
1595                 uint32_t MASK31:1;
1596                 uint32_t DATA16:1;
1597                 uint32_t DATA17:1;
1598                 uint32_t DATA18:1;
1599                 uint32_t DATA19:1;
1600                 uint32_t DATA20:1;
1601                 uint32_t DATA21:1;
1602                 uint32_t DATA22:1;
1603                 uint32_t DATA23:1;
1604                 uint32_t DATA24:1;
1605                 uint32_t DATA25:1;
1606                 uint32_t DATA26:1;
1607                 uint32_t DATA27:1;
1608                 uint32_t DATA28:1;
1609                 uint32_t DATA29:1;
1610                 uint32_t DATA30:1;
1611                 uint32_t DATA31:1;
1612             } B;
1613         } DSPIBL;
1614 
1615         union {              /* DSPI_C Mask Output High Register */
1616             uint32_t R;
1617             struct {
1618                 uint32_t MASK0:1;
1619                 uint32_t MASK1:1;
1620                 uint32_t MASK2:1;
1621                 uint32_t MASK3:1;
1622                 uint32_t MASK4:1;
1623                 uint32_t MASK5:1;
1624                 uint32_t MASK6:1;
1625                 uint32_t MASK7:1;
1626                 uint32_t MASK8:1;
1627                 uint32_t MASK9:1;
1628                 uint32_t MASK10:1;
1629                 uint32_t MASK11:1;
1630                 uint32_t MASK12:1;
1631                 uint32_t MASK13:1;
1632                 uint32_t MASK14:1;
1633                 uint32_t MASK15:1;
1634                 uint32_t DATA0:1;
1635                 uint32_t DATA1:1;
1636                 uint32_t DATA2:1;
1637                 uint32_t DATA3:1;
1638                 uint32_t DATA4:1;
1639                 uint32_t DATA5:1;
1640                 uint32_t DATA6:1;
1641                 uint32_t DATA7:1;
1642                 uint32_t DATA8:1;
1643                 uint32_t DATA9:1;
1644                 uint32_t DATA10:1;
1645                 uint32_t DATA11:1;
1646                 uint32_t DATA12:1;
1647                 uint32_t DATA13:1;
1648                 uint32_t DATA14:1;
1649                 uint32_t DATA15:1;
1650             } B;
1651         } DSPICH;
1652 
1653         union {              /* DSPI_C Mask Output Low Register */
1654             uint32_t R;
1655             struct {
1656                 uint32_t MASK16:1;
1657                 uint32_t MASK17:1;
1658                 uint32_t MASK18:1;
1659                 uint32_t MASK19:1;
1660                 uint32_t MASK20:1;
1661                 uint32_t MASK21:1;
1662                 uint32_t MASK22:1;
1663                 uint32_t MASK23:1;
1664                 uint32_t MASK24:1;
1665                 uint32_t MASK25:1;
1666                 uint32_t MASK26:1;
1667                 uint32_t MASK27:1;
1668                 uint32_t MASK28:1;
1669                 uint32_t MASK29:1;
1670                 uint32_t MASK30:1;
1671                 uint32_t MASK31:1;
1672                 uint32_t DATA16:1;
1673                 uint32_t DATA17:1;
1674                 uint32_t DATA18:1;
1675                 uint32_t DATA19:1;
1676                 uint32_t DATA20:1;
1677                 uint32_t DATA21:1;
1678                 uint32_t DATA22:1;
1679                 uint32_t DATA23:1;
1680                 uint32_t DATA24:1;
1681                 uint32_t DATA25:1;
1682                 uint32_t DATA26:1;
1683                 uint32_t DATA27:1;
1684                 uint32_t DATA28:1;
1685                 uint32_t DATA29:1;
1686                 uint32_t DATA30:1;
1687                 uint32_t DATA31:1;
1688             } B;
1689         } DSPICL;
1690 
1691         union {              /* DSPI_D Mask Output High Register */
1692             uint32_t R;
1693             struct {
1694                 uint32_t MASK0:1;
1695                 uint32_t MASK1:1;
1696                 uint32_t MASK2:1;
1697                 uint32_t MASK3:1;
1698                 uint32_t MASK4:1;
1699                 uint32_t MASK5:1;
1700                 uint32_t MASK6:1;
1701                 uint32_t MASK7:1;
1702                 uint32_t MASK8:1;
1703                 uint32_t MASK9:1;
1704                 uint32_t MASK10:1;
1705                 uint32_t MASK11:1;
1706                 uint32_t MASK12:1;
1707                 uint32_t MASK13:1;
1708                 uint32_t MASK14:1;
1709                 uint32_t MASK15:1;
1710                 uint32_t DATA0:1;
1711                 uint32_t DATA1:1;
1712                 uint32_t DATA2:1;
1713                 uint32_t DATA3:1;
1714                 uint32_t DATA4:1;
1715                 uint32_t DATA5:1;
1716                 uint32_t DATA6:1;
1717                 uint32_t DATA7:1;
1718                 uint32_t DATA8:1;
1719                 uint32_t DATA9:1;
1720                 uint32_t DATA10:1;
1721                 uint32_t DATA11:1;
1722                 uint32_t DATA12:1;
1723                 uint32_t DATA13:1;
1724                 uint32_t DATA14:1;
1725                 uint32_t DATA15:1;
1726             } B;
1727         } DSPIDH;
1728 
1729         union {              /* DSPI_D Mask Output Low Register */
1730             uint32_t R;
1731             struct {
1732                 uint32_t MASK16:1;
1733                 uint32_t MASK17:1;
1734                 uint32_t MASK18:1;
1735                 uint32_t MASK19:1;
1736                 uint32_t MASK20:1;
1737                 uint32_t MASK21:1;
1738                 uint32_t MASK22:1;
1739                 uint32_t MASK23:1;
1740                 uint32_t MASK24:1;
1741                 uint32_t MASK25:1;
1742                 uint32_t MASK26:1;
1743                 uint32_t MASK27:1;
1744                 uint32_t MASK28:1;
1745                 uint32_t MASK29:1;
1746                 uint32_t MASK30:1;
1747                 uint32_t MASK31:1;
1748                 uint32_t DATA16:1;
1749                 uint32_t DATA17:1;
1750                 uint32_t DATA18:1;
1751                 uint32_t DATA19:1;
1752                 uint32_t DATA20:1;
1753                 uint32_t DATA21:1;
1754                 uint32_t DATA22:1;
1755                 uint32_t DATA23:1;
1756                 uint32_t DATA24:1;
1757                 uint32_t DATA25:1;
1758                 uint32_t DATA26:1;
1759                 uint32_t DATA27:1;
1760                 uint32_t DATA28:1;
1761                 uint32_t DATA29:1;
1762                 uint32_t DATA30:1;
1763                 uint32_t DATA31:1;
1764             } B;
1765         } DSPIDL;
1766 
1767         int32_t SIU_reserved0D20[8];  /* 0x0D20-0x0D3F */
1768 
1769         union {               /* ETPU B Select Register */
1770             uint32_t R;
1771             struct {
1772                 uint32_t ETPUB15:1;
1773                 uint32_t ETPUB14:1;
1774                 uint32_t ETPUB13:1;
1775                 uint32_t ETPUB12:1;
1776                 uint32_t ETPUB11:1;
1777                 uint32_t ETPUB10:1;
1778                 uint32_t ETPUB9:1;
1779                 uint32_t ETPUB8:1;
1780                 uint32_t ETPUB7:1;
1781                 uint32_t ETPUB6:1;
1782                 uint32_t ETPUB5:1;
1783                 uint32_t ETPUB4:1;
1784                 uint32_t ETPUB3:1;
1785                 uint32_t ETPUB2:1;
1786                 uint32_t ETPUB1:1;
1787                 uint32_t ETPUB0:1;
1788                 uint32_t ETPUB31:1;
1789                 uint32_t ETPUB30:1;
1790                 uint32_t ETPUB29:1;
1791                 uint32_t ETPUB28:1;
1792                 uint32_t ETPUB27:1;
1793                 uint32_t ETPUB26:1;
1794                 uint32_t ETPUB25:1;
1795                 uint32_t ETPUB24:1;
1796                 uint32_t ETPUB23:1;
1797                 uint32_t ETPUB22:1;
1798                 uint32_t ETPUB21:1;
1799                 uint32_t ETPUB20:1;
1800                 uint32_t ETPUB19:1;
1801                 uint32_t ETPUB18:1;
1802                 uint32_t ETPUB17:1;
1803                 uint32_t ETPUB16:1;
1804             } B ;
1805         } ETPUBA;
1806 
1807         union {               /* EMIOS A Select Register */
1808             uint32_t R;
1809             struct {
1810                 uint32_t EMIOS7:1;
1811                 uint32_t EMIOS6:1;
1812                 uint32_t EMIOS5:1;
1813                 uint32_t EMIOS4:1;
1814                 uint32_t EMIOS3:1;
1815                 uint32_t EMIOS2:1;
1816                 uint32_t EMIOS1:1;
1817                 uint32_t EMIOS0:1;
1818                 uint32_t EMIOS8:1;
1819                 uint32_t EMIOS9:1;
1820                 uint32_t EMIOS10:1;
1821                 uint32_t EMIOS11:1;
1822                 uint32_t EMIOS12:1;
1823                 uint32_t EMIOS13:1;
1824                 uint32_t EMIOS14:1;
1825                 uint32_t EMIOS15:1;
1826                 uint32_t EMIOS16:1;
1827                 uint32_t EMIOS17:1;
1828                 uint32_t EMIOS18:1;
1829                 uint32_t EMIOS19:1;
1830                 uint32_t EMIOS20:1;
1831                 uint32_t EMIOS21:1;
1832                 uint32_t EMIOS22:1;
1833                 uint32_t EMIOS23:1;
1834                 uint32_t EMIOS0_0:1;
1835                 uint32_t EMIOS1_1:1;
1836                 uint32_t EMIOS2_2:1;
1837                 uint32_t EMIOS3_3:1;
1838                 uint32_t EMIOS4_4:1;
1839                 uint32_t EMIOS5_5:1;
1840                 uint32_t EMIOS6_6:1;
1841                 uint32_t EMIOS7_7:1;
1842             } B;
1843         } EMIOSA;
1844 
1845         union {             /* DSPIAH/L Select Register for DSPI A */
1846             uint32_t R;
1847             struct {
1848                 uint32_t DSPIAH0:1;
1849                 uint32_t DSPIAH1:1;
1850                 uint32_t DSPIAH2:1;
1851                 uint32_t DSPIAH3:1;
1852                 uint32_t DSPIAH4:1;
1853                 uint32_t DSPIAH5:1;
1854                 uint32_t DSPIAH6:1;
1855                 uint32_t DSPIAH7:1;
1856                 uint32_t DSPIAH8:1;
1857                 uint32_t DSPIAH9:1;
1858                 uint32_t DSPIAH10:1;
1859                 uint32_t DSPIAH11:1;
1860                 uint32_t DSPIAH12:1;
1861                 uint32_t DSPIAH13:1;
1862                 uint32_t DSPIAH14:1;
1863                 uint32_t DSPIAH15:1;
1864                 uint32_t DSPIAL16:1;
1865                 uint32_t DSPIAL17:1;
1866                 uint32_t DSPIAL18:1;
1867                 uint32_t DSPIAL19:1;
1868                 uint32_t DSPIAL20:1;
1869                 uint32_t DSPIAL21:1;
1870                 uint32_t DSPIAL22:1;
1871                 uint32_t DSPIAL23:1;
1872                 uint32_t DSPIAL24:1;
1873                 uint32_t DSPIAL25:1;
1874                 uint32_t DSPIAL26:1;
1875                 uint32_t DSPIAL27:1;
1876                 uint32_t DSPIAL28:1;
1877                 uint32_t DSPIAL29:1;
1878                 uint32_t DSPIAL30:1;
1879                 uint32_t DSPIAL31:1;
1880             } B;
1881         } DSPIAHLA;
1882 
1883         int32_t SIU_reserved0D4C;  /* 0x0D4C-0x0D4F */
1884 
1885         union {               /* ETPU A Select Register */
1886             uint32_t R;
1887             struct {
1888                 uint32_t ETPUA23:1;
1889                 uint32_t ETPUA22:1;
1890                 uint32_t ETPUA21:1;
1891                 uint32_t ETPUA20:1;
1892                 uint32_t ETPUA19:1;
1893                 uint32_t ETPUA18:1;
1894                 uint32_t ETPUA17:1;
1895                 uint32_t ETPUA16:1;
1896                 uint32_t ETPUA29:1;
1897                 uint32_t ETPUA28:1;
1898                 uint32_t ETPUA27:1;
1899                 uint32_t ETPUA26:1;
1900                 uint32_t ETPUA25:1;
1901                 uint32_t ETPUA24:1;
1902                 uint32_t ETPUA31:1;
1903                 uint32_t ETPUA30:1;
1904                 uint32_t ETPUA12:1;
1905                 uint32_t ETPUA13:1;
1906                 uint32_t ETPUA14:1;
1907                 uint32_t ETPUA15:1;
1908                 uint32_t ETPUA0:1;
1909                 uint32_t ETPUA1:1;
1910                 uint32_t ETPUA2:1;
1911                 uint32_t ETPUA3:1;
1912                 uint32_t ETPUA4:1;
1913                 uint32_t ETPUA5:1;
1914                 uint32_t ETPUA6:1;
1915                 uint32_t ETPUA7:1;
1916                 uint32_t ETPUA8:1;
1917                 uint32_t ETPUA9:1;
1918                 uint32_t ETPUA10:1;
1919                 uint32_t ETPUA11:1;
1920             } B ;
1921         } ETPUAB;
1922 
1923         union {               /* EMIOS B Select Register */
1924             uint32_t R;
1925             struct {
1926                 uint32_t EMIOS11:1;
1927                 uint32_t EMIOS10:1;
1928                 uint32_t EMIOS9:1;
1929                 uint32_t EMIOS8:1;
1930                 uint32_t EMIOS6:1;
1931                 uint32_t EMIOS5:1;
1932                 uint32_t EMIOS4:1;
1933                 uint32_t EMIOS3:1;
1934                 uint32_t EMIOS2:1;
1935                 uint32_t EMIOS1:1;
1936                 uint32_t EMIOS0:1;
1937                 uint32_t EMIOS23:1;
1938                 uint32_t EMIOS15:1;
1939                 uint32_t EMIOS14:1;
1940                 uint32_t EMIOS13:1;
1941                 uint32_t EMIOS12:1;
1942                 uint32_t EMIOS23_23:1;
1943                 uint32_t EMIOS15_15:1;
1944                 uint32_t EMIOS14_14:1;
1945                 uint32_t EMIOS13_13:1;
1946                 uint32_t EMIOS12_12:1;
1947                 uint32_t EMIOS11_11:1;
1948                 uint32_t EMIOS10_10:1;
1949                 uint32_t EMIOS9_9:1;
1950                 uint32_t EMIOS8_8:1;
1951                 uint32_t EMIOS6_6:1;
1952                 uint32_t EMIOS5_5:1;
1953                 uint32_t EMIOS4_4:1;
1954                 uint32_t EMIOS3_3:1;
1955                 uint32_t EMIOS2_2:1;
1956                 uint32_t EMIOS1_1:1;
1957                 uint32_t EMIOS0_0:1;
1958             } B;
1959         } EMIOSB;
1960 
1961         union {             /* DSPIBH/L Select Register for DSPI B */
1962             uint32_t R;
1963             struct {
1964                 uint32_t DSPIBH0:1;
1965                 uint32_t DSPIBH1:1;
1966                 uint32_t DSPIBH2:1;
1967                 uint32_t DSPIBH3:1;
1968                 uint32_t DSPIBH4:1;
1969                 uint32_t DSPIBH5:1;
1970                 uint32_t DSPIBH6:1;
1971                 uint32_t DSPIBH7:1;
1972                 uint32_t DSPIBH8:1;
1973                 uint32_t DSPIBH9:1;
1974                 uint32_t DSPIBH10:1;
1975                 uint32_t DSPIBH11:1;
1976                 uint32_t DSPIBH12:1;
1977                 uint32_t DSPIBH13:1;
1978                 uint32_t DSPIBH14:1;
1979                 uint32_t DSPIBH15:1;
1980                 uint32_t DSPIBL16:1;
1981                 uint32_t DSPIBL17:1;
1982                 uint32_t DSPIBL18:1;
1983                 uint32_t DSPIBL19:1;
1984                 uint32_t DSPIBL20:1;
1985                 uint32_t DSPIBL21:1;
1986                 uint32_t DSPIBL22:1;
1987                 uint32_t DSPIBL23:1;
1988                 uint32_t DSPIBL24:1;
1989                 uint32_t DSPIBL25:1;
1990                 uint32_t DSPIBL26:1;
1991                 uint32_t DSPIBL27:1;
1992                 uint32_t DSPIBL28:1;
1993                 uint32_t DSPIBL29:1;
1994                 uint32_t DSPIBL30:1;
1995                 uint32_t DSPIBL31:1;
1996             } B;
1997         } DSPIBHLB;
1998 
1999         int32_t SIU_reserved0D5C;  /* 0x0D5C-0x0D5F */
2000 
2001         union {               /* ETPU A Select Register */
2002             uint32_t R;
2003             struct {
2004                 uint32_t ETPUA12:1;
2005                 uint32_t ETPUA13:1;
2006                 uint32_t ETPUA14:1;
2007                 uint32_t ETPUA15:1;
2008                 uint32_t ETPUA0:1;
2009                 uint32_t ETPUA1:1;
2010                 uint32_t ETPUA2:1;
2011                 uint32_t ETPUA3:1;
2012                 uint32_t ETPUA4:1;
2013                 uint32_t ETPUA5:1;
2014                 uint32_t ETPUA6:1;
2015                 uint32_t ETPUA7:1;
2016                 uint32_t ETPUA8:1;
2017                 uint32_t ETPUA9:1;
2018                 uint32_t ETPUA10:1;
2019                 uint32_t ETPUA11:1;
2020                 uint32_t ETPUA23:1;
2021                 uint32_t ETPUA22:1;
2022                 uint32_t ETPUA21:1;
2023                 uint32_t ETPUA20:1;
2024                 uint32_t ETPUA19:1;
2025                 uint32_t ETPUA18:1;
2026                 uint32_t ETPUA17:1;
2027                 uint32_t ETPUA16:1;
2028                 uint32_t ETPUA29:1;
2029                 uint32_t ETPUA28:1;
2030                 uint32_t ETPUA27:1;
2031                 uint32_t ETPUA26:1;
2032                 uint32_t ETPUA25:1;
2033                 uint32_t ETPUA24:1;
2034                 uint32_t ETPUA31:1;
2035                 uint32_t ETPUA30:1;
2036             } B ;
2037         } ETPUAC;
2038 
2039         union {               /* EMIOS C Select Register */
2040             uint32_t R;
2041             struct {
2042                 uint32_t EMIOS12:1;
2043                 uint32_t EMIOS13:1;
2044                 uint32_t EMIOS14:1;
2045                 uint32_t EMIOS15:1;
2046                 uint32_t EMIOS23:1;
2047                 uint32_t EMIOS0:1;
2048                 uint32_t EMIOS1:1;
2049                 uint32_t EMIOS2:1;
2050                 uint32_t EMIOS3:1;
2051                 uint32_t EMIOS4:1;
2052                 uint32_t EMIOS5:1;
2053                 uint32_t EMIOS6:1;
2054                 uint32_t EMIOS8:1;
2055                 uint32_t EMIOS9:1;
2056                 uint32_t EMIOS10:1;
2057                 uint32_t EMIOS11:1;
2058                 uint32_t EMIOS23_23:1;
2059                 uint32_t EMIOS22:1;
2060                 uint32_t EMIOS21:1;
2061                 uint32_t EMIOS20:1;
2062                 uint32_t EMIOS19:1;
2063                 uint32_t EMIOS18:1;
2064                 uint32_t EMIOS17:1;
2065                 uint32_t EMIOS16:1;
2066                 uint32_t EMIOS29:1;
2067                 uint32_t EMIOS28:1;
2068                 uint32_t EMIOS27:1;
2069                 uint32_t EMIOS26:1;
2070                 uint32_t EMIOS25:1;
2071                 uint32_t EMIOS24:1;
2072                 uint32_t EMIOS31:1;
2073                 uint32_t EMIOS30:1;
2074             } B;
2075         } EMIOSC;
2076 
2077         union {             /* DSPICH/L Select Register for DSPI C */
2078             uint32_t R;
2079             struct {
2080                 uint32_t DSPICH0:1;
2081                 uint32_t DSPICH1:1;
2082                 uint32_t DSPICH2:1;
2083                 uint32_t DSPICH3:1;
2084                 uint32_t DSPICH4:1;
2085                 uint32_t DSPICH5:1;
2086                 uint32_t DSPICH6:1;
2087                 uint32_t DSPICH7:1;
2088                 uint32_t DSPICH8:1;
2089                 uint32_t DSPICH9:1;
2090                 uint32_t DSPICH10:1;
2091                 uint32_t DSPICH11:1;
2092                 uint32_t DSPICH12:1;
2093                 uint32_t DSPICH13:1;
2094                 uint32_t DSPICH14:1;
2095                 uint32_t DSPICH15:1;
2096                 uint32_t DSPICL16:1;
2097                 uint32_t DSPICL17:1;
2098                 uint32_t DSPICL18:1;
2099                 uint32_t DSPICL19:1;
2100                 uint32_t DSPICL20:1;
2101                 uint32_t DSPICL21:1;
2102                 uint32_t DSPICL22:1;
2103                 uint32_t DSPICL23:1;
2104                 uint32_t DSPICL24:1;
2105                 uint32_t DSPICL25:1;
2106                 uint32_t DSPICL26:1;
2107                 uint32_t DSPICL27:1;
2108                 uint32_t DSPICL28:1;
2109                 uint32_t DSPICL29:1;
2110                 uint32_t DSPICL30:1;
2111                 uint32_t DSPICL31:1;
2112             } B;
2113         } DSPICHLC;
2114 
2115         int32_t SIU_reserved0D6C;  /* 0x0D6C-0x0D6F */
2116 
2117         union {               /* ETPU B Select Register */
2118             uint32_t R;
2119             struct {
2120                 uint32_t ETPUB21:1;
2121                 uint32_t ETPUB20:1;
2122                 uint32_t ETPUB19:1;
2123                 uint32_t ETPUB18:1;
2124                 uint32_t ETPUB17:1;
2125                 uint32_t ETPUB16:1;
2126                 uint32_t:4;
2127                 uint32_t ETPUB29:1;
2128                 uint32_t ETPUB28:1;
2129                 uint32_t ETPUB27:1;
2130                 uint32_t ETPUB26:1;
2131                 uint32_t ETPUB25:1;
2132                 uint32_t ETPUB24:1;
2133                 uint32_t:16;
2134             } B ;
2135         } ETPUBD;
2136 
2137         union {               /* EMIOS D Select Register */
2138             uint32_t R;
2139             struct {
2140                 uint32_t:6;
2141                 uint32_t EMIOS11:1;
2142                 uint32_t EMIOS10:1;
2143                 uint32_t EMIOS13:1;
2144                 uint32_t EMIOS12:1;
2145                 uint32_t:22;
2146             } B;
2147         } EMIOSD;
2148 
2149         union {             /* DSPIDH/L Select Register for DSPI D */
2150             uint32_t R;
2151             struct {
2152                 uint32_t:32;
2153             } B;
2154         } DSPIDHLD;
2155 
2156         int32_t SIU_reserved0D7C;  /* 0x0D7C-0x0D7F */
2157 
2158         int32_t SIU_reserved0D80[32];  /* 0x0D80-0x0DFF */
2159 
2160         union {                 /* GPIO Pin Data Input Registers */
2161             uint8_t R;
2162             struct {
2163                 uint8_t:7;
2164                 uint8_t PDI:1;
2165             } B;
2166         } GPDI0_511[512];
2167 
2168         uint32_t SIU_reserved1000[3072];  /* 0x1000-0x3FFF */
2169     };
2170 
2171 /****************************************************************************/
2172 /*                          MODULE : EMIOS                                  */
2173 /****************************************************************************/
2174 
2175     struct EMIOS_tag {
2176 
2177         union EMIOS_MCR_tag {    /* Module Configuration Register */
2178             uint32_t R;
2179             struct {
2180                 uint32_t:1;
2181                 uint32_t MDIS:1;
2182                 uint32_t FRZ:1;
2183                 uint32_t GTBE:1;
2184                 uint32_t ETB:1;
2185                 uint32_t GPREN:1;
2186                 uint32_t:6;
2187                 uint32_t SRV:4;
2188                 uint32_t GPRE:8;
2189                 uint32_t:8;
2190             } B;
2191         } MCR;
2192 
2193         union {                  /* Global FLAG Register */
2194             uint32_t R;
2195             struct {
2196                 uint32_t F31:1;
2197                 uint32_t F30:1;
2198                 uint32_t F29:1;
2199                 uint32_t F28:1;
2200                 uint32_t F27:1;
2201                 uint32_t F26:1;
2202                 uint32_t F25:1;
2203                 uint32_t F24:1;
2204                 uint32_t F23:1;
2205                 uint32_t F22:1;
2206                 uint32_t F21:1;
2207                 uint32_t F20:1;
2208                 uint32_t F19:1;
2209                 uint32_t F18:1;
2210                 uint32_t F17:1;
2211                 uint32_t F16:1;
2212                 uint32_t F15:1;
2213                 uint32_t F14:1;
2214                 uint32_t F13:1;
2215                 uint32_t F12:1;
2216                 uint32_t F11:1;
2217                 uint32_t F10:1;
2218                 uint32_t F9:1;
2219                 uint32_t F8:1;
2220                 uint32_t F7:1;
2221                 uint32_t F6:1;
2222                 uint32_t F5:1;
2223                 uint32_t F4:1;
2224                 uint32_t F3:1;
2225                 uint32_t F2:1;
2226                 uint32_t F1:1;
2227                 uint32_t F0:1;
2228             } B;
2229         } GFR;
2230 
2231         union {                 /* Output Update Disable Register */
2232             uint32_t R;
2233             struct {
2234                 uint32_t OU31:1;
2235                 uint32_t OU30:1;
2236                 uint32_t OU29:1;
2237                 uint32_t OU28:1;
2238                 uint32_t OU27:1;
2239                 uint32_t OU26:1;
2240                 uint32_t OU25:1;
2241                 uint32_t OU24:1;
2242                 uint32_t OU23:1;
2243                 uint32_t OU22:1;
2244                 uint32_t OU21:1;
2245                 uint32_t OU20:1;
2246                 uint32_t OU19:1;
2247                 uint32_t OU18:1;
2248                 uint32_t OU17:1;
2249                 uint32_t OU16:1;
2250                 uint32_t OU15:1;
2251                 uint32_t OU14:1;
2252                 uint32_t OU13:1;
2253                 uint32_t OU12:1;
2254                 uint32_t OU11:1;
2255                 uint32_t OU10:1;
2256                 uint32_t OU9:1;
2257                 uint32_t OU8:1;
2258                 uint32_t OU7:1;
2259                 uint32_t OU6:1;
2260                 uint32_t OU5:1;
2261                 uint32_t OU4:1;
2262                 uint32_t OU3:1;
2263                 uint32_t OU2:1;
2264                 uint32_t OU1:1;
2265                 uint32_t OU0:1;
2266             } B;
2267         } OUDR;
2268 
2269         uint32_t eMIOS_reserved000C[5]; /* 0x000C-0x001F */
2270 
2271         struct EMIOS_CH_tag {
2272             union {              /* Channel A Data Register */
2273                 uint32_t R;
2274             } CADR;
2275 
2276             union {              /* Channel B Data Register */
2277                 uint32_t R;
2278             } CBDR;
2279 
2280             union {              /* Channel Counter Register */
2281                 uint32_t R;
2282             } CCNTR;
2283 
2284             union EMIOS_CCR_tag {/* Channel Control Register */
2285                 uint32_t R;
2286                 struct {
2287                     uint32_t FREN:1;
2288                     uint32_t ODIS:1;
2289                     uint32_t ODISSL:2;
2290                     uint32_t UCPRE:2;
2291                     uint32_t UCPREN:1;
2292                     uint32_t DMA:1;
2293                     uint32_t:1;
2294                     uint32_t IF:4;
2295                     uint32_t FCK:1;
2296                     uint32_t FEN:1;
2297                     uint32_t:3;
2298                     uint32_t FORCMA:1;
2299                     uint32_t FORCMB:1;
2300                     uint32_t:1;
2301                     uint32_t BSL:2;
2302                     uint32_t EDSEL:1;
2303                     uint32_t EDPOL:1;
2304                     uint32_t MODE:7;
2305                 } B;
2306             } CCR;
2307 
2308             union EMIOS_CSR_tag {/* Channel Status Register */
2309                 uint32_t R;
2310                 struct {
2311                     uint32_t OVR:1;
2312                     uint32_t:15;
2313                     uint32_t OVFL:1;
2314                     uint32_t:12;
2315                     uint32_t UCIN:1;
2316                     uint32_t UCOUT:1;
2317                     uint32_t FLAG:1;
2318                 } B;
2319             } CSR;
2320 
2321             union {              /* Alternate Channel A Data Register */
2322                 uint32_t R;
2323             } ALTA;
2324 
2325             uint32_t eMIOS_channel_reserved0018[2];  /* 0x0018-0x001F */
2326 
2327         } CH[32];
2328 
2329         uint32_t eMIOS_reserved0420[3832];  /* 0x0420-0x3FFF */
2330 
2331     };
2332 
2333 /****************************************************************************/
2334 /*                          MODULE : PMC                                    */
2335 /****************************************************************************/
2336 
2337     struct PMC_tag {
2338 
2339         union {
2340             uint32_t R;
2341             struct {
2342                 uint32_t LVRER:1;
2343                 uint32_t LVREH:1;
2344                 uint32_t LVRE50:1;
2345                 uint32_t LVRE33:1;
2346                 uint32_t LVREC:1;
2347                 uint32_t LVREA:1;
2348                 uint32_t:1;
2349                 uint32_t:1;
2350                 uint32_t LVIER:1;
2351                 uint32_t LVIEH:1;
2352                 uint32_t LVIE50:1;
2353                 uint32_t LVIE33:1;
2354                 uint32_t LVIEC:1;
2355                 uint32_t LVIEA:1;
2356                 uint32_t:1;
2357                 uint32_t TLK:1;
2358                 uint32_t:16;
2359             } B;
2360         } MCR;                  /* Module Configuration Register */
2361 
2362         union {
2363             uint32_t R;
2364             struct {
2365                 uint32_t :8;
2366                 uint32_t LVDATRIM:4;
2367                 uint32_t LVDREGTRIM:4;
2368                 uint32_t VDD33TRIM:4;
2369                 uint32_t LVD33TRIM:4;
2370                 uint32_t VDDCTRIM:4;
2371                 uint32_t LVDCTRIM:4;
2372             } B;
2373         } TRIMR;                /* Trimming register */
2374 
2375         union {
2376             uint32_t R;
2377             struct {
2378                 uint32_t :5;
2379                 uint32_t LVFSTBY:1;
2380                 uint32_t BGRDY:1;
2381                 uint32_t BGTS:1;
2382                 uint32_t :5;
2383                 uint32_t LVFCSTBY:1;
2384                 uint32_t :2;
2385                 uint32_t LVFCR:1;
2386                 uint32_t LVFCH:1;
2387                 uint32_t LVFC50:1;
2388                 uint32_t LVFC33:1;
2389                 uint32_t LVFCC:1;
2390                 uint32_t LVFCA:1;
2391                 uint32_t :2;
2392                 uint32_t LVFR:1;
2393                 uint32_t LVFH:1;
2394                 uint32_t LVF50:1;
2395                 uint32_t LVF33:1;
2396                 uint32_t LVFC:1;
2397                 uint32_t LVFA:1;
2398                 uint32_t :2;
2399             } B;
2400         } SR;                /* status register */
2401 
2402         uint32_t PMC_reserved000C[4093];  /* 0x000C-0x3FFF */
2403     };
2404 
2405 /****************************************************************************/
2406 /*                              MODULE :ETPU                                */
2407 /****************************************************************************/
2408 
2409 /***************************Configuration Registers**************************/
2410 
2411     struct ETPU_tag {
2412         union {                 /* MODULE CONFIGURATION REGISTER */
2413             uint32_t R;
2414             struct {
2415                 uint32_t GEC:1;        /* Global Exception Clear */
2416                 uint32_t SDMERR:1;     /* SDM Read Error */
2417                 uint32_t WDTOA:1;      /* Watchdog Timeout-eTPU_A */
2418                 uint32_t WDTOB:1;      /* Watchdog Timeout-eTPU_B */
2419                 uint32_t MGE1:1;       /* Microcode Global Exception-ETPU_A */
2420                 uint32_t MGE2:1;       /* Microcode Global Exception-ETPU_B */
2421                 uint32_t ILF1:1;       /* Illegal Instruction Flag-ETPU_A */
2422                 uint32_t ILF2:1;       /* Illegal Instruction Flag-ETPU_B */
2423                 uint32_t:3;
2424                 uint32_t SCMSIZE:5;    /* Shared Code Memory size */
2425                 uint32_t:4;
2426                 uint32_t SCMMISC:1;    /* SCM MISC Complete/Clear */
2427                 uint32_t SCMMISF:1;    /* SCM MISC Flag */
2428                 uint32_t SCMMISEN:1;   /* SCM MISC Enable */
2429                 uint32_t:2;
2430                 uint32_t VIS:1;        /* SCM Visability */
2431                 uint32_t:5;
2432                 uint32_t GTBE:1;       /* Global Time Base Enable */
2433             } B;
2434         } MCR;
2435 
2436         union {                 /* COHERENT DUAL-PARAMETER CONTROL */
2437             uint32_t R;
2438             struct {
2439                 uint32_t STS:1;        /* Start Status bit */
2440                 uint32_t CTBASE:5;     /* Channel Transfer Base */
2441                 uint32_t PBASE:10;     /* Parameter Buffer Base Address */
2442                 uint32_t PWIDTH:1;     /* Parameter Width */
2443                 uint32_t PARAM0:7;     /* Channel Parameter 0 */
2444                 uint32_t WR:1;         /* Read/Write selection */
2445                 uint32_t PARAM1:7;     /* Channel Parameter 1 */
2446             } B;
2447         } CDCR;
2448 
2449         uint32_t eTPU_reserved0008;  /* 0x0008-0x000B */
2450 
2451         union {                 /* MISC Compare Register */
2452             uint32_t R;
2453             struct {
2454                 uint32_t ETPUMISCCMP:32;
2455             } B;
2456         } MISCCMPR;
2457 
2458         union {                 /* SCM off-range Date Register */
2459             uint32_t R;
2460             struct {
2461                 uint32_t ETPUSCMOFFDATA:32;
2462             } B;
2463         } SCMOFFDATAR;
2464 
2465         union {                 /* ETPU_A Configuration Register */
2466             uint32_t R;
2467             struct {
2468                 uint32_t FEND:1;       /* Force END */
2469                 uint32_t MDIS:1;       /* Low power Stop */
2470                 uint32_t:1;
2471                 uint32_t STF:1;        /* Stop Flag */
2472                 uint32_t:4;
2473                 uint32_t HLTF:1;       /* Halt Mode Flag */
2474                 uint32_t:3;
2475                 uint32_t FCSS:1;       /* Filter Clock Source Select */
2476                 uint32_t FPSCK:3;      /* Filter Prescaler Clock Control */
2477                 uint32_t CDFC:2;
2478                 uint32_t:1;
2479                 uint32_t ERBA:5;       /* Engine Relative Base Address */
2480                 uint32_t SPPDIS:1;     /* Schedule Priority Passing Disable */
2481                 uint32_t:2;
2482                 uint32_t ETB:5;        /* Entry Table Base */
2483             } B;
2484         } ECR_A;
2485 
2486         union {                 /* ETPU_B Configuration Register */
2487             uint32_t R;
2488             struct {
2489                 uint32_t FEND:1;       /* Force END */
2490                 uint32_t MDIS:1;       /* Low power Stop */
2491                 uint32_t:1;
2492                 uint32_t STF:1;        /* Stop Flag */
2493                 uint32_t:4;
2494                 uint32_t HLTF:1;       /* Halt Mode Flag */
2495                 uint32_t:3;
2496                 uint32_t FCSS:1;       /* Filter Clock Source Select */
2497                 uint32_t FPSCK:3;      /* Filter Prescaler Clock Control */
2498                 uint32_t CDFC:2;
2499                 uint32_t:1;
2500                 uint32_t ERBA:5;       /* Engine Relative Base Address */
2501                 uint32_t SPPDIS:1;     /* Schedule Priority Passing Disable */
2502                 uint32_t:2;
2503                 uint32_t ETB:5;        /* Entry Table Base */
2504             } B;
2505         } ECR_B;
2506 
2507         uint32_t eTPU_reserved001C;  /* 0x001C-0x001F */
2508 
2509         union {                 /* ETPU_A Timebase Configuration Register */
2510             uint32_t R;
2511             struct {
2512                 uint32_t TCR2CTL:3;     /* TCR2 Clock/Gate Control */
2513                 uint32_t TCRCF:2;       /* TCRCLK Signal Filter Control */
2514                 uint32_t AM:2;          /* Angle Mode */
2515                 uint32_t:3;
2516                 uint32_t TCR2P:6;       /* TCR2 Prescaler Control */
2517                 uint32_t TCR1CTL:2;     /* TCR1 Clock/Gate Control */
2518                 uint32_t TCR1CS:1;      /* TCR1 Clock Source */
2519                 uint32_t:5;
2520                 uint32_t TCR1P:8;       /* TCR1 Prescaler Control */
2521             } B;
2522         } TBCR_A;
2523 
2524         union {                 /* ETPU_A TCR1 Visibility Register */
2525             uint32_t R;
2526             struct {
2527                 uint32_t:8;
2528                 uint32_t TCR1:24;
2529             } B;
2530         } TB1R_A;
2531 
2532         union {                 /* ETPU_A TCR2 Visibility Register */
2533             uint32_t R;
2534             struct {
2535                 uint32_t:8;
2536                 uint32_t TCR2:24;
2537             } B;
2538         } TB2R_A;
2539 
2540         union {                 /* ETPU_A STAC Configuration Register */
2541             uint32_t R;
2542             struct {
2543                 uint32_t REN1:1;       /* Resource Enable TCR1 */
2544                 uint32_t RSC1:1;       /* Resource Control TCR1 */
2545                 uint32_t:2;
2546                 uint32_t SERVER_ID1:4;   /* TCR1 Server ID */
2547                 uint32_t:4;
2548                 uint32_t SRV1:4;       /* Resource Server Slot */
2549                 uint32_t REN2:1;       /* Resource Enable TCR2 */
2550                 uint32_t RSC2:1;       /* Resource Control TCR2 */
2551                 uint32_t:2;
2552                 uint32_t SERVER_ID2:4;   /* TCR2 Server ID */
2553                 uint32_t:4;
2554                 uint32_t SRV2:4;       /* Resource Server Slot */
2555             } B;
2556         } REDCR_A;
2557 
2558         uint32_t eTPU_reserved0030[4];  /* 0x0030-0x003F */
2559 
2560         union {                 /* ETPU_B Timebase Configuration Register */
2561             uint32_t R;
2562             struct {
2563                 uint32_t TCR2CTL:3;     /* TCR2 Clock/Gate Control */
2564                 uint32_t TCRCF:2;       /* TCRCLK Signal Filter Control */
2565                 uint32_t AM:2;          /* Angle Mode */
2566                 uint32_t:3;
2567                 uint32_t TCR2P:6;       /* TCR2 Prescaler Control */
2568                 uint32_t TCR1CTL:2;     /* TCR1 Clock/Gate Control */
2569                 uint32_t TCR1CS:1;      /* TCR1 Clock Source */
2570                 uint32_t:5;
2571                 uint32_t TCR1P:8;       /* TCR1 Prescaler Control */
2572             } B;
2573         } TBCR_B;
2574 
2575         union {                 /* ETPU_B TCR1 Visibility Register */
2576             uint32_t R;
2577             struct {
2578                 uint32_t:8;
2579                 uint32_t TCR1:24;
2580             } B;
2581         } TB1R_B;
2582 
2583         union {                 /* ETPU_B TCR2 Visibility Register */
2584             uint32_t R;
2585             struct {
2586                 uint32_t:8;
2587                 uint32_t TCR2:24;
2588             } B;
2589         } TB2R_B;
2590 
2591         union {                 /* ETPU_B STAC Configuration Register */
2592             uint32_t R;
2593             struct {
2594                 uint32_t REN1:1;       /* Resource Enable TCR1 */
2595                 uint32_t RSC1:1;       /* Resource Control TCR1 */
2596                 uint32_t:2;
2597                 uint32_t SERVER_ID1:4;   /* TCR1 Server ID */
2598                 uint32_t:4;
2599                 uint32_t SRV1:4;       /* Resource Server Slot */
2600                 uint32_t REN2:1;       /* Resource Enable TCR2 */
2601                 uint32_t RSC2:1;       /* Resource Control TCR2 */
2602                 uint32_t:2;
2603                 uint32_t SERVER_ID2:4;   /* TCR2 Server ID */
2604                 uint32_t:4;
2605                 uint32_t SRV2:4;       /* Resource Server Slot */
2606             } B;
2607         } REDCR_B;
2608 
2609         uint32_t eTPU_reserved0050[4];  /* 0x0050-0x005F */
2610 
2611         union {                 /* Watchdog Timer Register A */
2612             uint32_t R;
2613             struct {
2614                 uint32_t WDM:2;          /* Watchdog Mode */
2615                 uint32_t:14;
2616                 uint32_t WDCNT:16;       /* Watchdog Count */
2617             } B;
2618         } WDTR_A;
2619 
2620         uint32_t eTPU_reserved0064;  /* 0x0064-0x0067 */
2621 
2622         union {                 /* Idle Counter Register A*/
2623             uint32_t R;
2624             struct {
2625                 uint32_t IDLE_CNT:31;
2626                 uint32_t ICLR:1;       /* Idle Clear */
2627             } B;
2628 
2629         } IDLE_A;
2630 
2631         uint32_t eTPU_reserved006C;  /* 0x006C-0x006F */
2632 
2633         union {                 /* Watchdog Timer Register B */
2634             uint32_t R;
2635             struct {
2636                 uint32_t WDM:2;          /* Watchdog Mode */
2637                 uint32_t:14;
2638                 uint32_t WDCNT:16;       /* Watchdog Count */
2639             } B;
2640         } WDTR_B;
2641 
2642         uint32_t eTPU_reserved0074;  /* 0x0074-0x0077 */
2643 
2644         union {                 /* Idle Counter Register B*/
2645             uint32_t R;
2646             struct {
2647                 uint32_t IDLE_CNT:31;
2648                 uint32_t ICLR:1;       /* Idle Clear */
2649             } B;
2650         } IDLE_B;
2651 
2652         uint32_t eTPU_reserved007C;  /* 0x007C-0x007F */
2653 
2654         uint32_t eTPU_reserved0080[96];  /* 0x0080-0x01FF */
2655 
2656 /*****************************Status and Control Registers**************************/
2657 
2658         union {                 /* ETPU_A Channel Interrut Status */
2659             uint32_t R;
2660             struct {
2661                 uint32_t CIS31:1;      /* Channel 31 Interrut Status */
2662                 uint32_t CIS30:1;      /* Channel 30 Interrut Status */
2663                 uint32_t CIS29:1;      /* Channel 29 Interrut Status */
2664                 uint32_t CIS28:1;      /* Channel 28 Interrut Status */
2665                 uint32_t CIS27:1;      /* Channel 27 Interrut Status */
2666                 uint32_t CIS26:1;      /* Channel 26 Interrut Status */
2667                 uint32_t CIS25:1;      /* Channel 25 Interrut Status */
2668                 uint32_t CIS24:1;      /* Channel 24 Interrut Status */
2669                 uint32_t CIS23:1;      /* Channel 23 Interrut Status */
2670                 uint32_t CIS22:1;      /* Channel 22 Interrut Status */
2671                 uint32_t CIS21:1;      /* Channel 21 Interrut Status */
2672                 uint32_t CIS20:1;      /* Channel 20 Interrut Status */
2673                 uint32_t CIS19:1;      /* Channel 19 Interrut Status */
2674                 uint32_t CIS18:1;      /* Channel 18 Interrut Status */
2675                 uint32_t CIS17:1;      /* Channel 17 Interrut Status */
2676                 uint32_t CIS16:1;      /* Channel 16 Interrut Status */
2677                 uint32_t CIS15:1;      /* Channel 15 Interrut Status */
2678                 uint32_t CIS14:1;      /* Channel 14 Interrut Status */
2679                 uint32_t CIS13:1;      /* Channel 13 Interrut Status */
2680                 uint32_t CIS12:1;      /* Channel 12 Interrut Status */
2681                 uint32_t CIS11:1;      /* Channel 11 Interrut Status */
2682                 uint32_t CIS10:1;      /* Channel 10 Interrut Status */
2683                 uint32_t CIS9:1;       /* Channel 9 Interrut Status */
2684                 uint32_t CIS8:1;       /* Channel 8 Interrut Status */
2685                 uint32_t CIS7:1;       /* Channel 7 Interrut Status */
2686                 uint32_t CIS6:1;       /* Channel 6 Interrut Status */
2687                 uint32_t CIS5:1;       /* Channel 5 Interrut Status */
2688                 uint32_t CIS4:1;       /* Channel 4 Interrut Status */
2689                 uint32_t CIS3:1;       /* Channel 3 Interrut Status */
2690                 uint32_t CIS2:1;       /* Channel 2 Interrut Status */
2691                 uint32_t CIS1:1;       /* Channel 1 Interrut Status */
2692                 uint32_t CIS0:1;       /* Channel 0 Interrut Status */
2693             } B;
2694         } CISR_A;
2695 
2696         union {                 /* ETPU_B Channel Interruput Status */
2697             uint32_t R;
2698             struct {
2699                 uint32_t CIS31:1;      /* Channel 31 Interrut Status */
2700                 uint32_t CIS30:1;      /* Channel 30 Interrut Status */
2701                 uint32_t CIS29:1;      /* Channel 29 Interrut Status */
2702                 uint32_t CIS28:1;      /* Channel 28 Interrut Status */
2703                 uint32_t CIS27:1;      /* Channel 27 Interrut Status */
2704                 uint32_t CIS26:1;      /* Channel 26 Interrut Status */
2705                 uint32_t CIS25:1;      /* Channel 25 Interrut Status */
2706                 uint32_t CIS24:1;      /* Channel 24 Interrut Status */
2707                 uint32_t CIS23:1;      /* Channel 23 Interrut Status */
2708                 uint32_t CIS22:1;      /* Channel 22 Interrut Status */
2709                 uint32_t CIS21:1;      /* Channel 21 Interrut Status */
2710                 uint32_t CIS20:1;      /* Channel 20 Interrut Status */
2711                 uint32_t CIS19:1;      /* Channel 19 Interrut Status */
2712                 uint32_t CIS18:1;      /* Channel 18 Interrut Status */
2713                 uint32_t CIS17:1;      /* Channel 17 Interrut Status */
2714                 uint32_t CIS16:1;      /* Channel 16 Interrut Status */
2715                 uint32_t CIS15:1;      /* Channel 15 Interrut Status */
2716                 uint32_t CIS14:1;      /* Channel 14 Interrut Status */
2717                 uint32_t CIS13:1;      /* Channel 13 Interrut Status */
2718                 uint32_t CIS12:1;      /* Channel 12 Interrut Status */
2719                 uint32_t CIS11:1;      /* Channel 11 Interrut Status */
2720                 uint32_t CIS10:1;      /* Channel 10 Interrut Status */
2721                 uint32_t CIS9:1;       /* Channel 9 Interrut Status */
2722                 uint32_t CIS8:1;       /* Channel 8 Interrut Status */
2723                 uint32_t CIS7:1;       /* Channel 7 Interrut Status */
2724                 uint32_t CIS6:1;       /* Channel 6 Interrut Status */
2725                 uint32_t CIS5:1;       /* Channel 5 Interrut Status */
2726                 uint32_t CIS4:1;       /* Channel 4 Interrut Status */
2727                 uint32_t CIS3:1;       /* Channel 3 Interrut Status */
2728                 uint32_t CIS2:1;       /* Channel 2 Interrut Status */
2729                 uint32_t CIS1:1;       /* Channel 1 Interrupt Status */
2730                 uint32_t CIS0:1;       /* Channel 0 Interrupt Status */
2731             } B;
2732         } CISR_B;
2733 
2734         uint32_t eTPU_reserved0208[2];  /* 0x0208-0x020F */
2735 
2736         union {                 /* ETPU_A Data Transfer Request Status */
2737             uint32_t R;
2738             struct {
2739                 uint32_t DTRS31:1;     /* Channel 31 Data Transfer Request Status */
2740                 uint32_t DTRS30:1;     /* Channel 30 Data Transfer Request Status */
2741                 uint32_t DTRS29:1;     /* Channel 29 Data Transfer Request Status */
2742                 uint32_t DTRS28:1;     /* Channel 28 Data Transfer Request Status */
2743                 uint32_t DTRS27:1;     /* Channel 27 Data Transfer Request Status */
2744                 uint32_t DTRS26:1;     /* Channel 26 Data Transfer Request Status */
2745                 uint32_t DTRS25:1;     /* Channel 25 Data Transfer Request Status */
2746                 uint32_t DTRS24:1;     /* Channel 24 Data Transfer Request Status */
2747                 uint32_t DTRS23:1;     /* Channel 23 Data Transfer Request Status */
2748                 uint32_t DTRS22:1;     /* Channel 22 Data Transfer Request Status */
2749                 uint32_t DTRS21:1;     /* Channel 21 Data Transfer Request Status */
2750                 uint32_t DTRS20:1;     /* Channel 20 Data Transfer Request Status */
2751                 uint32_t DTRS19:1;     /* Channel 19 Data Transfer Request Status */
2752                 uint32_t DTRS18:1;     /* Channel 18 Data Transfer Request Status */
2753                 uint32_t DTRS17:1;     /* Channel 17 Data Transfer Request Status */
2754                 uint32_t DTRS16:1;     /* Channel 16 Data Transfer Request Status */
2755                 uint32_t DTRS15:1;     /* Channel 15 Data Transfer Request Status */
2756                 uint32_t DTRS14:1;     /* Channel 14 Data Transfer Request Status */
2757                 uint32_t DTRS13:1;     /* Channel 13 Data Transfer Request Status */
2758                 uint32_t DTRS12:1;     /* Channel 12 Data Transfer Request Status */
2759                 uint32_t DTRS11:1;     /* Channel 11 Data Transfer Request Status */
2760                 uint32_t DTRS10:1;     /* Channel 10 Data Transfer Request Status */
2761                 uint32_t DTRS9:1;      /* Channel 9 Data Transfer Request Status */
2762                 uint32_t DTRS8:1;      /* Channel 8 Data Transfer Request Status */
2763                 uint32_t DTRS7:1;      /* Channel 7 Data Transfer Request Status */
2764                 uint32_t DTRS6:1;      /* Channel 6 Data Transfer Request Status */
2765                 uint32_t DTRS5:1;      /* Channel 5 Data Transfer Request Status */
2766                 uint32_t DTRS4:1;      /* Channel 4 Data Transfer Request Status */
2767                 uint32_t DTRS3:1;      /* Channel 3 Data Transfer Request Status */
2768                 uint32_t DTRS2:1;      /* Channel 2 Data Transfer Request Status */
2769                 uint32_t DTRS1:1;      /* Channel 1 Data Transfer Request Status */
2770                 uint32_t DTRS0:1;      /* Channel 0 Data Transfer Request Status */
2771             } B;
2772         } CDTRSR_A;
2773 
2774         union {                 /* ETPU_B Data Transfer Request Status */
2775             uint32_t R;
2776             struct {
2777                 uint32_t DTRS31:1;     /* Channel 31 Data Transfer Request Status */
2778                 uint32_t DTRS30:1;     /* Channel 30 Data Transfer Request Status */
2779                 uint32_t DTRS29:1;     /* Channel 29 Data Transfer Request Status */
2780                 uint32_t DTRS28:1;     /* Channel 28 Data Transfer Request Status */
2781                 uint32_t DTRS27:1;     /* Channel 27 Data Transfer Request Status */
2782                 uint32_t DTRS26:1;     /* Channel 26 Data Transfer Request Status */
2783                 uint32_t DTRS25:1;     /* Channel 25 Data Transfer Request Status */
2784                 uint32_t DTRS24:1;     /* Channel 24 Data Transfer Request Status */
2785                 uint32_t DTRS23:1;     /* Channel 23 Data Transfer Request Status */
2786                 uint32_t DTRS22:1;     /* Channel 22 Data Transfer Request Status */
2787                 uint32_t DTRS21:1;     /* Channel 21 Data Transfer Request Status */
2788                 uint32_t DTRS20:1;     /* Channel 20 Data Transfer Request Status */
2789                 uint32_t DTRS19:1;     /* Channel 19 Data Transfer Request Status */
2790                 uint32_t DTRS18:1;     /* Channel 18 Data Transfer Request Status */
2791                 uint32_t DTRS17:1;     /* Channel 17 Data Transfer Request Status */
2792                 uint32_t DTRS16:1;     /* Channel 16 Data Transfer Request Status */
2793                 uint32_t DTRS15:1;     /* Channel 15 Data Transfer Request Status */
2794                 uint32_t DTRS14:1;     /* Channel 14 Data Transfer Request Status */
2795                 uint32_t DTRS13:1;     /* Channel 13 Data Transfer Request Status */
2796                 uint32_t DTRS12:1;     /* Channel 12 Data Transfer Request Status */
2797                 uint32_t DTRS11:1;     /* Channel 11 Data Transfer Request Status */
2798                 uint32_t DTRS10:1;     /* Channel 10 Data Transfer Request Status */
2799                 uint32_t DTRS9:1;      /* Channel 9 Data Transfer Request Status */
2800                 uint32_t DTRS8:1;      /* Channel 8 Data Transfer Request Status */
2801                 uint32_t DTRS7:1;      /* Channel 7 Data Transfer Request Status */
2802                 uint32_t DTRS6:1;      /* Channel 6 Data Transfer Request Status */
2803                 uint32_t DTRS5:1;      /* Channel 5 Data Transfer Request Status */
2804                 uint32_t DTRS4:1;      /* Channel 4 Data Transfer Request Status */
2805                 uint32_t DTRS3:1;      /* Channel 3 Data Transfer Request Status */
2806                 uint32_t DTRS2:1;      /* Channel 2 Data Transfer Request Status */
2807                 uint32_t DTRS1:1;      /* Channel 1 Data Transfer Request Status */
2808                 uint32_t DTRS0:1;      /* Channel 0 Data Transfer Request Status */
2809             } B;
2810         } CDTRSR_B;
2811 
2812         uint32_t eTPU_reserved0218[2];  /* 0x0218-0x021F */
2813 
2814         union {                 /* ETPU_A Interruput Overflow Status */
2815             uint32_t R;
2816             struct {
2817                 uint32_t CIOS31:1;     /* Channel 31 Interruput Overflow Status */
2818                 uint32_t CIOS30:1;     /* Channel 30 Interruput Overflow Status */
2819                 uint32_t CIOS29:1;     /* Channel 29 Interruput Overflow Status */
2820                 uint32_t CIOS28:1;     /* Channel 28 Interruput Overflow Status */
2821                 uint32_t CIOS27:1;     /* Channel 27 Interruput Overflow Status */
2822                 uint32_t CIOS26:1;     /* Channel 26 Interruput Overflow Status */
2823                 uint32_t CIOS25:1;     /* Channel 25 Interruput Overflow Status */
2824                 uint32_t CIOS24:1;     /* Channel 24 Interruput Overflow Status */
2825                 uint32_t CIOS23:1;     /* Channel 23 Interruput Overflow Status */
2826                 uint32_t CIOS22:1;     /* Channel 22 Interruput Overflow Status */
2827                 uint32_t CIOS21:1;     /* Channel 21 Interruput Overflow Status */
2828                 uint32_t CIOS20:1;     /* Channel 20 Interruput Overflow Status */
2829                 uint32_t CIOS19:1;     /* Channel 19 Interruput Overflow Status */
2830                 uint32_t CIOS18:1;     /* Channel 18 Interruput Overflow Status */
2831                 uint32_t CIOS17:1;     /* Channel 17 Interruput Overflow Status */
2832                 uint32_t CIOS16:1;     /* Channel 16 Interruput Overflow Status */
2833                 uint32_t CIOS15:1;     /* Channel 15 Interruput Overflow Status */
2834                 uint32_t CIOS14:1;     /* Channel 14 Interruput Overflow Status */
2835                 uint32_t CIOS13:1;     /* Channel 13 Interruput Overflow Status */
2836                 uint32_t CIOS12:1;     /* Channel 12 Interruput Overflow Status */
2837                 uint32_t CIOS11:1;     /* Channel 11 Interruput Overflow Status */
2838                 uint32_t CIOS10:1;     /* Channel 10 Interruput Overflow Status */
2839                 uint32_t CIOS9:1;      /* Channel 9 Interruput Overflow Status */
2840                 uint32_t CIOS8:1;      /* Channel 8 Interruput Overflow Status */
2841                 uint32_t CIOS7:1;      /* Channel 7 Interruput Overflow Status */
2842                 uint32_t CIOS6:1;      /* Channel 6 Interruput Overflow Status */
2843                 uint32_t CIOS5:1;      /* Channel 5 Interruput Overflow Status */
2844                 uint32_t CIOS4:1;      /* Channel 4 Interruput Overflow Status */
2845                 uint32_t CIOS3:1;      /* Channel 3 Interruput Overflow Status */
2846                 uint32_t CIOS2:1;      /* Channel 2 Interruput Overflow Status */
2847                 uint32_t CIOS1:1;      /* Channel 1 Interruput Overflow Status */
2848                 uint32_t CIOS0:1;      /* Channel 0 Interruput Overflow Status */
2849             } B;
2850         } CIOSR_A;
2851 
2852         union {                 /* ETPU_B Interruput Overflow Status */
2853             uint32_t R;
2854             struct {
2855                 uint32_t CIOS31:1;     /* Channel 31 Interruput Overflow Status */
2856                 uint32_t CIOS30:1;     /* Channel 30 Interruput Overflow Status */
2857                 uint32_t CIOS29:1;     /* Channel 29 Interruput Overflow Status */
2858                 uint32_t CIOS28:1;     /* Channel 28 Interruput Overflow Status */
2859                 uint32_t CIOS27:1;     /* Channel 27 Interruput Overflow Status */
2860                 uint32_t CIOS26:1;     /* Channel 26 Interruput Overflow Status */
2861                 uint32_t CIOS25:1;     /* Channel 25 Interruput Overflow Status */
2862                 uint32_t CIOS24:1;     /* Channel 24 Interruput Overflow Status */
2863                 uint32_t CIOS23:1;     /* Channel 23 Interruput Overflow Status */
2864                 uint32_t CIOS22:1;     /* Channel 22 Interruput Overflow Status */
2865                 uint32_t CIOS21:1;     /* Channel 21 Interruput Overflow Status */
2866                 uint32_t CIOS20:1;     /* Channel 20 Interruput Overflow Status */
2867                 uint32_t CIOS19:1;     /* Channel 19 Interruput Overflow Status */
2868                 uint32_t CIOS18:1;     /* Channel 18 Interruput Overflow Status */
2869                 uint32_t CIOS17:1;     /* Channel 17 Interruput Overflow Status */
2870                 uint32_t CIOS16:1;     /* Channel 16 Interruput Overflow Status */
2871                 uint32_t CIOS15:1;     /* Channel 15 Interruput Overflow Status */
2872                 uint32_t CIOS14:1;     /* Channel 14 Interruput Overflow Status */
2873                 uint32_t CIOS13:1;     /* Channel 13 Interruput Overflow Status */
2874                 uint32_t CIOS12:1;     /* Channel 12 Interruput Overflow Status */
2875                 uint32_t CIOS11:1;     /* Channel 11 Interruput Overflow Status */
2876                 uint32_t CIOS10:1;     /* Channel 10 Interruput Overflow Status */
2877                 uint32_t CIOS9:1;      /* Channel 9 Interruput Overflow Status */
2878                 uint32_t CIOS8:1;      /* Channel 8 Interruput Overflow Status */
2879                 uint32_t CIOS7:1;      /* Channel 7 Interruput Overflow Status */
2880                 uint32_t CIOS6:1;      /* Channel 6 Interruput Overflow Status */
2881                 uint32_t CIOS5:1;      /* Channel 5 Interruput Overflow Status */
2882                 uint32_t CIOS4:1;      /* Channel 4 Interruput Overflow Status */
2883                 uint32_t CIOS3:1;      /* Channel 3 Interruput Overflow Status */
2884                 uint32_t CIOS2:1;      /* Channel 2 Interruput Overflow Status */
2885                 uint32_t CIOS1:1;      /* Channel 1 Interruput Overflow Status */
2886                 uint32_t CIOS0:1;      /* Channel 0 Interruput Overflow Status */
2887             } B;
2888         } CIOSR_B;
2889 
2890         uint32_t eTPU_reserved0228[2];  /* 0x0228-0x022F */
2891 
2892         union {                 /* ETPU_A Data Transfer Overflow Status */
2893             uint32_t R;
2894             struct {
2895                 uint32_t DTROS31:1;    /* Channel 31 Data Transfer Overflow Status */
2896                 uint32_t DTROS30:1;    /* Channel 30 Data Transfer Overflow Status */
2897                 uint32_t DTROS29:1;    /* Channel 29 Data Transfer Overflow Status */
2898                 uint32_t DTROS28:1;    /* Channel 28 Data Transfer Overflow Status */
2899                 uint32_t DTROS27:1;    /* Channel 27 Data Transfer Overflow Status */
2900                 uint32_t DTROS26:1;    /* Channel 26 Data Transfer Overflow Status */
2901                 uint32_t DTROS25:1;    /* Channel 25 Data Transfer Overflow Status */
2902                 uint32_t DTROS24:1;    /* Channel 24 Data Transfer Overflow Status */
2903                 uint32_t DTROS23:1;    /* Channel 23 Data Transfer Overflow Status */
2904                 uint32_t DTROS22:1;    /* Channel 22 Data Transfer Overflow Status */
2905                 uint32_t DTROS21:1;    /* Channel 21 Data Transfer Overflow Status */
2906                 uint32_t DTROS20:1;    /* Channel 20 Data Transfer Overflow Status */
2907                 uint32_t DTROS19:1;    /* Channel 19 Data Transfer Overflow Status */
2908                 uint32_t DTROS18:1;    /* Channel 18 Data Transfer Overflow Status */
2909                 uint32_t DTROS17:1;    /* Channel 17 Data Transfer Overflow Status */
2910                 uint32_t DTROS16:1;    /* Channel 16 Data Transfer Overflow Status */
2911                 uint32_t DTROS15:1;    /* Channel 15 Data Transfer Overflow Status */
2912                 uint32_t DTROS14:1;    /* Channel 14 Data Transfer Overflow Status */
2913                 uint32_t DTROS13:1;    /* Channel 13 Data Transfer Overflow Status */
2914                 uint32_t DTROS12:1;    /* Channel 12 Data Transfer Overflow Status */
2915                 uint32_t DTROS11:1;    /* Channel 11 Data Transfer Overflow Status */
2916                 uint32_t DTROS10:1;    /* Channel 10 Data Transfer Overflow Status */
2917                 uint32_t DTROS9:1;     /* Channel 9 Data Transfer Overflow Status */
2918                 uint32_t DTROS8:1;     /* Channel 8 Data Transfer Overflow Status */
2919                 uint32_t DTROS7:1;     /* Channel 7 Data Transfer Overflow Status */
2920                 uint32_t DTROS6:1;     /* Channel 6 Data Transfer Overflow Status */
2921                 uint32_t DTROS5:1;     /* Channel 5 Data Transfer Overflow Status */
2922                 uint32_t DTROS4:1;     /* Channel 4 Data Transfer Overflow Status */
2923                 uint32_t DTROS3:1;     /* Channel 3 Data Transfer Overflow Status */
2924                 uint32_t DTROS2:1;     /* Channel 2 Data Transfer Overflow Status */
2925                 uint32_t DTROS1:1;     /* Channel 1 Data Transfer Overflow Status */
2926                 uint32_t DTROS0:1;     /* Channel 0 Data Transfer Overflow Status */
2927             } B;
2928         } CDTROSR_A;
2929 
2930         union {                 /* ETPU_B Data Transfer Overflow Status */
2931             uint32_t R;
2932             struct {
2933                 uint32_t DTROS31:1;    /* Channel 31 Data Transfer Overflow Status */
2934                 uint32_t DTROS30:1;    /* Channel 30 Data Transfer Overflow Status */
2935                 uint32_t DTROS29:1;    /* Channel 29 Data Transfer Overflow Status */
2936                 uint32_t DTROS28:1;    /* Channel 28 Data Transfer Overflow Status */
2937                 uint32_t DTROS27:1;    /* Channel 27 Data Transfer Overflow Status */
2938                 uint32_t DTROS26:1;    /* Channel 26 Data Transfer Overflow Status */
2939                 uint32_t DTROS25:1;    /* Channel 25 Data Transfer Overflow Status */
2940                 uint32_t DTROS24:1;    /* Channel 24 Data Transfer Overflow Status */
2941                 uint32_t DTROS23:1;    /* Channel 23 Data Transfer Overflow Status */
2942                 uint32_t DTROS22:1;    /* Channel 22 Data Transfer Overflow Status */
2943                 uint32_t DTROS21:1;    /* Channel 21 Data Transfer Overflow Status */
2944                 uint32_t DTROS20:1;    /* Channel 20 Data Transfer Overflow Status */
2945                 uint32_t DTROS19:1;    /* Channel 19 Data Transfer Overflow Status */
2946                 uint32_t DTROS18:1;    /* Channel 18 Data Transfer Overflow Status */
2947                 uint32_t DTROS17:1;    /* Channel 17 Data Transfer Overflow Status */
2948                 uint32_t DTROS16:1;    /* Channel 16 Data Transfer Overflow Status */
2949                 uint32_t DTROS15:1;    /* Channel 15 Data Transfer Overflow Status */
2950                 uint32_t DTROS14:1;    /* Channel 14 Data Transfer Overflow Status */
2951                 uint32_t DTROS13:1;    /* Channel 13 Data Transfer Overflow Status */
2952                 uint32_t DTROS12:1;    /* Channel 12 Data Transfer Overflow Status */
2953                 uint32_t DTROS11:1;    /* Channel 11 Data Transfer Overflow Status */
2954                 uint32_t DTROS10:1;    /* Channel 10 Data Transfer Overflow Status */
2955                 uint32_t DTROS9:1;     /* Channel 9 Data Transfer Overflow Status */
2956                 uint32_t DTROS8:1;     /* Channel 8 Data Transfer Overflow Status */
2957                 uint32_t DTROS7:1;     /* Channel 7 Data Transfer Overflow Status */
2958                 uint32_t DTROS6:1;     /* Channel 6 Data Transfer Overflow Status */
2959                 uint32_t DTROS5:1;     /* Channel 5 Data Transfer Overflow Status */
2960                 uint32_t DTROS4:1;     /* Channel 4 Data Transfer Overflow Status */
2961                 uint32_t DTROS3:1;     /* Channel 3 Data Transfer Overflow Status */
2962                 uint32_t DTROS2:1;     /* Channel 2 Data Transfer Overflow Status */
2963                 uint32_t DTROS1:1;     /* Channel 1 Data Transfer Overflow Status */
2964                 uint32_t DTROS0:1;     /* Channel 0 Data Transfer Overflow Status */
2965             } B;
2966         } CDTROSR_B;
2967 
2968         uint32_t eTPU_reserved0238[2];  /* 0x0238-0x023F */
2969 
2970         union {                 /* ETPU_A Channel Interruput Enable */
2971             uint32_t R;
2972             struct {
2973                 uint32_t CIE31:1;      /* Channel 31 Interruput Enable */
2974                 uint32_t CIE30:1;      /* Channel 30 Interruput Enable */
2975                 uint32_t CIE29:1;      /* Channel 29 Interruput Enable */
2976                 uint32_t CIE28:1;      /* Channel 28 Interruput Enable */
2977                 uint32_t CIE27:1;      /* Channel 27 Interruput Enable */
2978                 uint32_t CIE26:1;      /* Channel 26 Interruput Enable */
2979                 uint32_t CIE25:1;      /* Channel 25 Interruput Enable */
2980                 uint32_t CIE24:1;      /* Channel 24 Interruput Enable */
2981                 uint32_t CIE23:1;      /* Channel 23 Interruput Enable */
2982                 uint32_t CIE22:1;      /* Channel 22 Interruput Enable */
2983                 uint32_t CIE21:1;      /* Channel 21 Interruput Enable */
2984                 uint32_t CIE20:1;      /* Channel 20 Interruput Enable */
2985                 uint32_t CIE19:1;      /* Channel 19 Interruput Enable */
2986                 uint32_t CIE18:1;      /* Channel 18 Interruput Enable */
2987                 uint32_t CIE17:1;      /* Channel 17 Interruput Enable */
2988                 uint32_t CIE16:1;      /* Channel 16 Interruput Enable */
2989                 uint32_t CIE15:1;      /* Channel 15 Interruput Enable */
2990                 uint32_t CIE14:1;      /* Channel 14 Interruput Enable */
2991                 uint32_t CIE13:1;      /* Channel 13 Interruput Enable */
2992                 uint32_t CIE12:1;      /* Channel 12 Interruput Enable */
2993                 uint32_t CIE11:1;      /* Channel 11 Interruput Enable */
2994                 uint32_t CIE10:1;      /* Channel 10 Interruput Enable */
2995                 uint32_t CIE9:1;       /* Channel 9 Interruput Enable */
2996                 uint32_t CIE8:1;       /* Channel 8 Interruput Enable */
2997                 uint32_t CIE7:1;       /* Channel 7 Interruput Enable */
2998                 uint32_t CIE6:1;       /* Channel 6 Interruput Enable */
2999                 uint32_t CIE5:1;       /* Channel 5 Interruput Enable */
3000                 uint32_t CIE4:1;       /* Channel 4 Interruput Enable */
3001                 uint32_t CIE3:1;       /* Channel 3 Interruput Enable */
3002                 uint32_t CIE2:1;       /* Channel 2 Interruput Enable */
3003                 uint32_t CIE1:1;       /* Channel 1 Interruput Enable */
3004                 uint32_t CIE0:1;       /* Channel 0 Interruput Enable */
3005             } B;
3006         } CIER_A;
3007 
3008         union {                 /* ETPU_B Channel Interruput Enable */
3009             uint32_t R;
3010             struct {
3011                 uint32_t CIE31:1;      /* Channel 31 Interruput Enable */
3012                 uint32_t CIE30:1;      /* Channel 30 Interruput Enable */
3013                 uint32_t CIE29:1;      /* Channel 29 Interruput Enable */
3014                 uint32_t CIE28:1;      /* Channel 28 Interruput Enable */
3015                 uint32_t CIE27:1;      /* Channel 27 Interruput Enable */
3016                 uint32_t CIE26:1;      /* Channel 26 Interruput Enable */
3017                 uint32_t CIE25:1;      /* Channel 25 Interruput Enable */
3018                 uint32_t CIE24:1;      /* Channel 24 Interruput Enable */
3019                 uint32_t CIE23:1;      /* Channel 23 Interruput Enable */
3020                 uint32_t CIE22:1;      /* Channel 22 Interruput Enable */
3021                 uint32_t CIE21:1;      /* Channel 21 Interruput Enable */
3022                 uint32_t CIE20:1;      /* Channel 20 Interruput Enable */
3023                 uint32_t CIE19:1;      /* Channel 19 Interruput Enable */
3024                 uint32_t CIE18:1;      /* Channel 18 Interruput Enable */
3025                 uint32_t CIE17:1;      /* Channel 17 Interruput Enable */
3026                 uint32_t CIE16:1;      /* Channel 16 Interruput Enable */
3027                 uint32_t CIE15:1;      /* Channel 15 Interruput Enable */
3028                 uint32_t CIE14:1;      /* Channel 14 Interruput Enable */
3029                 uint32_t CIE13:1;      /* Channel 13 Interruput Enable */
3030                 uint32_t CIE12:1;      /* Channel 12 Interruput Enable */
3031                 uint32_t CIE11:1;      /* Channel 11 Interruput Enable */
3032                 uint32_t CIE10:1;      /* Channel 10 Interruput Enable */
3033                 uint32_t CIE9:1;       /* Channel 9 Interruput Enable */
3034                 uint32_t CIE8:1;       /* Channel 8 Interruput Enable */
3035                 uint32_t CIE7:1;       /* Channel 7 Interruput Enable */
3036                 uint32_t CIE6:1;       /* Channel 6 Interruput Enable */
3037                 uint32_t CIE5:1;       /* Channel 5 Interruput Enable */
3038                 uint32_t CIE4:1;       /* Channel 4 Interruput Enable */
3039                 uint32_t CIE3:1;       /* Channel 3 Interruput Enable */
3040                 uint32_t CIE2:1;       /* Channel 2 Interruput Enable */
3041                 uint32_t CIE1:1;       /* Channel 1 Interruput Enable */
3042                 uint32_t CIE0:1;       /* Channel 0 Interruput Enable */
3043             } B;
3044         } CIER_B;
3045 
3046         uint32_t eTPU_reserved0248[2];  /* 0x0248-0x024F */
3047 
3048         union {                 /* ETPU_A Channel Data Transfer Request Enable */
3049             uint32_t R;
3050             struct {
3051                 uint32_t DTRE31:1;     /* Channel 31 Data Transfer Request Enable */
3052                 uint32_t DTRE30:1;     /* Channel 30 Data Transfer Request Enable */
3053                 uint32_t DTRE29:1;     /* Channel 29 Data Transfer Request Enable */
3054                 uint32_t DTRE28:1;     /* Channel 28 Data Transfer Request Enable */
3055                 uint32_t DTRE27:1;     /* Channel 27 Data Transfer Request Enable */
3056                 uint32_t DTRE26:1;     /* Channel 26 Data Transfer Request Enable */
3057                 uint32_t DTRE25:1;     /* Channel 25 Data Transfer Request Enable */
3058                 uint32_t DTRE24:1;     /* Channel 24 Data Transfer Request Enable */
3059                 uint32_t DTRE23:1;     /* Channel 23 Data Transfer Request Enable */
3060                 uint32_t DTRE22:1;     /* Channel 22 Data Transfer Request Enable */
3061                 uint32_t DTRE21:1;     /* Channel 21 Data Transfer Request Enable */
3062                 uint32_t DTRE20:1;     /* Channel 20 Data Transfer Request Enable */
3063                 uint32_t DTRE19:1;     /* Channel 19 Data Transfer Request Enable */
3064                 uint32_t DTRE18:1;     /* Channel 18 Data Transfer Request Enable */
3065                 uint32_t DTRE17:1;     /* Channel 17 Data Transfer Request Enable */
3066                 uint32_t DTRE16:1;     /* Channel 16 Data Transfer Request Enable */
3067                 uint32_t DTRE15:1;     /* Channel 15 Data Transfer Request Enable */
3068                 uint32_t DTRE14:1;     /* Channel 14 Data Transfer Request Enable */
3069                 uint32_t DTRE13:1;     /* Channel 13 Data Transfer Request Enable */
3070                 uint32_t DTRE12:1;     /* Channel 12 Data Transfer Request Enable */
3071                 uint32_t DTRE11:1;     /* Channel 11 Data Transfer Request Enable */
3072                 uint32_t DTRE10:1;     /* Channel 10 Data Transfer Request Enable */
3073                 uint32_t DTRE9:1;      /* Channel 9 Data Transfer Request Enable */
3074                 uint32_t DTRE8:1;      /* Channel 8 Data Transfer Request Enable */
3075                 uint32_t DTRE7:1;      /* Channel 7 Data Transfer Request Enable */
3076                 uint32_t DTRE6:1;      /* Channel 6 Data Transfer Request Enable */
3077                 uint32_t DTRE5:1;      /* Channel 5 Data Transfer Request Enable */
3078                 uint32_t DTRE4:1;      /* Channel 4 Data Transfer Request Enable */
3079                 uint32_t DTRE3:1;      /* Channel 3 Data Transfer Request Enable */
3080                 uint32_t DTRE2:1;      /* Channel 2 Data Transfer Request Enable */
3081                 uint32_t DTRE1:1;      /* Channel 1 Data Transfer Request Enable */
3082                 uint32_t DTRE0:1;      /* Channel 0 Data Transfer Request Enable */
3083             } B;
3084         } CDTRER_A;
3085 
3086         union {                 /* ETPU_B Channel Data Transfer Request Enable */
3087             uint32_t R;
3088             struct {
3089                 uint32_t DTRE31:1;     /* Channel 31 Data Transfer Request Enable */
3090                 uint32_t DTRE30:1;     /* Channel 30 Data Transfer Request Enable */
3091                 uint32_t DTRE29:1;     /* Channel 29 Data Transfer Request Enable */
3092                 uint32_t DTRE28:1;     /* Channel 28 Data Transfer Request Enable */
3093                 uint32_t DTRE27:1;     /* Channel 27 Data Transfer Request Enable */
3094                 uint32_t DTRE26:1;     /* Channel 26 Data Transfer Request Enable */
3095                 uint32_t DTRE25:1;     /* Channel 25 Data Transfer Request Enable */
3096                 uint32_t DTRE24:1;     /* Channel 24 Data Transfer Request Enable */
3097                 uint32_t DTRE23:1;     /* Channel 23 Data Transfer Request Enable */
3098                 uint32_t DTRE22:1;     /* Channel 22 Data Transfer Request Enable */
3099                 uint32_t DTRE21:1;     /* Channel 21 Data Transfer Request Enable */
3100                 uint32_t DTRE20:1;     /* Channel 20 Data Transfer Request Enable */
3101                 uint32_t DTRE19:1;     /* Channel 19 Data Transfer Request Enable */
3102                 uint32_t DTRE18:1;     /* Channel 18 Data Transfer Request Enable */
3103                 uint32_t DTRE17:1;     /* Channel 17 Data Transfer Request Enable */
3104                 uint32_t DTRE16:1;     /* Channel 16 Data Transfer Request Enable */
3105                 uint32_t DTRE15:1;     /* Channel 15 Data Transfer Request Enable */
3106                 uint32_t DTRE14:1;     /* Channel 14 Data Transfer Request Enable */
3107                 uint32_t DTRE13:1;     /* Channel 13 Data Transfer Request Enable */
3108                 uint32_t DTRE12:1;     /* Channel 12 Data Transfer Request Enable */
3109                 uint32_t DTRE11:1;     /* Channel 11 Data Transfer Request Enable */
3110                 uint32_t DTRE10:1;     /* Channel 10 Data Transfer Request Enable */
3111                 uint32_t DTRE9:1;      /* Channel 9 Data Transfer Request Enable */
3112                 uint32_t DTRE8:1;      /* Channel 8 Data Transfer Request Enable */
3113                 uint32_t DTRE7:1;      /* Channel 7 Data Transfer Request Enable */
3114                 uint32_t DTRE6:1;      /* Channel 6 Data Transfer Request Enable */
3115                 uint32_t DTRE5:1;      /* Channel 5 Data Transfer Request Enable */
3116                 uint32_t DTRE4:1;      /* Channel 4 Data Transfer Request Enable */
3117                 uint32_t DTRE3:1;      /* Channel 3 Data Transfer Request Enable */
3118                 uint32_t DTRE2:1;      /* Channel 2 Data Transfer Request Enable */
3119                 uint32_t DTRE1:1;      /* Channel 1 Data Transfer Request Enable */
3120                 uint32_t DTRE0:1;      /* Channel 0 Data Transfer Request Enable */
3121             } B;
3122         } CDTRER_B;
3123 
3124         uint32_t eTPU_reserved0258[2];  /* 0x0258-0x025F */
3125 
3126         union {                 /* Watchdog Status Register A */
3127             uint32_t R;
3128             struct {
3129                 uint32_t WDS31:1;
3130                 uint32_t WDS30:1;
3131                 uint32_t WDS29:1;
3132                 uint32_t WDS28:1;
3133                 uint32_t WDS27:1;
3134                 uint32_t WDS26:1;
3135                 uint32_t WDS25:1;
3136                 uint32_t WDS24:1;
3137                 uint32_t WDS23:1;
3138                 uint32_t WDS22:1;
3139                 uint32_t WDS21:1;
3140                 uint32_t WDS20:1;
3141                 uint32_t WDS19:1;
3142                 uint32_t WDS18:1;
3143                 uint32_t WDS17:1;
3144                 uint32_t WDS16:1;
3145                 uint32_t WDS15:1;
3146                 uint32_t WDS14:1;
3147                 uint32_t WDS13:1;
3148                 uint32_t WDS12:1;
3149                 uint32_t WDS11:1;
3150                 uint32_t WDS10:1;
3151                 uint32_t WDS9:1;
3152                 uint32_t WDS8:1;
3153                 uint32_t WDS7:1;
3154                 uint32_t WDS6:1;
3155                 uint32_t WDS5:1;
3156                 uint32_t WDS4:1;
3157                 uint32_t WDS3:1;
3158                 uint32_t WDS2:1;
3159                 uint32_t WDS1:1;
3160                 uint32_t WDS0:1;
3161             } B;
3162         } WDSR_A;
3163 
3164         union {                 /* Watchdog Status Register B */
3165             uint32_t R;
3166             struct {
3167                 uint32_t WDS31:1;
3168                 uint32_t WDS30:1;
3169                 uint32_t WDS29:1;
3170                 uint32_t WDS28:1;
3171                 uint32_t WDS27:1;
3172                 uint32_t WDS26:1;
3173                 uint32_t WDS25:1;
3174                 uint32_t WDS24:1;
3175                 uint32_t WDS23:1;
3176                 uint32_t WDS22:1;
3177                 uint32_t WDS21:1;
3178                 uint32_t WDS20:1;
3179                 uint32_t WDS19:1;
3180                 uint32_t WDS18:1;
3181                 uint32_t WDS17:1;
3182                 uint32_t WDS16:1;
3183                 uint32_t WDS15:1;
3184                 uint32_t WDS14:1;
3185                 uint32_t WDS13:1;
3186                 uint32_t WDS12:1;
3187                 uint32_t WDS11:1;
3188                 uint32_t WDS10:1;
3189                 uint32_t WDS9:1;
3190                 uint32_t WDS8:1;
3191                 uint32_t WDS7:1;
3192                 uint32_t WDS6:1;
3193                 uint32_t WDS5:1;
3194                 uint32_t WDS4:1;
3195                 uint32_t WDS3:1;
3196                 uint32_t WDS2:1;
3197                 uint32_t WDS1:1;
3198                 uint32_t WDS0:1;
3199             } B;
3200         } WDSR_B;
3201 
3202         uint32_t eTPU_reserved0268[6];  /* 0x0268-0x027F */
3203 
3204         union {                 /* ETPU_A Channel Pending Service Status */
3205             uint32_t R;
3206             struct {
3207                 uint32_t SR31:1;       /* Channel 31 Pending Service Status */
3208                 uint32_t SR30:1;       /* Channel 30 Pending Service Status */
3209                 uint32_t SR29:1;       /* Channel 29 Pending Service Status */
3210                 uint32_t SR28:1;       /* Channel 28 Pending Service Status */
3211                 uint32_t SR27:1;       /* Channel 27 Pending Service Status */
3212                 uint32_t SR26:1;       /* Channel 26 Pending Service Status */
3213                 uint32_t SR25:1;       /* Channel 25 Pending Service Status */
3214                 uint32_t SR24:1;       /* Channel 24 Pending Service Status */
3215                 uint32_t SR23:1;       /* Channel 23 Pending Service Status */
3216                 uint32_t SR22:1;       /* Channel 22 Pending Service Status */
3217                 uint32_t SR21:1;       /* Channel 21 Pending Service Status */
3218                 uint32_t SR20:1;       /* Channel 20 Pending Service Status */
3219                 uint32_t SR19:1;       /* Channel 19 Pending Service Status */
3220                 uint32_t SR18:1;       /* Channel 18 Pending Service Status */
3221                 uint32_t SR17:1;       /* Channel 17 Pending Service Status */
3222                 uint32_t SR16:1;       /* Channel 16 Pending Service Status */
3223                 uint32_t SR15:1;       /* Channel 15 Pending Service Status */
3224                 uint32_t SR14:1;       /* Channel 14 Pending Service Status */
3225                 uint32_t SR13:1;       /* Channel 13 Pending Service Status */
3226                 uint32_t SR12:1;       /* Channel 12 Pending Service Status */
3227                 uint32_t SR11:1;       /* Channel 11 Pending Service Status */
3228                 uint32_t SR10:1;       /* Channel 10 Pending Service Status */
3229                 uint32_t SR9:1;        /* Channel 9 Pending Service Status */
3230                 uint32_t SR8:1;        /* Channel 8 Pending Service Status */
3231                 uint32_t SR7:1;        /* Channel 7 Pending Service Status */
3232                 uint32_t SR6:1;        /* Channel 6 Pending Service Status */
3233                 uint32_t SR5:1;        /* Channel 5 Pending Service Status */
3234                 uint32_t SR4:1;        /* Channel 4 Pending Service Status */
3235                 uint32_t SR3:1;        /* Channel 3 Pending Service Status */
3236                 uint32_t SR2:1;        /* Channel 2 Pending Service Status */
3237                 uint32_t SR1:1;        /* Channel 1 Pending Service Status */
3238                 uint32_t SR0:1;        /* Channel 0 Pending Service Status */
3239             } B;
3240         } CPSSR_A;
3241 
3242         union {                 /* ETPU_B Channel Pending Service Status */
3243             uint32_t R;
3244             struct {
3245                 uint32_t SR31:1;       /* Channel 31 Pending Service Status */
3246                 uint32_t SR30:1;       /* Channel 30 Pending Service Status */
3247                 uint32_t SR29:1;       /* Channel 29 Pending Service Status */
3248                 uint32_t SR28:1;       /* Channel 28 Pending Service Status */
3249                 uint32_t SR27:1;       /* Channel 27 Pending Service Status */
3250                 uint32_t SR26:1;       /* Channel 26 Pending Service Status */
3251                 uint32_t SR25:1;       /* Channel 25 Pending Service Status */
3252                 uint32_t SR24:1;       /* Channel 24 Pending Service Status */
3253                 uint32_t SR23:1;       /* Channel 23 Pending Service Status */
3254                 uint32_t SR22:1;       /* Channel 22 Pending Service Status */
3255                 uint32_t SR21:1;       /* Channel 21 Pending Service Status */
3256                 uint32_t SR20:1;       /* Channel 20 Pending Service Status */
3257                 uint32_t SR19:1;       /* Channel 19 Pending Service Status */
3258                 uint32_t SR18:1;       /* Channel 18 Pending Service Status */
3259                 uint32_t SR17:1;       /* Channel 17 Pending Service Status */
3260                 uint32_t SR16:1;       /* Channel 16 Pending Service Status */
3261                 uint32_t SR15:1;       /* Channel 15 Pending Service Status */
3262                 uint32_t SR14:1;       /* Channel 14 Pending Service Status */
3263                 uint32_t SR13:1;       /* Channel 13 Pending Service Status */
3264                 uint32_t SR12:1;       /* Channel 12 Pending Service Status */
3265                 uint32_t SR11:1;       /* Channel 11 Pending Service Status */
3266                 uint32_t SR10:1;       /* Channel 10 Pending Service Status */
3267                 uint32_t SR9:1;        /* Channel 9 Pending Service Status */
3268                 uint32_t SR8:1;        /* Channel 8 Pending Service Status */
3269                 uint32_t SR7:1;        /* Channel 7 Pending Service Status */
3270                 uint32_t SR6:1;        /* Channel 6 Pending Service Status */
3271                 uint32_t SR5:1;        /* Channel 5 Pending Service Status */
3272                 uint32_t SR4:1;        /* Channel 4 Pending Service Status */
3273                 uint32_t SR3:1;        /* Channel 3 Pending Service Status */
3274                 uint32_t SR2:1;        /* Channel 2 Pending Service Status */
3275                 uint32_t SR1:1;        /* Channel 1 Pending Service Status */
3276                 uint32_t SR0:1;        /* Channel 0 Pending Service Status */
3277             } B;
3278         } CPSSR_B;
3279 
3280         uint32_t eTPU_reserved0288[2];  /* 0x0288-0x028F */
3281 
3282         union {                 /* ETPU_A Channel Service Status */
3283             uint32_t R;
3284             struct {
3285                 uint32_t SS31:1;       /* Channel 31 Service Status */
3286                 uint32_t SS30:1;       /* Channel 30 Service Status */
3287                 uint32_t SS29:1;       /* Channel 29 Service Status */
3288                 uint32_t SS28:1;       /* Channel 28 Service Status */
3289                 uint32_t SS27:1;       /* Channel 27 Service Status */
3290                 uint32_t SS26:1;       /* Channel 26 Service Status */
3291                 uint32_t SS25:1;       /* Channel 25 Service Status */
3292                 uint32_t SS24:1;       /* Channel 24 Service Status */
3293                 uint32_t SS23:1;       /* Channel 23 Service Status */
3294                 uint32_t SS22:1;       /* Channel 22 Service Status */
3295                 uint32_t SS21:1;       /* Channel 21 Service Status */
3296                 uint32_t SS20:1;       /* Channel 20 Service Status */
3297                 uint32_t SS19:1;       /* Channel 19 Service Status */
3298                 uint32_t SS18:1;       /* Channel 18 Service Status */
3299                 uint32_t SS17:1;       /* Channel 17 Service Status */
3300                 uint32_t SS16:1;       /* Channel 16 Service Status */
3301                 uint32_t SS15:1;       /* Channel 15 Service Status */
3302                 uint32_t SS14:1;       /* Channel 14 Service Status */
3303                 uint32_t SS13:1;       /* Channel 13 Service Status */
3304                 uint32_t SS12:1;       /* Channel 12 Service Status */
3305                 uint32_t SS11:1;       /* Channel 11 Service Status */
3306                 uint32_t SS10:1;       /* Channel 10 Service Status */
3307                 uint32_t SS9:1;        /* Channel 9 Service Status */
3308                 uint32_t SS8:1;        /* Channel 8 Service Status */
3309                 uint32_t SS7:1;        /* Channel 7 Service Status */
3310                 uint32_t SS6:1;        /* Channel 6 Service Status */
3311                 uint32_t SS5:1;        /* Channel 5 Service Status */
3312                 uint32_t SS4:1;        /* Channel 4 Service Status */
3313                 uint32_t SS3:1;        /* Channel 3 Service Status */
3314                 uint32_t SS2:1;        /* Channel 2 Service Status */
3315                 uint32_t SS1:1;        /* Channel 1 Service Status */
3316                 uint32_t SS0:1;        /* Channel 0 Service Status */
3317             } B;
3318         } CSSR_A;
3319 
3320         union {                 /* ETPU_B Channel Service Status */
3321             uint32_t R;
3322             struct {
3323                 uint32_t SS31:1;       /* Channel 31 Service Status */
3324                 uint32_t SS30:1;       /* Channel 30 Service Status */
3325                 uint32_t SS29:1;       /* Channel 29 Service Status */
3326                 uint32_t SS28:1;       /* Channel 28 Service Status */
3327                 uint32_t SS27:1;       /* Channel 27 Service Status */
3328                 uint32_t SS26:1;       /* Channel 26 Service Status */
3329                 uint32_t SS25:1;       /* Channel 25 Service Status */
3330                 uint32_t SS24:1;       /* Channel 24 Service Status */
3331                 uint32_t SS23:1;       /* Channel 23 Service Status */
3332                 uint32_t SS22:1;       /* Channel 22 Service Status */
3333                 uint32_t SS21:1;       /* Channel 21 Service Status */
3334                 uint32_t SS20:1;       /* Channel 20 Service Status */
3335                 uint32_t SS19:1;       /* Channel 19 Service Status */
3336                 uint32_t SS18:1;       /* Channel 18 Service Status */
3337                 uint32_t SS17:1;       /* Channel 17 Service Status */
3338                 uint32_t SS16:1;       /* Channel 16 Service Status */
3339                 uint32_t SS15:1;       /* Channel 15 Service Status */
3340                 uint32_t SS14:1;       /* Channel 14 Service Status */
3341                 uint32_t SS13:1;       /* Channel 13 Service Status */
3342                 uint32_t SS12:1;       /* Channel 12 Service Status */
3343                 uint32_t SS11:1;       /* Channel 11 Service Status */
3344                 uint32_t SS10:1;       /* Channel 10 Service Status */
3345                 uint32_t SS9:1;        /* Channel 9 Service Status */
3346                 uint32_t SS8:1;        /* Channel 8 Service Status */
3347                 uint32_t SS7:1;        /* Channel 7 Service Status */
3348                 uint32_t SS6:1;        /* Channel 6 Service Status */
3349                 uint32_t SS5:1;        /* Channel 5 Service Status */
3350                 uint32_t SS4:1;        /* Channel 4 Service Status */
3351                 uint32_t SS3:1;        /* Channel 3 Service Status */
3352                 uint32_t SS2:1;        /* Channel 2 Service Status */
3353                 uint32_t SS1:1;        /* Channel 1 Service Status */
3354                 uint32_t SS0:1;        /* Channel 0 Service Status */
3355             } B;
3356         } CSSR_B;
3357 
3358         uint32_t eTPU_reserved0298[2];  /* 0x0298-0x029F */
3359 
3360         uint32_t eTPU_reserved02A0[88];  /* 0x02A0-0x03FF */
3361 
3362 /*****************************Channels********************************/
3363 
3364         struct {
3365             union {    /* Channel Configuration Register */
3366                 uint32_t R;
3367                 struct {
3368                     uint32_t CIE:1;    /* Channel Interruput Enable */
3369                     uint32_t DTRE:1;   /* Data Transfer Request Enable */
3370                     uint32_t CPR:2;    /* Channel Priority */
3371                     uint32_t:2;
3372                     uint32_t ETPD:1;
3373                     uint32_t ETCS:1;   /* Entry Table Condition Select */
3374                     uint32_t:3;
3375                     uint32_t CFS:5;    /* Channel Function Select */
3376                     uint32_t ODIS:1;   /* Output disable */
3377                     uint32_t OPOL:1;   /* output polarity */
3378                     uint32_t:3;
3379                     uint32_t CPBA:11;  /* Channel Parameter Base Address */
3380                 } B;
3381             } CR;
3382 
3383             union {    /* Channel Status Control Register */
3384                 uint32_t R;
3385                 struct {
3386                     uint32_t CIS:1;    /* Channel Interruput Status */
3387                     uint32_t CIOS:1;   /* Channel Interruput Overflow Status */
3388                     uint32_t:6;
3389                     uint32_t DTRS:1;   /* Data Transfer Status */
3390                     uint32_t DTROS:1;  /* Data Transfer Overflow Status */
3391                     uint32_t:6;
3392                     uint32_t IPS:1;    /* Input Pin State */
3393                     uint32_t OPS:1;    /* Output Pin State */
3394                     uint32_t OBE:1;    /* Output Buffer Enable */
3395                     uint32_t:11;
3396                     uint32_t FM1:1;    /* Function mode */
3397                     uint32_t FM0:1;    /* Function mode */
3398                 } B;
3399             } SCR;
3400 
3401             union {    /* Channel Host Service Request Register */
3402                 uint32_t R;
3403                 struct {
3404                     uint32_t:29;       /* Host Service Request */
3405                     uint32_t HSR:3;
3406                 } B;
3407             } HSRR;
3408 
3409             uint32_t eTPU_ch_reserved00C;  /* channel offset 0x00C-0x00F */
3410 
3411         } CHAN[127];
3412 
3413         uint32_t eTPU_reserved1000[7168];  /* 0x1000-0x7FFF */
3414 
3415     };
3416 
3417 /****************************************************************************/
3418 /*                          MODULE : PIT / RTI                              */
3419 /****************************************************************************/
3420 
3421     struct PIT_tag {
3422         union {                  /* Module Configuration Register */
3423             uint32_t R;
3424             struct {
3425                 uint32_t:29;
3426                 uint32_t MDIS_RTI:1;
3427                 uint32_t MDIS:1;
3428                 uint32_t FRZ:1;
3429             } B;
3430         } MCR;
3431 
3432         uint32_t PIT_reserved0004[59];  /* 0x0004-0x00EF */
3433 
3434         struct {
3435             union {
3436                 uint32_t R;    /* <URM>TSVn</URM> */
3437             } LDVAL;            /* Timer Load Value Register */
3438 
3439             union {
3440                 uint32_t R;    /* <URM>TVLn</URM> */
3441             } CVAL;             /* Current Timer Value Register */
3442 
3443             union {
3444                 uint32_t R;
3445                 struct {
3446                     uint32_t:30;
3447                     uint32_t TIE:1;
3448                     uint32_t TEN:1;
3449                 } B;
3450             } TCTRL;            /* Timer Control Register */
3451 
3452             union {
3453                 uint32_t R;
3454                 struct {
3455                     uint32_t:31;
3456                     uint32_t TIF:1;
3457                 } B;
3458             } TFLG;             /* Timer Flag Register */
3459         } RTI;                  /* RTI Channel */
3460 
3461         struct {
3462             union {
3463                 uint32_t R;
3464                 struct {
3465                     uint32_t TSV:32;
3466                 } B;
3467             } LDVAL;
3468 
3469             union {
3470                 uint32_t R;
3471                 struct {
3472                     uint32_t TVL:32;
3473                 } B;
3474             } CVAL;
3475 
3476             union {
3477                 uint32_t R;
3478                 struct {
3479                     uint32_t:30;
3480                     uint32_t TIE:1;
3481                     uint32_t TEN:1;
3482                 } B;
3483             } TCTRL;
3484 
3485             union {
3486                 uint32_t R;
3487                 struct {
3488                     uint32_t:31;
3489                     uint32_t TIF:1;
3490                 } B;
3491             } TFLG;
3492         } CH[4];
3493 
3494         uint32_t PIT_reserved00140[4016];  /* 0x0140-0x3FFF */
3495     };
3496 
3497 /****************************************************************************/
3498 /*                          MODULE : XBAR CrossBar                          */
3499 /****************************************************************************/
3500 
3501     struct XBAR_tag {
3502 
3503         union {                 /* Master Priority Register for Slave Port 0 */
3504             uint32_t R;
3505             struct {
3506                 uint32_t:1;
3507                 uint32_t MSTR7:3; /* EBI (development bus) */
3508                 uint32_t:1;
3509                 uint32_t MSTR6:3; /* FlexRay */
3510                 uint32_t:1;
3511                 uint32_t MSTR5:3; /* eDMA_B */
3512                 uint32_t:1;
3513                 uint32_t MSTR4:3; /* eDMA_A */
3514                 uint32_t:1;
3515                 uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3516                 uint32_t:1;
3517                 uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3518                 uint32_t:1;
3519                 uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3520                 uint32_t:1;
3521                 uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3522             } B;
3523         } MPR0;
3524 
3525         uint32_t XBAR_reserved0004[3];  /* 0x0004-0x000F */
3526 
3527         union {               /* General Purpose Control Register for Slave Port 0 */
3528             uint32_t R;
3529             struct {
3530                 uint32_t RO:1;
3531                 uint32_t:21;
3532                 uint32_t ARB:2;
3533                 uint32_t:2;
3534                 uint32_t PCTL:2;
3535                 uint32_t:1;
3536                 uint32_t PARK:3;
3537             } B;
3538         } SGPCR0;
3539 
3540         uint32_t XBAR_reserved0014[59];  /* 0x0014-0x00FF */
3541 
3542         union {                 /* Master Priority Register for Slave Port 1 */
3543             uint32_t R;
3544             struct {
3545                 uint32_t:1;
3546                 uint32_t MSTR7:3; /* EBI (development bus) */
3547                 uint32_t:1;
3548                 uint32_t MSTR6:3; /* FlexRay */
3549                 uint32_t:1;
3550                 uint32_t MSTR5:3; /* eDMA_B */
3551                 uint32_t:1;
3552                 uint32_t MSTR4:3; /* eDMA_A */
3553                 uint32_t:1;
3554                 uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3555                 uint32_t:1;
3556                 uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3557                 uint32_t:1;
3558                 uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3559                 uint32_t:1;
3560                 uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3561             } B;
3562         } MPR1;
3563 
3564         uint32_t XBAR_reserved0104[3];  /* 0x0104-0x010F */
3565 
3566         union {               /* General Purpose Control Register for Slave Port 1 */
3567             uint32_t R;
3568             struct {
3569                 uint32_t RO:1;
3570                 uint32_t:21;
3571                 uint32_t ARB:2;
3572                 uint32_t:2;
3573                 uint32_t PCTL:2;
3574                 uint32_t:1;
3575                 uint32_t PARK:3;
3576             } B;
3577         } SGPCR1;
3578 
3579         uint32_t XBAR_reserved0114[59];  /* 0x0114-0x01FF */
3580 
3581         union {                 /* Master Priority Register for Slave Port 2 */
3582             uint32_t R;
3583             struct {
3584                 uint32_t:1;
3585                 uint32_t MSTR7:3; /* EBI (development bus) */
3586                 uint32_t:1;
3587                 uint32_t MSTR6:3; /* FlexRay */
3588                 uint32_t:1;
3589                 uint32_t MSTR5:3; /* eDMA_B */
3590                 uint32_t:1;
3591                 uint32_t MSTR4:3; /* eDMA_A */
3592                 uint32_t:1;
3593                 uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3594                 uint32_t:1;
3595                 uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3596                 uint32_t:1;
3597                 uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3598                 uint32_t:1;
3599                 uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3600             } B;
3601         } MPR2;
3602 
3603         uint32_t XBAR_reserved0204[3];  /* 0x0204-0x020F */
3604 
3605         union {               /* General Purpose Control Register for Slave Port 2 */
3606             uint32_t R;
3607             struct {
3608                 uint32_t RO:1;
3609                 uint32_t:21;
3610                 uint32_t ARB:2;
3611                 uint32_t:2;
3612                 uint32_t PCTL:2;
3613                 uint32_t:1;
3614                 uint32_t PARK:3;
3615             } B;
3616         } SGPCR2;
3617 
3618         uint32_t XBAR_reserved0214[59];  /* 0x0214-0x02FF */
3619 
3620         uint32_t XBAR_reserved0300[64];  /* 0x0300-0x03FF */
3621 
3622         uint32_t XBAR_reserved0400[64];  /* 0x0400-0x04FF */
3623 
3624         uint32_t XBAR_reserved0500[64];  /* 0x0500-0x05FF */
3625 
3626         union {                 /* Master Priority Register for Slave Port 6 */
3627             uint32_t R;
3628             struct {
3629                 uint32_t:1;
3630                 uint32_t MSTR7:3; /* EBI (development bus) */
3631                 uint32_t:1;
3632                 uint32_t MSTR6:3; /* FlexRay */
3633                 uint32_t:1;
3634                 uint32_t MSTR5:3; /* eDMA_B */
3635                 uint32_t:1;
3636                 uint32_t MSTR4:3; /* eDMA_A */
3637                 uint32_t:1;
3638                 uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3639                 uint32_t:1;
3640                 uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3641                 uint32_t:1;
3642                 uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3643                 uint32_t:1;
3644                 uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3645             } B;
3646         } MPR6;
3647 
3648         uint32_t XBAR_reserved604[3];  /* 0x0604-0x060F */
3649 
3650         union {               /* General Purpose Control Register for Slave Port 6 */
3651             uint32_t R;
3652             struct {
3653                 uint32_t RO:1;
3654                 uint32_t:21;
3655                 uint32_t ARB:2;
3656                 uint32_t:2;
3657                 uint32_t PCTL:2;
3658                 uint32_t:1;
3659                 uint32_t PARK:3;
3660             } B;
3661         } SGPCR6;
3662 
3663         uint32_t XBAR_reserved0614[59];  /* 0x0614-0x06FF */
3664 
3665         union {                 /* Master Priority Register for Slave Port 7 */
3666             uint32_t R;
3667             struct {
3668                 uint32_t:1;
3669                 uint32_t MSTR7:3; /* EBI (development bus) */
3670                 uint32_t:1;
3671                 uint32_t MSTR6:3; /* FlexRay */
3672                 uint32_t:1;
3673                 uint32_t MSTR5:3; /* eDMA_B */
3674                 uint32_t:1;
3675                 uint32_t MSTR4:3; /* eDMA_A */
3676                 uint32_t:1;
3677                 uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3678                 uint32_t:1;
3679                 uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3680                 uint32_t:1;
3681                 uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3682                 uint32_t:1;
3683                 uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3684             } B;
3685         } MPR7;
3686 
3687         uint32_t XBAR_reserved704[3];  /* 0x0704-0x070F */
3688 
3689         union {
3690             uint32_t R;
3691             struct {
3692                 uint32_t RO:1;
3693                   uint32_t:21;
3694                 uint32_t ARB:2;
3695                   uint32_t:2;
3696                 uint32_t PCTL:2;
3697                   uint32_t:1;
3698                 uint32_t PARK:3;
3699             } B;
3700         } SGPCR7;               /* General Purpose Control Register for Slave Port 7 */
3701 
3702         uint32_t XBAR_reserved0714[59];  /* 0x0714-0x07FF */
3703 
3704         uint32_t XBAR_reserved0800[3584];  /* 0x0800-0x3FFF */
3705     };
3706 
3707 /****************************************************************************/
3708 /*                          MODULE : MPU                                    */
3709 /****************************************************************************/
3710 
3711     struct MPU_tag {
3712 
3713         union {                 /* Module Control/Error Status Register */
3714             uint32_t R;
3715             struct {
3716                 uint32_t SPERR:8;
3717                   uint32_t:4;
3718                 uint32_t HRL:4;
3719                 uint32_t NSP:4;
3720                 uint32_t NRGD:4;
3721                   uint32_t:7;
3722                 uint32_t VLD:1;
3723             } B;
3724         } CESR;
3725 
3726         uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */
3727 
3728         struct {
3729             union {             /* MPU Error Address Registers */
3730                 uint32_t R;
3731                 struct {
3732                     uint32_t EADDR:32;
3733                 } B;
3734             } EAR;
3735 
3736             union {             /* MPU Error Detail Registers */
3737                 uint32_t R;
3738                 struct {
3739                     uint32_t EACD:16;
3740                     uint32_t EPID:8;
3741                     uint32_t EMN:4;
3742                     uint32_t EATTR:3;
3743                     uint32_t ERW:1;
3744                 } B;
3745             } EDR;
3746         } PORT[3];
3747 
3748         uint32_t MPU_reserved0028[246];  /* 0x0028-0x03FF */
3749 
3750         struct {
3751             union {            /* Region Descriptor n Word 0 */
3752                 uint32_t R;
3753                 struct {
3754                     uint32_t SRTADDR:27;
3755                     uint32_t:5;
3756                 } B;
3757             } WORD0;
3758 
3759             union {            /* Region Descriptor n Word 1 */
3760                 uint32_t R;
3761                 struct {
3762                     uint32_t ENDADDR:27;
3763                     uint32_t:5;
3764                 } B;
3765             } WORD1;
3766 
3767             union {            /* Region Descriptor n Word 2 */
3768                 uint32_t R;
3769                 struct {
3770                     uint32_t M7RE:1;
3771                     uint32_t M7WE:1;
3772                     uint32_t M6RE:1;
3773                     uint32_t M6WE:1;
3774                     uint32_t M5RE:1;
3775                     uint32_t M5WE:1;
3776                     uint32_t M4RE:1;
3777                     uint32_t M4WE:1;
3778                     uint32_t: 18;
3779                     uint32_t M0PE:1;
3780                     uint32_t M0SM:2;
3781                     uint32_t M0UM:3;
3782                 } B;
3783             } WORD2;
3784 
3785             union {            /* Region Descriptor n Word 3 */
3786                 uint32_t R;
3787                 struct {
3788                     uint32_t PID:8;
3789                     uint32_t PIDMASK:8;
3790                       uint32_t:15;
3791                     uint32_t VLD:1;
3792                 } B;
3793             } WORD3;
3794         } RGD[16];
3795 
3796         uint32_t MPU_reserved0500[192];  /* 0x0500-0x07FF */
3797 
3798         union {           /* Region Descriptor Alternate Access Control n */
3799             uint32_t R;
3800             struct {
3801                 uint32_t:6;
3802                 uint32_t M4RE:1;
3803                 uint32_t M4WE:1;
3804                 uint32_t M3PE:1;
3805                 uint32_t M3SM:2;
3806                 uint32_t M3UM:3;
3807                 uint32_t M2PE:1;
3808                 uint32_t M2SM:2;
3809                 uint32_t M2UM:3;
3810                 uint32_t M1PE:1;
3811                 uint32_t M1SM:2;
3812                 uint32_t M1UM:3;
3813                 uint32_t M0PE:1;
3814                 uint32_t M0SM:2;
3815                 uint32_t M0UM:3;
3816             } B;
3817         } RGDAAC[16];
3818 
3819         uint32_t MPU_reserved0840[3568];  /* 0x0840-0x3FFF */
3820 
3821     };
3822 
3823 /****************************************************************************/
3824 /*                     MODULE : SWT                                         */
3825 /****************************************************************************/
3826 
3827     struct SWT_tag {
3828 
3829         union {                  /* Module Configuration Register */
3830             uint32_t R;
3831             struct {
3832                 uint32_t MAP0:1;
3833                 uint32_t MAP1:1;
3834                 uint32_t:1;
3835                 uint32_t:1;
3836                 uint32_t MAP4:1;
3837                 uint32_t MAP5:1;
3838                 uint32_t MAP6:1;
3839                 uint32_t MAP7:1;
3840                 uint32_t:14;
3841                 uint32_t KEY:1;
3842                 uint32_t RIA:1;
3843                 uint32_t WND:1;
3844                 uint32_t ITR:1;
3845                 uint32_t HLK:1;
3846                 uint32_t SLK:1;
3847                 uint32_t CSL:1;
3848                 uint32_t STP:1;
3849                 uint32_t FRZ:1;
3850                 uint32_t WEN:1;
3851             } B;
3852         } MCR;
3853 
3854         union {                /* Interrupt register */
3855             uint32_t R;
3856             struct {
3857                 uint32_t :31;
3858                 uint32_t TIF:1;
3859             } B;
3860         } IR;
3861 
3862         union {                /* Timeout register */
3863             uint32_t R;
3864             struct {
3865                 uint32_t WTO:32;
3866             } B;
3867         } TO;
3868 
3869         union {                /* Window register */
3870             uint32_t R;
3871             struct {
3872                 uint32_t WST:32;
3873             } B;
3874         } WN;
3875 
3876         union {                /* Service register */
3877             uint32_t R;
3878             struct {
3879                 uint32_t :16;
3880                 uint32_t WSC:16;
3881             } B;
3882         } SR;
3883 
3884         union {                /* Counter output register */
3885             uint32_t R;
3886             struct {
3887                 uint32_t CNT:32;
3888             } B;
3889         } CO;
3890 
3891         union {                /* Service key register */
3892             uint32_t R;
3893             struct {
3894                 uint32_t :16;
3895                 uint32_t SK:16;
3896             } B;
3897         } SK;
3898 
3899         uint32_t SWT_reserved001C[4089]; /* 0x001C-0x3FFF */
3900 
3901     };
3902 
3903 /****************************************************************************/
3904 /*                     MODULE : STM                                         */
3905 /****************************************************************************/
3906 
3907     struct STM_tag {
3908 
3909         union {                  /* Control Register */
3910             uint32_t R;
3911             struct {
3912                 uint32_t :16;
3913                 uint32_t CPS:8;
3914                 uint32_t :6;
3915                 uint32_t FRZ:1;
3916                 uint32_t TEN:1;
3917             } B;
3918         } CR;
3919 
3920         union {                /* STM Counter */
3921             uint32_t R;
3922         } CNT;
3923 
3924         uint32_t STM_reserved0008[2];  /* 0x0008-0x000F */
3925 
3926  /* channel 0 registers */
3927         union {
3928             uint32_t R;
3929             struct {
3930                 uint32_t :31;
3931                 uint32_t CEN:1;
3932             } B;
3933         } CCR0;                /* Chan 0 Control Register */
3934 
3935         union {
3936             uint32_t R;
3937             struct {
3938                 uint32_t :31;
3939                 uint32_t CIF:1;
3940             } B;
3941         } CIR0;                /* Chan 0 Interrupt Register */
3942 
3943         union {
3944             uint32_t R;
3945         } CMP0;                /* Chan 0 Compare Register */
3946 
3947         uint32_t STM_reserved2[1];
3948 
3949 /* channel 1 registers */
3950         union {
3951             uint32_t R;
3952             struct {
3953                 uint32_t :31;
3954                 uint32_t CEN:1;
3955             } B;
3956         } CCR1;                /* Chan 1 Control Register */
3957 
3958         union {
3959             uint32_t R;
3960             struct {
3961                 uint32_t :31;
3962                 uint32_t CIF:1;
3963             } B;
3964         } CIR1;                /* Chan 1 Interrupt Register */
3965 
3966         union {
3967             uint32_t R;
3968         } CMP1;                /* Chan 1 Compare Register */
3969 
3970         uint32_t STM_reserved3[1];
3971 
3972 /* channel 2 registers */
3973         union {
3974             uint32_t R;
3975             struct {
3976                 uint32_t :31;
3977                 uint32_t CEN:1;
3978             } B;
3979         } CCR2;                /* Chan 2 Control Register */
3980 
3981         union {
3982             uint32_t R;
3983             struct {
3984                 uint32_t :31;
3985                 uint32_t CIF:1;
3986             } B;
3987         } CIR2;                /* Chan 2 Interrupt Register */
3988 
3989         union {
3990             uint32_t R;
3991         } CMP2;                /* Chan 2 Compare Register */
3992 
3993         uint32_t STM_reserved4[1];
3994 
3995 /* channel 3 registers */
3996         union {
3997             uint32_t R;
3998             struct {
3999                 uint32_t :31;
4000                 uint32_t CEN:1;
4001             } B;
4002         } CCR3;                /* Chan 3 Control Register */
4003 
4004         union {
4005             uint32_t R;
4006             struct {
4007                 uint32_t :31;
4008                 uint32_t CIF:1;
4009             } B;
4010         } CIR3;                /* Chan 3 Interrupt Register */
4011 
4012         union {
4013             uint32_t R;
4014         } CMP3;                /* Chan 3 Compare Register */
4015 
4016         uint32_t STM_reserved0050[4076];  /* 0x0050-0x3FFF */
4017 
4018     };
4019 
4020 /****************************************************************************/
4021 /*                     MODULE : ECSM                                        */
4022 /****************************************************************************/
4023 
4024     struct ECSM_tag {
4025 
4026         union {                /* Processor core type */
4027             uint16_t R;
4028         } PCT;
4029 
4030         union {                /* Platform revision */
4031             uint16_t R;
4032         } REV;
4033 
4034         uint32_t ECSM_reserved0004;  /* 0x0004-0x0007 */
4035 
4036         union {                 /* IPS Module Configuration */
4037             uint32_t R;
4038         } IMC;
4039 
4040         uint8_t ECSM_reserved000C[3];  /* 0x000C-0x000E */
4041 
4042         union {                 /* Miscellaneous Reset Status Register */
4043             uint8_t R;
4044             struct {
4045                 uint8_t POR:1;
4046                 uint8_t DIR:1;
4047                 uint8_t SWTR:1;
4048                 uint8_t:5;
4049             } B;
4050         } MRSR;
4051 
4052         uint8_t ECSM_reserved0010[51]; /* 0x0010-0x0042 */
4053 
4054         union {                  /* ECC Configuration Register */
4055             uint8_t R;
4056             struct {
4057                 uint8_t:2;
4058                 uint8_t ER1BR:1;
4059                 uint8_t EF1BR:1;
4060                 uint8_t:2;
4061                 uint8_t ERNCR:1;
4062                 uint8_t EFNCR:1;
4063             } B;
4064         } ECR;
4065 
4066         uint8_t ECSM_reserved0044[3];  /* 0x0044-0x0046 */
4067 
4068         union {                  /* ECC Status Register */
4069             uint8_t R;
4070             struct {
4071                 uint8_t:2;
4072                 uint8_t R1BC:1;
4073                 uint8_t F1BC:1;
4074                 uint8_t:2;
4075                 uint8_t RNCE:1;
4076                 uint8_t FNCE:1;
4077             } B;
4078         } ESR;
4079 
4080     uint16_t ECSM_reserved0048; /* 0x0048-0x0049 */
4081 
4082         union {                 /* ECC Error Generation Register */
4083             uint16_t R;
4084             struct {
4085                 uint16_t:2;
4086                 uint16_t FRC1BI:1;
4087                 uint16_t FR11BI:1;
4088                 uint16_t:2;
4089                 uint16_t FRCNCI:1;
4090                 uint16_t FR1NCI:1;
4091                 uint16_t:1;
4092                 uint16_t ERRBIT:7;
4093             } B;
4094         } EEGR;
4095 
4096         uint32_t ECSM_reserved004C; /* 0x004C-0x004F */
4097 
4098         union {                 /* Flash ECC Address Register */
4099             uint32_t R;
4100             struct {
4101                 uint32_t FEAR:32;
4102             } B;
4103         } FEAR;
4104 
4105         uint16_t ECSM_reserved0054; /* 0x0054-0x0055 */
4106 
4107         union {                 /* Flash ECC Master Number Register */
4108             uint8_t R;
4109             struct {
4110                 uint8_t:4;
4111                 uint8_t FEMR:4;
4112             } B;
4113         } FEMR;
4114 
4115         union {                 /* Flash ECC Attributes Register */
4116             uint8_t R;
4117             struct {
4118                 uint8_t WRITE:1;
4119                 uint8_t SIZE:3;
4120                 uint8_t PROT0:1;
4121                 uint8_t PROT1:1;
4122                 uint8_t PROT2:1;
4123                 uint8_t PROT3:1;
4124             } B;
4125         } FEAT;
4126 
4127         union {                /* Flash ECC Data Register High */
4128             uint32_t R;
4129             struct {
4130                 uint32_t FEDH:32;
4131             } B;
4132         } FEDRH;
4133 
4134         union {                /* Flash ECC Data Register Low */
4135             uint32_t R;
4136             struct {
4137                 uint32_t FEDL:32;
4138             } B;
4139         } FEDRL;
4140 
4141         union {                /* RAM ECC Address Register */
4142             uint32_t R;
4143             struct {
4144                 uint32_t REAR:32;
4145             } B;
4146         } REAR;
4147 
4148         uint16_t ECSM_reserved0064; /* 0x0064-0x0065 */
4149 
4150         union {                 /* RAM ECC Master Number Register */
4151             uint8_t R;
4152             struct {
4153                 uint8_t:4;
4154                 uint8_t REMR:4;
4155             } B;
4156         } REMR;
4157 
4158         union {                 /* RAM ECC Attributes Register */
4159             uint8_t R;
4160             struct {
4161                 uint8_t WRITE:1;
4162                 uint8_t SIZE:3;
4163                 uint8_t PROT0:1;
4164                 uint8_t PROT1:1;
4165                 uint8_t PROT2:1;
4166                 uint8_t PROT3:1;
4167             } B;
4168         } REAT;
4169 
4170         union {                /* RAM ECC Data Register */
4171             uint32_t R;
4172             struct {
4173                 uint32_t REDH:32;
4174             } B;
4175         } REDRH;
4176 
4177         union {                /* RAM ECC Data Register */
4178             uint32_t R;
4179             struct {
4180                 uint32_t REDL:32;
4181             } B;
4182         } REDRL;
4183 
4184         uint32_t ECSM_reserved0070[4068]; /* 0x0070-0x3FFF */
4185 
4186     };
4187 
4188 /****************************************************************************/
4189 /*                          MODULE : INTC                                   */
4190 /****************************************************************************/
4191 
4192     struct INTC_tag {
4193 
4194         union {                  /* Module Configuration Register */
4195             uint32_t R;
4196             struct {
4197                 uint32_t:26;
4198                 uint32_t VTES:1;
4199                 uint32_t:4;
4200                 uint32_t HVEN:1;
4201             } B;
4202         } MCR;
4203 
4204         uint32_t INTC_reserved0004;  /* 0x0004-0x0007 */
4205 
4206         union {                  /* Current Priority Register */
4207             uint32_t R;
4208             struct {
4209                 uint32_t:28;
4210                 uint32_t PRI:4;
4211             } B;
4212         } CPR;
4213 
4214         uint32_t INTC_reserved000C;  /* 0x000C-0x000F */
4215 
4216         union {                /* Interrupt Acknowledge Register */
4217             uint32_t R;
4218             struct {
4219                 uint32_t VTBA:21;
4220                 uint32_t INTVEC:9;
4221                   uint32_t:2;
4222             } B;
4223         } IACKR;
4224 
4225         uint32_t INTC_reserved0014;  /* 0x0014-0x0017 */
4226 
4227         union {                 /* End of Interrupt Register */
4228             uint32_t R;
4229             struct {
4230                 uint32_t EOIR:32;
4231             } B;
4232         } EOIR;
4233 
4234         uint32_t INTC_reserved001C;  /* 0x001C-0x001F */
4235 
4236         union {             /* Software Set/Clear Interruput Register */
4237             uint8_t R;
4238             struct {
4239                 uint8_t:6;
4240                 uint8_t SET:1;
4241                 uint8_t CLR:1;
4242             } B;
4243         } SSCIR[8];
4244 
4245         uint32_t INTC_reserved0028[6]; /* 0x0028-0x003F */
4246 
4247         union {             /* Software Set/Clear Interrupt Register */
4248             uint8_t R;
4249             struct {
4250                 uint8_t:4;
4251                 uint8_t PRI:4;
4252             } B;
4253         } PSR[480];
4254 
4255         uint16_t INTC_reserved0220[7920]; /* 0x0220-0x3FFF */
4256 
4257     };
4258 
4259 /****************************************************************************/
4260 /*                          MODULE : EQADC                                  */
4261 /****************************************************************************/
4262 
4263     struct EQADC_tag {
4264 
4265         union EQADC_MCR_tag {  /* Module Configuration Register */
4266             uint32_t R;
4267             struct {
4268                 uint32_t:24;
4269                 uint32_t ICEA0:1;
4270                 uint32_t ICEA1:1;
4271                 uint32_t:1;
4272                 uint32_t ESSIE:2;
4273                 uint32_t:1;
4274                 uint32_t DBG:2;
4275             } B;
4276         } MCR;
4277 
4278         uint32_t eQADC_reserved0004;  /* 0x0004-0x0007 */
4279 
4280         union EQADC_NMSFR_tag { /* Null Message Send Format Register */
4281             uint32_t R;
4282             struct {
4283                 uint32_t:6;
4284                 uint32_t NMF:26;
4285             } B;
4286         } NMSFR;
4287 
4288         union EQADC_ETDFR_tag { /* External Trigger Digital Filter Register */
4289             uint32_t R;
4290             struct {
4291                 uint32_t:28;
4292                 uint32_t DFL:4;
4293             } B;
4294         } ETDFR;
4295 
4296         union EQADC_CFPR_tag { /* CFIFO Push Registers */
4297             uint32_t R;
4298             struct {
4299                 uint32_t CFPUSH:32;
4300             } B;
4301         } CFPR[6];
4302 
4303         uint32_t eQADC_reserved0028[2];  /* 0x0028-0x002F */
4304 
4305         union EQADC_RFPR_tag { /* Result FIFO Pop Registers */
4306             uint32_t R;
4307             struct {
4308                 uint32_t:16;
4309                 uint32_t RFPOP:16;
4310             } B;
4311         } RFPR[6];
4312 
4313         uint32_t eQADC_reserved0048[2];  /* 0x0048-0x004F */
4314 
4315         union EQADC_CFCR_tag { /* CFIFO Control Registers */
4316             uint16_t R;
4317             struct {
4318                 uint16_t:3;
4319                 uint16_t CFEEE0:1;
4320                 uint16_t STRME0:1;
4321                 uint16_t SSE:1;
4322                 uint16_t CFINV:1;
4323                 uint16_t:1;
4324                 uint16_t MODE:4;
4325                 uint16_t AMODE0:4;
4326             } B;
4327         } CFCR[6];
4328 
4329         uint32_t eQADC_reserved005C;  /* 0x005C-0x005F */
4330 
4331         union EQADC_IDCR_tag { /* Interrupt and DMA Control Registers */
4332             uint16_t R;
4333             struct {
4334                 uint16_t NCIE:1;
4335                 uint16_t TORIE:1;
4336                 uint16_t PIE:1;
4337                 uint16_t EOQIE:1;
4338                 uint16_t CFUIE:1;
4339                 uint16_t:1;
4340                 uint16_t CFFE:1;
4341                 uint16_t CFFS:1;
4342                 uint16_t:4;
4343                 uint16_t RFOIE:1;
4344                 uint16_t:1;
4345                 uint16_t RFDE:1;
4346                 uint16_t RFDS:1;
4347             } B;
4348         } IDCR[6];
4349 
4350         uint32_t eQADC_reserved006C;  /* 0x006C-0x006F */
4351 
4352         union {              /* FIFO and Interrupt Status Registers */
4353             uint32_t R;
4354             struct {
4355                 uint32_t NCF:1;
4356                 uint32_t TORF:1;
4357                 uint32_t PF:1;
4358                 uint32_t EOQF:1;
4359                 uint32_t CFUF:1;
4360                 uint32_t SSS:1;
4361                 uint32_t CFFF:1;
4362                 uint32_t:5;
4363                 uint32_t RFOF:1;
4364                 uint32_t:1;
4365                 uint32_t RFDF:1;
4366                 uint32_t:1;
4367                 uint32_t CFCTR:4;
4368                 uint32_t TNXTPTR:4;
4369                 uint32_t RFCTR:4;
4370                 uint32_t POPNXTPTR:4;
4371             } B;
4372         } FISR[6];
4373 
4374         uint32_t eQADC_reserved0088[2];  /* 0x0088-0x008F */
4375 
4376         union {             /* CFIFO Transfer Counter Registers */
4377             uint16_t R;
4378             struct {
4379                 uint16_t:5;
4380                 uint16_t TCCF:11; /* Legacy naming - refer to TC_CF in Reference Manual */
4381             } B;
4382         } CFTCR[6];
4383 
4384         uint32_t eQADC_reserved009C[1];  /* 0x009F */
4385 
4386         union {               /* CFIFO Status Register 0 */
4387             uint32_t R;
4388             struct {
4389                 uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB0 in Reference Manual */
4390                 uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB0 in Reference Manual */
4391                 uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB0 in Reference Manual */
4392                 uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB0 in Reference Manual */
4393                 uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB0 in Reference Manual */
4394                 uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB0 in Reference Manual */
4395                 uint32_t:5;
4396                 uint32_t LCFTCB0:4;
4397                 uint32_t TC_LCFTCB0:11;
4398             } B;
4399         } CFSSR0;
4400 
4401         union {               /* CFIFO Status Register 1 */
4402             uint32_t R;
4403             struct {
4404                 uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB1 in Reference Manual */
4405                 uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB1 in Reference Manual */
4406                 uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB1 in Reference Manual */
4407                 uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB1 in Reference Manual */
4408                 uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB1 in Reference Manual */
4409                 uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB1 in Reference Manual */
4410                 uint32_t:5;
4411                 uint32_t LCFTCB1:4;
4412                 uint32_t TC_LCFTCB1:11;
4413             } B;
4414         } CFSSR1;
4415 
4416         union {               /* CFIFO Status Register 2 */
4417             uint32_t R;
4418             struct {
4419                 uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TSSI in Reference Manual */
4420                 uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TSSI in Reference Manual */
4421                 uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TSSI in Reference Manual */
4422                 uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TSSI in Reference Manual */
4423                 uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TSSI in Reference Manual */
4424                 uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TSSI in Reference Manual */
4425                 uint32_t:4;
4426                 uint32_t ECBNI:1;
4427                 uint32_t LCFTSSI:4;
4428                 uint32_t TC_LCFTSSI:11;
4429             } B;
4430         } CFSSR2;
4431 
4432         union {                 /* CFIFO Status Register */
4433             uint32_t R;
4434             struct {
4435                 uint32_t CFS0:2;
4436                 uint32_t CFS1:2;
4437                 uint32_t CFS2:2;
4438                 uint32_t CFS3:2;
4439                 uint32_t CFS4:2;
4440                 uint32_t CFS5:2;
4441                   uint32_t:20;
4442             } B;
4443         } CFSR;
4444 
4445         uint32_t eQADC_reserved00B0;  /* 0x00B0-0x00B3 */
4446 
4447         union EQADC_SSICR_tag { /* SSI Control Register */
4448             uint32_t R;
4449             struct {
4450                 uint32_t:21;
4451                 uint32_t MDT:3;
4452                 uint32_t:4;
4453                 uint32_t BR:4;
4454             } B;
4455         } SSICR;
4456 
4457         union {               /* SSI Recieve Data Register */
4458             uint32_t R;
4459             struct {
4460                 uint32_t RDV:1;
4461                 uint32_t:5;
4462                 uint32_t RDATA:26;
4463             } B;
4464         } SSIRDR;
4465 
4466         uint32_t eQADC_reserved00BC[17];  /* 0x00BC-0x00FF */
4467 
4468         struct {
4469             union {
4470                 uint32_t R;
4471                 struct {
4472                     uint32_t CFIFO_DATA:32;
4473                 } B;
4474             } R[4];
4475 
4476             uint32_t eQADC_cf_reserved010[12];  /* CFIFO offset 0x010-0x03F */
4477 
4478         } CF[6];
4479 
4480         uint32_t eQADC_reserved0280[32];  /* 0x0280-0x02FF */
4481 
4482         struct {
4483             union {
4484                 uint32_t R;
4485                 struct {
4486                     uint32_t RFIFO_DATA:32;
4487                 } B;
4488             } R[4];
4489 
4490             uint32_t eQADC_rf_reserved010[12];  /* RFIFO offset 0x010-0x03F */
4491 
4492         } RF[6];
4493 
4494         uint32_t eQADC_reserved0480[3808];  /* 0x0480-0x3FFF */
4495     };
4496 
4497 /****************************************************************************/
4498 /*                          MODULE : Decimation Filter                      */
4499 /****************************************************************************/
4500 
4501     struct DECFIL_tag {
4502 
4503         union {                  /* Module Configuration Register */
4504             uint32_t R;
4505             struct {
4506                 uint32_t MDIS:1;
4507                 uint32_t FREN:1;
4508                 uint32_t :1;
4509                 uint32_t FRZ:1;
4510                 uint32_t SRES:1;
4511                 uint32_t CASCD:2;
4512                 uint32_t IDEN:1;
4513                 uint32_t ODEN:1;
4514                 uint32_t ERREN:1;
4515                 uint32_t :1;
4516                 uint32_t FTYPE:2;
4517                 uint32_t :1;
4518                 uint32_t SCAL:2;
4519                 uint32_t :1;
4520                 uint32_t SAT:1;
4521                 uint32_t ISEL:1;
4522                 uint32_t :1;
4523                 uint32_t DEC_RATE:4;
4524                 uint32_t :1;
4525                 uint32_t DSEL:1;
4526                 uint32_t IBIE:1;
4527                 uint32_t OBIE:1;
4528                 uint32_t EDME:1;
4529                 uint32_t TORE:1;
4530                 uint32_t TRFE:1;
4531                 uint32_t :1;
4532             } B;
4533         } MCR;
4534 
4535         union {                  /* Module Status Register */
4536             uint32_t R;
4537             struct {
4538                 uint32_t BSY:1;
4539                 uint32_t:1;
4540                 uint32_t DEC_COUNTER:4;
4541                 uint32_t IDFC:1;
4542                 uint32_t ODFC:1;
4543                 uint32_t:1;
4544                 uint32_t IBIC:1;
4545                 uint32_t OBIC:1;
4546                 uint32_t:1;
4547                 uint32_t DIVRC:1;
4548                 uint32_t OVFC:1;
4549                 uint32_t OVRC:1;
4550                 uint32_t IVRC:1;
4551                 uint32_t:6;
4552                 uint32_t IDF:1;
4553                 uint32_t ODF:1;
4554                 uint32_t:1;
4555                 uint32_t IBIF:1;
4556                 uint32_t OBIF:1;
4557                 uint32_t:1;
4558                 uint32_t DIVR:1;
4559                 uint32_t OVF:1;
4560                 uint32_t OVR:1;
4561                 uint32_t IVR:1;
4562             } B;
4563         } SR;
4564 
4565         union {                  /* Module Extended Config Register */
4566             uint32_t R;
4567             struct {
4568                 uint32_t SDMAE:1;
4569                 uint32_t SSIG:1;
4570                 uint32_t SSAT:1;
4571                 uint32_t SCSAT:1;
4572                 uint32_t:10;
4573                 uint32_t SRQ:1;
4574                 uint32_t SZR0:1;
4575                 uint32_t:1;
4576                 uint32_t SISEL:1;
4577                 uint32_t SZROSEL:2;
4578                 uint32_t:2;
4579                 uint32_t SHLTSEL:2;
4580                 uint32_t:1;
4581                 uint32_t SRQSEL:3;
4582                 uint32_t:2;
4583                 uint32_t SENSEL:2;
4584             } B;
4585         } MXCR;
4586 
4587         union {                  /* Module Extended Status Register */
4588             uint32_t R;
4589             struct {
4590                 uint32_t:7;
4591                 uint32_t SDFC:1;
4592                 uint32_t:2;
4593                 uint32_t SSEC:1;
4594                 uint32_t SCEC:1;
4595                 uint32_t:1;
4596                 uint32_t SSOVFC:1;
4597                 uint32_t SCOVFC:1;
4598                 uint32_t SVRC:1;
4599                 uint32_t:7;
4600                 uint32_t SDF:1;
4601                 uint32_t:2;
4602                 uint32_t SSE:1;
4603                 uint32_t SCE:1;
4604                 uint32_t:1;
4605                 uint32_t SSOVF:1;
4606                 uint32_t SCOVF:1;
4607                 uint32_t SVR:1;
4608           } B;
4609         } MXSR;
4610 
4611         union {                  /* Interface Input Buffer Register */
4612             uint32_t R;
4613             struct {
4614                 uint32_t:14;
4615                 uint32_t PREFILL:1;
4616                 uint32_t FLUSH:1;
4617                 uint32_t INPBUF:16;
4618             } B;
4619         } IB;
4620 
4621         union {                  /* Interface Output Buffer Register */
4622             uint32_t R;
4623             struct {
4624                 uint32_t:9;
4625                 uint32_t TSI:1;
4626                 uint32_t:2;
4627                 uint32_t OUTTAG:4;
4628                 uint32_t OUTBUF:16;
4629             } B;
4630         } OB;
4631 
4632         uint32_t DFILT_reserved0018[2];  /* 0x0018-0x001F */
4633 
4634         union {                  /* Coefficient n Register */
4635             int32_t R;
4636             struct {
4637                 int32_t:8;
4638                 int32_t COEF:24;
4639             } B;
4640         } COEF[9];
4641 
4642         uint32_t DFILT_reserved0044[13];  /* 0x0044-0x0077 */
4643 
4644         union {                  /* TAP n Register */
4645             int32_t R;
4646             struct {
4647                 int32_t:8;
4648                 int32_t TAP:24;
4649             } B;
4650         } TAP[8];
4651 
4652         uint32_t DFILT_reserved0098[14]; /* 0x0098-0x00CF */
4653 
4654         union {                  /* EDID Register */
4655             uint32_t R;
4656             struct {
4657                 uint32_t:16;
4658                 uint32_t SAMP_DATA:16;
4659             } B;
4660         } EDID;
4661 
4662         uint32_t DFILT_reserved00D4[459]; /* 0x00D4-0x07FF */
4663 
4664     };
4665 
4666 /****************************************************************************/
4667 /*                          MODULE : DSPI                                   */
4668 /****************************************************************************/
4669 
4670     struct DSPI_tag {
4671 
4672         union DSPI_MCR_tag {     /* Module Configuration Register */
4673             uint32_t R;
4674             struct {
4675                 uint32_t MSTR:1;
4676                 uint32_t CONT_SCKE:1;
4677                 uint32_t DCONF:2;
4678                 uint32_t FRZ:1;
4679                 uint32_t MTFE:1;
4680                 uint32_t PCSSE:1;
4681                 uint32_t ROOE:1;
4682                 uint32_t PCSIS7:1;
4683                 uint32_t PCSIS6:1;
4684                 uint32_t PCSIS5:1;
4685                 uint32_t PCSIS4:1;
4686                 uint32_t PCSIS3:1;
4687                 uint32_t PCSIS2:1;
4688                 uint32_t PCSIS1:1;
4689                 uint32_t PCSIS0:1;
4690                 uint32_t DOZE:1;
4691                 uint32_t MDIS:1;
4692                 uint32_t DIS_TXF:1;
4693                 uint32_t DIS_RXF:1;
4694                 uint32_t CLR_TXF:1;
4695                 uint32_t CLR_RXF:1;
4696                 uint32_t SMPL_PT:2;
4697                 uint32_t:7;
4698                 uint32_t HALT:1;
4699             } B;
4700         } MCR;
4701 
4702         uint32_t DSPI_reserved0004;  /* 0x0004-0x0007 */
4703 
4704         union {              /* Transfer Count Register */
4705             uint32_t R;
4706             struct {
4707                 uint32_t TCNT:16;
4708                 uint32_t:16;
4709             } B;
4710         } TCR;
4711 
4712         union DSPI_CTAR_tag {/* Clock and Transfer Attributes Registers */
4713             uint32_t R;
4714             struct {
4715                 uint32_t DBR:1;
4716                 uint32_t FMSZ:4;
4717                 uint32_t CPOL:1;
4718                 uint32_t CPHA:1;
4719                 uint32_t LSBFE:1;
4720                 uint32_t PCSSCK:2;
4721                 uint32_t PASC:2;
4722                 uint32_t PDT:2;
4723                 uint32_t PBR:2;
4724                 uint32_t CSSCK:4;
4725                 uint32_t ASC:4;
4726                 uint32_t DT:4;
4727                 uint32_t BR:4;
4728             } B;
4729         } CTAR[8];
4730 
4731         union DSPI_SR_tag {       /* Status Register */
4732             uint32_t R;
4733             struct {
4734                 uint32_t TCF:1;
4735                 uint32_t TXRXS:1;
4736                 uint32_t:1;
4737                 uint32_t EOQF:1;
4738                 uint32_t TFUF:1;
4739                 uint32_t:1;
4740                 uint32_t TFFF:1;
4741                 uint32_t:5;
4742                 uint32_t RFOF:1;
4743                 uint32_t:1;
4744                 uint32_t RFDF:1;
4745                 uint32_t:1;
4746                 uint32_t TXCTR:4;
4747                 uint32_t TXNXTPTR:4;
4748                 uint32_t RXCTR:4;
4749                 uint32_t POPNXTPTR:4;
4750             } B;
4751         } SR;
4752 
4753         union DSPI_RSER_tag {   /* DMA/Interrupt Request Select and Enable Register */
4754             uint32_t R;
4755             struct {
4756                 uint32_t TCFRE:1;
4757                 uint32_t:2;
4758                 uint32_t EOQFRE:1;
4759                 uint32_t TFUFRE:1;
4760                 uint32_t:1;
4761                 uint32_t TFFFRE:1;
4762                 uint32_t TFFFDIRS:1;
4763                 uint32_t:4;
4764                 uint32_t RFOFRE:1;
4765                 uint32_t:1;
4766                 uint32_t RFDFRE:1;
4767                 uint32_t RFDFDIRS:1;
4768                 uint32_t:16;
4769             } B;
4770         } RSER;
4771 
4772         union DSPI_PUSHR_tag { /* PUSH TX FIFO Register */
4773             uint32_t R;
4774             struct {
4775                 uint32_t CONT:1;
4776                 uint32_t CTAS:3;
4777                 uint32_t EOQ:1;
4778                 uint32_t CTCNT:1;
4779                 uint32_t:2;
4780                 uint32_t PCS7:1;
4781                 uint32_t PCS6:1;
4782                 uint32_t PCS5:1;
4783                 uint32_t PCS4:1;
4784                 uint32_t PCS3:1;
4785                 uint32_t PCS2:1;
4786                 uint32_t PCS1:1;
4787                 uint32_t PCS0:1;
4788                 uint32_t TXDATA:16;
4789             } B;
4790         } PUSHR;
4791 
4792         union DSPI_POPR_tag {   /* POP RX FIFO Register */
4793             uint32_t R;
4794             struct {
4795                 uint32_t:16;
4796                 uint32_t RXDATA:16;
4797             } B;
4798         } POPR;
4799 
4800         union {              /* Transmit FIFO Registers */
4801             uint32_t R;
4802             struct {
4803                 uint32_t TXCMD:16;
4804                 uint32_t TXDATA:16;
4805             } B;
4806         } TXFR[4];
4807 
4808         uint32_t DSPI_reserved004C[12]; /* 0x004C-0x007B */
4809 
4810         union {              /* Transmit FIFO Registers */
4811             uint32_t R;
4812             struct {
4813                 uint32_t:16;
4814                 uint32_t RXDATA:16;
4815             } B;
4816         } RXFR[4];
4817 
4818         uint32_t DSPI_reserved008C[12]; /* 0x008C-0x00BB */
4819 
4820         union {                /* DSI Configuration Register */
4821             uint32_t R;
4822             struct {
4823                 uint32_t MTOE:1;
4824                 uint32_t:1;
4825                 uint32_t MTOCNT:6;
4826                 uint32_t:3;
4827                 uint32_t TSBC:1;
4828                 uint32_t TXSS:1;
4829                 uint32_t TPOL:1;
4830                 uint32_t TRRE:1;
4831                 uint32_t CID:1;
4832                 uint32_t DCONT:1;
4833                 uint32_t DSICTAS:3;
4834                 uint32_t:4;
4835                 uint32_t DPCS7:1;
4836                 uint32_t DPCS6:1;
4837                 uint32_t DPCS5:1;
4838                 uint32_t DPCS4:1;
4839                 uint32_t DPCS3:1;
4840                 uint32_t DPCS2:1;
4841                 uint32_t DPCS1:1;
4842                 uint32_t DPCS0:1;
4843             } B;
4844         } DSICR;
4845 
4846         union {                  /* DSI Serialization Data Register */
4847             uint32_t R;
4848             struct {
4849                 uint32_t SER_DATA:32;
4850             } B;
4851         } SDR;
4852 
4853         union {                 /* DSI Alternate Serialization Data Register */
4854             uint32_t R;
4855             struct {
4856                 uint32_t ASER_DATA:32;
4857             } B;
4858         } ASDR;
4859 
4860         union {                /* DSI Transmit Comparison Register */
4861             uint32_t R;
4862             struct {
4863                 uint32_t COMP_DATA:32;
4864             } B;
4865         } COMPR;
4866 
4867         union {                  /* DSI deserialization Data Register */
4868             uint32_t R;
4869             struct {
4870                 uint32_t DESER_DATA:32;
4871             } B;
4872         } DDR;
4873 
4874         union {
4875             uint32_t R;
4876             struct {
4877                 uint32_t:3;
4878                 uint32_t TSBCNT:5;
4879                   uint32_t:16;
4880                 uint32_t DPCS1_7:1;
4881                 uint32_t DPCS1_6:1;
4882                 uint32_t DPCS1_5:1;
4883                 uint32_t DPCS1_4:1;
4884                 uint32_t DPCS1_3:1;
4885                 uint32_t DPCS1_2:1;
4886                 uint32_t DPCS1_1:1;
4887                 uint32_t DPCS1_0:1;
4888             } B;
4889         } DSICR1;
4890         uint32_t DSPI_reserved00D4[4043];  /* 0x00D4-0x3FFF */
4891 
4892     };
4893 
4894 /****************************************************************************/
4895 /*                          MODULE : eSCI                                   */
4896 /****************************************************************************/
4897 
4898     struct ESCI_tag {
4899         union ESCI_CR1_tag {     /* Control Register 1 */
4900             uint32_t R;
4901             struct {
4902                 uint32_t:3;
4903                 uint32_t SBR:13;
4904                 uint32_t LOOPS:1;
4905                 uint32_t:1;
4906                 uint32_t RSRC:1;
4907                 uint32_t M:1;
4908                 uint32_t WAKE:1;
4909                 uint32_t ILT:1;
4910                 uint32_t PE:1;
4911                 uint32_t PT:1;
4912                 uint32_t TIE:1;
4913                 uint32_t TCIE:1;
4914                 uint32_t RIE:1;
4915                 uint32_t ILIE:1;
4916                 uint32_t TE:1;
4917                 uint32_t RE:1;
4918                 uint32_t RWU:1;
4919                 uint32_t SBK:1;
4920             } B;
4921         } CR1;
4922 
4923         union ESCI_CR2_tag {     /* Control Register 2 */
4924             uint16_t R;
4925             struct {
4926                 uint16_t MDIS:1;
4927                 uint16_t FBR:1;
4928                 uint16_t BSTP:1;
4929                 uint16_t IEBERR:1;
4930                 uint16_t RXDMA:1;
4931                 uint16_t TXDMA:1;
4932                 uint16_t BRK13:1;
4933                 uint16_t TXDIR:1;
4934                 uint16_t BESM13:1;
4935                 uint16_t SBSTP:1;
4936                 uint16_t RXPOL:1;
4937                 uint16_t PMSK:1;
4938                 uint16_t ORIE:1;
4939                 uint16_t NFIE:1;
4940                 uint16_t FEIE:1;
4941                 uint16_t PFIE:1;
4942             } B;
4943         } CR2;
4944 
4945         union ESCI_DR_tag {       /* Data Register */
4946             uint16_t R;
4947 
4948             struct {
4949                 uint16_t RN:1;
4950                 uint16_t TN:1;
4951                 uint16_t ERR:1;
4952                 uint16_t:1;
4953                 uint16_t RD_11:4;
4954                 uint16_t D:8;
4955             } B;
4956         } DR; /* Legacy naming - refer to SDR in Reference Manual */
4957 
4958         union ESCI_SR_tag {       /* Status Register */
4959             uint32_t R;
4960             struct {
4961                 uint32_t TDRE:1;
4962                 uint32_t TC:1;
4963                 uint32_t RDRF:1;
4964                 uint32_t IDLE:1;
4965                 uint32_t OR:1;
4966                 uint32_t NF:1;
4967                 uint32_t FE:1;
4968                 uint32_t PF:1;
4969                 uint32_t:3;
4970                 uint32_t BERR:1;
4971                 uint32_t:2;
4972                 uint32_t TACT:1;
4973                 uint32_t RAF:1;
4974                 uint32_t RXRDY:1;
4975                 uint32_t TXRDY:1;
4976                 uint32_t LWAKE:1;
4977                 uint32_t STO:1;
4978                 uint32_t PBERR:1;
4979                 uint32_t CERR:1;
4980                 uint32_t CKERR:1;
4981                 uint32_t FRC:1;
4982                 uint32_t:6;
4983                 uint32_t UREQ:1;
4984                 uint32_t OVFL:1;
4985             } B;
4986         } SR;
4987 
4988         union {                  /* LIN Control Register */
4989             uint32_t R;
4990             struct {
4991                 uint32_t LRES:1;
4992                 uint32_t WU:1;
4993                 uint32_t WUD0:1;
4994                 uint32_t WUD1:1;
4995                 uint32_t :2;
4996                 uint32_t PRTY:1;
4997                 uint32_t LIN:1;
4998                 uint32_t RXIE:1;
4999                 uint32_t TXIE:1;
5000                 uint32_t WUIE:1;
5001                 uint32_t STIE:1;
5002                 uint32_t PBIE:1;
5003                 uint32_t CIE:1;
5004                 uint32_t CKIE:1;
5005                 uint32_t FCIE:1;
5006                 uint32_t:6;
5007                 uint32_t UQIE:1;
5008                 uint32_t OFIE:1;
5009                 uint32_t:8;
5010             } B;
5011         } LCR;
5012 
5013         union {                  /* LIN Transmit Register */
5014             uint8_t R;
5015         } LTR;
5016 
5017         uint8_t eSCI_reserved0011[3];  /* 0x0011-0x0013 */
5018 
5019         union {                  /* LIN Recieve Register */
5020             uint8_t R;
5021             struct {
5022                 uint8_t D:8;
5023             } B;
5024         } LRR;
5025 
5026         uint8_t eSCI_reserved0015[3];  /* 0x0015-0x0017 */
5027 
5028         union {                  /* LIN CRC Polynom Register  */
5029             uint16_t R;
5030             struct {
5031                 uint16_t P:16;
5032             } B;
5033         } LPR;
5034 
5035         union {                  /* Control Register 3 */
5036             uint16_t R;
5037             struct {
5038                 uint16_t:3;
5039                 uint16_t SYNM:1;
5040                 uint16_t EROE:1;
5041                 uint16_t ERFE:1;
5042                 uint16_t ERPE:1;
5043                 uint16_t M2:1;
5044                 uint16_t:8;
5045             } B;
5046         } CR3;
5047 
5048         uint32_t eSCI_reserved001C; /* 0x001C-0x001F */
5049 
5050         uint32_t eSCI_reserved0020[4088];  /* 0x0020-0x3FFF */
5051 
5052     };
5053 
5054 /****************************************************************************/
5055 /*                          MODULE : FlexCAN                                */
5056 /****************************************************************************/
5057 
5058     struct FLEXCAN2_tag {
5059         union {                  /* Module Configuration Register */
5060             uint32_t R;
5061             struct {
5062                 uint32_t MDIS:1;
5063                 uint32_t FRZ:1;
5064                 uint32_t FEN:1;
5065                 uint32_t HALT:1;
5066                 uint32_t NOTRDY:1;
5067                 uint32_t WAK_MSK:1;
5068                 uint32_t SOFTRST:1;
5069                 uint32_t FRZACK:1;
5070                 uint32_t SUPV:1;
5071                 uint32_t SLF_WAK:1;
5072                 uint32_t WRNEN:1;
5073                 uint32_t MDISACK:1;
5074                 uint32_t WAK_SRC:1;
5075                 uint32_t DOZE:1;
5076                 uint32_t SRXDIS:1;
5077                 uint32_t BCC:1;
5078                 uint32_t:2;
5079                 uint32_t LPRIO_EN:1;
5080                 uint32_t AEN:1;
5081                 uint32_t:2;
5082                 uint32_t IDAM:2;
5083                 uint32_t:2;
5084                 uint32_t MAXMB:6;
5085             } B;
5086         } MCR;
5087 
5088         union {                   /* Control Register */
5089             uint32_t R;
5090             struct {
5091                 uint32_t PRESDIV:8;
5092                 uint32_t RJW:2;
5093                 uint32_t PSEG1:3;
5094                 uint32_t PSEG2:3;
5095                 uint32_t BOFFMSK:1;
5096                 uint32_t ERRMSK:1;
5097                 uint32_t CLKSRC:1;
5098                 uint32_t LPB:1;
5099                 uint32_t TWRNMSK:1;
5100                 uint32_t RWRNMSK:1;
5101                 uint32_t:2;
5102                 uint32_t SMP:1;
5103                 uint32_t BOFFREC:1;
5104                 uint32_t TSYN:1;
5105                 uint32_t LBUF:1;
5106                 uint32_t LOM:1;
5107                 uint32_t PROPSEG:3;
5108             } B;
5109         } CR; /* Legacy naming - refer to CTRL in Reference Manual */
5110 
5111         union {                /* Free Running Timer */
5112             uint32_t R;
5113         } TIMER;
5114 
5115         int32_t FLEXCAN_reserved000C;  /* 0x000C-0x000F */
5116 
5117         union {              /* RX Global Mask */
5118             uint32_t R;
5119             struct {
5120                 uint32_t MI31:1;
5121                 uint32_t MI30:1;
5122                 uint32_t MI29:1;
5123                 uint32_t MI28:1;
5124                 uint32_t MI27:1;
5125                 uint32_t MI26:1;
5126                 uint32_t MI25:1;
5127                 uint32_t MI24:1;
5128                 uint32_t MI23:1;
5129                 uint32_t MI22:1;
5130                 uint32_t MI21:1;
5131                 uint32_t MI20:1;
5132                 uint32_t MI19:1;
5133                 uint32_t MI18:1;
5134                 uint32_t MI17:1;
5135                 uint32_t MI16:1;
5136                 uint32_t MI15:1;
5137                 uint32_t MI14:1;
5138                 uint32_t MI13:1;
5139                 uint32_t MI12:1;
5140                 uint32_t MI11:1;
5141                 uint32_t MI10:1;
5142                 uint32_t MI9:1;
5143                 uint32_t MI8:1;
5144                 uint32_t MI7:1;
5145                 uint32_t MI6:1;
5146                 uint32_t MI5:1;
5147                 uint32_t MI4:1;
5148                 uint32_t MI3:1;
5149                 uint32_t MI2:1;
5150                 uint32_t MI1:1;
5151                 uint32_t MI0:1;
5152             } B;
5153         } RXGMASK;
5154 
5155         union {             /* RX 14 Mask */
5156             uint32_t R;
5157             struct {
5158                 uint32_t MI31:1;
5159                 uint32_t MI30:1;
5160                 uint32_t MI29:1;
5161                 uint32_t MI28:1;
5162                 uint32_t MI27:1;
5163                 uint32_t MI26:1;
5164                 uint32_t MI25:1;
5165                 uint32_t MI24:1;
5166                 uint32_t MI23:1;
5167                 uint32_t MI22:1;
5168                 uint32_t MI21:1;
5169                 uint32_t MI20:1;
5170                 uint32_t MI19:1;
5171                 uint32_t MI18:1;
5172                 uint32_t MI17:1;
5173                 uint32_t MI16:1;
5174                 uint32_t MI15:1;
5175                 uint32_t MI14:1;
5176                 uint32_t MI13:1;
5177                 uint32_t MI12:1;
5178                 uint32_t MI11:1;
5179                 uint32_t MI10:1;
5180                 uint32_t MI9:1;
5181                 uint32_t MI8:1;
5182                 uint32_t MI7:1;
5183                 uint32_t MI6:1;
5184                 uint32_t MI5:1;
5185                 uint32_t MI4:1;
5186                 uint32_t MI3:1;
5187                 uint32_t MI2:1;
5188                 uint32_t MI1:1;
5189                 uint32_t MI0:1;
5190             } B;
5191         } RX14MASK;
5192 
5193         union {             /* RX 15 Mask */
5194             uint32_t R;
5195             struct {
5196                 uint32_t MI31:1;
5197                 uint32_t MI30:1;
5198                 uint32_t MI29:1;
5199                 uint32_t MI28:1;
5200                 uint32_t MI27:1;
5201                 uint32_t MI26:1;
5202                 uint32_t MI25:1;
5203                 uint32_t MI24:1;
5204                 uint32_t MI23:1;
5205                 uint32_t MI22:1;
5206                 uint32_t MI21:1;
5207                 uint32_t MI20:1;
5208                 uint32_t MI19:1;
5209                 uint32_t MI18:1;
5210                 uint32_t MI17:1;
5211                 uint32_t MI16:1;
5212                 uint32_t MI15:1;
5213                 uint32_t MI14:1;
5214                 uint32_t MI13:1;
5215                 uint32_t MI12:1;
5216                 uint32_t MI11:1;
5217                 uint32_t MI10:1;
5218                 uint32_t MI9:1;
5219                 uint32_t MI8:1;
5220                 uint32_t MI7:1;
5221                 uint32_t MI6:1;
5222                 uint32_t MI5:1;
5223                 uint32_t MI4:1;
5224                 uint32_t MI3:1;
5225                 uint32_t MI2:1;
5226                 uint32_t MI1:1;
5227                 uint32_t MI0:1;
5228             } B;
5229         } RX15MASK;
5230 
5231         union {                  /* Error Counter Register */
5232             uint32_t R;
5233             struct {
5234                 uint32_t:16;
5235                 uint32_t RXECNT:8;
5236                 uint32_t TXECNT:8;
5237             } B;
5238         } ECR;
5239 
5240         union {                  /* Error and Status Register */
5241             uint32_t R;
5242             struct {
5243                 uint32_t:14;
5244 
5245                 uint32_t TWRNINT:1;
5246                 uint32_t RWRNINT:1;
5247                 uint32_t BIT1ERR:1;
5248                 uint32_t BIT0ERR:1;
5249                 uint32_t ACKERR:1;
5250                 uint32_t CRCERR:1;
5251                 uint32_t FRMERR:1;
5252                 uint32_t STFERR:1;
5253                 uint32_t TXWRN:1;
5254                 uint32_t RXWRN:1;
5255                 uint32_t IDLE:1;
5256                 uint32_t TXRX:1;
5257                 uint32_t FLTCONF:2;
5258                 uint32_t:1;
5259                 uint32_t BOFFINT:1;
5260                 uint32_t ERRINT:1;
5261                 uint32_t WAKINT:1;
5262             } B;
5263         } ESR;
5264 
5265         union {                 /* Interruput Masks Register */
5266             uint32_t R;
5267             struct {
5268                 uint32_t BUF63M:1;
5269                 uint32_t BUF62M:1;
5270                 uint32_t BUF61M:1;
5271                 uint32_t BUF60M:1;
5272                 uint32_t BUF59M:1;
5273                 uint32_t BUF58M:1;
5274                 uint32_t BUF57M:1;
5275                 uint32_t BUF56M:1;
5276                 uint32_t BUF55M:1;
5277                 uint32_t BUF54M:1;
5278                 uint32_t BUF53M:1;
5279                 uint32_t BUF52M:1;
5280                 uint32_t BUF51M:1;
5281                 uint32_t BUF50M:1;
5282                 uint32_t BUF49M:1;
5283                 uint32_t BUF48M:1;
5284                 uint32_t BUF47M:1;
5285                 uint32_t BUF46M:1;
5286                 uint32_t BUF45M:1;
5287                 uint32_t BUF44M:1;
5288                 uint32_t BUF43M:1;
5289                 uint32_t BUF42M:1;
5290                 uint32_t BUF41M:1;
5291                 uint32_t BUF40M:1;
5292                 uint32_t BUF39M:1;
5293                 uint32_t BUF38M:1;
5294                 uint32_t BUF37M:1;
5295                 uint32_t BUF36M:1;
5296                 uint32_t BUF35M:1;
5297                 uint32_t BUF34M:1;
5298                 uint32_t BUF33M:1;
5299                 uint32_t BUF32M:1;
5300             } B;
5301         } IMRH; /* Legacy naming - refer to IMASK2 in Reference Manual */
5302 
5303         union {                 /* Interruput Masks Register */
5304             uint32_t R;
5305             struct {
5306                 uint32_t BUF31M:1;
5307                 uint32_t BUF30M:1;
5308                 uint32_t BUF29M:1;
5309                 uint32_t BUF28M:1;
5310                 uint32_t BUF27M:1;
5311                 uint32_t BUF26M:1;
5312                 uint32_t BUF25M:1;
5313                 uint32_t BUF24M:1;
5314                 uint32_t BUF23M:1;
5315                 uint32_t BUF22M:1;
5316                 uint32_t BUF21M:1;
5317                 uint32_t BUF20M:1;
5318                 uint32_t BUF19M:1;
5319                 uint32_t BUF18M:1;
5320                 uint32_t BUF17M:1;
5321                 uint32_t BUF16M:1;
5322                 uint32_t BUF15M:1;
5323                 uint32_t BUF14M:1;
5324                 uint32_t BUF13M:1;
5325                 uint32_t BUF12M:1;
5326                 uint32_t BUF11M:1;
5327                 uint32_t BUF10M:1;
5328                 uint32_t BUF09M:1;
5329                 uint32_t BUF08M:1;
5330                 uint32_t BUF07M:1;
5331                 uint32_t BUF06M:1;
5332                 uint32_t BUF05M:1;
5333                 uint32_t BUF04M:1;
5334                 uint32_t BUF03M:1;
5335                 uint32_t BUF02M:1;
5336                 uint32_t BUF01M:1;
5337                 uint32_t BUF00M:1;
5338             } B;
5339         } IMRL; /* Legacy naming - refer to IMASK1 in Reference Manual */
5340 
5341         union {                 /* Interruput Flag Register */
5342             uint32_t R;
5343             struct {
5344                 uint32_t BUF63I:1;
5345                 uint32_t BUF62I:1;
5346                 uint32_t BUF61I:1;
5347                 uint32_t BUF60I:1;
5348                 uint32_t BUF59I:1;
5349                 uint32_t BUF58I:1;
5350                 uint32_t BUF57I:1;
5351                 uint32_t BUF56I:1;
5352                 uint32_t BUF55I:1;
5353                 uint32_t BUF54I:1;
5354                 uint32_t BUF53I:1;
5355                 uint32_t BUF52I:1;
5356                 uint32_t BUF51I:1;
5357                 uint32_t BUF50I:1;
5358                 uint32_t BUF49I:1;
5359                 uint32_t BUF48I:1;
5360                 uint32_t BUF47I:1;
5361                 uint32_t BUF46I:1;
5362                 uint32_t BUF45I:1;
5363                 uint32_t BUF44I:1;
5364                 uint32_t BUF43I:1;
5365                 uint32_t BUF42I:1;
5366                 uint32_t BUF41I:1;
5367                 uint32_t BUF40I:1;
5368                 uint32_t BUF39I:1;
5369                 uint32_t BUF38I:1;
5370                 uint32_t BUF37I:1;
5371                 uint32_t BUF36I:1;
5372                 uint32_t BUF35I:1;
5373                 uint32_t BUF34I:1;
5374                 uint32_t BUF33I:1;
5375                 uint32_t BUF32I:1;
5376             } B;
5377         } IFRH; /* Legacy naming - refer to IFLAG2 in Reference Manual */
5378 
5379         union {                 /* Interruput Flag Register */
5380             uint32_t R;
5381             struct {
5382                 uint32_t BUF31I:1;
5383                 uint32_t BUF30I:1;
5384                 uint32_t BUF29I:1;
5385                 uint32_t BUF28I:1;
5386                 uint32_t BUF27I:1;
5387                 uint32_t BUF26I:1;
5388                 uint32_t BUF25I:1;
5389                 uint32_t BUF24I:1;
5390                 uint32_t BUF23I:1;
5391                 uint32_t BUF22I:1;
5392                 uint32_t BUF21I:1;
5393                 uint32_t BUF20I:1;
5394                 uint32_t BUF19I:1;
5395                 uint32_t BUF18I:1;
5396                 uint32_t BUF17I:1;
5397                 uint32_t BUF16I:1;
5398                 uint32_t BUF15I:1;
5399                 uint32_t BUF14I:1;
5400                 uint32_t BUF13I:1;
5401                 uint32_t BUF12I:1;
5402                 uint32_t BUF11I:1;
5403                 uint32_t BUF10I:1;
5404                 uint32_t BUF09I:1;
5405                 uint32_t BUF08I:1;
5406                 uint32_t BUF07I:1;
5407                 uint32_t BUF06I:1;
5408                 uint32_t BUF05I:1;
5409                 uint32_t BUF04I:1;
5410                 uint32_t BUF03I:1;
5411                 uint32_t BUF02I:1;
5412                 uint32_t BUF01I:1;
5413                 uint32_t BUF00I:1;
5414             } B;
5415         } IFRL; /* Legacy naming - refer to IFLAG1 in Reference Manual */
5416 
5417         uint32_t FLEXCAN_reserved0034[19];  /* 0x0034-0x007F */
5418 
5419         struct canbuf_t {
5420             union {
5421                 uint32_t R;
5422                 struct {
5423                     uint32_t:4;
5424                     uint32_t CODE:4;
5425                     uint32_t:1;
5426                     uint32_t SRR:1;
5427                     uint32_t IDE:1;
5428                     uint32_t RTR:1;
5429                     uint32_t LENGTH:4;
5430                     uint32_t TIMESTAMP:16;
5431                 } B;
5432             } CS;
5433 
5434             union {
5435                 uint32_t R;
5436                 struct {
5437                     uint32_t PRIO:3;
5438                     uint32_t STD_ID:11;
5439                     uint32_t EXT_ID:18;
5440                 } B;
5441             } ID;
5442 
5443             union {
5444                 uint8_t B[8];  /* Data buffer in Bytes (8 bits) */
5445                 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
5446                 uint32_t W[2]; /* Data buffer in words (32 bits) */
5447                 uint32_t R[2]; /* Data buffer in words (32 bits) */
5448             } DATA;
5449 
5450         } BUF[64];
5451 
5452         int32_t FLEXCAN_reserved0480[256]; /* 0x0480-0x087F */
5453 
5454         union {            /* RX Individual Mask Registers */
5455             uint32_t R;
5456             struct {
5457                 uint32_t MI31:1;
5458                 uint32_t MI30:1;
5459                 uint32_t MI29:1;
5460                 uint32_t MI28:1;
5461                 uint32_t MI27:1;
5462                 uint32_t MI26:1;
5463                 uint32_t MI25:1;
5464                 uint32_t MI24:1;
5465                 uint32_t MI23:1;
5466                 uint32_t MI22:1;
5467                 uint32_t MI21:1;
5468                 uint32_t MI20:1;
5469                 uint32_t MI19:1;
5470                 uint32_t MI18:1;
5471                 uint32_t MI17:1;
5472                 uint32_t MI16:1;
5473                 uint32_t MI15:1;
5474                 uint32_t MI14:1;
5475                 uint32_t MI13:1;
5476                 uint32_t MI12:1;
5477                 uint32_t MI11:1;
5478                 uint32_t MI10:1;
5479                 uint32_t MI9:1;
5480                 uint32_t MI8:1;
5481                 uint32_t MI7:1;
5482                 uint32_t MI6:1;
5483                 uint32_t MI5:1;
5484                 uint32_t MI4:1;
5485                 uint32_t MI3:1;
5486                 uint32_t MI2:1;
5487                 uint32_t MI1:1;
5488                 uint32_t MI0:1;
5489             } B;
5490         } RXIMR[64];
5491 
5492         int32_t FLEXCAN_reserved0980[3488]; /* 0x0980-0x3FFF */
5493 
5494     };
5495 
5496 /****************************************************************************/
5497 /*                          MODULE : FlexRay                                */
5498 /****************************************************************************/
5499 
5500     typedef union uMVR {
5501         uint16_t R;
5502         struct {
5503             uint16_t CHIVER:8; /* CHI Version Number */
5504             uint16_t PEVER:8;  /* PE Version Number */
5505         } B;
5506     } MVR_t;
5507 
5508     typedef union uMCR {
5509         uint16_t R;
5510         struct {
5511             uint16_t MEN:1;    /* module enable */
5512               uint16_t:1;
5513             uint16_t SCMD:1;   /* single channel mode */
5514             uint16_t CHB:1;    /* channel B enable */
5515             uint16_t CHA:1;    /* channel A enable */
5516             uint16_t SFFE:1;   /* synchronization frame filter enable */
5517               uint16_t:5;
5518             uint16_t CLKSEL:1; /* protocol engine clock source select */
5519             uint16_t PRESCALE:3;       /* protocol engine clock prescaler */
5520               uint16_t:1;
5521         } B;
5522     } MCR_t;
5523 
5524     typedef union uSTBSCR {
5525         uint16_t R;
5526         struct {
5527             uint16_t WMD:1;    /* write mode */
5528             uint16_t STBSSEL:7;        /* strobe signal select */
5529               uint16_t:3;
5530             uint16_t ENB:1;    /* strobe signal enable */
5531               uint16_t:2;
5532             uint16_t STBPSEL:2;        /* strobe port select */
5533         } B;
5534     } STBSCR_t;
5535     typedef union uSTBPCR {
5536         uint16_t R;
5537         struct {
5538             uint16_t:12;
5539             uint16_t STB3EN:1; /* strobe port enable */
5540             uint16_t STB2EN:1; /* strobe port enable */
5541             uint16_t STB1EN:1; /* strobe port enable */
5542             uint16_t STB0EN:1; /* strobe port enable */
5543         } B;
5544     } STBPCR_t;
5545 
5546     typedef union uMBDSR {
5547         uint16_t R;
5548         struct {
5549             uint16_t:1;
5550             uint16_t MBSEG2DS:7;       /* message buffer segment 2 data size */
5551               uint16_t:1;
5552             uint16_t MBSEG1DS:7;       /* message buffer segment 1 data size */
5553         } B;
5554     } MBDSR_t;
5555     typedef union uMBSSUTR {
5556         uint16_t R;
5557         struct {
5558 
5559             uint16_t:1;
5560             uint16_t LAST_MB_SEG1:7;   /* last message buffer control register for message buffer segment 1 */
5561               uint16_t:1;
5562             uint16_t LAST_MB_UTIL:7;   /* last message buffer utilized */
5563         } B;
5564     } MBSSUTR_t;
5565 
5566     typedef union uPOCR {
5567         uint16_t R;
5568         uint8_t byte[2];
5569         struct {
5570             uint16_t WME:1;    /* write mode external correction command */
5571               uint16_t:3;
5572             uint16_t EOC_AP:2; /* external offset correction application */
5573             uint16_t ERC_AP:2; /* external rate correction application */
5574             uint16_t BSY:1;    /* command write busy / write mode command */
5575               uint16_t:3;
5576             uint16_t POCCMD:4; /* protocol command */
5577         } B;
5578     } POCR_t;
5579 /* protocol commands */
5580     typedef union uGIFER {
5581         uint16_t R;
5582         struct {
5583             uint16_t MIF:1;    /* module interrupt flag */
5584             uint16_t PRIF:1;   /* protocol interrupt flag */
5585             uint16_t CHIF:1;   /* CHI interrupt flag */
5586             uint16_t WKUPIF:1; /* wakeup interrupt flag */
5587             uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
5588             uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
5589             uint16_t RBIF:1;   /* receive message buffer interrupt flag */
5590             uint16_t TBIF:1;   /* transmit buffer interrupt flag */
5591             uint16_t MIE:1;    /* module interrupt enable */
5592             uint16_t PRIE:1;   /* protocol interrupt enable */
5593             uint16_t CHIE:1;   /* CHI interrupt enable */
5594             uint16_t WKUPIE:1; /* wakeup interrupt enable */
5595             uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
5596             uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
5597             uint16_t RBIE:1;   /* receive message buffer interrupt enable */
5598             uint16_t TBIE:1;   /* transmit buffer interrupt enable */
5599         } B;
5600     } GIFER_t;
5601     typedef union uPIFR0 {
5602         uint16_t R;
5603         struct {
5604             uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
5605             uint16_t INTLIF:1; /* internal protocol error interrupt flag */
5606             uint16_t ILCFIF:1; /* illegal protocol configuration flag */
5607             uint16_t CSAIF:1;  /* cold start abort interrupt flag */
5608             uint16_t MRCIF:1;  /* missing rate correctio interrupt flag */
5609             uint16_t MOCIF:1;  /* missing offset correctio interrupt flag */
5610             uint16_t CCLIF:1;  /* clock correction limit reached interrupt flag */
5611             uint16_t MXSIF:1;  /* max sync frames detected interrupt flag */
5612             uint16_t MTXIF:1;  /* media access test symbol received flag */
5613             uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
5614             uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
5615             uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
5616             uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
5617             uint16_t TI2IF:1;  /* timer 2 expired interrupt flag */
5618             uint16_t TI1IF:1;  /* timer 1 expired interrupt flag */
5619             uint16_t CYSIF:1;  /* cycle start interrupt flag */
5620         } B;
5621     } PIFR0_t;
5622     typedef union uPIFR1 {
5623         uint16_t R;
5624         struct {
5625             uint16_t EMCIF:1;  /* error mode changed interrupt flag */
5626             uint16_t IPCIF:1;  /* illegal protocol command interrupt flag */
5627             uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
5628             uint16_t PSCIF:1;  /* Protocol State Changed Interrupt Flag */
5629             uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
5630             uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
5631             uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
5632             uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
5633               uint16_t:2;
5634             uint16_t EVTIF:1;  /* even cycle table written interrupt flag */
5635             uint16_t ODTIF:1;  /* odd cycle table written interrupt flag */
5636               uint16_t:4;
5637         } B;
5638     } PIFR1_t;
5639     typedef union uPIER0 {
5640         uint16_t R;
5641         struct {
5642             uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
5643             uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable  */
5644             uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
5645             uint16_t CSAIE:1;  /* cold start abort interrupt enable */
5646             uint16_t MRCIE:1;  /* missing rate correctio interrupt enable */
5647             uint16_t MOCIE:1;  /* missing offset correctio interrupt enable */
5648             uint16_t CCLIE:1;  /* clock correction limit reached interrupt enable */
5649             uint16_t MXSIE:1;  /* max sync frames detected interrupt enable */
5650             uint16_t MTXIE:1;  /* media access test symbol received interrupt enable */
5651             uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
5652             uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
5653             uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
5654             uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
5655             uint16_t TI2IE:1;  /* timer 2 expired interrupt enable */
5656             uint16_t TI1IE:1;  /* timer 1 expired interrupt enable */
5657             uint16_t CYSIE:1;  /* cycle start interrupt enable */
5658         } B;
5659     } PIER0_t;
5660     typedef union uPIER1 {
5661         uint16_t R;
5662         struct {
5663             uint16_t EMCIE:1;  /* error mode changed interrupt enable */
5664             uint16_t IPCIE:1;  /* illegal protocol command interrupt enable */
5665             uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
5666             uint16_t PSCIE:1;  /* Protocol State Changed Interrupt enable */
5667             uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
5668             uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
5669             uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
5670             uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
5671               uint16_t:2;
5672             uint16_t EVTIE:1;  /* even cycle table written interrupt enable */
5673             uint16_t ODTIE:1;  /* odd cycle table written interrupt enable */
5674               uint16_t:4;
5675         } B;
5676     } PIER1_t;
5677     typedef union uCHIERFR {
5678         uint16_t R;
5679         struct {
5680             uint16_t FRLBEF:1; /* flame lost channel B error flag */
5681             uint16_t FRLAEF:1; /* frame lost channel A error flag */
5682             uint16_t PCMIEF:1; /* command ignored error flag */
5683             uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
5684             uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
5685             uint16_t MSBEF:1;  /* message buffer search error flag */
5686             uint16_t MBUEF:1;  /* message buffer utilization error flag */
5687             uint16_t LCKEF:1;  /* lock error flag */
5688             uint16_t DBLEF:1;  /* double transmit message buffer lock error flag */
5689             uint16_t SBCFEF:1; /* system bus communication failure error flag */
5690             uint16_t FIDEF:1;  /* frame ID error flag */
5691             uint16_t DPLEF:1;  /* dynamic payload length error flag */
5692             uint16_t SPLEF:1;  /* static payload length error flag */
5693             uint16_t NMLEF:1;  /* network management length error flag */
5694             uint16_t NMFEF:1;  /* network management frame error flag */
5695             uint16_t ILSAEF:1; /* illegal access error flag */
5696         } B;
5697     } CHIERFR_t;
5698     typedef union uMBIVEC {
5699         uint16_t R;
5700         struct {
5701 
5702             uint16_t:1;
5703             uint16_t TBIVEC:7; /* transmit buffer interrupt vector */
5704               uint16_t:1;
5705             uint16_t RBIVEC:7; /* receive buffer interrupt vector */
5706         } B;
5707     } MBIVEC_t;
5708 
5709     typedef union uPSR0 {
5710         uint16_t R;
5711         struct {
5712             uint16_t ERRMODE:2;        /* error mode */
5713             uint16_t SLOTMODE:2;       /* slot mode */
5714               uint16_t:1;
5715             uint16_t PROTSTATE:3;      /* protocol state */
5716             uint16_t SUBSTATE:4;       /* protocol sub state */
5717               uint16_t:1;
5718             uint16_t WAKEUPSTATUS:3;   /* wakeup status */
5719         } B;
5720     } PSR0_t;
5721 
5722 /* protocol states */
5723 /* protocol sub-states */
5724 /* wakeup status */
5725     typedef union uPSR1 {
5726         uint16_t R;
5727         struct {
5728             uint16_t CSAA:1;   /* cold start attempt abort flag */
5729             uint16_t SCP:1;    /* cold start path */
5730               uint16_t:1;
5731             uint16_t REMCSAT:5;        /* remanining coldstart attempts */
5732             uint16_t CPN:1;    /* cold start noise path */
5733             uint16_t HHR:1;    /* host halt request pending */
5734             uint16_t FRZ:1;    /* freeze occured */
5735             uint16_t APTAC:5;  /* allow passive to active counter */
5736         } B;
5737     } PSR1_t;
5738     typedef union uPSR2 {
5739         uint16_t R;
5740         struct {
5741             uint16_t NBVB:1;   /* NIT boundary violation on channel B */
5742             uint16_t NSEB:1;   /* NIT syntax error on channel B */
5743             uint16_t STCB:1;   /* symbol window transmit conflict on channel B */
5744             uint16_t SBVB:1;   /* symbol window boundary violation on channel B */
5745             uint16_t SSEB:1;   /* symbol window syntax error on channel B */
5746             uint16_t MTB:1;    /* media access test symbol MTS received on channel B */
5747             uint16_t NBVA:1;   /* NIT boundary violation on channel A */
5748             uint16_t NSEA:1;   /* NIT syntax error on channel A */
5749             uint16_t STCA:1;   /* symbol window transmit conflict on channel A */
5750             uint16_t SBVA:1;   /* symbol window boundary violation on channel A */
5751             uint16_t SSEA:1;   /* symbol window syntax error on channel A */
5752             uint16_t MTA:1;    /* media access test symbol MTS received on channel A */
5753             uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
5754         } B;
5755     } PSR2_t;
5756     typedef union uPSR3 {
5757         uint16_t R;
5758         struct {
5759             uint16_t:2;
5760             uint16_t WUB:1;    /* wakeup symbol received on channel B */
5761             uint16_t ABVB:1;   /* aggregated boundary violation on channel B */
5762             uint16_t AACB:1;   /* aggregated additional communication on channel B */
5763             uint16_t ACEB:1;   /* aggregated content error on channel B */
5764             uint16_t ASEB:1;   /* aggregated syntax error on channel B */
5765             uint16_t AVFB:1;   /* aggregated valid frame on channel B */
5766               uint16_t:2;
5767             uint16_t WUA:1;    /* wakeup symbol received on channel A */
5768             uint16_t ABVA:1;   /* aggregated boundary violation on channel A */
5769             uint16_t AACA:1;   /* aggregated additional communication on channel A */
5770             uint16_t ACEA:1;   /* aggregated content error on channel A */
5771             uint16_t ASEA:1;   /* aggregated syntax error on channel A */
5772             uint16_t AVFA:1;   /* aggregated valid frame on channel A */
5773         } B;
5774     } PSR3_t;
5775     typedef union uCIFRR {
5776         uint16_t R;
5777         struct {
5778             uint16_t:8;
5779             uint16_t MIFR:1;   /* module interrupt flag */
5780             uint16_t PRIFR:1;  /* protocol interrupt flag */
5781             uint16_t CHIFR:1;  /* CHI interrupt flag */
5782             uint16_t WUPIFR:1; /* wakeup interrupt flag */
5783             uint16_t FNEBIFR:1;        /* receive fifo channel B no empty interrupt flag */
5784             uint16_t FNEAIFR:1;        /* receive fifo channel A no empty interrupt flag */
5785             uint16_t RBIFR:1;  /* receive message buffer interrupt flag */
5786             uint16_t TBIFR:1;  /* transmit buffer interrupt flag */
5787         } B;
5788     } CIFRR_t;
5789     typedef union uSFCNTR {
5790         uint16_t R;
5791         struct {
5792             uint16_t SFEVB:4;  /* sync frames channel B, even cycle */
5793             uint16_t SFEVA:4;  /* sync frames channel A, even cycle */
5794             uint16_t SFODB:4;  /* sync frames channel B, odd cycle */
5795             uint16_t SFODA:4;  /* sync frames channel A, odd cycle */
5796         } B;
5797     } SFCNTR_t;
5798 
5799     typedef union uSFTCCSR {
5800         uint16_t R;
5801         struct {
5802             uint16_t ELKT:1;   /* even cycle tables lock and unlock trigger */
5803             uint16_t OLKT:1;   /* odd cycle tables lock and unlock trigger */
5804             uint16_t CYCNUM:6; /* cycle number */
5805             uint16_t ELKS:1;   /* even cycle tables lock status */
5806             uint16_t OLKS:1;   /* odd cycle tables lock status */
5807             uint16_t EVAL:1;   /* even cycle tables valid */
5808             uint16_t OVAL:1;   /* odd cycle tables valid */
5809               uint16_t:1;
5810             uint16_t OPT:1;    /*one pair trigger */
5811             uint16_t SDVEN:1;  /* sync frame deviation table enable */
5812             uint16_t SIDEN:1;  /* sync frame ID table enable */
5813         } B;
5814     } SFTCCSR_t;
5815     typedef union uSFIDRFR {
5816         uint16_t R;
5817         struct {
5818             uint16_t:6;
5819             uint16_t SYNFRID:10;       /* sync frame rejection ID */
5820         } B;
5821     } SFIDRFR_t;
5822 
5823     typedef union uTICCR {
5824         uint16_t R;
5825         struct {
5826             uint16_t:2;
5827             uint16_t T2CFG:1;  /* timer 2 configuration */
5828             uint16_t T2REP:1;  /* timer 2 repetitive mode */
5829               uint16_t:1;
5830             uint16_t T2SP:1;   /* timer 2 stop */
5831             uint16_t T2TR:1;   /* timer 2 trigger */
5832             uint16_t T2ST:1;   /* timer 2 state */
5833               uint16_t:3;
5834             uint16_t T1REP:1;  /* timer 1 repetitive mode */
5835               uint16_t:1;
5836             uint16_t T1SP:1;   /* timer 1 stop */
5837             uint16_t T1TR:1;   /* timer 1 trigger */
5838             uint16_t T1ST:1;   /* timer 1 state */
5839 
5840         } B;
5841     } TICCR_t;
5842     typedef union uTI1CYSR {
5843         uint16_t R;
5844         struct {
5845             uint16_t:2;
5846             uint16_t TI1CYCVAL:6;      /* timer 1 cycle filter value */
5847               uint16_t:2;
5848             uint16_t TI1CYCMSK:6;      /* timer 1 cycle filter mask */
5849 
5850         } B;
5851     } TI1CYSR_t;
5852 
5853     typedef union uSSSR {
5854         uint16_t R;
5855         struct {
5856             uint16_t WMD:1;    /* write mode */
5857               uint16_t:1;
5858             uint16_t SEL:2;    /* static slot number */
5859               uint16_t:1;
5860             uint16_t SLOTNUMBER:11;    /* selector */
5861         } B;
5862     } SSSR_t;
5863 
5864     typedef union uSSCCR {
5865         uint16_t R;
5866         struct {
5867             uint16_t WMD:1;    /* write mode */
5868               uint16_t:1;
5869             uint16_t SEL:2;    /* selector */
5870               uint16_t:1;
5871             uint16_t CNTCFG:2; /* counter configuration */
5872             uint16_t MCY:1;    /* multi cycle selection */
5873             uint16_t VFR:1;    /* valid frame selection */
5874             uint16_t SYF:1;    /* sync frame selection */
5875             uint16_t NUF:1;    /* null frame selection  */
5876             uint16_t SUF:1;    /* startup frame selection */
5877             uint16_t STATUSMASK:4;     /* slot status mask */
5878         } B;
5879     } SSCCR_t;
5880     typedef union uSSR {
5881         uint16_t R;
5882         struct {
5883             uint16_t VFB:1;    /* valid frame on channel B */
5884             uint16_t SYB:1;    /* valid sync frame on channel B */
5885             uint16_t NFB:1;    /* valid null frame on channel B */
5886             uint16_t SUB:1;    /* valid startup frame on channel B */
5887             uint16_t SEB:1;    /* syntax error on channel B */
5888             uint16_t CEB:1;    /* content error on channel B */
5889             uint16_t BVB:1;    /* boundary violation on channel B */
5890             uint16_t TCB:1;    /* tx conflict on channel B */
5891             uint16_t VFA:1;    /* valid frame on channel A */
5892             uint16_t SYA:1;    /* valid sync frame on channel A */
5893             uint16_t NFA:1;    /* valid null frame on channel A */
5894             uint16_t SUA:1;    /* valid startup frame on channel A */
5895             uint16_t SEA:1;    /* syntax error on channel A */
5896             uint16_t CEA:1;    /* content error on channel A */
5897             uint16_t BVA:1;    /* boundary violation on channel A */
5898             uint16_t TCA:1;    /* tx conflict on channel A */
5899         } B;
5900     } SSR_t;
5901     typedef union uMTSCFR {
5902         uint16_t R;
5903         struct {
5904             uint16_t MTE:1;    /* media access test symbol transmission enable */
5905               uint16_t:1;
5906             uint16_t CYCCNTMSK:6;      /* cycle counter mask */
5907               uint16_t:2;
5908             uint16_t CYCCNTVAL:6;      /* cycle counter value */
5909         } B;
5910     } MTSCFR_t;
5911     typedef union uRSBIR {
5912         uint16_t R;
5913         struct {
5914             uint16_t WMD:1;    /* write mode */
5915               uint16_t:1;
5916             uint16_t SEL:2;    /* selector */
5917               uint16_t:4;
5918             uint16_t RSBIDX:8; /* receive shadow buffer index */
5919         } B;
5920     } RSBIR_t;
5921     typedef union uRFDSR {
5922         uint16_t R;
5923         struct {
5924             uint16_t FIFODEPTH:8;      /* fifo depth */
5925               uint16_t:1;
5926             uint16_t ENTRYSIZE:7;      /* entry size */
5927         } B;
5928     } RFDSR_t;
5929 
5930     typedef union uRFRFCFR {
5931         uint16_t R;
5932         struct {
5933             uint16_t WMD:1;    /* write mode */
5934             uint16_t IBD:1;    /* interval boundary */
5935             uint16_t SEL:2;    /* filter number */
5936               uint16_t:1;
5937             uint16_t SID:11;   /* slot ID */
5938         } B;
5939     } RFRFCFR_t;
5940 
5941     typedef union uRFRFCTR {
5942         uint16_t R;
5943         struct {
5944             uint16_t:4;
5945             uint16_t F3MD:1;   /* filter mode */
5946             uint16_t F2MD:1;   /* filter mode */
5947             uint16_t F1MD:1;   /* filter mode */
5948             uint16_t F0MD:1;   /* filter mode */
5949               uint16_t:4;
5950             uint16_t F3EN:1;   /* filter enable */
5951             uint16_t F2EN:1;   /* filter enable */
5952             uint16_t F1EN:1;   /* filter enable */
5953             uint16_t F0EN:1;   /* filter enable */
5954         } B;
5955     } RFRFCTR_t;
5956     typedef union uPCR0 {
5957         uint16_t R;
5958         struct {
5959             uint16_t ACTION_POINT_OFFSET:6;
5960             uint16_t STATIC_SLOT_LENGTH:10;
5961         } B;
5962     } PCR0_t;
5963 
5964     typedef union uPCR1 {
5965         uint16_t R;
5966         struct {
5967             uint16_t:2;
5968             uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
5969         } B;
5970     } PCR1_t;
5971 
5972     typedef union uPCR2 {
5973         uint16_t R;
5974         struct {
5975             uint16_t MINISLOT_AFTER_ACTION_POINT:6;
5976             uint16_t NUMBER_OF_STATIC_SLOTS:10;
5977         } B;
5978     } PCR2_t;
5979 
5980     typedef union uPCR3 {
5981         uint16_t R;
5982         struct {
5983             uint16_t WAKEUP_SYMBOL_RX_LOW:6;
5984             uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
5985             uint16_t COLDSTART_ATTEMPTS:5;
5986         } B;
5987     } PCR3_t;
5988 
5989     typedef union uPCR4 {
5990         uint16_t R;
5991         struct {
5992             uint16_t CAS_RX_LOW_MAX:7;
5993             uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
5994         } B;
5995     } PCR4_t;
5996 
5997     typedef union uPCR5 {
5998         uint16_t R;
5999         struct {
6000             uint16_t TSS_TRANSMITTER:4;
6001             uint16_t WAKEUP_SYMBOL_TX_LOW:6;
6002             uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
6003         } B;
6004     } PCR5_t;
6005 
6006     typedef union uPCR6 {
6007         uint16_t R;
6008         struct {
6009             uint16_t:1;
6010             uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
6011             uint16_t MACRO_INITIAL_OFFSET_A:7;
6012         } B;
6013     } PCR6_t;
6014 
6015     typedef union uPCR7 {
6016         uint16_t R;
6017         struct {
6018             uint16_t DECODING_CORRECTION_B:9;
6019             uint16_t MICRO_PER_MACRO_NOM_HALF:7;
6020         } B;
6021     } PCR7_t;
6022 
6023     typedef union uPCR8 {
6024         uint16_t R;
6025         struct {
6026             uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
6027             uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
6028             uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
6029         } B;
6030     } PCR8_t;
6031 
6032     typedef union uPCR9 {
6033         uint16_t R;
6034         struct {
6035             uint16_t MINISLOT_EXISTS:1;
6036             uint16_t SYMBOL_WINDOW_EXISTS:1;
6037             uint16_t OFFSET_CORRECTION_OUT:14;
6038         } B;
6039     } PCR9_t;
6040 
6041     typedef union uPCR10 {
6042         uint16_t R;
6043         struct {
6044             uint16_t SINGLE_SLOT_ENABLED:1;
6045             uint16_t WAKEUP_CHANNEL:1;
6046             uint16_t MACRO_PER_CYCLE:14;
6047         } B;
6048     } PCR10_t;
6049 
6050     typedef union uPCR11 {
6051         uint16_t R;
6052         struct {
6053             uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
6054             uint16_t KEY_SLOT_USED_FOR_SYNC:1;
6055             uint16_t OFFSET_CORRECTION_START:14;
6056         } B;
6057     } PCR11_t;
6058 
6059     typedef union uPCR12 {
6060         uint16_t R;
6061         struct {
6062             uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
6063             uint16_t KEY_SLOT_HEADER_CRC:11;
6064         } B;
6065     } PCR12_t;
6066 
6067     typedef union uPCR13 {
6068         uint16_t R;
6069         struct {
6070             uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
6071             uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
6072         } B;
6073     } PCR13_t;
6074 
6075     typedef union uPCR14 {
6076         uint16_t R;
6077         struct {
6078             uint16_t RATE_CORRECTION_OUT:11;
6079             uint16_t LISTEN_TIMEOUT_H:5;
6080         } B;
6081     } PCR14_t;
6082 
6083     typedef union uPCR15 {
6084         uint16_t R;
6085         struct {
6086             uint16_t LISTEN_TIMEOUT_L:16;
6087         } B;
6088     } PCR15_t;
6089 
6090     typedef union uPCR16 {
6091         uint16_t R;
6092         struct {
6093             uint16_t MACRO_INITIAL_OFFSET_B:7;
6094             uint16_t NOISE_LISTEN_TIMEOUT_H:9;
6095         } B;
6096     } PCR16_t;
6097 
6098     typedef union uPCR17 {
6099         uint16_t R;
6100         struct {
6101             uint16_t NOISE_LISTEN_TIMEOUT_L:16;
6102         } B;
6103     } PCR17_t;
6104 
6105     typedef union uPCR18 {
6106         uint16_t R;
6107         struct {
6108             uint16_t WAKEUP_PATTERN:6;
6109             uint16_t KEY_SLOT_ID:10;
6110         } B;
6111     } PCR18_t;
6112 
6113     typedef union uPCR19 {
6114         uint16_t R;
6115         struct {
6116             uint16_t DECODING_CORRECTION_A:9;
6117             uint16_t PAYLOAD_LENGTH_STATIC:7;
6118         } B;
6119     } PCR19_t;
6120 
6121     typedef union uPCR20 {
6122         uint16_t R;
6123         struct {
6124             uint16_t MICRO_INITIAL_OFFSET_B:8;
6125             uint16_t MICRO_INITIAL_OFFSET_A:8;
6126         } B;
6127     } PCR20_t;
6128 
6129     typedef union uPCR21 {
6130         uint16_t R;
6131         struct {
6132             uint16_t EXTERN_RATE_CORRECTION:3;
6133             uint16_t LATEST_TX:13;
6134         } B;
6135     } PCR21_t;
6136 
6137     typedef union uPCR22 {
6138         uint16_t R;
6139         struct {
6140             uint16_t:1;
6141             uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
6142             uint16_t MICRO_PER_CYCLE_H:4;
6143         } B;
6144     } PCR22_t;
6145 
6146     typedef union uPCR23 {
6147         uint16_t R;
6148         struct {
6149             uint16_t micro_per_cycle_l:16;
6150         } B;
6151     } PCR23_t;
6152 
6153     typedef union uPCR24 {
6154         uint16_t R;
6155         struct {
6156             uint16_t CLUSTER_DRIFT_DAMPING:5;
6157             uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
6158             uint16_t MICRO_PER_CYCLE_MIN_H:4;
6159         } B;
6160     } PCR24_t;
6161 
6162     typedef union uPCR25 {
6163         uint16_t R;
6164         struct {
6165             uint16_t MICRO_PER_CYCLE_MIN_L:16;
6166         } B;
6167     } PCR25_t;
6168 
6169     typedef union uPCR26 {
6170         uint16_t R;
6171         struct {
6172             uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
6173             uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
6174             uint16_t MICRO_PER_CYCLE_MAX_H:4;
6175         } B;
6176     } PCR26_t;
6177 
6178     typedef union uPCR27 {
6179         uint16_t R;
6180         struct {
6181             uint16_t MICRO_PER_CYCLE_MAX_L:16;
6182         } B;
6183     } PCR27_t;
6184 
6185     typedef union uPCR28 {
6186         uint16_t R;
6187         struct {
6188             uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
6189             uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
6190         } B;
6191     } PCR28_t;
6192 
6193     typedef union uPCR29 {
6194         uint16_t R;
6195         struct {
6196             uint16_t EXTERN_OFFSET_CORRECTION:3;
6197             uint16_t MINISLOTS_MAX:13;
6198         } B;
6199     } PCR29_t;
6200 
6201     typedef union uPCR30 {
6202         uint16_t R;
6203         struct {
6204             uint16_t:12;
6205             uint16_t SYNC_NODE_MAX:4;
6206         } B;
6207     } PCR30_t;
6208 
6209     typedef struct uMSG_BUFF_CCS {
6210         union {
6211             uint16_t R;
6212             struct {
6213                 uint16_t:1;
6214                 uint16_t MCM:1;        /* message buffer commit mode */
6215                 uint16_t MBT:1;        /* message buffer type */
6216                 uint16_t MTD:1;        /* message buffer direction */
6217                 uint16_t CMT:1;        /* commit for transmission */
6218                 uint16_t EDT:1;        /* enable / disable trigger */
6219                 uint16_t LCKT:1;       /* lock request trigger */
6220                 uint16_t MBIE:1;       /* message buffer interrupt enable */
6221                   uint16_t:3;
6222                 uint16_t DUP:1;        /* data updated  */
6223                 uint16_t DVAL:1;       /* data valid */
6224                 uint16_t EDS:1;        /* lock status */
6225                 uint16_t LCKS:1;       /* enable / disable status */
6226                 uint16_t MBIF:1;       /* message buffer interrupt flag */
6227             } B;
6228         } MBCCSR;
6229         union {
6230             uint16_t R;
6231             struct {
6232                 uint16_t MTM:1;        /* message buffer transmission mode */
6233                 uint16_t CHNLA:1;      /* channel assignement */
6234                 uint16_t CHNLB:1;      /* channel assignement */
6235                 uint16_t CCFE:1;       /* cycle counter filter enable */
6236                 uint16_t CCFMSK:6;     /* cycle counter filter mask */
6237                 uint16_t CCFVAL:6;     /* cycle counter filter value */
6238             } B;
6239         } MBCCFR;
6240         union {
6241             uint16_t R;
6242             struct {
6243                 uint16_t:5;
6244                 uint16_t FID:11;       /* frame ID */
6245             } B;
6246         } MBFIDR;
6247         union {
6248             uint16_t R;
6249             struct {
6250                 uint16_t:8;
6251                 uint16_t MBIDX:8;      /* message buffer index */
6252             } B;
6253         } MBIDXR;
6254     } MSG_BUFF_CCS_t;
6255     typedef union uSYSBADHR {
6256         uint16_t R;
6257     } SYSBADHR_t;
6258     typedef union uSYSBADLR {
6259         uint16_t R;
6260     } SYSBADLR_t;
6261     typedef union uPDAR {
6262         uint16_t R;
6263     } PDAR_t;
6264     typedef union uCASERCR {
6265         uint16_t R;
6266     } CASERCR_t;
6267     typedef union uCBSERCR {
6268         uint16_t R;
6269     } CBSERCR_t;
6270     typedef union uCYCTR {
6271         uint16_t R;
6272     } CYCTR_t;
6273     typedef union uMTCTR {
6274         uint16_t R;
6275     } MTCTR_t;
6276     typedef union uSLTCTAR {
6277         uint16_t R;
6278     } SLTCTAR_t;
6279     typedef union uSLTCTBR {
6280         uint16_t R;
6281     } SLTCTBR_t;
6282     typedef union uRTCORVR {
6283         uint16_t R;
6284     } RTCORVR_t;
6285     typedef union uOFCORVR {
6286         uint16_t R;
6287     } OFCORVR_t;
6288     typedef union uSFTOR {
6289         uint16_t R;
6290     } SFTOR_t;
6291     typedef union uSFIDAFVR {
6292         uint16_t R;
6293     } SFIDAFVR_t;
6294     typedef union uSFIDAFMR {
6295         uint16_t R;
6296     } SFIDAFMR_t;
6297     typedef union uNMVR {
6298         uint16_t R;
6299     } NMVR_t;
6300     typedef union uNMVLR {
6301         uint16_t R;
6302     } NMVLR_t;
6303     typedef union uT1MTOR {
6304         uint16_t R;
6305     } T1MTOR_t;
6306     typedef union uTI2CR0 {
6307         uint16_t R;
6308     } TI2CR0_t;
6309     typedef union uTI2CR1 {
6310         uint16_t R;
6311     } TI2CR1_t;
6312     typedef union uSSCR {
6313         uint16_t R;
6314     } SSCR_t;
6315     typedef union uRFSR {
6316         uint16_t R;
6317     } RFSR_t;
6318     typedef union uRFSIR {
6319         uint16_t R;
6320     } RFSIR_t;
6321     typedef union uRFARIR {
6322         uint16_t R;
6323     } RFARIR_t;
6324     typedef union uRFBRIR {
6325         uint16_t R;
6326     } RFBRIR_t;
6327     typedef union uRFMIDAFVR {
6328         uint16_t R;
6329     } RFMIDAFVR_t;
6330     typedef union uRFMIAFMR {
6331         uint16_t R;
6332     } RFMIAFMR_t;
6333     typedef union uRFFIDRFVR {
6334         uint16_t R;
6335     } RFFIDRFVR_t;
6336     typedef union uRFFIDRFMR {
6337         uint16_t R;
6338     } RFFIDRFMR_t;
6339     typedef union uLDTXSLAR {
6340         uint16_t R;
6341     } LDTXSLAR_t;
6342     typedef union uLDTXSLBR {
6343         uint16_t R;
6344     } LDTXSLBR_t;
6345 
6346     typedef struct FR_tag {
6347         volatile MVR_t MVR;     /*module version register *//*0  */
6348         volatile MCR_t MCR;     /*module configuration register *//*2  */
6349         volatile SYSBADHR_t SYSBADHR;   /*system memory base address high register *//*4        */
6350         volatile SYSBADLR_t SYSBADLR;   /*system memory base address low register *//*6         */
6351         volatile STBSCR_t STBSCR;       /*strobe signal control register *//*8      */
6352         volatile STBPCR_t STBPCR;       /*strobe port control register *//*A        */
6353         volatile MBDSR_t MBDSR; /*message buffer data size register *//*C  */
6354         volatile MBSSUTR_t MBSSUTR;     /*message buffer segment size and utilization register *//*E  */
6355         uint16_t reserved3a[1];        /*10 */
6356         volatile PDAR_t PDAR;   /*PE data register *//*12 */
6357         volatile POCR_t POCR;   /*Protocol operation control register *//*14 */
6358         volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
6359         volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
6360         volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
6361         volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
6362         volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
6363         volatile CHIERFR_t CHIERFR;     /*CHI error flag register *//*20 */
6364         volatile MBIVEC_t MBIVEC;       /*message buffer interrupt vector register *//*22 */
6365         volatile CASERCR_t CASERCR;     /*channel A status error counter register *//*24 */
6366         volatile CBSERCR_t CBSERCR;     /*channel B status error counter register *//*26 */
6367         volatile PSR0_t PSR0;   /*protocol status register 0 *//*28 */
6368         volatile PSR1_t PSR1;   /*protocol status register 1 *//*2A */
6369         volatile PSR2_t PSR2;   /*protocol status register 2 *//*2C */
6370         volatile PSR3_t PSR3;   /*protocol status register 3 *//*2E */
6371         volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
6372         volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
6373         volatile SLTCTAR_t SLTCTAR;     /*slot counter channel A register *//*34 */
6374         volatile SLTCTBR_t SLTCTBR;     /*slot counter channel B register *//*36 */
6375         volatile RTCORVR_t RTCORVR;     /*rate correction value register *//*38 */
6376         volatile OFCORVR_t OFCORVR;     /*offset correction value register *//*3A */
6377         volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
6378         uint16_t reserved3[1]; /*3E */
6379         volatile SFCNTR_t SFCNTR;       /*sync frame counter register *//*40 */
6380         volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
6381         volatile SFTCCSR_t SFTCCSR;     /*sync frame table configuration, control, status register *//*44 */
6382         volatile SFIDRFR_t SFIDRFR;     /*sync frame ID rejection filter register *//*46 */
6383         volatile SFIDAFVR_t SFIDAFVR;   /*sync frame ID acceptance filter value regiater *//*48 */
6384         volatile SFIDAFMR_t SFIDAFMR;   /*sync frame ID acceptance filter mask register *//*4A */
6385         volatile NMVR_t NMVR[6];        /*network management vector registers (12 bytes) *//*4C */
6386         volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
6387         volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
6388         volatile TI1CYSR_t TI1CYSR;     /*timer 1 cycle set register *//*5C */
6389         volatile T1MTOR_t T1MTOR;       /*timer 1 macrotick offset register *//*5E */
6390         volatile TI2CR0_t TI2CR0;       /*timer 2 configuration register 0 *//*60 */
6391         volatile TI2CR1_t TI2CR1;       /*timer 2 configuration register 1 *//*62 */
6392         volatile SSSR_t SSSR;   /*slot status selection register *//*64 */
6393         volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
6394         volatile SSR_t SSR[8];  /*slot status registers 0-7 *//*68 */
6395         volatile SSCR_t SSCR[4];        /*slot status counter registers 0-3 *//*78 */
6396         volatile MTSCFR_t MTSACFR;      /*mts a config register *//*80 */
6397         volatile MTSCFR_t MTSBCFR;      /*mts b config register *//*82 */
6398         volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
6399         volatile RFSR_t RFSR;   /*receive fifo selection register *//*86 */
6400         volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
6401         volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
6402         volatile RFARIR_t RFARIR;       /*receive fifo a read index register *//*8C */
6403         volatile RFBRIR_t RFBRIR;       /*receive fifo b read index register *//*8E */
6404         volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
6405         volatile RFMIAFMR_t RFMIAFMR;   /*receive fifo message ID acceptance filter mask register *//*92 */
6406         volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
6407         volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
6408         volatile RFRFCFR_t RFRFCFR;     /*receive fifo range filter configuration register *//*98 */
6409         volatile RFRFCTR_t RFRFCTR;     /*receive fifo range filter control register *//*9A */
6410         volatile LDTXSLAR_t LDTXSLAR;   /*last dynamic transmit slot channel A register *//*9C */
6411         volatile LDTXSLBR_t LDTXSLBR;   /*last dynamic transmit slot channel B register *//*9E */
6412         volatile PCR0_t PCR0;   /*protocol configuration register 0 *//*A0 */
6413         volatile PCR1_t PCR1;   /*protocol configuration register 1 *//*A2 */
6414         volatile PCR2_t PCR2;   /*protocol configuration register 2 *//*A4 */
6415         volatile PCR3_t PCR3;   /*protocol configuration register 3 *//*A6 */
6416         volatile PCR4_t PCR4;   /*protocol configuration register 4 *//*A8 */
6417         volatile PCR5_t PCR5;   /*protocol configuration register 5 *//*AA */
6418         volatile PCR6_t PCR6;   /*protocol configuration register 6 *//*AC */
6419         volatile PCR7_t PCR7;   /*protocol configuration register 7 *//*AE */
6420         volatile PCR8_t PCR8;   /*protocol configuration register 8 *//*B0 */
6421         volatile PCR9_t PCR9;   /*protocol configuration register 9 *//*B2 */
6422         volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
6423         volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
6424         volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
6425         volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
6426         volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
6427         volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
6428         volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
6429         volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
6430         volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
6431         volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
6432         volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
6433         volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
6434         volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
6435         volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
6436         volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
6437         volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
6438         volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
6439         volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
6440         volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
6441         volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
6442         volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
6443         uint16_t reserved2[17];
6444         volatile MSG_BUFF_CCS_t MBCCS[128];     /* message buffer configuration, control & status registers 0-31 *//*100 */
6445     } FR_tag_t;
6446 
6447     typedef union uF_HEADER     /* frame header */
6448     {
6449         struct {
6450             uint16_t:5;
6451             uint16_t HDCRC:11; /* Header CRC */
6452               uint16_t:2;
6453             uint16_t CYCCNT:6; /* Cycle Count */
6454               uint16_t:1;
6455             uint16_t PLDLEN:7; /* Payload Length */
6456               uint16_t:1;
6457             uint16_t PPI:1;    /* Payload Preamble Indicator */
6458             uint16_t NUF:1;    /* Null Frame Indicator */
6459             uint16_t SYF:1;    /* Sync Frame Indicator */
6460             uint16_t SUF:1;    /* Startup Frame Indicator */
6461             uint16_t FID:11;   /* Frame ID */
6462         } B;
6463         uint16_t WORDS[3];
6464     } F_HEADER_t;
6465     typedef union uS_STSTUS     /* slot status */
6466     {
6467         struct {
6468             uint16_t VFB:1;    /* Valid Frame on channel B */
6469             uint16_t SYB:1;    /* Sync Frame Indicator channel B */
6470             uint16_t NFB:1;    /* Null Frame Indicator channel B */
6471             uint16_t SUB:1;    /* Startup Frame Indicator channel B */
6472             uint16_t SEB:1;    /* Syntax Error on channel B */
6473             uint16_t CEB:1;    /* Content Error on channel B */
6474             uint16_t BVB:1;    /* Boundary Violation on channel B */
6475             uint16_t CH:1;     /* Channel */
6476             uint16_t VFA:1;    /* Valid Frame on channel A */
6477             uint16_t SYA:1;    /* Sync Frame Indicator channel A */
6478             uint16_t NFA:1;    /* Null Frame Indicator channel A */
6479             uint16_t SUA:1;    /* Startup Frame Indicator channel A */
6480             uint16_t SEA:1;    /* Syntax Error on channel A */
6481             uint16_t CEA:1;    /* Content Error on channel A */
6482             uint16_t BVA:1;    /* Boundary Violation on channel A */
6483               uint16_t:1;
6484         } RX;
6485         struct {
6486             uint16_t VFB:1;    /* Valid Frame on channel B */
6487             uint16_t SYB:1;    /* Sync Frame Indicator channel B */
6488             uint16_t NFB:1;    /* Null Frame Indicator channel B */
6489             uint16_t SUB:1;    /* Startup Frame Indicator channel B */
6490             uint16_t SEB:1;    /* Syntax Error on channel B */
6491             uint16_t CEB:1;    /* Content Error on channel B */
6492             uint16_t BVB:1;    /* Boundary Violation on channel B */
6493             uint16_t TCB:1;    /* Tx Conflict on channel B */
6494             uint16_t VFA:1;    /* Valid Frame on channel A */
6495             uint16_t SYA:1;    /* Sync Frame Indicator channel A */
6496             uint16_t NFA:1;    /* Null Frame Indicator channel A */
6497             uint16_t SUA:1;    /* Startup Frame Indicator channel A */
6498             uint16_t SEA:1;    /* Syntax Error on channel A */
6499             uint16_t CEA:1;    /* Content Error on channel A */
6500             uint16_t BVA:1;    /* Boundary Violation on channel A */
6501             uint16_t TCA:1;    /* Tx Conflict on channel A */
6502         } TX;
6503         uint16_t R;
6504     } S_STATUS_t;
6505 
6506     typedef struct uMB_HEADER   /* message buffer header */
6507     {
6508         F_HEADER_t FRAME_HEADER;
6509         uint16_t DATA_OFFSET;
6510         S_STATUS_t SLOT_STATUS;
6511     } MB_HEADER_t;
6512 
6513 /* Define memories */
6514 
6515 #define SRAM_START    0x40000000
6516 #define SRAM_SIZE        0x40000
6517 #define SRAM_END      0x4003FFFF
6518 
6519 #define FLASH_START   0x00000000
6520 #define FLASH_SIZE      0x400000
6521 #define FLASH_END     0x003FFFFF
6522 
6523 /* Define instances of modules */
6524 #define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *)  0xC3F00000)
6525 #define FMPLL     (*( volatile struct FMPLL_tag *)      0xC3F80000)
6526 #define EBI       (*( volatile struct EBI_tag *)        0xC3F84000)
6527 #define FLASH_A   (*( volatile struct FLASH_tag *)      0xC3F88000)
6528 #define FLASH FLASH_A
6529 #define FLASH_B   (*( volatile struct FLASH_tag *)      0xC3F8C000)
6530 #define SIU       (*( volatile struct SIU_tag *)        0xC3F90000)
6531 
6532 #define EMIOS     (*( volatile struct EMIOS_tag *)      0xC3FA0000)
6533 #define PMC       (*( volatile struct PMC_tag *)        0xC3FBC000)
6534 
6535 #define ETPU      (*( volatile struct ETPU_tag *)       0xC3FC0000)
6536 #define ETPU_DATA_RAM      (*( uint32_t *)              0xC3FC8000)
6537 #define ETPU_DATA_RAM_END                               0xC3FC8FFC
6538 #define ETPU_DATA_RAM_EXT  (*( uint32_t *)              0xC3FCC000)
6539 #define CODE_RAM           (*( uint32_t *)              0xC3FD0000)
6540 #define ETPU_CODE_RAM      (*( uint32_t *)              0xC3FD0000)
6541 
6542 #define PIT       (*( volatile struct PIT_tag *)        0xC3FF0000)
6543 
6544 #define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *)  0xFFF00000)
6545 #define XBAR      (*( volatile struct XBAR_tag *)       0xFFF04000)
6546 #define MPU       (*( volatile struct MPU_tag *)        0xFFF10000)
6547 #define SWT       (*( volatile struct SWT_tag *)        0xFFF38000)
6548 #define STM       (*( volatile struct STM_tag *)        0xFFF3C000)
6549 #define ECSM      (*( volatile struct ECSM_tag *)       0xFFF40000)
6550 #define EDMA_A    (*( volatile struct EDMA_tag *)       0xFFF44000)
6551 #define EDMA EDMA_A
6552 #define INTC      (*( volatile struct INTC_tag *)       0xFFF48000)
6553 #define EDMA_B    (*( volatile struct EDMA_tag *)       0xFFF54000)
6554 
6555 #define EQADC_A   (*( volatile struct EQADC_tag *)      0xFFF80000)
6556 #define EQADC EQADC_A
6557 #define EQADC_B   (*( volatile struct EQADC_tag *)      0xFFF84000)
6558 
6559 #define DECFIL_A   (*( volatile struct DECFIL_tag *)      0xFFF88000)
6560 #define DECFIL_B   (*( volatile struct DECFIL_tag *)      0xFFF88800)
6561 #define DECFIL_C   (*( volatile struct DECFIL_tag *)      0xFFF89000)
6562 #define DECFIL_D   (*( volatile struct DECFIL_tag *)      0xFFF89800)
6563 #define DECFIL_E   (*( volatile struct DECFIL_tag *)      0xFFF8A000)
6564 #define DECFIL_F   (*( volatile struct DECFIL_tag *)      0xFFF8A800)
6565 #define DECFIL_G   (*( volatile struct DECFIL_tag *)      0xFFF8B000)
6566 #define DECFIL_H   (*( volatile struct DECFIL_tag *)      0xFFF8B800)
6567 
6568 #define DSPI_A    (*( volatile struct DSPI_tag *)       0xFFF90000)
6569 #define DSPI_B    (*( volatile struct DSPI_tag *)       0xFFF94000)
6570 #define DSPI_C    (*( volatile struct DSPI_tag *)       0xFFF98000)
6571 #define DSPI_D    (*( volatile struct DSPI_tag *)       0xFFF9C000)
6572 
6573 #define ESCI_A    (*( volatile struct ESCI_tag *)       0xFFFB0000)
6574 #define ESCI_B    (*( volatile struct ESCI_tag *)       0xFFFB4000)
6575 #define ESCI_C    (*( volatile struct ESCI_tag *)       0xFFFB8000)
6576 #define ESCI_D    (*( volatile struct ESCI_tag *)       0xFFFBC000)
6577 
6578 #define CAN_A     (*( volatile struct FLEXCAN2_tag *)   0xFFFC0000)
6579 #define CAN_B     (*( volatile struct FLEXCAN2_tag *)   0xFFFC4000)
6580 #define CAN_C     (*( volatile struct FLEXCAN2_tag *)   0xFFFC8000)
6581 #define CAN_D     (*( volatile struct FLEXCAN2_tag *)   0xFFFCC000)
6582 
6583 #define FR        (*( volatile struct FR_tag *)         0xFFFE0000)
6584 #define TSENS     (*( volatile struct TSENS_tag *)      0xFFFEC000)
6585 
6586 #ifdef __MWERKS__
6587 #pragma pop
6588 #endif
6589 
6590 #ifdef  __cplusplus
6591 }
6592 #endif
6593 #endif /* ASM */
6594 #endif                          /* ifdef _MPC5674_H */
6595 /*********************************************************************
6596  *
6597  * Copyright:
6598  *  Freescale Semiconductor, INC. All Rights Reserved.
6599  *  You are hereby granted a copyright license to use, modify, and
6600  *  distribute the SOFTWARE so long as this entire notice is
6601  *  retained without alteration in any modified and/or redistributed
6602  *  versions, and that such modified versions are clearly identified
6603  *  as such. No licenses are granted by implication, estoppel or
6604  *  otherwise under any patents or trademarks of Freescale
6605  *  Semiconductor, Inc. This software is provided on an "AS IS"
6606  *  basis and without warranty.
6607  *
6608  *  To the maximum extent permitted by applicable law, Freescale
6609  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
6610  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
6611  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
6612  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
6613  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
6614  *
6615  *  To the maximum extent permitted by applicable law, IN NO EVENT
6616  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
6617  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
6618  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
6619  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
6620  *
6621  *  Freescale Semiconductor assumes no responsibility for the
6622  *  maintenance and support of this software
6623  *
6624  ********************************************************************/
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