include/mpc55xx/fsl-mpc5668.h

0001 /*
0002  * Modifications of the original file provided by Freescale are:
0003  *
0004  * Copyright (c) 2013 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0016  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0017  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0018  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0019  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0020  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0021  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0022  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0023  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0024  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0025  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 /**************************************************************************
0029  * FILE NAME: mpc5668.h                      COPYRIGHT (c) Freescale 2009 *
0030  * REVISION:  1.1                                     All Rights Reserved *
0031  *                                                                        *
0032  * DESCRIPTION:                                                           *
0033  * This file contain all of the register and bit field definitions for    *
0034  * MPC5668.                                                               *
0035  **************************************************************************/
0036 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
0037
0038 /**************************************************************************
0039  * Example register & bit field write:                                    *
0040  *                                                                        *
0041  *  <MODULE>.<REGISTER>.B.<BIT> = 1;                                      *
0042  *  <MODULE>.<REGISTER>.R       = 0x10000000;                             *
0043  *                                                                        *
0044  **************************************************************************/
0045
0046 #ifndef _MPC5668_H_
0047 #define _MPC5668_H_
0048
0049 #ifndef ASM
0050
0051 #include <stdint.h>
0052
0053 #include <mpc55xx/regs-edma.h>
0054
0055 #ifdef  __cplusplus
0056 extern "C" {
0057 #endif
0058
0059 #ifdef __MWERKS__
0060 #pragma push
0061 #pragma ANSI_strict off
0062 #endif
0063
0064 /*************************************************************************/
0065 /*                          MODULE : ADC                                 */
0066 /*************************************************************************/
0067     struct ADC_tag {
0068
0069         union {
0070             uint32_t R;
0071             struct {
0072                 uint32_t OWREN:1;
0073                 uint32_t WLSIDE:1;
0074                 uint32_t MODE:1;
0075                 uint32_t EDGLEV:1;
0076                 uint32_t TRGEN:1;
0077                 uint32_t EDGE:1;
0078                 uint32_t XSTRTEN:1;
0079                 uint32_t NSTART:1;
0080                   uint32_t:1;
0081                 uint32_t JTRGEN:1;
0082                 uint32_t JEDGE:1;
0083                 uint32_t JSTART:1;
0084                   uint32_t:2;
0085                 uint32_t CTUEN:1;
0086                   uint32_t:8;
0087                 uint32_t ADCLKSEL:1;
0088                 uint32_t ABORTCHAIN:1;
0089                 uint32_t ABORT:1;
0090                 uint32_t ACKO:1;
0091                 uint32_t OFFREFRESH:1;
0092                 uint32_t OFFCANC:1;
0093                   uint32_t:2;
0094                 uint32_t PWDN:1;
0095             } B;
0096         } MCR;                  /* MAIN CONFIGURATION REGISTER */
0097
0098         union {
0099             uint32_t R;
0100             struct {
0101                 uint32_t:7;
0102                 uint32_t NSTART:1;
0103                 uint32_t JABORT:1;
0104                   uint32_t:2;
0105                 uint32_t JSTART:1;
0106                   uint32_t:3;
0107                 uint32_t CTUSTART:1;
0108                 uint32_t CHADDR:7;
0109                   uint32_t:3;
0110                 uint32_t ACKO:1;
0111                 uint32_t OFFREFRESH:1;
0112                 uint32_t OFFCANC:1;
0113                 uint32_t ADCSTATUS:3;
0114             } B;
0115         } MSR;                  /* MAIN STATUS REGISTER */
0116
0117         uint32_t adc_reserved1[2];
0118
0119         union {
0120             uint32_t R;
0121             struct {
0122                 uint32_t:25;
0123                 uint32_t OFFCANCOVR:1;
0124                 uint32_t EOFFSET:1;
0125                 uint32_t EOCTU:1;
0126                 uint32_t JEOC:1;
0127                 uint32_t JECH:1;
0128                 uint32_t EOC:1;
0129                 uint32_t ECH:1;
0130             } B;
0131         } ISR;                  /* INTERRUPT STATUS REGISTER */
0132
0133         union {
0134             uint32_t R;
0135             struct {
0136                 uint32_t EOCCH31:1;
0137                 uint32_t EOCCH30:1;
0138                 uint32_t EOCCH29:1;
0139                 uint32_t EOCCH28:1;
0140                 uint32_t EOCCH27:1;
0141                 uint32_t EOCCH26:1;
0142                 uint32_t EOCCH25:1;
0143                 uint32_t EOCCH24:1;
0144                 uint32_t EOCCH23:1;
0145                 uint32_t EOCCH22:1;
0146                 uint32_t EOCCH21:1;
0147                 uint32_t EOCCH20:1;
0148                 uint32_t EOCCH19:1;
0149                 uint32_t EOCCH18:1;
0150                 uint32_t EOCCH17:1;
0151                 uint32_t EOCCH16:1;
0152                 uint32_t EOCCH15:1;
0153                 uint32_t EOCCH14:1;
0154                 uint32_t EOCCH13:1;
0155                 uint32_t EOCCH12:1;
0156                 uint32_t EOCCH11:1;
0157                 uint32_t EOCCH10:1;
0158                 uint32_t EOCCH9:1;
0159                 uint32_t EOCCH8:1;
0160                 uint32_t EOCCH7:1;
0161                 uint32_t EOCCH6:1;
0162                 uint32_t EOCCH5:1;
0163                 uint32_t EOCCH4:1;
0164                 uint32_t EOCCH3:1;
0165                 uint32_t EOCCH2:1;
0166                 uint32_t EOCCH1:1;
0167                 uint32_t EOCCH0:1;
0168             } B;
0169         } CEOCFR0;              /* CHANNEL PENDING REGISTER 0 */
0170
0171         union {
0172             uint32_t R;
0173             struct {
0174                 uint32_t EOCCH63:1;
0175                 uint32_t EOCCH62:1;
0176                 uint32_t EOCCH61:1;
0177                 uint32_t EOCCH60:1;
0178                 uint32_t EOCCH59:1;
0179                 uint32_t EOCCH58:1;
0180                 uint32_t EOCCH57:1;
0181                 uint32_t EOCCH56:1;
0182                 uint32_t EOCCH55:1;
0183                 uint32_t EOCCH54:1;
0184                 uint32_t EOCCH53:1;
0185                 uint32_t EOCCH52:1;
0186                 uint32_t EOCCH51:1;
0187                 uint32_t EOCCH50:1;
0188                 uint32_t EOCCH49:1;
0189                 uint32_t EOCCH48:1;
0190                 uint32_t EOCCH47:1;
0191                 uint32_t EOCCH46:1;
0192                 uint32_t EOCCH45:1;
0193                 uint32_t EOCCH44:1;
0194                 uint32_t EOCCH43:1;
0195                 uint32_t EOCCH42:1;
0196                 uint32_t EOCCH41:1;
0197                 uint32_t EOCCH40:1;
0198                 uint32_t EOCCH39:1;
0199                 uint32_t EOCCH38:1;
0200                 uint32_t EOCCH37:1;
0201                 uint32_t EOCCH36:1;
0202                 uint32_t EOCCH35:1;
0203                 uint32_t EOCCH34:1;
0204                 uint32_t EOCCH33:1;
0205                 uint32_t EOCCH32:1;
0206             } B;
0207         } CEOCFR1;              /* CHANNEL PENDING REGISTER 1 */
0208
0209         union {
0210             uint32_t R;
0211             struct {
0212                 uint32_t EOCCH95:1;
0213                 uint32_t EOCCH94:1;
0214                 uint32_t EOCCH93:1;
0215                 uint32_t EOCCH92:1;
0216                 uint32_t EOCCH91:1;
0217                 uint32_t EOCCH90:1;
0218                 uint32_t EOCCH89:1;
0219                 uint32_t EOCCH88:1;
0220                 uint32_t EOCCH87:1;
0221                 uint32_t EOCCH86:1;
0222                 uint32_t EOCCH85:1;
0223                 uint32_t EOCCH84:1;
0224                 uint32_t EOCCH83:1;
0225                 uint32_t EOCCH82:1;
0226                 uint32_t EOCCH81:1;
0227                 uint32_t EOCCH80:1;
0228                 uint32_t EOCCH79:1;
0229                 uint32_t EOCCH78:1;
0230                 uint32_t EOCCH77:1;
0231                 uint32_t EOCCH76:1;
0232                 uint32_t EOCCH75:1;
0233                 uint32_t EOCCH74:1;
0234                 uint32_t EOCCH73:1;
0235                 uint32_t EOCCH72:1;
0236                 uint32_t EOCCH71:1;
0237                 uint32_t EOCCH70:1;
0238                 uint32_t EOCCH69:1;
0239                 uint32_t EOCCH68:1;
0240                 uint32_t EOCCH67:1;
0241                 uint32_t EOCCH66:1;
0242                 uint32_t EOCCH65:1;
0243                 uint32_t EOCCH64:1;
0244             } B;
0245         } CEOCFR2;              /* CHANNEL PENDING REGISTER 2 */
0246
0247         union {
0248             uint32_t R;
0249             struct {
0250                 uint32_t:25;
0251                 uint32_t MSKOFFCANCOVR:1;
0252                 uint32_t MSKEOFFSET:1;
0253                 uint32_t MSKEOCTU:1;
0254                 uint32_t MSKJEOC:1;
0255                 uint32_t MSKJECH:1;
0256                 uint32_t MSKEOC:1;
0257                 uint32_t MSKECH:1;
0258             } B;
0259         } IMR;                  /* INTERRUPT MASK REGISTER */
0260
0261         union {
0262             uint32_t R;
0263             struct {
0264                 uint32_t CIM31:1;
0265                 uint32_t CIM30:1;
0266                 uint32_t CIM29:1;
0267                 uint32_t CIM28:1;
0268                 uint32_t CIM27:1;
0269                 uint32_t CIM26:1;
0270                 uint32_t CIM25:1;
0271                 uint32_t CIM24:1;
0272                 uint32_t CIM23:1;
0273                 uint32_t CIM22:1;
0274                 uint32_t CIM21:1;
0275                 uint32_t CIM20:1;
0276                 uint32_t CIM19:1;
0277                 uint32_t CIM18:1;
0278                 uint32_t CIM17:1;
0279                 uint32_t CIM16:1;
0280                 uint32_t CIM15:1;
0281                 uint32_t CIM14:1;
0282                 uint32_t CIM13:1;
0283                 uint32_t CIM12:1;
0284                 uint32_t CIM11:1;
0285                 uint32_t CIM10:1;
0286                 uint32_t CIM9:1;
0287                 uint32_t CIM8:1;
0288                 uint32_t CIM7:1;
0289                 uint32_t CIM6:1;
0290                 uint32_t CIM5:1;
0291                 uint32_t CIM4:1;
0292                 uint32_t CIM3:1;
0293                 uint32_t CIM2:1;
0294                 uint32_t CIM1:1;
0295                 uint32_t CIM0:1;
0296             } B;
0297         } CIMR0;                /* CHANNEL INTERRUPT MASK REGISTER 0 */
0298
0299         union {
0300             uint32_t R;
0301             struct {
0302                 uint32_t CIM63:1;
0303                 uint32_t CIM62:1;
0304                 uint32_t CIM61:1;
0305                 uint32_t CIM60:1;
0306                 uint32_t CIM59:1;
0307                 uint32_t CIM58:1;
0308                 uint32_t CIM57:1;
0309                 uint32_t CIM56:1;
0310                 uint32_t CIM55:1;
0311                 uint32_t CIM54:1;
0312                 uint32_t CIM53:1;
0313                 uint32_t CIM52:1;
0314                 uint32_t CIM51:1;
0315                 uint32_t CIM50:1;
0316                 uint32_t CIM49:1;
0317                 uint32_t CIM48:1;
0318                 uint32_t CIM47:1;
0319                 uint32_t CIM46:1;
0320                 uint32_t CIM45:1;
0321                 uint32_t CIM44:1;
0322                 uint32_t CIM43:1;
0323                 uint32_t CIM42:1;
0324                 uint32_t CIM41:1;
0325                 uint32_t CIM40:1;
0326                 uint32_t CIM39:1;
0327                 uint32_t CIM38:1;
0328                 uint32_t CIM37:1;
0329                 uint32_t CIM36:1;
0330                 uint32_t CIM35:1;
0331                 uint32_t CIM34:1;
0332                 uint32_t CIM33:1;
0333                 uint32_t CIM32:1;
0334             } B;
0335         } CIMR1;                /* CHANNEL INTERRUPT MASK REGISTER 1 */
0336
0337         union {
0338             uint32_t R;
0339             struct {
0340                 uint32_t CIM63:1;
0341                 uint32_t CIM62:1;
0342                 uint32_t CIM61:1;
0343                 uint32_t CIM60:1;
0344                 uint32_t CIM59:1;
0345                 uint32_t CIM58:1;
0346                 uint32_t CIM57:1;
0347                 uint32_t CIM56:1;
0348                 uint32_t CIM55:1;
0349                 uint32_t CIM54:1;
0350                 uint32_t CIM53:1;
0351                 uint32_t CIM52:1;
0352                 uint32_t CIM51:1;
0353                 uint32_t CIM50:1;
0354                 uint32_t CIM49:1;
0355                 uint32_t CIM48:1;
0356                 uint32_t CIM47:1;
0357                 uint32_t CIM46:1;
0358                 uint32_t CIM45:1;
0359                 uint32_t CIM44:1;
0360                 uint32_t CIM43:1;
0361                 uint32_t CIM42:1;
0362                 uint32_t CIM41:1;
0363                 uint32_t CIM40:1;
0364                 uint32_t CIM39:1;
0365                 uint32_t CIM38:1;
0366                 uint32_t CIM37:1;
0367                 uint32_t CIM36:1;
0368                 uint32_t CIM35:1;
0369                 uint32_t CIM34:1;
0370                 uint32_t CIM33:1;
0371                 uint32_t CIM32:1;
0372             } B;
0373         } CIMR2;                /* CHANNEL INTERRUPT MASK REGISTER 2 */
0374
0375         union {
0376             uint32_t R;
0377             struct {
0378                 uint32_t:24;
0379                 uint32_t WDG3H:1;
0380                 uint32_t WDG2H:1;
0381                 uint32_t WDG1H:1;
0382                 uint32_t WDG0H:1;
0383                 uint32_t WDG3L:1;
0384                 uint32_t WDG2L:1;
0385                 uint32_t WDG1L:1;
0386                 uint32_t WDG0L:1;
0387             } B;
0388         } WTISR;                /* WATCHDOG INTERRUPT THRESHOLD REGISTER */
0389
0390         union {
0391             uint32_t R;
0392             struct {
0393                 uint32_t:24;
0394                 uint32_t MSKWDG3H:1;
0395                 uint32_t MSKWDG2H:1;
0396                 uint32_t MSKWDG1H:1;
0397                 uint32_t MSKWDG0H:1;
0398                 uint32_t MSKWDG3L:1;
0399                 uint32_t MSKWDG2L:1;
0400                 uint32_t MSKWDG1L:1;
0401                 uint32_t MSKWDG0L:1;
0402             } B;
0403         } WTIMR;                /* WATCHDOG INTERRUPT THRESHOLD MASK REGISTER */
0404
0405         uint32_t adc_reserved2[2];
0406
0407         union {
0408             uint32_t R;
0409             struct {
0410                 uint32_t:30;
0411                 uint32_t DCLR:1;
0412                 uint32_t DMAEN:1;
0413             } B;
0414         } DMAE;                 /* DMA ENABLE REGISTER */
0415
0416         union {
0417             uint32_t R;
0418             struct {
0419                 uint32_t DMA31:1;
0420                 uint32_t DMA30:1;
0421                 uint32_t DMA29:1;
0422                 uint32_t DMA28:1;
0423                 uint32_t DMA27:1;
0424                 uint32_t DMA26:1;
0425                 uint32_t DMA25:1;
0426                 uint32_t DMA24:1;
0427                 uint32_t DMA23:1;
0428                 uint32_t DMA22:1;
0429                 uint32_t DMA21:1;
0430                 uint32_t DMA20:1;
0431                 uint32_t DMA19:1;
0432                 uint32_t DMA18:1;
0433                 uint32_t DMA17:1;
0434                 uint32_t DMA16:1;
0435                 uint32_t DMA15:1;
0436                 uint32_t DMA14:1;
0437                 uint32_t DMA13:1;
0438                 uint32_t DMA12:1;
0439                 uint32_t DMA11:1;
0440                 uint32_t DMA10:1;
0441                 uint32_t DMA9:1;
0442                 uint32_t DMA8:1;
0443                 uint32_t DMA7:1;
0444                 uint32_t DMA6:1;
0445                 uint32_t DMA5:1;
0446                 uint32_t DMA4:1;
0447                 uint32_t DMA3:1;
0448                 uint32_t DMA2:1;
0449                 uint32_t DMA1:1;
0450                 uint32_t DMA0:1;
0451             } B;
0452         } DMAR0;                /* DMA CHANNEL SELECT REGISTER 0 */
0453
0454         union {
0455             uint32_t R;
0456             struct {
0457                 uint32_t DMA63:1;
0458                 uint32_t DMA62:1;
0459                 uint32_t DMA61:1;
0460                 uint32_t DMA60:1;
0461                 uint32_t DMA59:1;
0462                 uint32_t DMA58:1;
0463                 uint32_t DMA57:1;
0464                 uint32_t DMA56:1;
0465                 uint32_t DMA55:1;
0466                 uint32_t DMA54:1;
0467                 uint32_t DMA53:1;
0468                 uint32_t DMA52:1;
0469                 uint32_t DMA51:1;
0470                 uint32_t DMA50:1;
0471                 uint32_t DMA49:1;
0472                 uint32_t DMA48:1;
0473                 uint32_t DMA47:1;
0474                 uint32_t DMA46:1;
0475                 uint32_t DMA45:1;
0476                 uint32_t DMA44:1;
0477                 uint32_t DMA43:1;
0478                 uint32_t DMA42:1;
0479                 uint32_t DMA41:1;
0480                 uint32_t DMA40:1;
0481                 uint32_t DMA39:1;
0482                 uint32_t DMA38:1;
0483                 uint32_t DMA37:1;
0484                 uint32_t DMA36:1;
0485                 uint32_t DMA35:1;
0486                 uint32_t DMA34:1;
0487                 uint32_t DMA33:1;
0488                 uint32_t DMA32:1;
0489             } B;
0490         } DMAR1;                /* DMA CHANNEL SELECT REGISTER 1 */
0491
0492         union {
0493             uint32_t R;
0494             struct {
0495                 uint32_t DMA95:1;
0496                 uint32_t DMA94:1;
0497                 uint32_t DMA93:1;
0498                 uint32_t DMA92:1;
0499                 uint32_t DMA91:1;
0500                 uint32_t DMA90:1;
0501                 uint32_t DMA89:1;
0502                 uint32_t DMA88:1;
0503                 uint32_t DMA87:1;
0504                 uint32_t DMA86:1;
0505                 uint32_t DMA85:1;
0506                 uint32_t DMA84:1;
0507                 uint32_t DMA83:1;
0508                 uint32_t DMA82:1;
0509                 uint32_t DMA81:1;
0510                 uint32_t DMA80:1;
0511                 uint32_t DMA79:1;
0512                 uint32_t DMA78:1;
0513                 uint32_t DMA77:1;
0514                 uint32_t DMA76:1;
0515                 uint32_t DMA75:1;
0516                 uint32_t DMA74:1;
0517                 uint32_t DMA73:1;
0518                 uint32_t DMA72:1;
0519                 uint32_t DMA71:1;
0520                 uint32_t DMA70:1;
0521                 uint32_t DMA69:1;
0522                 uint32_t DMA68:1;
0523                 uint32_t DMA67:1;
0524                 uint32_t DMA66:1;
0525                 uint32_t DMA65:1;
0526                 uint32_t DMA64:1;
0527             } B;
0528         } DMAR2;                /* DMA CHANNEL SELECT REGISTER 2 */
0529
0530         union {
0531             uint32_t R;
0532             struct {
0533                 uint32_t:16;
0534                 uint32_t THREN:1;
0535                 uint32_t THRINV:1;
0536                 uint32_t THROP:1;
0537                   uint32_t:6;
0538                 uint32_t THRCH:7;
0539             } B;
0540         } TRC[4];               /* THRESHOLD CONTROL REGISTER */
0541
0542         union {
0543             uint32_t R;
0544             struct {
0545                 uint32_t:6;
0546                 uint32_t THRH:10;
0547                   uint32_t:6;
0548                 uint32_t THRL:10;
0549             } B;
0550         } THRHLR[4];            /* THRESHOLD REGISTER */
0551
0552         union {
0553             uint32_t R;
0554             struct {
0555                 uint32_t:6;
0556                 uint32_t THRH:10;
0557                   uint32_t:6;
0558                 uint32_t THRL:10;
0559             } B;
0560         } THRALT[4];            /* ALTERNATE THRESHOLD REGISTER */
0561
0562         union {
0563             uint32_t R;
0564             struct {
0565                 uint32_t:25;
0566                 uint32_t PREVAL2:2;
0567                 uint32_t PREVAL1:2;
0568                 uint32_t PREVAL0:2;
0569                 uint32_t PRECONV:1;
0570             } B;
0571         } PSCR;                 /* PRESAMPLING CONTROL REGISTER */
0572
0573         union {
0574             uint32_t R;
0575             struct {
0576                 uint32_t PSR31:1;
0577                 uint32_t PSR30:1;
0578                 uint32_t PSR29:1;
0579                 uint32_t PSR28:1;
0580                 uint32_t PSR27:1;
0581                 uint32_t PSR26:1;
0582                 uint32_t PSR25:1;
0583                 uint32_t PSR24:1;
0584                 uint32_t PSR23:1;
0585                 uint32_t PSR22:1;
0586                 uint32_t PSR21:1;
0587                 uint32_t PSR20:1;
0588                 uint32_t PSR19:1;
0589                 uint32_t PSR18:1;
0590                 uint32_t PSR17:1;
0591                 uint32_t PSR16:1;
0592                 uint32_t PSR15:1;
0593                 uint32_t PSR14:1;
0594                 uint32_t PSR13:1;
0595                 uint32_t PSR12:1;
0596                 uint32_t PSR11:1;
0597                 uint32_t PSR10:1;
0598                 uint32_t PSR9:1;
0599                 uint32_t PSR8:1;
0600                 uint32_t PSR7:1;
0601                 uint32_t PSR6:1;
0602                 uint32_t PSR5:1;
0603                 uint32_t PSR4:1;
0604                 uint32_t PSR3:1;
0605                 uint32_t PSR2:1;
0606                 uint32_t PSR1:1;
0607                 uint32_t PSR0:1;
0608             } B;
0609         } PSR0;                 /* PRESAMPLING REGISTER 0 */
0610
0611         union {
0612             uint32_t R;
0613             struct {
0614                 uint32_t PSR63:1;
0615                 uint32_t PSR62:1;
0616                 uint32_t PSR61:1;
0617                 uint32_t PSR60:1;
0618                 uint32_t PSR59:1;
0619                 uint32_t PSR58:1;
0620                 uint32_t PSR57:1;
0621                 uint32_t PSR56:1;
0622                 uint32_t PSR55:1;
0623                 uint32_t PSR54:1;
0624                 uint32_t PSR53:1;
0625                 uint32_t PSR52:1;
0626                 uint32_t PSR51:1;
0627                 uint32_t PSR50:1;
0628                 uint32_t PSR49:1;
0629                 uint32_t PSR48:1;
0630                 uint32_t PSR47:1;
0631                 uint32_t PSR46:1;
0632                 uint32_t PSR45:1;
0633                 uint32_t PSR44:1;
0634                 uint32_t PSR43:1;
0635                 uint32_t PSR42:1;
0636                 uint32_t PSR41:1;
0637                 uint32_t PSR40:1;
0638                 uint32_t PSR39:1;
0639                 uint32_t PSR38:1;
0640                 uint32_t PSR37:1;
0641                 uint32_t PSR36:1;
0642                 uint32_t PSR35:1;
0643                 uint32_t PSR34:1;
0644                 uint32_t PSR33:1;
0645                 uint32_t PSR32:1;
0646             } B;
0647         } PSR1;                 /* PRESAMPLING REGISTER 1 */
0648
0649         union {
0650             uint32_t R;
0651             struct {
0652                 uint32_t PSR95:1;
0653                 uint32_t PSR94:1;
0654                 uint32_t PSR93:1;
0655                 uint32_t PSR92:1;
0656                 uint32_t PSR91:1;
0657                 uint32_t PSR90:1;
0658                 uint32_t PSR89:1;
0659                 uint32_t PSR88:1;
0660                 uint32_t PSR87:1;
0661                 uint32_t PSR86:1;
0662                 uint32_t PSR85:1;
0663                 uint32_t PSR84:1;
0664                 uint32_t PSR83:1;
0665                 uint32_t PSR82:1;
0666                 uint32_t PSR81:1;
0667                 uint32_t PSR80:1;
0668                 uint32_t PSR79:1;
0669                 uint32_t PSR78:1;
0670                 uint32_t PSR77:1;
0671                 uint32_t PSR76:1;
0672                 uint32_t PSR75:1;
0673                 uint32_t PSR74:1;
0674                 uint32_t PSR73:1;
0675                 uint32_t PSR72:1;
0676                 uint32_t PSR71:1;
0677                 uint32_t PSR70:1;
0678                 uint32_t PSR69:1;
0679                 uint32_t PSR68:1;
0680                 uint32_t PSR67:1;
0681                 uint32_t PSR66:1;
0682                 uint32_t PSR65:1;
0683                 uint32_t PSR64:1;
0684             } B;
0685         } PSR2;                 /* PRESAMPLING REGISTER 2 */
0686
0687         uint32_t adc_reserved3;
0688
0689         union {
0690             uint32_t R;
0691             struct {
0692                 uint32_t:16;
0693                 uint32_t INPLATCH:1;
0694                   uint32_t:1;
0695                 uint32_t OFFSHIFT:2;
0696                   uint32_t:1;
0697                 uint32_t INPCMP:2;
0698                   uint32_t:1;
0699                 uint32_t INPSAMP:8;
0700             } B;
0701         } CTR0;                 /* CONVERSION TIMING REGISTER 0 */
0702
0703         union {
0704             uint32_t R;
0705             struct {
0706                 uint32_t:16;
0707                 uint32_t INPLATCH:1;
0708                   uint32_t:4;
0709                 uint32_t INPCMP:2;
0710                   uint32_t:1;
0711                 uint32_t INPSAMP:8;
0712             } B;
0713         } CTR1;                 /* CONVERSION TIMING REGISTER 1 */
0714
0715         union {
0716             uint32_t R;
0717             struct {
0718                 uint32_t:16;
0719                 uint32_t INPLATCH:1;
0720                   uint32_t:4;
0721                 uint32_t INPCMP:2;
0722                   uint32_t:1;
0723                 uint32_t INPSAMP:8;
0724             } B;
0725         } CTR2;                 /* CONVERSION TIMING REGISTER 2 */
0726
0727         uint32_t adc_reserved4;
0728
0729         union {
0730             uint32_t R;
0731             struct {
0732                 uint32_t CH31:1;
0733                 uint32_t CH30:1;
0734                 uint32_t CH29:1;
0735                 uint32_t CH28:1;
0736                 uint32_t CH27:1;
0737                 uint32_t CH26:1;
0738                 uint32_t CH25:1;
0739                 uint32_t CH24:1;
0740                 uint32_t CH23:1;
0741                 uint32_t CH22:1;
0742                 uint32_t CH21:1;
0743                 uint32_t CH20:1;
0744                 uint32_t CH19:1;
0745                 uint32_t CH18:1;
0746                 uint32_t CH17:1;
0747                 uint32_t CH16:1;
0748                 uint32_t CH15:1;
0749                 uint32_t CH14:1;
0750                 uint32_t CH13:1;
0751                 uint32_t CH12:1;
0752                 uint32_t CH11:1;
0753                 uint32_t CH10:1;
0754                 uint32_t CH9:1;
0755                 uint32_t CH8:1;
0756                 uint32_t CH7:1;
0757                 uint32_t CH6:1;
0758                 uint32_t CH5:1;
0759                 uint32_t CH4:1;
0760                 uint32_t CH3:1;
0761                 uint32_t CH2:1;
0762                 uint32_t CH1:1;
0763                 uint32_t CH0:1;
0764             } B;
0765         } NCMR0;                /* NORMAL CONVERSION MASK REGISTER 0 */
0766
0767         union {
0768             uint32_t R;
0769             struct {
0770                 uint32_t CH63:1;
0771                 uint32_t CH62:1;
0772                 uint32_t CH61:1;
0773                 uint32_t CH60:1;
0774                 uint32_t CH59:1;
0775                 uint32_t CH58:1;
0776                 uint32_t CH57:1;
0777                 uint32_t CH56:1;
0778                 uint32_t CH55:1;
0779                 uint32_t CH54:1;
0780                 uint32_t CH53:1;
0781                 uint32_t CH52:1;
0782                 uint32_t CH51:1;
0783                 uint32_t CH50:1;
0784                 uint32_t CH49:1;
0785                 uint32_t CH48:1;
0786                 uint32_t CH47:1;
0787                 uint32_t CH46:1;
0788                 uint32_t CH45:1;
0789                 uint32_t CH44:1;
0790                 uint32_t CH43:1;
0791                 uint32_t CH42:1;
0792                 uint32_t CH41:1;
0793                 uint32_t CH40:1;
0794                 uint32_t CH39:1;
0795                 uint32_t CH38:1;
0796                 uint32_t CH37:1;
0797                 uint32_t CH36:1;
0798                 uint32_t CH35:1;
0799                 uint32_t CH34:1;
0800                 uint32_t CH33:1;
0801                 uint32_t CH32:1;
0802             } B;
0803         } NCMR1;                /* NORMAL CONVERSION MASK REGISTER 1 */
0804
0805         union {
0806             uint32_t R;
0807             struct {
0808                 uint32_t PSR95:1;
0809                 uint32_t PSR94:1;
0810                 uint32_t PSR93:1;
0811                 uint32_t PSR92:1;
0812                 uint32_t PSR91:1;
0813                 uint32_t PSR90:1;
0814                 uint32_t PSR89:1;
0815                 uint32_t PSR88:1;
0816                 uint32_t PSR87:1;
0817                 uint32_t PSR86:1;
0818                 uint32_t PSR85:1;
0819                 uint32_t PSR84:1;
0820                 uint32_t PSR83:1;
0821                 uint32_t PSR82:1;
0822                 uint32_t PSR81:1;
0823                 uint32_t PSR80:1;
0824                 uint32_t PSR79:1;
0825                 uint32_t PSR78:1;
0826                 uint32_t PSR77:1;
0827                 uint32_t PSR76:1;
0828                 uint32_t PSR75:1;
0829                 uint32_t PSR74:1;
0830                 uint32_t PSR73:1;
0831                 uint32_t PSR72:1;
0832                 uint32_t PSR71:1;
0833                 uint32_t PSR70:1;
0834                 uint32_t PSR69:1;
0835                 uint32_t PSR68:1;
0836                 uint32_t PSR67:1;
0837                 uint32_t PSR66:1;
0838                 uint32_t PSR65:1;
0839                 uint32_t PSR64:1;
0840             } B;
0841         } NCMR2;                /* NORMAL CONVERSION MASK REGISTER 2 */
0842
0843         uint32_t adc_reserved5;
0844
0845         union {
0846             uint32_t R;
0847             struct {
0848                 uint32_t CH31:1;
0849                 uint32_t CH30:1;
0850                 uint32_t CH29:1;
0851                 uint32_t CH28:1;
0852                 uint32_t CH27:1;
0853                 uint32_t CH26:1;
0854                 uint32_t CH25:1;
0855                 uint32_t CH24:1;
0856                 uint32_t CH23:1;
0857                 uint32_t CH22:1;
0858                 uint32_t CH21:1;
0859                 uint32_t CH20:1;
0860                 uint32_t CH19:1;
0861                 uint32_t CH18:1;
0862                 uint32_t CH17:1;
0863                 uint32_t CH16:1;
0864                 uint32_t CH15:1;
0865                 uint32_t CH14:1;
0866                 uint32_t CH13:1;
0867                 uint32_t CH12:1;
0868                 uint32_t CH11:1;
0869                 uint32_t CH10:1;
0870                 uint32_t CH9:1;
0871                 uint32_t CH8:1;
0872                 uint32_t CH7:1;
0873                 uint32_t CH6:1;
0874                 uint32_t CH5:1;
0875                 uint32_t CH4:1;
0876                 uint32_t CH3:1;
0877                 uint32_t CH2:1;
0878                 uint32_t CH1:1;
0879                 uint32_t CH0:1;
0880             } B;
0881         } JCMR0;                /* INJECTED CONVERSION MASK REGISTER 0 */
0882
0883         union {
0884             uint32_t R;
0885             struct {
0886                 uint32_t CH63:1;
0887                 uint32_t CH62:1;
0888                 uint32_t CH61:1;
0889                 uint32_t CH60:1;
0890                 uint32_t CH59:1;
0891                 uint32_t CH58:1;
0892                 uint32_t CH57:1;
0893                 uint32_t CH56:1;
0894                 uint32_t CH55:1;
0895                 uint32_t CH54:1;
0896                 uint32_t CH53:1;
0897                 uint32_t CH52:1;
0898                 uint32_t CH51:1;
0899                 uint32_t CH50:1;
0900                 uint32_t CH49:1;
0901                 uint32_t CH48:1;
0902                 uint32_t CH47:1;
0903                 uint32_t CH46:1;
0904                 uint32_t CH45:1;
0905                 uint32_t CH44:1;
0906                 uint32_t CH43:1;
0907                 uint32_t CH42:1;
0908                 uint32_t CH41:1;
0909                 uint32_t CH40:1;
0910                 uint32_t CH39:1;
0911                 uint32_t CH38:1;
0912                 uint32_t CH37:1;
0913                 uint32_t CH36:1;
0914                 uint32_t CH35:1;
0915                 uint32_t CH34:1;
0916                 uint32_t CH33:1;
0917                 uint32_t CH32:1;
0918             } B;
0919         } JCMR1;                /* INJECTED CONVERSION MASK REGISTER 1 */
0920
0921         union {
0922             uint32_t R;
0923             struct {
0924                 uint32_t PSR95:1;
0925                 uint32_t PSR94:1;
0926                 uint32_t PSR93:1;
0927                 uint32_t PSR92:1;
0928                 uint32_t PSR91:1;
0929                 uint32_t PSR90:1;
0930                 uint32_t PSR89:1;
0931                 uint32_t PSR88:1;
0932                 uint32_t PSR87:1;
0933                 uint32_t PSR86:1;
0934                 uint32_t PSR85:1;
0935                 uint32_t PSR84:1;
0936                 uint32_t PSR83:1;
0937                 uint32_t PSR82:1;
0938                 uint32_t PSR81:1;
0939                 uint32_t PSR80:1;
0940                 uint32_t PSR79:1;
0941                 uint32_t PSR78:1;
0942                 uint32_t PSR77:1;
0943                 uint32_t PSR76:1;
0944                 uint32_t PSR75:1;
0945                 uint32_t PSR74:1;
0946                 uint32_t PSR73:1;
0947                 uint32_t PSR72:1;
0948                 uint32_t PSR71:1;
0949                 uint32_t PSR70:1;
0950                 uint32_t PSR69:1;
0951                 uint32_t PSR68:1;
0952                 uint32_t PSR67:1;
0953                 uint32_t PSR66:1;
0954                 uint32_t PSR65:1;
0955                 uint32_t PSR64:1;
0956             } B;
0957         } JCMR2;                /* INJECTED CONVERSION MASK REGISTER 2 */
0958
0959         union {
0960             uint32_t R;
0961             struct {
0962                 uint32_t:15;
0963                 uint32_t OFFSETLOAD:1;
0964                   uint32_t:8;
0965                 uint32_t OFFSET_WORD:8;
0966             } B;
0967         } OFFWR;                /* OFFSET WORD REGISTER */
0968
0969         union {
0970             uint32_t R;
0971             struct {
0972                 uint32_t:24;
0973                 uint32_t DSD:8;
0974             } B;
0975         } DSDR;                 /* DECODE SIGNALS DELAY REGISTER */
0976
0977         union {
0978             uint32_t R;
0979             struct {
0980                 uint32_t:24;
0981                 uint32_t PDED:8;
0982             } B;
0983         } PDEDR;                /* DECODE SIGNALS DELAY REGISTER */
0984
0985         uint32_t adc_reserved6[9];
0986
0987         union {
0988             uint32_t R;
0989             struct {
0990                 uint32_t:16;
0991                 uint32_t TEST_CTL:16;
0992             } B;
0993         } TCTLR;                /* TEST CONTROL REGISTER */
0994
0995         uint32_t adc_reserved7[3];
0996
0997         union {
0998             uint32_t R;
0999             struct {
1000                 uint32_t:12;
1001                 uint32_t VALID:1;
1002                 uint32_t OVERW:1;
1003                 uint32_t RESULT:2;
1004                   uint32_t:6;
1005                 uint32_t CDATA:10;
1006             } B;
1007         } PRECDATAREG[32];      /* PRESISION DATA REGISTER */
1008
1009         union {
1010             uint32_t R;
1011             struct {
1012                 uint32_t:12;
1013                 uint32_t VALID:1;
1014                 uint32_t OVERW:1;
1015                 uint32_t RESULT:2;
1016                   uint32_t:6;
1017                 uint32_t CDATA:10;
1018             } B;
1019         } INTDATAREG[32];       /* PRESISION DATA REGISTER */
1020
1021         union {
1022             uint32_t R;
1023             struct {
1024                 uint32_t:12;
1025                 uint32_t VALID:1;
1026                 uint32_t OVERW:1;
1027                 uint32_t RESULT:2;
1028                   uint32_t:6;
1029                 uint32_t CDATA:10;
1030             } B;
1031         } EXTDATAREG[32];       /* PRESISION DATA REGISTER */
1032
1033     };                          /* end of ADC_tag */
1034 /**************************************************************************/
1035 /*                  MODULE : AXBS Crossbar Switch (XBAR)                  */
1036 /**************************************************************************/
1037     struct XBAR_tag {
1038
1039         union {
1040             uint32_t R;
1041             struct {
1042                 uint32_t:1;
1043                 uint32_t MSTR7:3;
1044                   uint32_t:1;
1045                 uint32_t MSTR6:3;
1046                   uint32_t:9;
1047                 uint32_t MSTR5:3;
1048                   uint32_t:1;
1049                 uint32_t MSTR3:3;
1050                   uint32_t:1;
1051                 uint32_t MSTR2:3;
1052                   uint32_t:1;
1053                 uint32_t MSTR1:3;
1054                   uint32_t:1;
1055                 uint32_t MSTR0:1;
1056             } B;
1057         } MPR0;                 /* Master Priority Register 0 */
1058
1059         uint32_t xbar_reserved1[3];
1060
1061         union {
1062             uint32_t R;
1063             struct {
1064                 uint32_t R0:1;
1065                   uint32_t:21;
1066                 uint32_t ARB:2;
1067                   uint32_t:2;
1068                 uint32_t PCTL:2;
1069                   uint32_t:1;
1070                 uint32_t PARK:3;
1071             } B;
1072         } SGPCR0;               /* Master Priority Register 0 */
1073
1074         uint32_t xbar_reserved2[58];
1075
1076         union {
1077             uint32_t R;
1078             struct {
1079                 uint32_t:1;
1080                 uint32_t MSTR7:3;
1081                   uint32_t:1;
1082                 uint32_t MSTR6:3;
1083                   uint32_t:9;
1084                 uint32_t MSTR5:3;
1085                   uint32_t:1;
1086                 uint32_t MSTR3:3;
1087                   uint32_t:1;
1088                 uint32_t MSTR2:3;
1089                   uint32_t:1;
1090                 uint32_t MSTR1:3;
1091                   uint32_t:1;
1092                 uint32_t MSTR0:1;
1093             } B;
1094         } MPR1;                 /* Master Priority Register 1 */
1095
1096         uint32_t xbar_reserved3[3];
1097
1098         union {
1099             uint32_t R;
1100             struct {
1101                 uint32_t R0:1;
1102                   uint32_t:21;
1103                 uint32_t ARB:2;
1104                   uint32_t:2;
1105                 uint32_t PCTL:2;
1106                   uint32_t:1;
1107                 uint32_t PARK:3;
1108             } B;
1109         } SGPCR1;               /* Master Priority Register 1 */
1110
1111         uint32_t xbar_reserved4[58];
1112
1113         union {
1114             uint32_t R;
1115             struct {
1116                 uint32_t:1;
1117                 uint32_t MSTR7:3;
1118                   uint32_t:1;
1119                 uint32_t MSTR6:3;
1120                   uint32_t:9;
1121                 uint32_t MSTR5:3;
1122                   uint32_t:1;
1123                 uint32_t MSTR3:3;
1124                   uint32_t:1;
1125                 uint32_t MSTR2:3;
1126                   uint32_t:1;
1127                 uint32_t MSTR1:3;
1128                   uint32_t:1;
1129                 uint32_t MSTR0:1;
1130             } B;
1131         } MPR2;                 /* Master Priority Register 2 */
1132
1133         uint32_t xbar_reserved5[3];
1134
1135         union {
1136             uint32_t R;
1137             struct {
1138                 uint32_t R0:1;
1139                   uint32_t:21;
1140                 uint32_t ARB:2;
1141                   uint32_t:2;
1142                 uint32_t PCTL:2;
1143                   uint32_t:1;
1144                 uint32_t PARK:3;
1145             } B;
1146         } SGPCR2;               /* Master Priority Register 2 */
1147
1148         uint32_t xbar_reserved6[58];
1149
1150         union {
1151             uint32_t R;
1152             struct {
1153                 uint32_t:1;
1154                 uint32_t MSTR7:3;
1155                   uint32_t:1;
1156                 uint32_t MSTR6:3;
1157                   uint32_t:9;
1158                 uint32_t MSTR5:3;
1159                   uint32_t:1;
1160                 uint32_t MSTR3:3;
1161                   uint32_t:1;
1162                 uint32_t MSTR2:3;
1163                   uint32_t:1;
1164                 uint32_t MSTR1:3;
1165                   uint32_t:1;
1166                 uint32_t MSTR0:1;
1167             } B;
1168         } MPR3;                 /* Master Priority Register 3 */
1169
1170         uint32_t xbar_reserved7[3];
1171
1172         union {
1173             uint32_t R;
1174             struct {
1175                 uint32_t R0:1;
1176                   uint32_t:21;
1177                 uint32_t ARB:2;
1178                   uint32_t:2;
1179                 uint32_t PCTL:2;
1180                   uint32_t:1;
1181                 uint32_t PARK:3;
1182             } B;
1183         } SGPCR3;               /* Master Priority Register 3 */
1184
1185         uint32_t xbar_reserved8[186];
1186
1187         union {
1188             uint32_t R;
1189             struct {
1190                 uint32_t:1;
1191                 uint32_t MSTR7:3;
1192                   uint32_t:1;
1193                 uint32_t MSTR6:3;
1194                   uint32_t:9;
1195                 uint32_t MSTR5:3;
1196                   uint32_t:1;
1197                 uint32_t MSTR3:3;
1198                   uint32_t:1;
1199                 uint32_t MSTR2:3;
1200                   uint32_t:1;
1201                 uint32_t MSTR1:3;
1202                   uint32_t:1;
1203                 uint32_t MSTR0:1;
1204             } B;
1205         } MPR6;                 /* Master Priority Register 6 */
1206
1207         uint32_t xbar_reserved9[3];
1208
1209         union {
1210             uint32_t R;
1211             struct {
1212                 uint32_t R0:1;
1213                   uint32_t:21;
1214                 uint32_t ARB:2;
1215                   uint32_t:2;
1216                 uint32_t PCTL:2;
1217                   uint32_t:1;
1218                 uint32_t PARK:3;
1219             } B;
1220         } SGPCR6;               /* Master Priority Register 6 */
1221
1222         uint32_t xbar_reserved10[58];
1223
1224         union {
1225             uint32_t R;
1226             struct {
1227                 uint32_t:1;
1228                 uint32_t MSTR7:3;
1229                   uint32_t:1;
1230                 uint32_t MSTR6:3;
1231                   uint32_t:9;
1232                 uint32_t MSTR5:3;
1233                   uint32_t:1;
1234                 uint32_t MSTR3:3;
1235                   uint32_t:1;
1236                 uint32_t MSTR2:3;
1237                   uint32_t:1;
1238                 uint32_t MSTR1:3;
1239                   uint32_t:1;
1240                 uint32_t MSTR0:1;
1241             } B;
1242         } MPR7;                 /* Master Priority Register 7 */
1243
1244         uint32_t xbar_reserved11[3];
1245
1246         union {
1247             uint32_t R;
1248             struct {
1249                 uint32_t R0:1;
1250                   uint32_t:21;
1251                 uint32_t ARB:2;
1252                   uint32_t:2;
1253                 uint32_t PCTL:2;
1254                   uint32_t:1;
1255                 uint32_t PARK:3;
1256             } B;
1257         } SGPCR7;               /* Master Priority Register 7 */
1258
1259         uint32_t xbar_reserved12[506];
1260
1261         union {
1262             uint32_t R;
1263             struct {
1264                 uint32_t R0:1;
1265                   uint32_t:21;
1266                 uint32_t ARB:2;
1267                   uint32_t:2;
1268                 uint32_t PCTL:2;
1269                   uint32_t:1;
1270                 uint32_t PARK:3;
1271             } B;
1272         } MGPCR7;               /* Master General Purpose Register 7 */
1273
1274     };
1275 /*************************************************************************/
1276 /*                            MODULE : CRP                               */
1277 /*************************************************************************/
1278     struct CRP_tag {
1279
1280         union {
1281             uint32_t R;
1282             struct {
1283                 uint32_t IRCTRIMEN:1;
1284                   uint32_t:4;
1285                 uint32_t PREDIV:3;
1286                   uint32_t:4;
1287                 uint32_t EN128KIRC:1;
1288                 uint32_t EN32KOSC:1;
1289                 uint32_t ENLPOSC:1;
1290                 uint32_t EN40MOSC:1;
1291                   uint32_t:3;
1292                 uint32_t TRIM128IRC:5;
1293                   uint32_t:2;
1294                 uint32_t TRIM16IRC:6;
1295             } B;
1296         } CLKSRC;               /* CLOCK SOURCE REGISTER */
1297
1298         uint32_t crp_reserved1[3];
1299
1300         union {
1301             uint32_t R;
1302             struct {
1303                 uint32_t CNTEN:1;
1304                 uint32_t RTCIE:1;
1305                 uint32_t FRZEN:1;
1306                 uint32_t ROVREN:1;
1307                 uint32_t RTCVAL:12;
1308                 uint32_t APIEN:1;
1309                 uint32_t APIIE:1;
1310                 uint32_t CLKSEL:2;
1311                 uint32_t DIV512EN:1;
1312                 uint32_t DIV32EN:1;
1313                 uint32_t APIVAL:10;
1314             } B;
1315         } RTCC;                 /* RTC CONTROL REGISTER */
1316
1317         union {
1318             uint32_t R;
1319             struct {
1320                 uint32_t:2;
1321                 uint32_t RTCF:1;
1322                   uint32_t:15;
1323                 uint32_t APIF:1;
1324                   uint32_t:2;
1325                 uint32_t ROVRF:1;
1326                   uint32_t:10;
1327             } B;
1328         } RTSC;                 /* RTC STATUS REGISTER */
1329
1330         union {
1331             uint32_t R;
1332             struct {
1333                 uint32_t RTCCNT:32;
1334             } B;
1335         } RTCCNT;               /* RTC Counter Register */
1336
1337         uint32_t crp_reserved2[9];
1338
1339         union {
1340             uint32_t R;
1341             struct {
1342                 uint32_t PWK31:2;
1343                 uint32_t PWK30:2;
1344                 uint32_t PWK29:2;
1345                 uint32_t PWK28:2;
1346                 uint32_t PWK27:2;
1347                 uint32_t PWK26:2;
1348                 uint32_t PWK25:2;
1349                 uint32_t PWK24:2;
1350                 uint32_t PWK23:2;
1351                 uint32_t PWK22:2;
1352                 uint32_t PWK21:2;
1353                 uint32_t PWK20:2;
1354                 uint32_t PWK19:2;
1355                 uint32_t PWK18:2;
1356                 uint32_t PWK17:2;
1357                 uint32_t PWK16:2;
1358             } B;
1359         } PWKENH;               /* PIN WAKEUP ENABLE HIGH REGISTER */
1360
1361         union {
1362             uint32_t R;
1363             struct {
1364                 uint32_t PWK15:2;
1365                 uint32_t PWK14:2;
1366                 uint32_t PWK13:2;
1367                 uint32_t PWK12:2;
1368                 uint32_t PWK11:2;
1369                 uint32_t PWK10:2;
1370                 uint32_t PWK9:2;
1371                 uint32_t PWK8:2;
1372                 uint32_t PWK7:2;
1373                 uint32_t PWK6:2;
1374                 uint32_t PWK5:2;
1375                 uint32_t PWK4:2;
1376                 uint32_t PWK3:2;
1377                 uint32_t PWK2:2;
1378                 uint32_t PWK1:2;
1379                 uint32_t PWK0:2;
1380             } B;
1381         } PWKENL;               /* PIN WAKEUP ENABLE LOW REGISTER */
1382
1383         union {
1384             uint32_t R;
1385             struct {
1386                 uint32_t PWKSRCIE31:1;
1387                 uint32_t PWKSRCIE30:1;
1388                 uint32_t PWKSRCIE29:1;
1389                 uint32_t PWKSRCIE28:1;
1390                 uint32_t PWKSRCIE27:1;
1391                 uint32_t PWKSRCIE26:1;
1392                 uint32_t PWKSRCIE25:1;
1393                 uint32_t PWKSRCIE24:1;
1394                 uint32_t PWKSRCIE23:1;
1395                 uint32_t PWKSRCIE22:1;
1396                 uint32_t PWKSRCIE21:1;
1397                 uint32_t PWKSRCIE20:1;
1398                 uint32_t PWKSRCIE19:1;
1399                 uint32_t PWKSRCIE18:1;
1400                 uint32_t PWKSRCIE17:1;
1401                 uint32_t PWKSRCIE16:1;
1402                 uint32_t PWKSRCIE15:1;
1403                 uint32_t PWKSRCIE14:1;
1404                 uint32_t PWKSRCIE13:1;
1405                 uint32_t PWKSRCIE12:1;
1406                 uint32_t PWKSRCIE11:1;
1407                 uint32_t PWKSRCIE10:1;
1408                 uint32_t PWKSRCIE9:1;
1409                 uint32_t PWKSRCIE8:1;
1410                 uint32_t PWKSRCIE7:1;
1411                 uint32_t PWKSRCIE6:1;
1412                 uint32_t PWKSRCIE5:1;
1413                 uint32_t PWKSRCIE4:1;
1414                 uint32_t PWKSRCIE3:1;
1415                 uint32_t PWKSRCIE2:1;
1416                 uint32_t PWKSRCIE1:1;
1417                 uint32_t PWKSRCIE0:1;
1418             } B;
1419         } PWKSRCIE;             /* PIN WAKEUP SOURCE INTERRUPT ENABLE REGISTER */
1420
1421         union {
1422             uint32_t R;
1423             struct {
1424                 uint32_t PWKSRCIE31:1;
1425                 uint32_t PWKSRCIE30:1;
1426                 uint32_t PWKSRCIE29:1;
1427                 uint32_t PWKSRCIE28:1;
1428                 uint32_t PWKSRCIE27:1;
1429                 uint32_t PWKSRCIE26:1;
1430                 uint32_t PWKSRCIE25:1;
1431                 uint32_t PWKSRCIE24:1;
1432                 uint32_t PWKSRCIE23:1;
1433                 uint32_t PWKSRCIE22:1;
1434                 uint32_t PWKSRCIE21:1;
1435                 uint32_t PWKSRCIE20:1;
1436                 uint32_t PWKSRCIE19:1;
1437                 uint32_t PWKSRCIE18:1;
1438                 uint32_t PWKSRCIE17:1;
1439                 uint32_t PWKSRCIE16:1;
1440                 uint32_t PWKSRCIE15:1;
1441                 uint32_t PWKSRCIE14:1;
1442                 uint32_t PWKSRCIE13:1;
1443                 uint32_t PWKSRCIE12:1;
1444                 uint32_t PWKSRCIE11:1;
1445                 uint32_t PWKSRCIE10:1;
1446                 uint32_t PWKSRCIE9:1;
1447                 uint32_t PWKSRCIE8:1;
1448                 uint32_t PWKSRCIE7:1;
1449                 uint32_t PWKSRCIE6:1;
1450                 uint32_t PWKSRCIE5:1;
1451                 uint32_t PWKSRCIE4:1;
1452                 uint32_t PWKSRCIE3:1;
1453                 uint32_t PWKSRCIE2:1;
1454                 uint32_t PWKSRCIE1:1;
1455                 uint32_t PWKSRCIE0:1;
1456             } B;
1457         } PWKSRCF;              /* PIN WAKEUP SOURCE FLAG REGISTER */
1458
1459         union {
1460             uint32_t R;
1461             struct {
1462                 uint32_t Z6VECB:20;
1463                   uint32_t:10;
1464                 uint32_t Z6RST:1;
1465                 uint32_t VLE:1;
1466             } B;
1467         } Z6VEC;                /* Z6 RESET VECTOR REGISTER */
1468
1469         union {
1470             uint32_t R;
1471             struct {
1472                 uint32_t Z0VECB:30;
1473                 uint32_t Z0RST:1;
1474                   uint32_t:1;
1475             } B;
1476         } Z0VEC;                /* Z0 RESET VECTOR REGISTER */
1477
1478         union {
1479             uint32_t R;
1480             struct {
1481                 uint32_t RECPTR:30;
1482                 uint32_t FASTREC:1;
1483                   uint32_t:1;
1484             } B;
1485         } RECPTR;               /* RESET RECOVERY POINTER REGISTER */
1486
1487         uint32_t crp_reserved3;
1488
1489         union {
1490             uint32_t R;
1491             struct {
1492                 uint32_t SLEEPF:1;
1493                   uint32_t:12;
1494                 uint32_t RTCOVRWKF:1;
1495                 uint32_t RTCWKF:1;
1496                 uint32_t APIWKF:1;
1497                 uint32_t SLEEP:1;
1498                   uint32_t:4;
1499                 uint32_t RAMSEL:3;
1500                   uint32_t:4;
1501                 uint32_t WKCLKSEL:1;
1502                 uint32_t RTCOVRWKEN:1;
1503                 uint32_t RTCWKEN:1;
1504                 uint32_t APIWKEN:1;
1505             } B;
1506         } PSCR;                 /* POWER STATUS AND CONTROL REGISTER */
1507
1508         uint32_t crp_reserved4[3];
1509
1510         union {
1511             uint32_t R;
1512             struct {
1513                 uint32_t LVI5LOCK:1;
1514                 uint32_t LVI5RE:1;
1515                   uint32_t:7;
1516                 uint32_t LVI5HIE:1;
1517                 uint32_t LVI5NIE:1;
1518                 uint32_t LVI5IE:1;
1519                   uint32_t:2;
1520                 uint32_t FRIE:1;
1521                 uint32_t FDIS:1;
1522                   uint32_t:9;
1523                 uint32_t LVI5HIF:1;
1524                 uint32_t LVI5NF:1;
1525                 uint32_t LVI5F:1;
1526                   uint32_t:2;
1527                 uint32_t FRF:1;
1528                 uint32_t FRDY:1;
1529             } B;
1530         } SOCSC;                /* LVI Status and Control Register */
1531
1532     };                          /* end of CRP_tag */
1533 /*************************************************************************/
1534 /*                          MODULE : CTU                                 */
1535 /*************************************************************************/
1536     struct CTU_tag {
1537
1538         union {
1539             uint32_t R;
1540             struct {
1541                 uint32_t:24;
1542                 uint32_t TRGIEN:1;
1543                 uint32_t TRGI:1;
1544                   uint32_t:2;
1545                 uint32_t PRESC_CONF:4;
1546             } B;
1547         } CSR;                  /* Control Status Register */
1548
1549         union {
1550             uint32_t R;
1551             struct {
1552                 uint32_t:23;
1553                 uint32_t SV:9;
1554             } B;
1555         } SVR[7];               /* Start Value Register */
1556
1557         union {
1558             uint32_t R;
1559             struct {
1560                 uint32_t:23;
1561                 uint32_t CV:9;
1562             } B;
1563         } CVR[4];               /* Current Value Register */
1564
1565         union {
1566             uint32_t R;
1567             struct {
1568                 uint32_t:16;
1569                 uint32_t TM:1;
1570                   uint32_t:1;
1571                 uint32_t COUNT_GROUP:2;
1572                   uint32_t:1;
1573                 uint32_t DELAY_INDEX:3;
1574                 uint32_t CLR_FG:1;
1575                   uint32_t:1;
1576                 uint32_t CHANNEL_VALUE:6;
1577             } B;
1578         } EVTCFGR[33];          /* Event Configuration Register */
1579
1580     };                          /* end of CTU_tag */
1581 /*************************************************************************/
1582 /*                          MODULE : DMAMUX                              */
1583 /*************************************************************************/
1584     struct DMAMUX_tag {
1585         union {
1586             uint8_t R;
1587             struct {
1588                 uint8_t ENBL:1;
1589                 uint8_t TRIG:1;
1590                 uint8_t SOURCE:6;
1591             } B;
1592         } CHCONFIG[32];         /* DMA Channel Configuration Register */
1593
1594     };                          /* end of DMAMUX_tag */
1595 /*************************************************************************/
1596 /*                          MODULE : DSPI                                */
1597 /*************************************************************************/
1598     struct DSPI_tag {
1599         union DSPI_MCR_tag {
1600             uint32_t R;
1601             struct {
1602                 uint32_t MSTR:1;
1603                 uint32_t CONT_SCKE:1;
1604                 uint32_t DCONF:2;
1605                 uint32_t FRZ:1;
1606                 uint32_t MTFE:1;
1607                 uint32_t PCSSE:1;
1608                 uint32_t ROOE:1;
1609                   uint32_t:2;
1610                 uint32_t PCSIS5:1;
1611                 uint32_t PCSIS4:1;
1612                 uint32_t PCSIS3:1;
1613                 uint32_t PCSIS2:1;
1614                 uint32_t PCSIS1:1;
1615                 uint32_t PCSIS0:1;
1616                   uint32_t:1;
1617                 uint32_t MDIS:1;
1618                 uint32_t DIS_TXF:1;
1619                 uint32_t DIS_RXF:1;
1620                 uint32_t CLR_TXF:1;
1621                 uint32_t CLR_RXF:1;
1622                 uint32_t SMPL_PT:2;
1623                   uint32_t:7;
1624                 uint32_t HALT:1;
1625             } B;
1626         } MCR;                  /* Module Configuration Register */
1627
1628         uint32_t dspi_reserved1;
1629
1630         union {
1631             uint32_t R;
1632             struct {
1633                 uint32_t SPI_TCNT:16;
1634                   uint32_t:16;
1635             } B;
1636         } TCR;
1637
1638         union DSPI_CTAR_tag {
1639             uint32_t R;
1640             struct {
1641                 uint32_t DBR:1;
1642                 uint32_t FMSZ:4;
1643                 uint32_t CPOL:1;
1644                 uint32_t CPHA:1;
1645                 uint32_t LSBFE:1;
1646                 uint32_t PCSSCK:2;
1647                 uint32_t PASC:2;
1648                 uint32_t PDT:2;
1649                 uint32_t PBR:2;
1650                 uint32_t CSSCK:4;
1651                 uint32_t ASC:4;
1652                 uint32_t DT:4;
1653                 uint32_t BR:4;
1654             } B;
1655         } CTAR[8];              /* Clock and Transfer Attributes Registers */
1656
1657         union DSPI_SR_tag {
1658             uint32_t R;
1659             struct {
1660                 uint32_t TCF:1;
1661                 uint32_t TXRXS:1;
1662                   uint32_t:1;
1663                 uint32_t EOQF:1;
1664                 uint32_t TFUF:1;
1665                   uint32_t:1;
1666                 uint32_t TFFF:1;
1667                   uint32_t:5;
1668                 uint32_t RFOF:1;
1669                   uint32_t:1;
1670                 uint32_t RFDF:1;
1671                   uint32_t:1;
1672                 uint32_t TXCTR:4;
1673                 uint32_t TXNXTPTR:4;
1674                 uint32_t RXCTR:4;
1675                 uint32_t POPNXTPTR:4;
1676             } B;
1677         } SR;                   /* Status Register */
1678
1679         union DSPI_RSER_tag {
1680             uint32_t R;
1681             struct {
1682                 uint32_t TCFRE:1;
1683                   uint32_t:2;
1684                 uint32_t EOQFRE:1;
1685                 uint32_t TFUFRE:1;
1686                   uint32_t:1;
1687                 uint32_t TFFFRE:1;
1688                 uint32_t TFFFDIRS:1;
1689                   uint32_t:4;
1690                 uint32_t RFOFRE:1;
1691                   uint32_t:1;
1692                 uint32_t RFDFRE:1;
1693                 uint32_t RFDFDIRS:1;
1694                   uint32_t:16;
1695             } B;
1696         } RSER;                 /* DMA/Interrupt Request Select and Enable Register */
1697
1698         union DSPI_PUSHR_tag {
1699             uint32_t R;
1700             struct {
1701                 uint32_t CONT:1;
1702                 uint32_t CTAS:3;
1703                 uint32_t EOQ:1;
1704                 uint32_t CTCNT:1;
1705                   uint32_t:4;
1706                 uint32_t PCS5:1;
1707                 uint32_t PCS4:1;
1708                 uint32_t PCS3:1;
1709                 uint32_t PCS2:1;
1710                 uint32_t PCS1:1;
1711                 uint32_t PCS0:1;
1712                 uint32_t TXDATA:16;
1713             } B;
1714         } PUSHR;                /* PUSH TX FIFO Register */
1715
1716         union DSPI_POPR_tag {
1717             uint32_t R;
1718             struct {
1719                 uint32_t:16;
1720                 uint32_t RXDATA:16;
1721             } B;
1722         } POPR;                 /* POP RX FIFO Register */
1723
1724         union {
1725             uint32_t R;
1726             struct {
1727                 uint32_t TXCMD:16;
1728                 uint32_t TXDATA:16;
1729             } B;
1730         } TXFR[4];              /* Transmit FIFO Registers */
1731
1732         uint32_t DSPI_reserved_txf[12];
1733
1734         union {
1735             uint32_t R;
1736             struct {
1737                 uint32_t:16;
1738                 uint32_t RXDATA:16;
1739             } B;
1740         } RXFR[4];              /* Transmit FIFO Registers */
1741
1742         uint32_t DSPI_reserved_rxf[12];
1743
1744         union {
1745             uint32_t R;
1746             struct {
1747                 uint32_t:11;
1748                 uint32_t TSBC:1;
1749                 uint32_t TXSS:1;
1750                   uint32_t:2;
1751                 uint32_t CID:1;
1752                 uint32_t DCONT:1;
1753                 uint32_t DSICTAS:3;
1754                   uint32_t:6;
1755                 uint32_t DPCS5:1;
1756                 uint32_t DPCS4:1;
1757                 uint32_t DPCS3:1;
1758                 uint32_t DPCS2:1;
1759                 uint32_t DPCS1:1;
1760                 uint32_t DPCS0:1;
1761             } B;
1762         } DSICR;                /* DSI Configuration Register */
1763
1764         union {
1765             uint32_t R;
1766             struct {
1767                 uint32_t SER_DATA:32;
1768             } B;
1769         } SDR;                  /* DSI Serialization Data Register */
1770
1771         union {
1772             uint32_t R;
1773             struct {
1774                 uint32_t ASER_DATA:32;
1775             } B;
1776         } ASDR;                 /* DSI Alternate Serialization Data Register */
1777
1778         union {
1779             uint32_t R;
1780             struct {
1781                 uint32_t COMP_DATA:32;
1782             } B;
1783         } COMPR;                /* DSI Transmit Comparison Register */
1784
1785         union {
1786             uint32_t R;
1787             struct {
1788                 uint32_t DESER_DATA:32;
1789             } B;
1790         } DDR;                  /* DSI deserialization Data Register */
1791
1792         union {
1793             uint32_t R;
1794             struct {
1795                 uint32_t:3;
1796                 uint32_t TSBCNT:5;
1797                   uint32_t:16;
1798                 uint32_t DPCS1_7:1;
1799                 uint32_t DPCS1_6:1;
1800                 uint32_t DPCS1_5:1;
1801                 uint32_t DPCS1_4:1;
1802                 uint32_t DPCS1_3:1;
1803                 uint32_t DPCS1_2:1;
1804                 uint32_t DPCS1_1:1;
1805                 uint32_t DPCS1_0:1;
1806             } B;
1807         } DSICR1;               /* DSI Configuration Register 1 */
1808
1809     };                          /* end of DSPI_tag */
1810 /*************************************************************************/
1811 /*                           MODULE : ECSM                               */
1812 /*************************************************************************/
1813     struct ECSM_tag {
1814
1815         uint32_t ecsm_reserved1[9];
1816
1817         union {
1818             uint32_t R;
1819             struct {
1820                 uint32_t FXSBE0:1;
1821                 uint32_t FXSBE1:1;
1822                 uint32_t FXSBE2:1;
1823                 uint32_t FXSBE3:1;
1824                   uint32_t:2;
1825                 uint32_t FXSBE6:1;
1826                 uint32_t FXSBE7:1;
1827                 uint32_t RBEN:1;
1828                 uint32_t WBEN:1;
1829                 uint32_t ACCERR:1;
1830                   uint32_t:21;
1831             } B;
1832         } FBOMCR;               /* FEC Burst Optimisation Master Control Register */
1833
1834         uint8_t ecsm_reserved2[27];
1835
1836         union {
1837             uint8_t R;
1838             struct {
1839                 uint8_t:2;
1840                 uint8_t EPR1BR:1;
1841                 uint8_t EPF1BR:1;
1842                   uint8_t:2;
1843                 uint8_t EPRNCR:1;
1844                 uint8_t EPFNCR:1;
1845             } B;
1846         } ECR;                  /* ECC Configuration Register */
1847
1848         uint8_t ecsm_reserved3[3];
1849
1850         union {
1851             uint8_t R;
1852             struct {
1853                 uint8_t:2;
1854                 uint8_t PR1BC:1;
1855                 uint8_t PF1BC:1;
1856                   uint8_t:2;
1857                 uint8_t PRNCE:1;
1858                 uint8_t PFNCE:1;
1859             } B;
1860         } ESR;                  /* ECC Status Register */
1861
1862         uint16_t ecsm_reserved4;
1863
1864         union {
1865             uint16_t R;
1866             struct {
1867                 uint16_t:2;
1868                 uint16_t FRC1BI:1;
1869                 uint16_t FR11BI:1;
1870                   uint16_t:2;
1871                 uint16_t FRCNCI:1;
1872                 uint16_t FR1NCI:1;
1873                 uint16_t PREI_SEL:1;
1874                 uint16_t ERRBIT:7;
1875             } B;
1876         } EEGR;                 /* ECC Error Generation Register */
1877
1878         uint32_t ecsm_reserved5;
1879
1880         union {
1881             uint32_t R;
1882             struct {
1883                 uint32_t PFEAR:32;
1884             } B;
1885         } PFEAR;                /* Platform Flash ECC Address Register */
1886
1887         uint16_t ecsm_reserved6;
1888
1889         union {
1890             uint8_t R;
1891             struct {
1892                 uint8_t:4;
1893                 uint8_t PFEMR:4;
1894             } B;
1895         } PFEMR;                /* Platform Flash ECC Address Register */
1896
1897         union {
1898             uint8_t R;
1899             struct {
1900                 uint8_t WRITE:1;
1901                 uint8_t SIZE:3;
1902                 uint8_t PROTECTION:4;
1903             } B;
1904         } PFEAT;                /* Flash ECC Attributes Register */
1905
1906         union {
1907             uint32_t R;
1908             struct {
1909                 uint32_t PFEDRH:32;
1910             } B;
1911         } PFEDRH;               /* Flash ECC Data High Register */
1912
1913         union {
1914             uint32_t R;
1915             struct {
1916                 uint32_t PFEDRL:32;
1917             } B;
1918         } PFEDRL;               /* Flash ECC Data Low Register */
1919
1920         union {
1921             uint32_t R;
1922             struct {
1923                 uint32_t PREAR:32;
1924             } B;
1925         } PREAR;                /* Platform RAM ECC Address Register */
1926
1927         uint16_t ecsm_reserved8;
1928
1929         union {
1930             uint8_t R;
1931             struct {
1932                 uint8_t:4;
1933                 uint8_t PREMR:4;
1934             } B;
1935         } PREMR;                /* RAM ECC Attributes Register */
1936
1937         union {
1938             uint8_t R;
1939             struct {
1940                 uint8_t WRITE:1;
1941                 uint8_t SIZE:3;
1942                 uint8_t PROTECTION:4;
1943             } B;
1944         } PREAT;                /* Platform RAM ECC Attributes Register */
1945
1946         union {
1947             uint32_t R;
1948             struct {
1949                 uint32_t PREDR:32;
1950             } B;
1951         } PREDRH;               /* Platform RAM ECC Data Low Register High */
1952
1953         union {
1954             uint32_t R;
1955             struct {
1956                 uint32_t PREDR:32;
1957             } B;
1958         } PREDRL;               /* Platform RAM ECC Data Low Register Low */
1959
1960     };                          /* end of ECSM_tag */
1961 /*************************************************************************/
1962 /*                          MODULE : EMIOS                               */
1963 /*************************************************************************/
1964     struct EMIOS_tag {
1965         union EMIOS_MCR_tag {
1966             uint32_t R;
1967             struct {
1968                 uint32_t:1;
1969                 uint32_t MDIS:1;
1970                 uint32_t FRZ:1;
1971                 uint32_t GTBE:1;
1972                   uint32_t:1;
1973                 uint32_t GPREN:1;
1974                   uint32_t:10;
1975                 uint32_t GPRE:8;
1976                   uint32_t:8;
1977             } B;
1978         } MCR;                  /* Module Configuration Register */
1979
1980         union {
1981             uint32_t R;
1982             struct {
1983                 uint32_t F31:1;
1984                 uint32_t F30:1;
1985                 uint32_t F29:1;
1986                 uint32_t F28:1;
1987                 uint32_t F27:1;
1988                 uint32_t F26:1;
1989                 uint32_t F25:1;
1990                 uint32_t F24:1;
1991                 uint32_t F23:1;
1992                 uint32_t F22:1;
1993                 uint32_t F21:1;
1994                 uint32_t F20:1;
1995                 uint32_t F19:1;
1996                 uint32_t F18:1;
1997                 uint32_t F17:1;
1998                 uint32_t F16:1;
1999                 uint32_t F15:1;
2000                 uint32_t F14:1;
2001                 uint32_t F13:1;
2002                 uint32_t F12:1;
2003                 uint32_t F11:1;
2004                 uint32_t F10:1;
2005                 uint32_t F9:1;
2006                 uint32_t F8:1;
2007                 uint32_t F7:1;
2008                 uint32_t F6:1;
2009                 uint32_t F5:1;
2010                 uint32_t F4:1;
2011                 uint32_t F3:1;
2012                 uint32_t F2:1;
2013                 uint32_t F1:1;
2014                 uint32_t F0:1;
2015             } B;
2016         } GFR;                  /* Global FLAG Register */
2017
2018         union {
2019             uint32_t R;
2020             struct {
2021                 uint32_t OU31:1;
2022                 uint32_t OU30:1;
2023                 uint32_t OU29:1;
2024                 uint32_t OU28:1;
2025                 uint32_t OU27:1;
2026                 uint32_t OU26:1;
2027                 uint32_t OU25:1;
2028                 uint32_t OU24:1;
2029                 uint32_t OU23:1;
2030                 uint32_t OU22:1;
2031                 uint32_t OU21:1;
2032                 uint32_t OU20:1;
2033                 uint32_t OU19:1;
2034                 uint32_t OU18:1;
2035                 uint32_t OU17:1;
2036                 uint32_t OU16:1;
2037                 uint32_t OU15:1;
2038                 uint32_t OU14:1;
2039                 uint32_t OU13:1;
2040                 uint32_t OU12:1;
2041                 uint32_t OU11:1;
2042                 uint32_t OU10:1;
2043                 uint32_t OU9:1;
2044                 uint32_t OU8:1;
2045                 uint32_t OU7:1;
2046                 uint32_t OU6:1;
2047                 uint32_t OU5:1;
2048                 uint32_t OU4:1;
2049                 uint32_t OU3:1;
2050                 uint32_t OU2:1;
2051                 uint32_t OU1:1;
2052                 uint32_t OU0:1;
2053             } B;
2054         } OUDR;                 /* Output Update Disable Register */
2055
2056         union {
2057             uint32_t R;
2058             struct {
2059                 uint32_t UC31:1;
2060                 uint32_t UC30:1;
2061                 uint32_t UC29:1;
2062                 uint32_t UC28:1;
2063                 uint32_t UC27:1;
2064                 uint32_t UC26:1;
2065                 uint32_t UC25:1;
2066                 uint32_t UC24:1;
2067                 uint32_t UC23:1;
2068                 uint32_t UC22:1;
2069                 uint32_t UC21:1;
2070                 uint32_t UC20:1;
2071                 uint32_t UC19:1;
2072                 uint32_t UC18:1;
2073                 uint32_t UC17:1;
2074                 uint32_t UC16:1;
2075                 uint32_t UC15:1;
2076                 uint32_t UC14:1;
2077                 uint32_t UC13:1;
2078                 uint32_t UC12:1;
2079                 uint32_t UC11:1;
2080                 uint32_t UC10:1;
2081                 uint32_t UC9:1;
2082                 uint32_t UC8:1;
2083                 uint32_t UC7:1;
2084                 uint32_t UC6:1;
2085                 uint32_t UC5:1;
2086                 uint32_t UC4:1;
2087                 uint32_t UC3:1;
2088                 uint32_t UC2:1;
2089                 uint32_t UC1:1;
2090                 uint32_t UC0:1;
2091             } B;
2092         } UCDIS;                /* Disable Channel Register */
2093
2094         uint32_t emios_reserved1[4];
2095
2096         struct EMIOS_CH_tag {
2097             union {
2098                 uint32_t R;
2099                 struct {
2100                     uint32_t:16;
2101                     uint32_t A:16;     /* Channel A Data Register */
2102                 } B;
2103             } CADR;
2104
2105             union {
2106                 uint32_t R;
2107                 struct {
2108                     uint32_t:16;
2109                     uint32_t B:16;     /* Channel B Data Register */
2110                 } B;
2111             } CBDR;
2112
2113             union {
2114                 uint32_t R;    /* Channel Counter Register */
2115                 struct {
2116                     uint32_t:16;
2117                     uint32_t C:16;     /* Channel C Data Register */
2118                 } B;
2119             } CCNTR;
2120
2121             union EMIOS_CCR_tag {
2122                 uint32_t R;
2123                 struct {
2124                     uint32_t FREN:1;
2125                     uint32_t ODIS:1;
2126                     uint32_t ODISSL:2;
2127                     uint32_t UCPRE:2;
2128                     uint32_t UCPREN:1;
2129                     uint32_t DMA:1;
2130                       uint32_t:1;
2131                     uint32_t IF:4;
2132                     uint32_t FCK:1;
2133                     uint32_t FEN:1;
2134                       uint32_t:3;
2135                     uint32_t FORCMA:1;
2136                     uint32_t FORCMB:1;
2137                       uint32_t:1;
2138                     uint32_t BSL:2;
2139                     uint32_t EDSEL:1;
2140                     uint32_t EDPOL:1;
2141                     uint32_t MODE:7;
2142                 } B;
2143             } CCR;              /* Channel Control Register */
2144
2145             union EMIOS_CSR_tag {
2146                 uint32_t R;
2147                 struct {
2148                     uint32_t OVR:1;
2149                       uint32_t:15;
2150                     uint32_t OVFL:1;
2151                       uint32_t:12;
2152                     uint32_t UCIN:1;
2153                     uint32_t UCOUT:1;
2154                     uint32_t FLAG:1;
2155                 } B;
2156             } CSR;              /* Channel Status Register */
2157
2158             union {
2159                 uint32_t R;    /* Alternate Channel A Data Register */
2160             } ALTA;
2161
2162             uint32_t emios_channel_reserved[2];
2163
2164         } CH[32];
2165
2166     };                          /* end of EMIOS_tag */
2167 /*************************************************************************/
2168 /*                             MODULE : eSCI                             */
2169 /*************************************************************************/
2170     struct ESCI_tag {
2171         union ESCI_CR1_tag {
2172             uint32_t R;
2173             struct {
2174                 uint32_t:3;
2175                 uint32_t SBR:13;
2176                 uint32_t LOOPS:1;
2177                   uint32_t:1;
2178                 uint32_t RSRC:1;
2179                 uint32_t M:1;
2180                 uint32_t WAKE:1;
2181                 uint32_t ILT:1;
2182                 uint32_t PE:1;
2183                 uint32_t PT:1;
2184                 uint32_t TIE:1;
2185                 uint32_t TCIE:1;
2186                 uint32_t RIE:1;
2187                 uint32_t ILIE:1;
2188                 uint32_t TE:1;
2189                 uint32_t RE:1;
2190                 uint32_t RWU:1;
2191                 uint32_t SBK:1;
2192             } B;
2193         } CR1;                  /* Control Register 1 */
2194
2195         union ESCI_CR2_tag {
2196             uint16_t R;
2197             struct {
2198                 uint16_t MDIS:1;
2199                 uint16_t FBR:1;
2200                 uint16_t BSTP:1;
2201                 uint16_t IEBERR:1;
2202                 uint16_t RXDMA:1;
2203                 uint16_t TXDMA:1;
2204                 uint16_t BRK13:1;
2205                 uint16_t TXDIR:1;
2206                 uint16_t BESM13:1;
2207                 uint16_t SBSTP:1;
2208                 uint16_t RXPOL:1;
2209                 uint16_t PMSK:1;
2210                 uint16_t ORIE:1;
2211                 uint16_t NFIE:1;
2212                 uint16_t FEIE:1;
2213                 uint16_t PFIE:1;
2214             } B;
2215         } CR2;                  /* Control Register 2 */
2216
2217         union ESCI_DR_tag {
2218             uint16_t R;
2219             struct {
2220                 uint16_t RN:1;
2221                 uint16_t TN:1;
2222                 uint16_t ERR:1;
2223                   uint16_t:1;
2224                 uint16_t RD_11:4;
2225                 uint16_t D:8;
2226             } B;
2227         } DR;                   /* Data Register */
2228
2229         union ESCI_SR_tag {
2230             uint32_t R;
2231             struct {
2232                 uint32_t TDRE:1;
2233                 uint32_t TC:1;
2234                 uint32_t RDRF:1;
2235                 uint32_t IDLE:1;
2236                 uint32_t OR:1;
2237                 uint32_t NF:1;
2238                 uint32_t FE:1;
2239                 uint32_t PF:1;
2240                   uint32_t:3;
2241                 uint32_t BERR:1;
2242                   uint32_t:2;
2243                 uint32_t TACT:1;
2244                 uint32_t RACT:1;
2245                 uint32_t RXRDY:1;
2246                 uint32_t TXRDY:1;
2247                 uint32_t LWAKE:1;
2248                 uint32_t STO:1;
2249                 uint32_t PBERR:1;
2250                 uint32_t CERR:1;
2251                 uint32_t CKERR:1;
2252                 uint32_t FRC:1;
2253                   uint32_t:6;
2254                 uint32_t UREQ:1;
2255                 uint32_t OVFL:1;
2256             } B;
2257         } SR;                   /* Status Register */
2258
2259         union {
2260             uint32_t R;
2261             struct {
2262                 uint32_t LRES:1;
2263                 uint32_t WU:1;
2264                 uint32_t WUD0:1;
2265                 uint32_t WUD1:1;
2266                   uint32_t:2;
2267                 uint32_t PRTY:1;
2268                 uint32_t LIN:1;
2269                 uint32_t RXIE:1;
2270                 uint32_t TXIE:1;
2271                 uint32_t WUIE:1;
2272                 uint32_t STIE:1;
2273                 uint32_t PBIE:1;
2274                 uint32_t CIE:1;
2275                 uint32_t CKIE:1;
2276                 uint32_t FCIE:1;
2277                   uint32_t:6;
2278                 uint32_t UQIE:1;
2279                 uint32_t OFIE:1;
2280                   uint32_t:8;
2281             } B;
2282         } LCR;                  /* LIN Control Register */
2283
2284         union {
2285             uint8_t R;
2286         } LTR;                  /* LIN Transmit Register */
2287
2288         uint8_t eSCI_reserved1[3];
2289
2290         union {
2291             uint8_t R;
2292         } LRR;                  /* LIN Recieve Register */
2293
2294         uint8_t eSCI_reserved2[3];
2295
2296         union {
2297             uint16_t R;
2298         } LPR;                  /* LIN CRC Polynom Register  */
2299
2300         union {
2301             uint8_t R;
2302             struct {
2303                 uint8_t:3;
2304                 uint8_t SYNM:1;
2305                 uint8_t EROE:1;
2306                 uint8_t ERFE:1;
2307                 uint8_t ERPE:1;
2308                 uint8_t M2:1;
2309             } B;
2310         } CR3;                  /* Control Register 3 */
2311
2312         uint8_t eSCI_reserved3[5];
2313     };                          /* end of ESCI_tag */
2314 /*************************************************************************/
2315 /*                             MODULE : FEC                              */
2316 /*************************************************************************/
2317     struct FEC_tag {
2318
2319         uint32_t fec_reserved_start;
2320
2321         union {
2322             uint32_t R;
2323             struct {
2324                 uint32_t HBERR:1;
2325                 uint32_t BABR:1;
2326                 uint32_t BABT:1;
2327                 uint32_t GRA:1;
2328                 uint32_t TXF:1;
2329                 uint32_t TXB:1;
2330                 uint32_t RXF:1;
2331                 uint32_t RXB:1;
2332                 uint32_t MII:1;
2333                 uint32_t EBERR:1;
2334                 uint32_t LC:1;
2335                 uint32_t RL:1;
2336                 uint32_t UN:1;
2337                   uint32_t:19;
2338             } B;
2339         } EIR;                  /*  Interrupt Event Register */
2340
2341         union {
2342             uint32_t R;
2343             struct {
2344                 uint32_t HBERR:1;
2345                 uint32_t BABR:1;
2346                 uint32_t BABT:1;
2347                 uint32_t GRA:1;
2348                 uint32_t TXF:1;
2349                 uint32_t TXB:1;
2350                 uint32_t RXF:1;
2351                 uint32_t RXB:1;
2352                 uint32_t MII:1;
2353                 uint32_t EBERR:1;
2354                 uint32_t LC:1;
2355                 uint32_t RL:1;
2356                 uint32_t UN:1;
2357                   uint32_t:19;
2358             } B;
2359         } EIMR;                 /*  Interrupt Mask Register  */
2360
2361         uint32_t fec_reserved_eimr;
2362
2363         union {
2364             uint32_t R;
2365             struct {
2366                 uint32_t:7;
2367                 uint32_t R_DES_ACTIVE:1;
2368                   uint32_t:24;
2369             } B;
2370         } RDAR;                 /*  Receive Descriptor Active Register  */
2371
2372         union {
2373             uint32_t R;
2374             struct {
2375                 uint32_t:7;
2376                 uint32_t X_DES_ACTIVE:1;
2377                   uint32_t:24;
2378             } B;
2379         } TDAR;                 /*  Transmit Descriptor Active Register  */
2380
2381         uint32_t fec_reserved_tdar[3];
2382
2383         union {
2384             uint32_t R;
2385             struct {
2386                 uint32_t:30;
2387                 uint32_t ETHER_EN:1;
2388                 uint32_t RESET:1;
2389             } B;
2390         } ECR;                  /*  Ethernet Control Register  */
2391
2392         uint32_t fec_reserved_ecr[6];
2393
2394         union {
2395             uint32_t R;
2396             struct {
2397                 uint32_t ST:2;
2398                 uint32_t OP:2;
2399                 uint32_t PA:5;
2400                 uint32_t RA:5;
2401                 uint32_t TA:2;
2402                 uint32_t DATA:16;
2403             } B;
2404         } MMFR;                 /* MII Data Register */
2405
2406         union {
2407             uint32_t R;
2408             struct {
2409                 uint32_t:24;
2410                 uint32_t DIS_PREAMBLE:1;
2411                 uint32_t MII_SPEED:6;
2412                   uint32_t:1;
2413             } B;
2414         } MSCR;                 /* MII Speed Control Register */
2415
2416         uint32_t fec_reserved_mscr[7];
2417
2418         union {
2419             uint32_t R;
2420             struct {
2421                 uint32_t MIB_DISABLE:1;
2422                 uint32_t MIB_IDLE:1;
2423                   uint32_t:30;
2424             } B;
2425         } MIBC;                 /* MIB Control Register */
2426
2427         uint32_t fec_reserved_mibc[7];
2428
2429         union {
2430             uint32_t R;
2431             struct {
2432                 uint32_t:5;
2433                 uint32_t MAX_FL:11;
2434                   uint32_t:10;
2435                 uint32_t FCE:1;
2436                 uint32_t BC_REJ:1;
2437                 uint32_t PROM:1;
2438                 uint32_t MII_MODE:1;
2439                 uint32_t DRT:1;
2440                 uint32_t LOOP:1;
2441             } B;
2442         } RCR;                  /* Receive Control Register */
2443
2444         uint32_t fec_reserved_rcr[15];
2445
2446         union {
2447             uint32_t R;
2448             struct {
2449                 uint32_t:27;
2450                 uint32_t RFC_PAUSE:1;
2451                 uint32_t TFC_PAUSE:1;
2452                 uint32_t FDEN:1;
2453                 uint32_t HBC:1;
2454                 uint32_t GTS:1;
2455             } B;
2456         } TCR;                  /* Transmit Control Register */
2457
2458         uint32_t fec_reserved_tcr[7];
2459
2460         union {
2461             uint32_t R;
2462             struct {
2463                 uint32_t PADDR1:32;
2464             } B;
2465         } PALR;                 /* Physical Address Low Register */
2466
2467         union {
2468             uint32_t R;
2469             struct {
2470                 uint32_t PADDR2:16;
2471                 uint32_t TYPE:16;
2472             } B;
2473         } PAUR;                 /* Physical Address High + Type Register */
2474
2475         union {
2476             uint32_t R;
2477             struct {
2478                 uint32_t OPCODE:16;
2479                 uint32_t PAUSE_DUR:16;
2480             } B;
2481         } OPD;                  /* Opcode/Pause Duration Register */
2482
2483         uint32_t fec_reserved_opd[10];
2484
2485         union {
2486             uint32_t R;
2487             struct {
2488                 uint32_t IADDR1:32;
2489             } B;
2490         } IAUR;                 /* Descriptor Individual Upper Address Register */
2491
2492         union {
2493             uint32_t R;
2494             struct {
2495                 uint32_t IADDR2:32;
2496             } B;
2497         } IALR;                 /* Descriptor Individual Lower Address Register */
2498
2499         union {
2500             uint32_t R;
2501             struct {
2502                 uint32_t GADDR1:32;
2503             } B;
2504         } GAUR;                 /* Descriptor Group Upper Address Register */
2505
2506         union {
2507             uint32_t R;
2508             struct {
2509                 uint32_t GADDR2:32;
2510             } B;
2511         } GALR;                 /* Descriptor Group Lower Address Register */
2512
2513         uint32_t fec_reserved_galr[7];
2514
2515         union {
2516             uint32_t R;
2517             struct {
2518                 uint32_t:30;
2519                 uint32_t X_WMRK:2;
2520             } B;
2521         } TFWR;                 /* FIFO Transmit FIFO Watermark Register */
2522
2523         uint32_t fec_reserved_tfwr;
2524
2525         union {
2526             uint32_t R;
2527             struct {
2528                 uint32_t:22;
2529                 uint32_t R_BOUND:8;
2530                   uint32_t:2;
2531             } B;
2532         } FRBR;                 /* FIFO Receive Bound Register */
2533
2534         union {
2535             uint32_t R;
2536             struct {
2537                 uint32_t:22;
2538                 uint32_t R_FSTART:8;
2539                   uint32_t:2;
2540             } B;
2541         } FRSR;                 /* FIFO Receive Start Register */
2542
2543         uint32_t fec_reserved_frsr[11];
2544
2545         union {
2546             uint32_t R;
2547             struct {
2548                 uint32_t R_DES_START:30;
2549                   uint32_t:2;
2550             } B;
2551         } ERDSR;                /* Receive Descriptor Ring Start Register */
2552
2553         union {
2554             uint32_t R;
2555             struct {
2556                 uint32_t X_DES_START:30;
2557                   uint32_t:2;
2558             } B;
2559         } ETDSR;                /* Transmit Descriptor Ring Start Register */
2560
2561         union {
2562             uint32_t R;
2563             struct {
2564                 uint32_t:21;
2565                 uint32_t R_BUF_SIZE:7;
2566                   uint32_t:4;
2567             } B;
2568         } EMRBR;                /* Receive Buffer Size Register */
2569
2570         uint32_t fec_reserved_emrbr[29];
2571
2572         union {
2573             uint32_t R;
2574         } RMON_T_DROP;          /* Count of frames not counted correctly */
2575
2576         union {
2577             uint32_t R;
2578         } RMON_T_PACKETS;       /* RMON Tx packet count */
2579
2580         union {
2581             uint32_t R;
2582         } RMON_T_BC_PKT;        /* RMON Tx Broadcast Packets */
2583
2584         union {
2585             uint32_t R;
2586         } RMON_T_MC_PKT;        /* RMON Tx Multicast Packets */
2587
2588         union {
2589             uint32_t R;
2590         } RMON_T_CRC_ALIGN;     /* RMON Tx Packets w CRC/Align error */
2591
2592         union {
2593             uint32_t R;
2594         } RMON_T_UNDERSIZE;     /* RMON Tx Packets < 64 bytes, good crc */
2595
2596         union {
2597             uint32_t R;
2598         } RMON_T_OVERSIZE;      /* RMON Tx Packets > MAX_FL bytes, good crc */
2599
2600         union {
2601             uint32_t R;
2602         } RMON_T_FRAG;          /* RMON Tx Packets < 64 bytes, bad crc */
2603
2604         union {
2605             uint32_t R;
2606         } RMON_T_JAB;           /* RMON Tx Packets > MAX_FL bytes, bad crc */
2607
2608         union {
2609             uint32_t R;
2610         } RMON_T_COL;           /* RMON Tx collision count */
2611
2612         union {
2613             uint32_t R;
2614         } RMON_T_P64;           /* RMON Tx 64 byte packets */
2615
2616         union {
2617             uint32_t R;
2618         } RMON_T_P65TO127;      /* RMON Tx 65 to 127 byte packets */
2619
2620         union {
2621             uint32_t R;
2622         } RMON_T_P128TO255;     /* RMON Tx 128 to 255 byte packets */
2623
2624         union {
2625             uint32_t R;
2626         } RMON_T_P256TO511;     /* RMON Tx 256 to 511 byte packets */
2627
2628         union {
2629             uint32_t R;
2630         } RMON_T_P512TO1023;    /* RMON Tx 512 to 1023 byte packets */
2631
2632         union {
2633             uint32_t R;
2634         } RMON_T_P1024TO2047;   /* RMON Tx 1024 to 2047 byte packets */
2635
2636         union {
2637             uint32_t R;
2638         } RMON_T_P_GTE2048;     /* RMON Tx packets w > 2048 bytes */
2639
2640         union {
2641             uint32_t R;
2642         } RMON_T_OCTETS;        /* RMON Tx Octets */
2643
2644         union {
2645             uint32_t R;
2646         } IEEE_T_DROP;          /* Count of frames not counted correctly */
2647
2648         union {
2649             uint32_t R;
2650         } IEEE_T_FRAME_OK;      /* Frames Transmitted OK */
2651
2652         union {
2653             uint32_t R;
2654         } IEEE_T_1COL;          /* Frames Transmitted with Single Collision */
2655
2656         union {
2657             uint32_t R;
2658         } IEEE_T_MCOL;          /* Frames Transmitted with Multiple Collisions */
2659
2660         union {
2661             uint32_t R;
2662         } IEEE_T_DEF;           /* Frames Transmitted after Deferral Delay */
2663
2664         union {
2665             uint32_t R;
2666         } IEEE_T_LCOL;          /* Frames Transmitted with Late Collision */
2667
2668         union {
2669             uint32_t R;
2670         } IEEE_T_EXCOL;         /* Frames Transmitted with Excessive Collisions */
2671
2672         union {
2673             uint32_t R;
2674         } IEEE_T_MACERR;        /* Frames Transmitted with Tx FIFO Underrun */
2675
2676         union {
2677             uint32_t R;
2678         } IEEE_T_CSERR;         /* Frames Transmitted with Carrier Sense Error */
2679
2680         union {
2681             uint32_t R;
2682         } IEEE_T_SQE;           /* Frames Transmitted with SQE Error */
2683
2684         union {
2685             uint32_t R;
2686         } IEEE_T_FDXFC;         /* Flow Control Pause frames transmitted */
2687
2688         union {
2689             uint32_t R;
2690         } IEEE_T_OCTETS_OK;     /* Octet count for Frames Transmitted w/o Error */
2691
2692         uint32_t fec_reserved_rmon_t_octets_ok[2];
2693
2694         union {
2695             uint32_t R;
2696         } RMON_R_DROP;          /*  Count of frames not counted correctly  */
2697
2698         union {
2699             uint32_t R;
2700         } RMON_R_PACKETS;       /* RMON Rx packet count */
2701
2702         union {
2703             uint32_t R;
2704         } RMON_R_BC_PKT;        /* RMON Rx Broadcast Packets */
2705
2706         union {
2707             uint32_t R;
2708         } RMON_R_MC_PKT;        /* RMON Rx Multicast Packets */
2709
2710         union {
2711             uint32_t R;
2712         } RMON_R_CRC_ALIGN;     /* RMON Rx Packets w CRC/Align error */
2713
2714         union {
2715             uint32_t R;
2716         } RMON_R_UNDERSIZE;     /* RMON Rx Packets < 64 bytes, good crc */
2717
2718         union {
2719             uint32_t R;
2720         } RMON_R_OVERSIZE;      /* RMON Rx Packets > MAX_FL bytes, good crc */
2721
2722         union {
2723             uint32_t R;
2724         } RMON_R_FRAG;          /* RMON Rx Packets < 64 bytes, bad crc */
2725
2726         union {
2727             uint32_t R;
2728         } RMON_R_JAB;           /* RMON Rx Packets > MAX_FL bytes, bad crc */
2729
2730         uint32_t fec_reserved_rmon_r_jab;
2731
2732         union {
2733             uint32_t R;
2734         } RMON_R_P64;           /* RMON Rx 64 byte packets */
2735
2736         union {
2737             uint32_t R;
2738         } RMON_R_P65TO127;      /* RMON Rx 65 to 127 byte packets */
2739
2740         union {
2741             uint32_t R;
2742         } RMON_R_P128TO255;     /* RMON Rx 128 to 255 byte packets */
2743
2744         union {
2745             uint32_t R;
2746         } RMON_R_P256TO511;     /* RMON Rx 256 to 511 byte packets */
2747
2748         union {
2749             uint32_t R;
2750         } RMON_R_P512TO1023;    /* RMON Rx 512 to 1023 byte packets */
2751
2752         union {
2753             uint32_t R;
2754         } RMON_R_P1024TO2047;   /* RMON Rx 1024 to 2047 byte packets */
2755
2756         union {
2757             uint32_t R;
2758         } RMON_R_P_GTE2048;     /* RMON Rx packets w > 2048 bytes */
2759
2760         union {
2761             uint32_t R;
2762         } RMON_R_OCTETS;        /* RMON Rx Octets */
2763
2764         union {
2765             uint32_t R;
2766         } IEEE_R_DROP;          /* Count of frames not counted correctly */
2767
2768         union {
2769             uint32_t R;
2770         } IEEE_R_FRAME_OK;      /* Frames Received OK */
2771
2772         union {
2773             uint32_t R;
2774         } IEEE_R_CRC;           /* Frames Received with CRC Error */
2775
2776         union {
2777             uint32_t R;
2778         } IEEE_R_ALIGN;         /* Frames Received with Alignment Error */
2779
2780         union {
2781             uint32_t R;
2782         } IEEE_R_MACERR;        /* Receive Fifo Overflow count */
2783
2784         union {
2785             uint32_t R;
2786         } IEEE_R_FDXFC;         /* Flow Control Pause frames received */
2787
2788         union {
2789             uint32_t R;
2790         } IEEE_R_OCTETS_OK;     /* Octet count for Frames Rcvd w/o Error */
2791
2792     };                          /* end of FEC_tag */
2793 /*************************************************************************/
2794 /*                            MODULE : FLASH                             */
2795 /*************************************************************************/
2796     struct FLASH_tag {
2797         union {
2798             uint32_t R;
2799             struct {
2800                 uint32_t:5;
2801                 uint32_t SIZE:3;
2802                   uint32_t:1;
2803                 uint32_t LAS:3;
2804                   uint32_t:3;
2805                 uint32_t MAS:1;
2806                 uint32_t EER:1;
2807                 uint32_t RWE:1;
2808                 uint32_t SBC:1;
2809                   uint32_t:1;
2810                 uint32_t PEAS:1;
2811                 uint32_t DONE:1;
2812                 uint32_t PEG:1;
2813                   uint32_t:4;
2814                 uint32_t PGM:1;
2815                 uint32_t PSUS:1;
2816                 uint32_t ERS:1;
2817                 uint32_t ESUS:1;
2818                 uint32_t EHV:1;
2819             } B;
2820         } MCR;                  /* Module Configuration Register */
2821
2822         union {
2823             uint32_t R;
2824             struct {
2825                 uint32_t LME:1;
2826                   uint32_t:10;
2827                 uint32_t SLOCK:1;
2828                   uint32_t:2;
2829                 uint32_t MLOCK:2;
2830                   uint32_t:6;
2831                 uint32_t LLOCK:10;
2832             } B;
2833         } LML;                  /* Low/Mid-address space block locking Register */
2834
2835         union {
2836             uint32_t R;
2837             struct {
2838                 uint32_t HBE:1;
2839                   uint32_t:25;
2840                 uint32_t HBLOCK:6;
2841             } B;
2842         } HBL;                  /* High-address space block locking Register */
2843
2844         union {
2845             uint32_t R;
2846             struct {
2847                 uint32_t SLE:1;
2848                   uint32_t:10;
2849                 uint32_t SSLOCK:1;
2850                   uint32_t:2;
2851                 uint32_t SMLOCK:2;
2852                   uint32_t:6;
2853                 uint32_t SLLOCK:10;
2854             } B;
2855         } SLL;                  /* Secondary low/mid-address space block locking Register */
2856
2857         union {
2858             uint32_t R;
2859             struct {
2860                 uint32_t:14;
2861                 uint32_t MSEL:2;
2862                   uint32_t:6;
2863                 uint32_t LSEL:10;
2864             } B;
2865         } LMS;                  /* Low/Mid-address space block locking Register */
2866
2867         union {
2868             uint32_t R;
2869             struct {
2870                 uint32_t:26;
2871                 uint32_t HBSEL:6;
2872             } B;
2873         } HBS;                  /* High-address space block locking Register */
2874
2875         union {
2876             uint32_t R;
2877             struct {
2878                 uint32_t SAD:1;
2879                   uint32_t:10;
2880                 uint32_t ADDR:18;
2881                   uint32_t:3;
2882             } B;
2883         } ADR;                  /* Address Register */
2884
2885         union {
2886             uint32_t R;
2887             struct {
2888                 uint32_t LBCFG:4;
2889                 uint32_t ARB:1;
2890                 uint32_t PRI:1;
2891                   uint32_t:1;
2892                 uint32_t M8PFE:1;
2893                   uint32_t:1;
2894                 uint32_t M6PFE:1;
2895                 uint32_t M5PFE:1;
2896                 uint32_t M4PFE:1;
2897                   uint32_t:1;
2898                 uint32_t M2PFE:1;
2899                 uint32_t M1PFE:1;
2900                 uint32_t M0PFE:1;
2901                 uint32_t APC:3;
2902                 uint32_t WWSC:2;
2903                 uint32_t RWSC:3;
2904                   uint32_t:1;
2905                 uint32_t DPFEN:1;
2906                   uint32_t:1;
2907                 uint32_t IPFEN:1;
2908                   uint32_t:1;
2909                 uint32_t PFLIM:2;
2910                 uint32_t BFEN:1;
2911             } B;
2912         } PFCRP0;               /* Platform Flash Configuration Register for Port 0 */
2913
2914         union {
2915             uint32_t R;
2916             struct {
2917                 uint32_t LBCFG:4;
2918                   uint32_t:3;
2919                 uint32_t M8PFE:1;
2920                   uint32_t:1;
2921                 uint32_t M6PFE:1;
2922                 uint32_t M5PFE:1;
2923                 uint32_t M4PFE:1;
2924                   uint32_t:1;
2925                 uint32_t M2PFE:1;
2926                 uint32_t M1PFE:1;
2927                 uint32_t M0PFE:1;
2928                 uint32_t APC:3;
2929                 uint32_t WWSC:2;
2930                 uint32_t RWSC:3;
2931                   uint32_t:1;
2932                 uint32_t DPFEN:1;
2933                   uint32_t:1;
2934                 uint32_t IPFEN:1;
2935                   uint32_t:1;
2936                 uint32_t PFLIM:2;
2937                 uint32_t BFEN:1;
2938             } B;
2939         } PFCRP1;               /* Platform Flash Configuration Register for Port 1 */
2940
2941         union {
2942             uint32_t R;
2943             struct {
2944                 uint32_t M7AP:2;
2945                 uint32_t M6AP:2;
2946                 uint32_t M5AP:2;
2947                 uint32_t M4AP:2;
2948                 uint32_t M3AP:2;
2949                 uint32_t M2AP:2;
2950                 uint32_t M1AP:2;
2951                 uint32_t M0AP:2;
2952                 uint32_t SHSACC:4;
2953                   uint32_t:4;
2954                 uint32_t SHDACC:4;
2955                   uint32_t:4;
2956             } B;
2957         } PFAPR;                /* Platform Flash access protection Register */
2958
2959         union {
2960             uint32_t R;
2961             struct {
2962                 uint32_t:1;
2963                 uint32_t SACC:31;
2964             } B;
2965         } PFSACC;               /* PFlash Supervisor Access Control Register */
2966
2967         union {
2968             uint32_t R;
2969             struct {
2970                 uint32_t:1;
2971                 uint32_t DACC:31;
2972             } B;
2973         } PFDACC;               /* PFlash Data Access Control Register */
2974
2975         uint32_t FLASH_reserved1[3];
2976
2977         union {
2978             uint32_t R;
2979             struct {
2980                 uint32_t UTE:1;
2981                 uint32_t SCBE:1;
2982                   uint32_t:6;
2983                 uint32_t DSI:8;
2984                   uint32_t:10;
2985                 uint32_t MRE:1;
2986                 uint32_t MRV:1;
2987                 uint32_t EIE:1;
2988                 uint32_t AIS:1;
2989                 uint32_t AIE:1;
2990                 uint32_t AID:1;
2991             } B;
2992         } UT0;                  /* User Test Register 0 */
2993
2994         union {
2995             uint32_t R;
2996             struct {
2997                 uint32_t DAI:32;
2998             } B;
2999         } UT1;                  /* User Test Register 1 */
3000
3001         union {
3002             uint32_t R;
3003             struct {
3004                 uint32_t DAI:32;
3005             } B;
3006         } UT2;                  /* User Test Register 2 */
3007
3008         union {
3009             uint32_t R;
3010             struct {
3011                 uint32_t MISR:32;
3012             } B;
3013         } MISR[5];              /* Multiple Input Signature Register */
3014
3015     };                          /* end of FLASH_tag */
3016 /*************************************************************************/
3017 /*                          MODULE : FlexCAN                             */
3018 /*************************************************************************/
3019     struct FLEXCAN_tag {
3020         union {
3021             uint32_t R;
3022             struct {
3023                 uint32_t MDIS:1;
3024                 uint32_t FRZ:1;
3025                 uint32_t FEN:1;
3026                 uint32_t HALT:1;
3027                 uint32_t NOTRDY:1;
3028                 uint32_t WAKMSK:1;
3029                 uint32_t SOFTRST:1;
3030                 uint32_t FRZACK:1;
3031                 uint32_t SUPV:1;
3032                 uint32_t SLFWAK:1;
3033                 uint32_t WRNEN:1;
3034                 uint32_t LPMACK:1;
3035                 uint32_t WAKSRC:1;
3036                 uint32_t DOZE:1;
3037                 uint32_t SRXDIS:1;
3038                 uint32_t BCC:1;
3039                   uint32_t:2;
3040                 uint32_t LPRIO_EN:1;
3041                 uint32_t AEN:1;
3042                   uint32_t:2;
3043                 uint32_t IDAM:2;
3044                   uint32_t:2;
3045                 uint32_t MAXMB:6;
3046             } B;
3047         } MCR;                  /* Module Configuration Register */
3048
3049         union {
3050             uint32_t R;
3051             struct {
3052                 uint32_t PRESDIV:8;
3053                 uint32_t RJW:2;
3054                 uint32_t PSEG1:3;
3055                 uint32_t PSEG2:3;
3056                 uint32_t BOFFMSK:1;
3057                 uint32_t ERRMSK:1;
3058                 uint32_t CLKSRC:1;
3059                 uint32_t LPB:1;
3060                 uint32_t TWRNMSK:1;
3061                 uint32_t RWRNMSK:1;
3062                   uint32_t:2;
3063                 uint32_t SMP:1;
3064                 uint32_t BOFFREC:1;
3065                 uint32_t TSYN:1;
3066                 uint32_t LBUF:1;
3067                 uint32_t LOM:1;
3068                 uint32_t PROPSEG:3;
3069             } B;
3070         } CTRL;                 /* Control Register */
3071
3072         union {
3073             uint32_t R;
3074         } TIMER;                /* Free Running Timer */
3075
3076         uint32_t FLEXCAN_reserved1;
3077
3078         union {
3079             uint32_t R;
3080             struct {
3081                 uint32_t MI:32;
3082             } B;
3083         } RXGMASK;              /* RX Global Mask */
3084
3085         union {
3086             uint32_t R;
3087             struct {
3088                 uint32_t MI:32;
3089             } B;
3090         } RX14MASK;             /* RX 14 Mask */
3091
3092         union {
3093             uint32_t R;
3094             struct {
3095                 uint32_t MI:32;
3096             } B;
3097         } RX15MASK;             /* RX 15 Mask */
3098
3099         union {
3100             uint32_t R;
3101             struct {
3102                 uint32_t:16;
3103                 uint32_t RXECNT:8;
3104                 uint32_t TXECNT:8;
3105             } B;
3106         } ECR;                  /* Error Counter Register */
3107
3108         union {
3109             uint32_t R;
3110             struct {
3111                 uint32_t:14;
3112                 uint32_t TWRNINT:1;
3113                 uint32_t RWRNINT:1;
3114                 uint32_t BIT1ERR:1;
3115                 uint32_t BIT0ERR:1;
3116                 uint32_t ACKERR:1;
3117                 uint32_t CRCERR:1;
3118                 uint32_t FRMERR:1;
3119                 uint32_t STFERR:1;
3120                 uint32_t TXWRN:1;
3121                 uint32_t RXWRN:1;
3122                 uint32_t IDLE:1;
3123                 uint32_t TXRX:1;
3124                 uint32_t FLTCONF:2;
3125                   uint32_t:1;
3126                 uint32_t BOFFINT:1;
3127                 uint32_t ERRINT:1;
3128                 uint32_t WAKINT:1;
3129             } B;
3130         } ESR;                  /* Error and Status Register */
3131
3132         union {
3133             uint32_t R;
3134             struct {
3135                 uint32_t BUF63M:1;
3136                 uint32_t BUF62M:1;
3137                 uint32_t BUF61M:1;
3138                 uint32_t BUF60M:1;
3139                 uint32_t BUF59M:1;
3140                 uint32_t BUF58M:1;
3141                 uint32_t BUF57M:1;
3142                 uint32_t BUF56M:1;
3143                 uint32_t BUF55M:1;
3144                 uint32_t BUF54M:1;
3145                 uint32_t BUF53M:1;
3146                 uint32_t BUF52M:1;
3147                 uint32_t BUF51M:1;
3148                 uint32_t BUF50M:1;
3149                 uint32_t BUF49M:1;
3150                 uint32_t BUF48M:1;
3151                 uint32_t BUF47M:1;
3152                 uint32_t BUF46M:1;
3153                 uint32_t BUF45M:1;
3154                 uint32_t BUF44M:1;
3155                 uint32_t BUF43M:1;
3156                 uint32_t BUF42M:1;
3157                 uint32_t BUF41M:1;
3158                 uint32_t BUF40M:1;
3159                 uint32_t BUF39M:1;
3160                 uint32_t BUF38M:1;
3161                 uint32_t BUF37M:1;
3162                 uint32_t BUF36M:1;
3163                 uint32_t BUF35M:1;
3164                 uint32_t BUF34M:1;
3165                 uint32_t BUF33M:1;
3166                 uint32_t BUF32M:1;
3167             } B;
3168         } IMASK2;               /* Interruput Masks Register */
3169
3170         union {
3171             uint32_t R;
3172             struct {
3173                 uint32_t BUF31M:1;
3174                 uint32_t BUF30M:1;
3175                 uint32_t BUF29M:1;
3176                 uint32_t BUF28M:1;
3177                 uint32_t BUF27M:1;
3178                 uint32_t BUF26M:1;
3179                 uint32_t BUF25M:1;
3180                 uint32_t BUF24M:1;
3181                 uint32_t BUF23M:1;
3182                 uint32_t BUF22M:1;
3183                 uint32_t BUF21M:1;
3184                 uint32_t BUF20M:1;
3185                 uint32_t BUF19M:1;
3186                 uint32_t BUF18M:1;
3187                 uint32_t BUF17M:1;
3188                 uint32_t BUF16M:1;
3189                 uint32_t BUF15M:1;
3190                 uint32_t BUF14M:1;
3191                 uint32_t BUF13M:1;
3192                 uint32_t BUF12M:1;
3193                 uint32_t BUF11M:1;
3194                 uint32_t BUF10M:1;
3195                 uint32_t BUF09M:1;
3196                 uint32_t BUF08M:1;
3197                 uint32_t BUF07M:1;
3198                 uint32_t BUF06M:1;
3199                 uint32_t BUF05M:1;
3200                 uint32_t BUF04M:1;
3201                 uint32_t BUF03M:1;
3202                 uint32_t BUF02M:1;
3203                 uint32_t BUF01M:1;
3204                 uint32_t BUF00M:1;
3205             } B;
3206         } IMASK1;               /* Interruput Masks Register */
3207
3208         union {
3209             uint32_t R;
3210             struct {
3211                 uint32_t BUF63I:1;
3212                 uint32_t BUF62I:1;
3213                 uint32_t BUF61I:1;
3214                 uint32_t BUF60I:1;
3215                 uint32_t BUF59I:1;
3216                 uint32_t BUF58I:1;
3217                 uint32_t BUF57I:1;
3218                 uint32_t BUF56I:1;
3219                 uint32_t BUF55I:1;
3220                 uint32_t BUF54I:1;
3221                 uint32_t BUF53I:1;
3222                 uint32_t BUF52I:1;
3223                 uint32_t BUF51I:1;
3224                 uint32_t BUF50I:1;
3225                 uint32_t BUF49I:1;
3226                 uint32_t BUF48I:1;
3227                 uint32_t BUF47I:1;
3228                 uint32_t BUF46I:1;
3229                 uint32_t BUF45I:1;
3230                 uint32_t BUF44I:1;
3231                 uint32_t BUF43I:1;
3232                 uint32_t BUF42I:1;
3233                 uint32_t BUF41I:1;
3234                 uint32_t BUF40I:1;
3235                 uint32_t BUF39I:1;
3236                 uint32_t BUF38I:1;
3237                 uint32_t BUF37I:1;
3238                 uint32_t BUF36I:1;
3239                 uint32_t BUF35I:1;
3240                 uint32_t BUF34I:1;
3241                 uint32_t BUF33I:1;
3242                 uint32_t BUF32I:1;
3243             } B;
3244         } IFLAG2;               /* Interruput Flag Register */
3245
3246         union {
3247             uint32_t R;
3248             struct {
3249                 uint32_t BUF31I:1;
3250                 uint32_t BUF30I:1;
3251                 uint32_t BUF29I:1;
3252                 uint32_t BUF28I:1;
3253                 uint32_t BUF27I:1;
3254                 uint32_t BUF26I:1;
3255                 uint32_t BUF25I:1;
3256                 uint32_t BUF24I:1;
3257                 uint32_t BUF23I:1;
3258                 uint32_t BUF22I:1;
3259                 uint32_t BUF21I:1;
3260                 uint32_t BUF20I:1;
3261                 uint32_t BUF19I:1;
3262                 uint32_t BUF18I:1;
3263                 uint32_t BUF17I:1;
3264                 uint32_t BUF16I:1;
3265                 uint32_t BUF15I:1;
3266                 uint32_t BUF14I:1;
3267                 uint32_t BUF13I:1;
3268                 uint32_t BUF12I:1;
3269                 uint32_t BUF11I:1;
3270                 uint32_t BUF10I:1;
3271                 uint32_t BUF09I:1;
3272                 uint32_t BUF08I:1;
3273                 uint32_t BUF07I:1;
3274                 uint32_t BUF06I:1;
3275                 uint32_t BUF05I:1;
3276                 uint32_t BUF04I:1;
3277                 uint32_t BUF03I:1;
3278                 uint32_t BUF02I:1;
3279                 uint32_t BUF01I:1;
3280                 uint32_t BUF00I:1;
3281             } B;
3282         } IFLAG1;               /* Interruput Flag Register */
3283
3284         uint32_t FLEXCAN_reserved2[19];
3285
3286         struct canbuf_t {
3287             union {
3288                 uint32_t R;
3289                 struct {
3290                     uint32_t:4;
3291                     uint32_t CODE:4;
3292                       uint32_t:1;
3293                     uint32_t SRR:1;
3294                     uint32_t IDE:1;
3295                     uint32_t RTR:1;
3296                     uint32_t LENGTH:4;
3297                     uint32_t TIMESTAMP:16;
3298                 } B;
3299             } CS;
3300
3301             union {
3302                 uint32_t R;
3303                 struct {
3304                     uint32_t PRIO:3;
3305                     uint32_t STD_ID:11;
3306                     uint32_t EXT_ID:18;
3307                 } B;
3308             } ID;
3309
3310             union {
3311                 /* uint8_t  B[8];  Data buffer in Bytes (8 bits) */
3312                 /* uint16_t H[4];  Data buffer in Half-words (16 bits) */
3313                 uint32_t W[2]; /* Data buffer in words (32 bits) */
3314                 /* uint32_t R[2];    Data buffer in words (32 bits) */
3315             } DATA;
3316
3317         } BUF[64];
3318
3319         uint32_t FLEXCAN_reserved3[256];
3320
3321         union {
3322             uint32_t R;
3323             struct {
3324                 uint32_t MI:32;
3325             } B;
3326         } RXIMR[64];            /* RX Individual Mask Registers */
3327
3328     };                          /* end of CTU_tag */
3329 /**************************************************************************/
3330 /*                          MODULE : FlexRay                              */
3331 /**************************************************************************/
3332
3333     typedef union uMVR {
3334         uint16_t R;
3335         struct {
3336             uint16_t CHIVER:8; /* CHI Version Number */
3337             uint16_t PEVER:8;  /* PE Version Number */
3338         } B;
3339     } MVR_t;
3340
3341     typedef union uMCR {
3342         uint16_t R;
3343         struct {
3344             uint16_t MEN:1;    /* module enable */
3345               uint16_t:1;
3346             uint16_t SCMD:1;   /* single channel mode */
3347             uint16_t CHB:1;    /* channel B enable */
3348             uint16_t CHA:1;    /* channel A enable */
3349             uint16_t SFFE:1;   /* synchronization frame filter enable */
3350               uint16_t:5;
3351             uint16_t CLKSEL:1; /* protocol engine clock source select */
3352             uint16_t PRESCALE:3;       /* protocol engine clock prescaler */
3353               uint16_t:1;
3354         } B;
3355     } MCR_t;
3356     typedef union uSTBSCR {
3357         uint16_t R;
3358         struct {
3359             uint16_t WMD:1;    /* write mode */
3360             uint16_t STBSSEL:7;        /* strobe signal select */
3361               uint16_t:3;
3362             uint16_t ENB:1;    /* strobe signal enable */
3363               uint16_t:2;
3364             uint16_t STBPSEL:2;        /* strobe port select */
3365         } B;
3366     } STBSCR_t;
3367     typedef union uMBDSR {
3368         uint16_t R;
3369         struct {
3370             uint16_t:1;
3371             uint16_t MBSEG2DS:7;       /* message buffer segment 2 data size */
3372               uint16_t:1;
3373             uint16_t MBSEG1DS:7;       /* message buffer segment 1 data size */
3374         } B;
3375     } MBDSR_t;
3376
3377     typedef union uMBSSUTR {
3378         uint16_t R;
3379         struct {
3380
3381             uint16_t:2;
3382             uint16_t LAST_MB_SEG1:6;   /* last message buffer control register for message buffer segment 1 */
3383               uint16_t:2;
3384             uint16_t LAST_MB_UTIL:6;   /* last message buffer utilized */
3385         } B;
3386     } MBSSUTR_t;
3387
3388     typedef union uPOCR {
3389         uint16_t R;
3390         uint8_t byte[2];
3391         struct {
3392             uint16_t WME:1;    /* write mode external correction command */
3393               uint16_t:3;
3394             uint16_t EOC_AP:2; /* external offset correction application */
3395             uint16_t ERC_AP:2; /* external rate correction application */
3396             uint16_t BSY:1;    /* command write busy / write mode command */
3397               uint16_t:3;
3398             uint16_t POCCMD:4; /* protocol command */
3399         } B;
3400     } POCR_t;
3401 /* protocol commands */
3402     typedef union uGIFER {
3403         uint16_t R;
3404         struct {
3405             uint16_t MIF:1;    /* module interrupt flag */
3406             uint16_t PRIF:1;   /* protocol interrupt flag */
3407             uint16_t CHIF:1;   /* CHI interrupt flag */
3408             uint16_t WKUPIF:1; /* wakeup interrupt flag */
3409             uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
3410             uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
3411             uint16_t RBIF:1;   /* receive message buffer interrupt flag */
3412             uint16_t TBIF:1;   /* transmit buffer interrupt flag */
3413             uint16_t MIE:1;    /* module interrupt enable */
3414             uint16_t PRIE:1;   /* protocol interrupt enable */
3415             uint16_t CHIE:1;   /* CHI interrupt enable */
3416             uint16_t WKUPIE:1; /* wakeup interrupt enable */
3417             uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
3418             uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
3419             uint16_t RBIE:1;   /* receive message buffer interrupt enable */
3420             uint16_t TBIE:1;   /* transmit buffer interrupt enable */
3421         } B;
3422     } GIFER_t;
3423     typedef union uPIFR0 {
3424         uint16_t R;
3425         struct {
3426             uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
3427             uint16_t INTLIF:1; /* internal protocol error interrupt flag */
3428             uint16_t ILCFIF:1; /* illegal protocol configuration flag */
3429             uint16_t CSAIF:1;  /* cold start abort interrupt flag */
3430             uint16_t MRCIF:1;  /* missing rate correctio interrupt flag */
3431             uint16_t MOCIF:1;  /* missing offset correctio interrupt flag */
3432             uint16_t CCLIF:1;  /* clock correction limit reached interrupt flag */
3433             uint16_t MXSIF:1;  /* max sync frames detected interrupt flag */
3434             uint16_t MTXIF:1;  /* media access test symbol received flag */
3435             uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
3436             uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
3437             uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
3438             uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
3439             uint16_t TI2IF:1;  /* timer 2 expired interrupt flag */
3440             uint16_t TI1IF:1;  /* timer 1 expired interrupt flag */
3441             uint16_t CYSIF:1;  /* cycle start interrupt flag */
3442         } B;
3443     } PIFR0_t;
3444     typedef union uPIFR1 {
3445         uint16_t R;
3446         struct {
3447             uint16_t EMCIF:1;  /* error mode changed interrupt flag */
3448             uint16_t IPCIF:1;  /* illegal protocol command interrupt flag */
3449             uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
3450             uint16_t PSCIF:1;  /* Protocol State Changed Interrupt Flag */
3451             uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
3452             uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
3453             uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
3454             uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
3455               uint16_t:2;
3456             uint16_t EVTIF:1;  /* even cycle table written interrupt flag */
3457             uint16_t ODTIF:1;  /* odd cycle table written interrupt flag */
3458               uint16_t:4;
3459         } B;
3460     } PIFR1_t;
3461     typedef union uPIER0 {
3462         uint16_t R;
3463         struct {
3464             uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
3465             uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable  */
3466             uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
3467             uint16_t CSAIE:1;  /* cold start abort interrupt enable */
3468             uint16_t MRCIE:1;  /* missing rate correctio interrupt enable */
3469             uint16_t MOCIE:1;  /* missing offset correctio interrupt enable */
3470             uint16_t CCLIE:1;  /* clock correction limit reached interrupt enable */
3471             uint16_t MXSIE:1;  /* max sync frames detected interrupt enable */
3472             uint16_t MTXIE:1;  /* media access test symbol received interrupt enable */
3473             uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
3474             uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
3475             uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
3476             uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
3477             uint16_t TI2IE:1;  /* timer 2 expired interrupt enable */
3478             uint16_t TI1IE:1;  /* timer 1 expired interrupt enable */
3479             uint16_t CYSIE:1;  /* cycle start interrupt enable */
3480         } B;
3481     } PIER0_t;
3482     typedef union uPIER1 {
3483         uint16_t R;
3484         struct {
3485             uint16_t EMCIE:1;  /* error mode changed interrupt enable */
3486             uint16_t IPCIE:1;  /* illegal protocol command interrupt enable */
3487             uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
3488             uint16_t PSCIE:1;  /* Protocol State Changed Interrupt enable */
3489             uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
3490             uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
3491             uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
3492             uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
3493               uint16_t:2;
3494             uint16_t EVTIE:1;  /* even cycle table written interrupt enable */
3495             uint16_t ODTIE:1;  /* odd cycle table written interrupt enable */
3496               uint16_t:4;
3497         } B;
3498     } PIER1_t;
3499     typedef union uCHIERFR {
3500         uint16_t R;
3501         struct {
3502             uint16_t FRLBEF:1; /* flame lost channel B error flag */
3503             uint16_t FRLAEF:1; /* frame lost channel A error flag */
3504             uint16_t PCMIEF:1; /* command ignored error flag */
3505             uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
3506             uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
3507             uint16_t MSBEF:1;  /* message buffer search error flag */
3508             uint16_t MBUEF:1;  /* message buffer utilization error flag */
3509             uint16_t LCKEF:1;  /* lock error flag */
3510             uint16_t DBLEF:1;  /* double transmit message buffer lock error flag */
3511             uint16_t SBCFEF:1; /* system bus communication failure error flag */
3512             uint16_t FIDEF:1;  /* frame ID error flag */
3513             uint16_t DPLEF:1;  /* dynamic payload length error flag */
3514             uint16_t SPLEF:1;  /* static payload length error flag */
3515             uint16_t NMLEF:1;  /* network management length error flag */
3516             uint16_t NMFEF:1;  /* network management frame error flag */
3517             uint16_t ILSAEF:1; /* illegal access error flag */
3518         } B;
3519     } CHIERFR_t;
3520     typedef union uMBIVEC {
3521         uint16_t R;
3522         struct {
3523
3524             uint16_t:2;
3525             uint16_t TBIVEC:6; /* transmit buffer interrupt vector */
3526               uint16_t:2;
3527             uint16_t RBIVEC:6; /* receive buffer interrupt vector */
3528         } B;
3529     } MBIVEC_t;
3530
3531     typedef union uPSR0 {
3532         uint16_t R;
3533         struct {
3534             uint16_t ERRMODE:2;        /* error mode */
3535             uint16_t SLOTMODE:2;       /* slot mode */
3536               uint16_t:1;
3537             uint16_t PROTSTATE:3;      /* protocol state */
3538             uint16_t SUBSTATE:4;       /* protocol sub state */
3539               uint16_t:1;
3540             uint16_t WAKEUPSTATUS:3;   /* wakeup status */
3541         } B;
3542     } PSR0_t;
3543
3544 /* protocol states */
3545 /* protocol sub-states */
3546 /* wakeup status */
3547     typedef union uPSR1 {
3548         uint16_t R;
3549         struct {
3550             uint16_t CSAA:1;   /* cold start attempt abort flag */
3551             uint16_t SCP:1;    /* cold start path */
3552               uint16_t:1;
3553             uint16_t REMCSAT:5;        /* remanining coldstart attempts */
3554             uint16_t CPN:1;    /* cold start noise path */
3555             uint16_t HHR:1;    /* host halt request pending */
3556             uint16_t FRZ:1;    /* freeze occured */
3557             uint16_t APTAC:5;  /* allow passive to active counter */
3558         } B;
3559     } PSR1_t;
3560     typedef union uPSR2 {
3561         uint16_t R;
3562         struct {
3563             uint16_t NBVB:1;   /* NIT boundary violation on channel B */
3564             uint16_t NSEB:1;   /* NIT syntax error on channel B */
3565             uint16_t STCB:1;   /* symbol window transmit conflict on channel B */
3566             uint16_t SBVB:1;   /* symbol window boundary violation on channel B */
3567             uint16_t SSEB:1;   /* symbol window syntax error on channel B */
3568             uint16_t MTB:1;    /* media access test symbol MTS received on channel B */
3569             uint16_t NBVA:1;   /* NIT boundary violation on channel A */
3570             uint16_t NSEA:1;   /* NIT syntax error on channel A */
3571             uint16_t STCA:1;   /* symbol window transmit conflict on channel A */
3572             uint16_t SBVA:1;   /* symbol window boundary violation on channel A */
3573             uint16_t SSEA:1;   /* symbol window syntax error on channel A */
3574             uint16_t MTA:1;    /* media access test symbol MTS received on channel A */
3575             uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3576         } B;
3577     } PSR2_t;
3578     typedef union uPSR3 {
3579         uint16_t R;
3580         struct {
3581             uint16_t:2;
3582             uint16_t WUB:1;    /* wakeup symbol received on channel B */
3583             uint16_t ABVB:1;   /* aggregated boundary violation on channel B */
3584             uint16_t AACB:1;   /* aggregated additional communication on channel B */
3585             uint16_t ACEB:1;   /* aggregated content error on channel B */
3586             uint16_t ASEB:1;   /* aggregated syntax error on channel B */
3587             uint16_t AVFB:1;   /* aggregated valid frame on channel B */
3588               uint16_t:2;
3589             uint16_t WUA:1;    /* wakeup symbol received on channel A */
3590             uint16_t ABVA:1;   /* aggregated boundary violation on channel A */
3591             uint16_t AACA:1;   /* aggregated additional communication on channel A */
3592             uint16_t ACEA:1;   /* aggregated content error on channel A */
3593             uint16_t ASEA:1;   /* aggregated syntax error on channel A */
3594             uint16_t AVFA:1;   /* aggregated valid frame on channel A */
3595         } B;
3596     } PSR3_t;
3597     typedef union uCIFRR {
3598         uint16_t R;
3599         struct {
3600             uint16_t:8;
3601             uint16_t MIFR:1;   /* module interrupt flag */
3602             uint16_t PRIFR:1;  /* protocol interrupt flag */
3603             uint16_t CHIFR:1;  /* CHI interrupt flag */
3604             uint16_t WUPIFR:1; /* wakeup interrupt flag */
3605             uint16_t FNEBIFR:1;        /* receive fifo channel B no empty interrupt flag */
3606             uint16_t FNEAIFR:1;        /* receive fifo channel A no empty interrupt flag */
3607             uint16_t RBIFR:1;  /* receive message buffer interrupt flag */
3608             uint16_t TBIFR:1;  /* transmit buffer interrupt flag */
3609         } B;
3610     } CIFRR_t;
3611     typedef union uSYMATOR {
3612         uint16_t R;
3613         struct {
3614             uint16_t:11;
3615             uint16_t TIMEOUT:5;        /* system memory time out value */
3616         } B;
3617     } SYMATOR_t;
3618
3619     typedef union uSFCNTR {
3620         uint16_t R;
3621         struct {
3622             uint16_t SFEVB:4;  /* sync frames channel B, even cycle */
3623             uint16_t SFEVA:4;  /* sync frames channel A, even cycle */
3624             uint16_t SFODB:4;  /* sync frames channel B, odd cycle */
3625             uint16_t SFODA:4;  /* sync frames channel A, odd cycle */
3626         } B;
3627     } SFCNTR_t;
3628
3629     typedef union uSFTCCSR {
3630         uint16_t R;
3631         struct {
3632             uint16_t ELKT:1;   /* even cycle tables lock and unlock trigger */
3633             uint16_t OLKT:1;   /* odd cycle tables lock and unlock trigger */
3634             uint16_t CYCNUM:6; /* cycle number */
3635             uint16_t ELKS:1;   /* even cycle tables lock status */
3636             uint16_t OLKS:1;   /* odd cycle tables lock status */
3637             uint16_t EVAL:1;   /* even cycle tables valid */
3638             uint16_t OVAL:1;   /* odd cycle tables valid */
3639               uint16_t:1;
3640             uint16_t OPT:1;    /*one pair trigger */
3641             uint16_t SDVEN:1;  /* sync frame deviation table enable */
3642             uint16_t SIDEN:1;  /* sync frame ID table enable */
3643         } B;
3644     } SFTCCSR_t;
3645     typedef union uSFIDRFR {
3646         uint16_t R;
3647         struct {
3648             uint16_t:6;
3649             uint16_t SYNFRID:10;       /* sync frame rejection ID */
3650         } B;
3651     } SFIDRFR_t;
3652
3653     typedef union uTICCR {
3654         uint16_t R;
3655         struct {
3656             uint16_t:2;
3657             uint16_t T2CFG:1;  /* timer 2 configuration */
3658             uint16_t T2REP:1;  /* timer 2 repetitive mode */
3659               uint16_t:1;
3660             uint16_t T2SP:1;   /* timer 2 stop */
3661             uint16_t T2TR:1;   /* timer 2 trigger */
3662             uint16_t T2ST:1;   /* timer 2 state */
3663               uint16_t:3;
3664             uint16_t T1REP:1;  /* timer 1 repetitive mode */
3665               uint16_t:1;
3666             uint16_t T1SP:1;   /* timer 1 stop */
3667             uint16_t T1TR:1;   /* timer 1 trigger */
3668             uint16_t T1ST:1;   /* timer 1 state */
3669
3670         } B;
3671     } TICCR_t;
3672     typedef union uTI1CYSR {
3673         uint16_t R;
3674         struct {
3675             uint16_t:2;
3676             uint16_t TI1CYCVAL:6;      /* timer 1 cycle filter value */
3677               uint16_t:2;
3678             uint16_t TI1CYCMSK:6;      /* timer 1 cycle filter mask */
3679
3680         } B;
3681     } TI1CYSR_t;
3682
3683     typedef union uSSSR {
3684         uint16_t R;
3685         struct {
3686             uint16_t WMD:1;    /* write mode */
3687               uint16_t:1;
3688             uint16_t SEL:2;    /* static slot number */
3689               uint16_t:1;
3690             uint16_t SLOTNUMBER:11;    /* selector */
3691         } B;
3692     } SSSR_t;
3693
3694     typedef union uSSCCR {
3695         uint16_t R;
3696         struct {
3697             uint16_t WMD:1;    /* write mode */
3698               uint16_t:1;
3699             uint16_t SEL:2;    /* selector */
3700               uint16_t:1;
3701             uint16_t CNTCFG:2; /* counter configuration */
3702             uint16_t MCY:1;    /* multi cycle selection */
3703             uint16_t VFR:1;    /* valid frame selection */
3704             uint16_t SYF:1;    /* sync frame selection */
3705             uint16_t NUF:1;    /* null frame selection  */
3706             uint16_t SUF:1;    /* startup frame selection */
3707             uint16_t STATUSMASK:4;     /* slot status mask */
3708         } B;
3709     } SSCCR_t;
3710     typedef union uSSR {
3711         uint16_t R;
3712         struct {
3713             uint16_t VFB:1;    /* valid frame on channel B */
3714             uint16_t SYB:1;    /* valid sync frame on channel B */
3715             uint16_t NFB:1;    /* valid null frame on channel B */
3716             uint16_t SUB:1;    /* valid startup frame on channel B */
3717             uint16_t SEB:1;    /* syntax error on channel B */
3718             uint16_t CEB:1;    /* content error on channel B */
3719             uint16_t BVB:1;    /* boundary violation on channel B */
3720             uint16_t TCB:1;    /* tx conflict on channel B */
3721             uint16_t VFA:1;    /* valid frame on channel A */
3722             uint16_t SYA:1;    /* valid sync frame on channel A */
3723             uint16_t NFA:1;    /* valid null frame on channel A */
3724             uint16_t SUA:1;    /* valid startup frame on channel A */
3725             uint16_t SEA:1;    /* syntax error on channel A */
3726             uint16_t CEA:1;    /* content error on channel A */
3727             uint16_t BVA:1;    /* boundary violation on channel A */
3728             uint16_t TCA:1;    /* tx conflict on channel A */
3729         } B;
3730     } SSR_t;
3731     typedef union uMTSCFR {
3732         uint16_t R;
3733         struct {
3734             uint16_t MTE:1;    /* media access test symbol transmission enable */
3735               uint16_t:1;
3736             uint16_t CYCCNTMSK:6;      /* cycle counter mask */
3737               uint16_t:2;
3738             uint16_t CYCCNTVAL:6;      /* cycle counter value */
3739         } B;
3740     } MTSCFR_t;
3741
3742     typedef union uRSBIR {
3743         uint16_t R;
3744         struct {
3745             uint16_t WMD:1;    /* write mode */
3746               uint16_t:1;
3747             uint16_t SEL:2;    /* selector */
3748               uint16_t:5;
3749             uint16_t RSBIDX:7; /* receive shadow buffer index */
3750         } B;
3751     } RSBIR_t;
3752
3753     typedef union uRFDSR {
3754         uint16_t R;
3755         struct {
3756             uint16_t FIFODEPTH:8;      /* fifo depth */
3757               uint16_t:1;
3758             uint16_t ENTRYSIZE:7;      /* entry size */
3759         } B;
3760     } RFDSR_t;
3761
3762     typedef union uRFRFCFR {
3763         uint16_t R;
3764         struct {
3765             uint16_t WMD:1;    /* write mode */
3766             uint16_t IBD:1;    /* interval boundary */
3767             uint16_t SEL:2;    /* filter number */
3768               uint16_t:1;
3769             uint16_t SID:11;   /* slot ID */
3770         } B;
3771     } RFRFCFR_t;
3772
3773     typedef union uRFRFCTR {
3774         uint16_t R;
3775         struct {
3776             uint16_t:4;
3777             uint16_t F3MD:1;   /* filter mode */
3778             uint16_t F2MD:1;   /* filter mode */
3779             uint16_t F1MD:1;   /* filter mode */
3780             uint16_t F0MD:1;   /* filter mode */
3781               uint16_t:4;
3782             uint16_t F3EN:1;   /* filter enable */
3783             uint16_t F2EN:1;   /* filter enable */
3784             uint16_t F1EN:1;   /* filter enable */
3785             uint16_t F0EN:1;   /* filter enable */
3786         } B;
3787     } RFRFCTR_t;
3788     typedef union uPCR0 {
3789         uint16_t R;
3790         struct {
3791             uint16_t ACTION_POINT_OFFSET:6;
3792             uint16_t STATIC_SLOT_LENGTH:10;
3793         } B;
3794     } PCR0_t;
3795
3796     typedef union uPCR1 {
3797         uint16_t R;
3798         struct {
3799             uint16_t:2;
3800             uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3801         } B;
3802     } PCR1_t;
3803
3804     typedef union uPCR2 {
3805         uint16_t R;
3806         struct {
3807             uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3808             uint16_t NUMBER_OF_STATIC_SLOTS:10;
3809         } B;
3810     } PCR2_t;
3811
3812     typedef union uPCR3 {
3813         uint16_t R;
3814         struct {
3815             uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3816             uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3817             uint16_t COLDSTART_ATTEMPTS:5;
3818         } B;
3819     } PCR3_t;
3820
3821     typedef union uPCR4 {
3822         uint16_t R;
3823         struct {
3824             uint16_t CAS_RX_LOW_MAX:7;
3825             uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3826         } B;
3827     } PCR4_t;
3828
3829     typedef union uPCR5 {
3830         uint16_t R;
3831         struct {
3832             uint16_t TSS_TRANSMITTER:4;
3833             uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3834             uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3835         } B;
3836     } PCR5_t;
3837
3838     typedef union uPCR6 {
3839         uint16_t R;
3840         struct {
3841             uint16_t:1;
3842             uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3843             uint16_t MACRO_INITIAL_OFFSET_A:7;
3844         } B;
3845     } PCR6_t;
3846
3847     typedef union uPCR7 {
3848         uint16_t R;
3849         struct {
3850             uint16_t DECODING_CORRECTION_B:9;
3851             uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3852         } B;
3853     } PCR7_t;
3854
3855     typedef union uPCR8 {
3856         uint16_t R;
3857         struct {
3858             uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3859             uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3860             uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3861         } B;
3862     } PCR8_t;
3863
3864     typedef union uPCR9 {
3865         uint16_t R;
3866         struct {
3867             uint16_t MINISLOT_EXISTS:1;
3868             uint16_t SYMBOL_WINDOW_EXISTS:1;
3869             uint16_t OFFSET_CORRECTION_OUT:14;
3870         } B;
3871     } PCR9_t;
3872
3873     typedef union uPCR10 {
3874         uint16_t R;
3875         struct {
3876             uint16_t SINGLE_SLOT_ENABLED:1;
3877             uint16_t WAKEUP_CHANNEL:1;
3878             uint16_t MACRO_PER_CYCLE:14;
3879         } B;
3880     } PCR10_t;
3881
3882     typedef union uPCR11 {
3883         uint16_t R;
3884         struct {
3885             uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
3886             uint16_t KEY_SLOT_USED_FOR_SYNC:1;
3887             uint16_t OFFSET_CORRECTION_START:14;
3888         } B;
3889     } PCR11_t;
3890
3891     typedef union uPCR12 {
3892         uint16_t R;
3893         struct {
3894             uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
3895             uint16_t KEY_SLOT_HEADER_CRC:11;
3896         } B;
3897     } PCR12_t;
3898
3899     typedef union uPCR13 {
3900         uint16_t R;
3901         struct {
3902             uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
3903             uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
3904         } B;
3905     } PCR13_t;
3906
3907     typedef union uPCR14 {
3908         uint16_t R;
3909         struct {
3910             uint16_t RATE_CORRECTION_OUT:11;
3911             uint16_t LISTEN_TIMEOUT_H:5;
3912         } B;
3913     } PCR14_t;
3914
3915     typedef union uPCR15 {
3916         uint16_t R;
3917         struct {
3918             uint16_t LISTEN_TIMEOUT_L:16;
3919         } B;
3920     } PCR15_t;
3921
3922     typedef union uPCR16 {
3923         uint16_t R;
3924         struct {
3925             uint16_t MACRO_INITIAL_OFFSET_B:7;
3926             uint16_t NOISE_LISTEN_TIMEOUT_H:9;
3927         } B;
3928     } PCR16_t;
3929
3930     typedef union uPCR17 {
3931         uint16_t R;
3932         struct {
3933             uint16_t NOISE_LISTEN_TIMEOUT_L:16;
3934         } B;
3935     } PCR17_t;
3936
3937     typedef union uPCR18 {
3938         uint16_t R;
3939         struct {
3940             uint16_t WAKEUP_PATTERN:6;
3941             uint16_t KEY_SLOT_ID:10;
3942         } B;
3943     } PCR18_t;
3944
3945     typedef union uPCR19 {
3946         uint16_t R;
3947         struct {
3948             uint16_t DECODING_CORRECTION_A:9;
3949             uint16_t PAYLOAD_LENGTH_STATIC:7;
3950         } B;
3951     } PCR19_t;
3952
3953     typedef union uPCR20 {
3954         uint16_t R;
3955         struct {
3956             uint16_t MICRO_INITIAL_OFFSET_B:8;
3957             uint16_t MICRO_INITIAL_OFFSET_A:8;
3958         } B;
3959     } PCR20_t;
3960
3961     typedef union uPCR21 {
3962         uint16_t R;
3963         struct {
3964             uint16_t EXTERN_RATE_CORRECTION:3;
3965             uint16_t LATEST_TX:13;
3966         } B;
3967     } PCR21_t;
3968
3969     typedef union uPCR22 {
3970         uint16_t R;
3971         struct {
3972             uint16_t:1;
3973             uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
3974             uint16_t MICRO_PER_CYCLE_H:4;
3975         } B;
3976     } PCR22_t;
3977
3978     typedef union uPCR23 {
3979         uint16_t R;
3980         struct {
3981             uint16_t micro_per_cycle_l:16;
3982         } B;
3983     } PCR23_t;
3984
3985     typedef union uPCR24 {
3986         uint16_t R;
3987         struct {
3988             uint16_t CLUSTER_DRIFT_DAMPING:5;
3989             uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
3990             uint16_t MICRO_PER_CYCLE_MIN_H:4;
3991         } B;
3992     } PCR24_t;
3993
3994     typedef union uPCR25 {
3995         uint16_t R;
3996         struct {
3997             uint16_t MICRO_PER_CYCLE_MIN_L:16;
3998         } B;
3999     } PCR25_t;
4000
4001     typedef union uPCR26 {
4002         uint16_t R;
4003         struct {
4004             uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
4005             uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
4006             uint16_t MICRO_PER_CYCLE_MAX_H:4;
4007         } B;
4008     } PCR26_t;
4009
4010     typedef union uPCR27 {
4011         uint16_t R;
4012         struct {
4013             uint16_t MICRO_PER_CYCLE_MAX_L:16;
4014         } B;
4015     } PCR27_t;
4016
4017     typedef union uPCR28 {
4018         uint16_t R;
4019         struct {
4020             uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
4021             uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
4022         } B;
4023     } PCR28_t;
4024
4025     typedef union uPCR29 {
4026         uint16_t R;
4027         struct {
4028             uint16_t EXTERN_OFFSET_CORRECTION:3;
4029             uint16_t MINISLOTS_MAX:13;
4030         } B;
4031     } PCR29_t;
4032
4033     typedef union uPCR30 {
4034         uint16_t R;
4035         struct {
4036             uint16_t:12;
4037             uint16_t SYNC_NODE_MAX:4;
4038         } B;
4039     } PCR30_t;
4040
4041     typedef struct uMSG_BUFF_CCS {
4042         union {
4043             uint16_t R;
4044             struct {
4045                 uint16_t:1;
4046                 uint16_t MCM:1;        /* message buffer commit mode */
4047                 uint16_t MBT:1;        /* message buffer type */
4048                 uint16_t MTD:1;        /* message buffer direction */
4049                 uint16_t CMT:1;        /* commit for transmission */
4050                 uint16_t EDT:1;        /* enable / disable trigger */
4051                 uint16_t LCKT:1;       /* lock request trigger */
4052                 uint16_t MBIE:1;       /* message buffer interrupt enable */
4053                   uint16_t:3;
4054                 uint16_t DUP:1;        /* data updated  */
4055                 uint16_t DVAL:1;       /* data valid */
4056                 uint16_t EDS:1;        /* lock status */
4057                 uint16_t LCKS:1;       /* enable / disable status */
4058                 uint16_t MBIF:1;       /* message buffer interrupt flag */
4059             } B;
4060         } MBCCSR;
4061         union {
4062             uint16_t R;
4063             struct {
4064                 uint16_t MTM:1;        /* message buffer transmission mode */
4065                 uint16_t CHNLA:1;      /* channel assignement */
4066                 uint16_t CHNLB:1;      /* channel assignement */
4067                 uint16_t CCFE:1;       /* cycle counter filter enable */
4068                 uint16_t CCFMSK:6;     /* cycle counter filter mask */
4069                 uint16_t CCFVAL:6;     /* cycle counter filter value */
4070             } B;
4071         } MBCCFR;
4072         union {
4073             uint16_t R;
4074             struct {
4075                 uint16_t:5;
4076                 uint16_t FID:11;       /* frame ID */
4077             } B;
4078         } MBFIDR;
4079
4080         union {
4081             uint16_t R;
4082             struct {
4083                 uint16_t:9;
4084                 uint16_t MBIDX:7;      /* message buffer index */
4085             } B;
4086         } MBIDXR;
4087     } MSG_BUFF_CCS_t;
4088     typedef union uSYSBADHR {
4089         uint16_t R;
4090     } SYSBADHR_t;
4091     typedef union uSYSBADLR {
4092         uint16_t R;
4093     } SYSBADLR_t;
4094     typedef union uPADR {
4095         uint16_t R;
4096     } PADR_t;
4097     typedef union uPDAR {
4098         uint16_t R;
4099     } PDAR_t;
4100     typedef union uCASERCR {
4101         uint16_t R;
4102     } CASERCR_t;
4103     typedef union uCBSERCR {
4104         uint16_t R;
4105     } CBSERCR_t;
4106     typedef union uCYCTR {
4107         uint16_t R;
4108     } CYCTR_t;
4109     typedef union uMTCTR {
4110         uint16_t R;
4111     } MTCTR_t;
4112     typedef union uSLTCTAR {
4113         uint16_t R;
4114     } SLTCTAR_t;
4115     typedef union uSLTCTBR {
4116         uint16_t R;
4117     } SLTCTBR_t;
4118     typedef union uRTCORVR {
4119         uint16_t R;
4120     } RTCORVR_t;
4121     typedef union uOFCORVR {
4122         uint16_t R;
4123     } OFCORVR_t;
4124     typedef union uSFTOR {
4125         uint16_t R;
4126     } SFTOR_t;
4127     typedef union uSFIDAFVR {
4128         uint16_t R;
4129     } SFIDAFVR_t;
4130     typedef union uSFIDAFMR {
4131         uint16_t R;
4132     } SFIDAFMR_t;
4133     typedef union uNMVR {
4134         uint16_t R;
4135     } NMVR_t;
4136     typedef union uNMVLR {
4137         uint16_t R;
4138     } NMVLR_t;
4139     typedef union uT1MTOR {
4140         uint16_t R;
4141     } T1MTOR_t;
4142     typedef union uTI2CR0 {
4143         uint16_t R;
4144     } TI2CR0_t;
4145     typedef union uTI2CR1 {
4146         uint16_t R;
4147     } TI2CR1_t;
4148     typedef union uSSCR {
4149         uint16_t R;
4150     } SSCR_t;
4151     typedef union uRFSR {
4152         uint16_t R;
4153     } RFSR_t;
4154     typedef union uRFSIR {
4155         uint16_t R;
4156     } RFSIR_t;
4157     typedef union uRFARIR {
4158         uint16_t R;
4159     } RFARIR_t;
4160     typedef union uRFBRIR {
4161         uint16_t R;
4162     } RFBRIR_t;
4163     typedef union uRFMIDAFVR {
4164         uint16_t R;
4165     } RFMIDAFVR_t;
4166     typedef union uRFMIAFMR {
4167         uint16_t R;
4168     } RFMIAFMR_t;
4169     typedef union uRFFIDRFVR {
4170         uint16_t R;
4171     } RFFIDRFVR_t;
4172     typedef union uRFFIDRFMR {
4173         uint16_t R;
4174     } RFFIDRFMR_t;
4175     typedef union uLDTXSLAR {
4176         uint16_t R;
4177     } LDTXSLAR_t;
4178     typedef union uLDTXSLBR {
4179         uint16_t R;
4180     } LDTXSLBR_t;
4181
4182     typedef struct FR_tag {
4183         volatile MVR_t MVR;     /*module version register *//*0  */
4184         volatile MCR_t MCR;     /*module configuration register *//*2  */
4185         volatile SYSBADHR_t SYSBADHR;   /*system memory base address high register *//*4        */
4186         volatile SYSBADLR_t SYSBADLR;   /*system memory base address low register *//*6         */
4187         volatile STBSCR_t STBSCR;       /*strobe signal control register *//*8      */
4188         uint16_t reserved0[1]; /*A    */
4189         volatile MBDSR_t MBDSR; /*message buffer data size register *//*C  */
4190         volatile MBSSUTR_t MBSSUTR;     /*message buffer segment size and utilization register *//*E  */
4191         uint16_t reserved1[1]; /*10 */
4192         uint16_t reserved2[1]; /*12 */
4193         volatile POCR_t POCR;   /*Protocol operation control register *//*14 */
4194         volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
4195         volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
4196         volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
4197         volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
4198         volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
4199         volatile CHIERFR_t CHIERFR;     /*CHI error flag register *//*20 */
4200         volatile MBIVEC_t MBIVEC;       /*message buffer interrupt vector register *//*22 */
4201         volatile CASERCR_t CASERCR;     /*channel A status error counter register *//*24 */
4202         volatile CBSERCR_t CBSERCR;     /*channel B status error counter register *//*26 */
4203         volatile PSR0_t PSR0;   /*protocol status register 0 *//*28 */
4204         volatile PSR1_t PSR1;   /*protocol status register 1 *//*2A */
4205         volatile PSR2_t PSR2;   /*protocol status register 2 *//*2C */
4206         volatile PSR3_t PSR3;   /*protocol status register 3 *//*2E */
4207         volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
4208         volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
4209         volatile SLTCTAR_t SLTCTAR;     /*slot counter channel A register *//*34 */
4210         volatile SLTCTBR_t SLTCTBR;     /*slot counter channel B register *//*36 */
4211         volatile RTCORVR_t RTCORVR;     /*rate correction value register *//*38 */
4212         volatile OFCORVR_t OFCORVR;     /*offset correction value register *//*3A */
4213         volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
4214         volatile SYMATOR_t SYMATOR;     /*system memory acess time-out register *//*3E */
4215         volatile SFCNTR_t SFCNTR;       /*sync frame counter register *//*40 */
4216         volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
4217         volatile SFTCCSR_t SFTCCSR;     /*sync frame table configuration, control, status register *//*44 */
4218         volatile SFIDRFR_t SFIDRFR;     /*sync frame ID rejection filter register *//*46 */
4219         volatile SFIDAFVR_t SFIDAFVR;   /*sync frame ID acceptance filter value regiater *//*48 */
4220         volatile SFIDAFMR_t SFIDAFMR;   /*sync frame ID acceptance filter mask register *//*4A */
4221         volatile NMVR_t NMVR[6];        /*network management vector registers (12 bytes) *//*4C */
4222         volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
4223         volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
4224         volatile TI1CYSR_t TI1CYSR;     /*timer 1 cycle set register *//*5C */
4225         volatile T1MTOR_t T1MTOR;       /*timer 1 macrotick offset register *//*5E */
4226         volatile TI2CR0_t TI2CR0;       /*timer 2 configuration register 0 *//*60 */
4227         volatile TI2CR1_t TI2CR1;       /*timer 2 configuration register 1 *//*62 */
4228         volatile SSSR_t SSSR;   /*slot status selection register *//*64 */
4229         volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
4230         volatile SSR_t SSR[8];  /*slot status registers 0-7 *//*68 */
4231         volatile SSCR_t SSCR[4];        /*slot status counter registers 0-3 *//*78 */
4232         volatile MTSCFR_t MTSACFR;      /*mts a config register *//*80 */
4233         volatile MTSCFR_t MTSBCFR;      /*mts b config register *//*82 */
4234         volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
4235         volatile RFSR_t RFSR;   /*receive fifo selection register *//*86 */
4236         volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
4237         volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
4238         volatile RFARIR_t RFARIR;       /*receive fifo a read index register *//*8C */
4239         volatile RFBRIR_t RFBRIR;       /*receive fifo b read index register *//*8E */
4240         volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
4241         volatile RFMIAFMR_t RFMIAFMR;   /*receive fifo message ID acceptance filter mask register *//*92 */
4242         volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
4243         volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
4244         volatile RFRFCFR_t RFRFCFR;     /*receive fifo range filter configuration register *//*98 */
4245         volatile RFRFCTR_t RFRFCTR;     /*receive fifo range filter control register *//*9A */
4246         volatile LDTXSLAR_t LDTXSLAR;   /*last dynamic transmit slot channel A register *//*9C */
4247         volatile LDTXSLBR_t LDTXSLBR;   /*last dynamic transmit slot channel B register *//*9E */
4248         volatile PCR0_t PCR0;   /*protocol configuration register 0 *//*A0 */
4249         volatile PCR1_t PCR1;   /*protocol configuration register 1 *//*A2 */
4250         volatile PCR2_t PCR2;   /*protocol configuration register 2 *//*A4 */
4251         volatile PCR3_t PCR3;   /*protocol configuration register 3 *//*A6 */
4252         volatile PCR4_t PCR4;   /*protocol configuration register 4 *//*A8 */
4253         volatile PCR5_t PCR5;   /*protocol configuration register 5 *//*AA */
4254         volatile PCR6_t PCR6;   /*protocol configuration register 6 *//*AC */
4255         volatile PCR7_t PCR7;   /*protocol configuration register 7 *//*AE */
4256         volatile PCR8_t PCR8;   /*protocol configuration register 8 *//*B0 */
4257         volatile PCR9_t PCR9;   /*protocol configuration register 9 *//*B2 */
4258         volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
4259         volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
4260         volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
4261         volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
4262         volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
4263         volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
4264         volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
4265         volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
4266         volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
4267         volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
4268         volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
4269         volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
4270         volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
4271         volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
4272         volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
4273         volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
4274         volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
4275         volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
4276         volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
4277         volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
4278         volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
4279         uint16_t reserved3[17];
4280         volatile MSG_BUFF_CCS_t MBCCS[128];     /* message buffer configuration, control & status registers 0-31 *//*100 */
4281     } FR_tag_t;
4282
4283     typedef union uF_HEADER     /* frame header */
4284     {
4285         struct {
4286             uint16_t:5;
4287             uint16_t HDCRC:11; /* Header CRC */
4288               uint16_t:2;
4289             uint16_t CYCCNT:6; /* Cycle Count */
4290               uint16_t:1;
4291             uint16_t PLDLEN:7; /* Payload Length */
4292               uint16_t:1;
4293             uint16_t PPI:1;    /* Payload Preamble Indicator */
4294             uint16_t NUF:1;    /* Null Frame Indicator */
4295             uint16_t SYF:1;    /* Sync Frame Indicator */
4296             uint16_t SUF:1;    /* Startup Frame Indicator */
4297             uint16_t FID:11;   /* Frame ID */
4298         } B;
4299         uint16_t WORDS[3];
4300     } F_HEADER_t;
4301     typedef union uS_STSTUS     /* slot status */
4302     {
4303         struct {
4304             uint16_t VFB:1;    /* Valid Frame on channel B */
4305             uint16_t SYB:1;    /* Sync Frame Indicator channel B */
4306             uint16_t NFB:1;    /* Null Frame Indicator channel B */
4307             uint16_t SUB:1;    /* Startup Frame Indicator channel B */
4308             uint16_t SEB:1;    /* Syntax Error on channel B */
4309             uint16_t CEB:1;    /* Content Error on channel B */
4310             uint16_t BVB:1;    /* Boundary Violation on channel B */
4311             uint16_t CH:1;     /* Channel */
4312             uint16_t VFA:1;    /* Valid Frame on channel A */
4313             uint16_t SYA:1;    /* Sync Frame Indicator channel A */
4314             uint16_t NFA:1;    /* Null Frame Indicator channel A */
4315             uint16_t SUA:1;    /* Startup Frame Indicator channel A */
4316             uint16_t SEA:1;    /* Syntax Error on channel A */
4317             uint16_t CEA:1;    /* Content Error on channel A */
4318             uint16_t BVA:1;    /* Boundary Violation on channel A */
4319               uint16_t:1;
4320         } RX;
4321         struct {
4322             uint16_t VFB:1;    /* Valid Frame on channel B */
4323             uint16_t SYB:1;    /* Sync Frame Indicator channel B */
4324             uint16_t NFB:1;    /* Null Frame Indicator channel B */
4325             uint16_t SUB:1;    /* Startup Frame Indicator channel B */
4326             uint16_t SEB:1;    /* Syntax Error on channel B */
4327             uint16_t CEB:1;    /* Content Error on channel B */
4328             uint16_t BVB:1;    /* Boundary Violation on channel B */
4329             uint16_t TCB:1;    /* Tx Conflict on channel B */
4330             uint16_t VFA:1;    /* Valid Frame on channel A */
4331             uint16_t SYA:1;    /* Sync Frame Indicator channel A */
4332             uint16_t NFA:1;    /* Null Frame Indicator channel A */
4333             uint16_t SUA:1;    /* Startup Frame Indicator channel A */
4334             uint16_t SEA:1;    /* Syntax Error on channel A */
4335             uint16_t CEA:1;    /* Content Error on channel A */
4336             uint16_t BVA:1;    /* Boundary Violation on channel A */
4337             uint16_t TCA:1;    /* Tx Conflict on channel A */
4338         } TX;
4339         uint16_t R;
4340     } S_STATUS_t;
4341
4342     typedef struct uMB_HEADER   /* message buffer header */
4343     {
4344         F_HEADER_t FRAME_HEADER;
4345         uint16_t DATA_OFFSET;
4346         S_STATUS_t SLOT_STATUS;
4347     } MB_HEADER_t;
4348 /**************************************************************************/
4349 /*                     MODULE : FMPLL                                     */
4350 /**************************************************************************/
4351     struct FMPLL_tag {
4352
4353         uint32_t FMPLL_reserved0;
4354
4355         union FMPLL_SYNSR_tag { /* Synthesiser Status Register */
4356             uint32_t R;
4357             struct {
4358                 uint32_t:22;
4359                 uint32_t LOLF:1;
4360                 uint32_t LOC:1;
4361                 uint32_t MODE:1;
4362                 uint32_t PLLSEL:1;
4363                 uint32_t PLLREF:1;
4364                 uint32_t LOCKS:1;
4365                 uint32_t LOCK:1;
4366                 uint32_t LOCF:1;
4367                 uint32_t CALDONE:1;
4368                 uint32_t CALPASS:1;
4369             } B;
4370         } SYNSR;
4371
4372         union FMPLL_ESYNCR1_tag {
4373             uint32_t R;
4374             struct {
4375                 uint32_t:1;
4376                 uint32_t CLKCFG:3;
4377                   uint32_t:8;
4378                 uint32_t EPREDIV:4;
4379                   uint32_t:8;
4380                 uint32_t EMFD:8;
4381             } B;
4382         } ESYNCR1;
4383
4384         union FMPLL_ESYNCR2_tag {
4385             uint32_t R;
4386             struct {
4387                 uint32_t:8;
4388                 uint32_t LOCEN:1;
4389                 uint32_t LOLRE:1;
4390                 uint32_t LOCRE:1;
4391                 uint32_t LOLIRQ:1;
4392                 uint32_t LOCIRQ:1;
4393                   uint32_t:1;
4394                 uint32_t ERATE:2;
4395                   uint32_t:5;
4396                 uint32_t EDEPTH:3;
4397                   uint32_t:2;
4398                 uint32_t ERFD:6;
4399             } B;
4400         } ESYNCR2;
4401
4402     };
4403 /*************************************************************************/
4404 /*                          MODULE : i2c                                 */
4405 /*************************************************************************/
4406     struct I2C_tag {
4407         union {
4408             uint8_t R;
4409             struct {
4410                 uint8_t AD:7;
4411                   uint8_t:1;
4412             } B;
4413         } IBAD;                 /* Module Bus Address Register */
4414
4415         union {
4416             uint8_t R;
4417             struct {
4418                 uint8_t MULT:2;
4419                 uint8_t ICR:6;
4420             } B;
4421         } IBFD;                 /* Module Bus Frequency Register */
4422
4423         union {
4424             uint8_t R;
4425             struct {
4426                 uint8_t MDIS:1;
4427                 uint8_t IBIE:1;
4428                 uint8_t MS:1;
4429                 uint8_t TX:1;
4430                 uint8_t NOACK:1;
4431                 uint8_t RSTA:1;
4432                 uint8_t DMAEN:1;
4433                   uint8_t:1;
4434             } B;
4435         } IBCR;                 /* Module Bus Control Register */
4436
4437         union {
4438             uint8_t R;
4439             struct {
4440                 uint8_t TCF:1;
4441                 uint8_t IAAS:1;
4442                 uint8_t IBB:1;
4443                 uint8_t IBAL:1;
4444                   uint8_t:1;
4445                 uint8_t SRW:1;
4446                 uint8_t IBIF:1;
4447                 uint8_t RXAK:1;
4448             } B;
4449         } IBSR;                 /* Module Status Register */
4450
4451         union {
4452             uint8_t R;
4453             struct {
4454                 uint8_t DATA:8;
4455             } B;
4456         } IBDR;                 /* Module Data Register */
4457
4458         union {
4459             uint8_t R;
4460             struct {
4461                 uint8_t BIIE:1;
4462                   uint8_t:7;
4463             } B;
4464         } IBIC;                 /* Module Interrupt Configuration Register */
4465
4466     };                          /* end of i2c_tag */
4467 /*************************************************************************/
4468 /*                          MODULE : INTC                                */
4469 /*************************************************************************/
4470     struct INTC_tag {
4471         union {
4472             uint32_t R;
4473             struct {
4474                 uint32_t:18;
4475                 uint32_t VTES_PRC1:1;
4476                   uint32_t:4;
4477                 uint32_t HVEN_PRC1:1;
4478                   uint32_t:2;
4479                 uint32_t VTES:1;
4480                   uint32_t:4;
4481                 uint32_t HVEN:1;
4482             } B;
4483         } MCR;                  /* Module Configuration Register */
4484
4485         int32_t INTC_reserved1;
4486
4487         union {
4488             uint32_t R;
4489             struct {
4490                 uint32_t:28;
4491                 uint32_t PRI:4;
4492             } B;
4493         } CPR;                  /* Processor 0 (Z6) Current Priority Register */
4494
4495         union {
4496             uint32_t R;
4497             struct {
4498                 uint32_t:28;
4499                 uint32_t PRI:4;
4500             } B;
4501         } CPR_PRC1;             /* Processor 1 (Z0) Current Priority Register */
4502
4503         union {
4504             uint32_t R;
4505             struct {
4506                 uint32_t VTBA:21;
4507                 uint32_t INTVEC:9;
4508                   uint32_t:2;
4509             } B;
4510         } IACKR;                /* Processor 0 (Z6) Interrupt Acknowledge Register */
4511
4512         union {
4513             uint32_t R;
4514             struct {
4515                 uint32_t VTBA_PRC1:21;
4516                 uint32_t INTVEC_PRC1:9;
4517                   uint32_t:2;
4518             } B;
4519         } IACKR_PRC1;           /* Processor 1 (Z0) Interrupt Acknowledge Register */
4520
4521         union {
4522             uint32_t R;
4523             struct {
4524                 uint32_t:32;
4525             } B;
4526         } EOIR;                 /* Processor 0 End of Interrupt Register */
4527
4528         union {
4529             uint32_t R;
4530             struct {
4531                 uint32_t:32;
4532             } B;
4533         } EOIR_PRC1;            /* Processor 1 End of Interrupt Register */
4534
4535         union {
4536             uint8_t R;
4537             struct {
4538                 uint8_t:6;
4539                 uint8_t SET:1;
4540                 uint8_t CLR:1;
4541             } B;
4542         } SSCIR[8];             /* Software Set/Clear Interruput Register */
4543
4544         uint32_t intc_reserved2[6];
4545
4546         union {
4547             uint8_t R;
4548             struct {
4549                 uint8_t PRC_SEL:2;
4550                   uint8_t:2;
4551                 uint8_t PRI:4;
4552             } B;
4553         } PSR[316];             /* Software Set/Clear Interrupt Register */
4554
4555     };                          /* end of INTC_tag */
4556 /*************************************************************************/
4557 /*                           MODULE : MLB                                */
4558 /*************************************************************************/
4559     struct MLB_tag {
4560
4561         union {
4562             uint32_t R;
4563             struct {
4564                 uint32_t MDE:1;
4565                 uint32_t LBM:1;
4566                 uint32_t MCS:2;
4567                   uint32_t:1;
4568                 uint32_t MLK:1;
4569                 uint32_t MLE:1;
4570                 uint32_t MHRE:1;
4571                 uint32_t MRS:1;
4572                   uint32_t:15;
4573                 uint32_t MDA:8;
4574             } B;
4575         } DCCR;                 /* Device Control Configuration Register */
4576
4577         union {
4578             uint32_t R;
4579             struct {
4580                 uint32_t:24;
4581                 uint32_t SSRE:1;
4582                 uint32_t SDMU:1;
4583                 uint32_t SDML:1;
4584                 uint32_t SDSC:1;
4585                 uint32_t SDCS:1;
4586                 uint32_t SDNU:1;
4587                 uint32_t SDNL:1;
4588                 uint32_t SDR:1;
4589             } B;
4590         } SSCR;                 /* MLB Blank Register */
4591
4592         union {
4593             uint32_t R;
4594             struct {
4595                 uint32_t MSD:32;
4596             } B;
4597         } SDCR;                 /* MLB Status Register */
4598
4599         union {
4600             uint32_t R;
4601             struct {
4602                 uint32_t:25;
4603                 uint32_t SMMU:1;
4604                 uint32_t SMML:1;
4605                 uint32_t SMSC:1;
4606                 uint32_t SMCS:1;
4607                 uint32_t SMNU:1;
4608                 uint32_t SMNL:1;
4609                 uint32_t SMR:1;
4610             } B;
4611         } SMCR;                 /* RX Control Channel Address Register */
4612
4613         uint32_t MLB_reserved1[3];
4614
4615         union {
4616             uint32_t R;
4617             struct {
4618                 uint32_t UMA:8;
4619                 uint32_t UMI:8;
4620                 uint32_t MMA:8;
4621                 uint32_t MMI:8;
4622             } B;
4623         } VCCR;                 /* Version Control Configuration Register */
4624
4625         union {
4626             uint32_t R;
4627             struct {
4628                 uint32_t SRBA:16;
4629                 uint32_t STBA:16;
4630             } B;
4631         } SBCR;                 /* Sync Base Address Config Register */
4632
4633         union {
4634             uint32_t R;
4635             struct {
4636                 uint32_t ARBA:16;
4637                 uint32_t ATBA:16;
4638             } B;
4639         } ABCR;                 /* Async Base Address Channel Config Register */
4640
4641         union {
4642             uint32_t R;
4643             struct {
4644                 uint32_t CRBA:16;
4645                 uint32_t CTBA:16;
4646             } B;
4647         } CBCR;                 /* Control Base Address Config Register */
4648
4649         union {
4650             uint32_t R;
4651             struct {
4652                 uint32_t IRBA:16;
4653                 uint32_t ITBA:16;
4654             } B;
4655         } IBCR;                 /* Isochronous Base Address Config Register */
4656
4657         union {
4658             uint32_t R;
4659             struct {
4660                 uint32_t:16;
4661                 uint32_t CSU:16;
4662             } B;
4663         } CICR;                 /* Channel Interrupt Config Register */
4664
4665         uint32_t MLB_reserved2[3];
4666
4667         struct mlbch_t {
4668
4669             union {
4670                 uint32_t R;
4671                 struct {
4672                     uint32_t CE:1;
4673                     uint32_t TR:1;
4674                     uint32_t CT:2;
4675                     uint32_t FSE_FCE:1;
4676                     uint32_t MDS:2;
4677                       uint32_t:2;
4678                     uint32_t MLFS:1;
4679                       uint32_t:1;
4680                     uint32_t MBE:1;
4681                     uint32_t MBS:1;
4682                     uint32_t MBD:1;
4683                     uint32_t MDB:1;
4684                     uint32_t MPE:1;
4685                     uint32_t FSCD_IPL:1;
4686                     uint32_t IPL:2;
4687                     uint32_t FSPC_IPL:5;
4688                     uint32_t CA:8;
4689                 } B;
4690             } CECR;             /* Channel Entry Config Register */
4691
4692             union {
4693                 uint32_t R;
4694                 struct {
4695                     uint32_t BM:1;
4696                     uint32_t BF:1;
4697                       uint32_t:10;
4698                     uint32_t IVB:2;
4699                     uint32_t GIRB_GB:1;
4700                     uint32_t RDY:1;
4701                       uint32_t:4;
4702                     uint32_t PBS:1;
4703                     uint32_t PBD:1;
4704                     uint32_t PBDB:1;
4705                     uint32_t PBPE:1;
4706                       uint32_t:1;
4707                     uint32_t LFS:1;
4708                     uint32_t HBE:1;
4709                     uint32_t BE:1;
4710                     uint32_t CBS:1;
4711                     uint32_t CBD:1;
4712                     uint32_t CBDB:1;
4713                     uint32_t CBPE:1;
4714                 } B;
4715             } CSCR;             /* Channel Status Config Register */
4716
4717             union {
4718                 uint32_t R;
4719                 struct {
4720                     uint32_t BCA:16;
4721                     uint32_t BFA:16;
4722                 } B;
4723             } CCBCR;            /* Channel Current Buffer Config Register */
4724
4725             union {
4726                 uint32_t R;
4727                 struct {
4728                     uint32_t BSA:16;
4729                     uint32_t BEA:16;
4730                 } B;
4731             } CNBCR;            /* Channel Next Buffer Config Register */
4732
4733         } CH[16];
4734
4735         uint32_t MLB_reserved3[80];
4736
4737         union {
4738             uint32_t R;
4739             struct {
4740                 uint32_t BSA:16;
4741                 uint32_t BEA:16;
4742             } B;
4743         } LCBCR[16];            /* Local Channel Buffer Config Register */
4744
4745     };                          /* end of MLB_tag */
4746 /*************************************************************************/
4747 /*                          MODULE : MPU                                 */
4748 /*************************************************************************/
4749     struct MPU_tag {
4750         union {
4751             uint32_t R;
4752             struct {
4753                 uint32_t MPERR:8;
4754                   uint32_t:4;
4755                 uint32_t HRL:4;
4756                 uint32_t NSP:4;
4757                 uint32_t NGRD:4;
4758                   uint32_t:7;
4759                 uint32_t VLD:1;
4760             } B;
4761         } CESR;                 /* Module Control/Error Status Register */
4762
4763         uint32_t mpu_reserved1[3];
4764
4765         union {
4766             uint32_t R;
4767             struct {
4768                 uint32_t EADDR:32;
4769             } B;
4770         } EAR0;                 /* Error Address Register */
4771
4772         union {
4773             uint32_t R;
4774             struct {
4775                 uint32_t EACD:16;
4776                 uint32_t EPID:8;
4777                 uint32_t EMN:4;
4778                 uint32_t EATTR:3;
4779                 uint32_t ERW:1;
4780             } B;
4781         } EDR0;                 /* Error Detail Register */
4782
4783         union {
4784             uint32_t R;
4785             struct {
4786                 uint32_t EADDR:32;
4787             } B;
4788         } EAR1;
4789
4790         union {
4791             uint32_t R;
4792             struct {
4793                 uint32_t EACD:16;
4794                 uint32_t EPID:8;
4795                 uint32_t EMN:4;
4796                 uint32_t EATTR:3;
4797                 uint32_t ERW:1;
4798             } B;
4799         } EDR1;
4800
4801         union {
4802             uint32_t R;
4803             struct {
4804                 uint32_t EADDR:32;
4805             } B;
4806         } EAR2;
4807
4808         union {
4809             uint32_t R;
4810             struct {
4811                 uint32_t EACD:16;
4812                 uint32_t EPID:8;
4813                 uint32_t EMN:4;
4814                 uint32_t EATTR:3;
4815                 uint32_t ERW:1;
4816             } B;
4817         } EDR3;
4818
4819         union {
4820             uint32_t R;
4821             struct {
4822                 uint32_t EADDR:32;
4823             } B;
4824         } EAR3;
4825
4826         union {
4827             uint32_t R;
4828             struct {
4829                 uint32_t EACD:16;
4830                 uint32_t EPID:8;
4831                 uint32_t EMN:4;
4832                 uint32_t EATTR:3;
4833                 uint32_t ERW:1;
4834             } B;
4835         } EDR2;
4836
4837         uint32_t mpu_reserved2[244];
4838
4839         struct {
4840             union {
4841                 uint32_t R;
4842                 struct {
4843                     uint32_t SRTADDR:27;
4844                       uint32_t:5;
4845                 } B;
4846             } WORD0;            /* Region Descriptor n Word 0 */
4847
4848             union {
4849                 uint32_t R;
4850                 struct {
4851                     uint32_t ENDADDR:27;
4852                       uint32_t:5;
4853                 } B;
4854             } WORD1;            /* Region Descriptor n Word 1 */
4855
4856             union {
4857                 uint32_t R;
4858                 struct {
4859                     uint32_t:2;
4860                     uint32_t M6RE:1;
4861                     uint32_t M6WE:1;
4862                     uint32_t M5RE:1;
4863                     uint32_t M5WE:1;
4864                     uint32_t M4RE:1;
4865                     uint32_t M4WE:1;
4866                       uint32_t:6;
4867                     uint32_t M2PE:1;
4868                     uint32_t M2SM:2;
4869                     uint32_t M2UM:3;
4870                     uint32_t M1PE:1;
4871                     uint32_t M1SM:2;
4872                     uint32_t M1UM:3;
4873                     uint32_t M0PE:1;
4874                     uint32_t M0SM:2;
4875                     uint32_t M0UM:3;
4876                 } B;
4877             } WORD2;            /* Region Descriptor n Word 2 */
4878
4879             union {
4880                 uint32_t R;
4881                 struct {
4882                     uint32_t PID:8;
4883                     uint32_t PIDMASK:8;
4884                       uint32_t:15;
4885                     uint32_t VLD:1;
4886                 } B;
4887             } WORD3;            /* Region Descriptor n Word 3 */
4888
4889         } RGD[16];
4890
4891         uint32_t mpu_reserved3[192];
4892
4893         union {
4894             uint32_t R;
4895             struct {
4896                 uint32_t:2;
4897                 uint32_t M6RE:1;
4898                 uint32_t M6WE:1;
4899                 uint32_t M5RE:1;
4900                 uint32_t M5WE:1;
4901                 uint32_t M4RE:1;
4902                 uint32_t M4WE:1;
4903                   uint32_t:6;
4904                 uint32_t M2PE:1;
4905                 uint32_t M2SM:2;
4906                 uint32_t M2UM:3;
4907                 uint32_t M1PE:1;
4908                 uint32_t M1SM:2;
4909                 uint32_t M1UM:3;
4910                 uint32_t M0PE:1;
4911                 uint32_t M0SM:2;
4912                 uint32_t M0UM:3;
4913             } B;
4914         } RGDAAC[16];           /* Region Descriptor Alternate Access Control n */
4915     };
4916 /**************************************************************************/
4917 /*                          MODULE : pit                                  */
4918 /**************************************************************************/
4919     struct PIT_tag {
4920
4921         union PIT_MCR_tag {
4922             uint32_t R;
4923             struct {
4924                 uint32_t:30;
4925                 uint32_t MDIS:1;
4926                 uint32_t FRZ:1;
4927             } B;
4928         } PITMCR;
4929
4930         uint32_t pit_reserved1[59];
4931
4932         struct PIT_CHANNEL_tag {
4933             union {
4934                 uint32_t R;
4935                 struct {
4936                     uint32_t TSV:32;
4937                 } B;
4938             } LDVAL;
4939
4940             union {
4941                 uint32_t R;
4942                 struct {
4943                     uint32_t TVL:32;
4944                 } B;
4945             } CVAL;
4946
4947             union PIT_TCTRL_tag {
4948                 uint32_t R;
4949                 struct {
4950                     uint32_t:30;
4951                     uint32_t TIE:1;
4952                     uint32_t TEN:1;
4953                 } B;
4954             } TCTRL;
4955
4956             union PIT_TFLG_tag {
4957                 uint32_t R;
4958                 struct {
4959                     uint32_t:31;
4960                     uint32_t TIF:1;
4961                 } B;
4962             } TFLG;
4963         } CHANNEL[9];
4964     };
4965
4966     /* Compatibility with MPC5643L */
4967     typedef struct PIT_CHANNEL_tag PIT_RTI_CHANNEL_tag;
4968     typedef union PIT_MCR_tag PIT_RTI_PITMCR_32B_tag;
4969     typedef union PIT_TCTRL_tag PIT_RTI_TCTRL_32B_tag;
4970     typedef union PIT_TFLG_tag PIT_RTI_TFLG_32B_tag;
4971 /**************************************************************************/
4972 /*                          MODULE : sem4                                 */
4973 /**************************************************************************/
4974     struct SEMA4_tag {
4975         union {
4976             uint8_t R;
4977             struct {
4978                 uint8_t:6;
4979                 uint8_t GTFSM:2;
4980             } B;
4981         } GATE[16];             /* Gate n Register */
4982
4983         uint32_t sema4_reserved1[12];   /* {0x40-0x10}/4 = 0x0C */
4984
4985         union {
4986             uint16_t R;
4987             struct {
4988                 uint16_t INE0:1;
4989                 uint16_t INE1:1;
4990                 uint16_t INE2:1;
4991                 uint16_t INE3:1;
4992                 uint16_t INE4:1;
4993                 uint16_t INE5:1;
4994                 uint16_t INE6:1;
4995                 uint16_t INE7:1;
4996                 uint16_t INE8:1;
4997                 uint16_t INE9:1;
4998                 uint16_t INE10:1;
4999                 uint16_t INE11:1;
5000                 uint16_t INE12:1;
5001                 uint16_t INE13:1;
5002                 uint16_t INE14:1;
5003                 uint16_t INE15:1;
5004             } B;
5005         } CP0INE;
5006
5007         uint16_t sema4_reserved2[3];    /* {0x48-0x42}/2 = 0x03 */
5008
5009         union {
5010             uint16_t R;
5011             struct {
5012                 uint16_t INE0:1;
5013                 uint16_t INE1:1;
5014                 uint16_t INE2:1;
5015                 uint16_t INE3:1;
5016                 uint16_t INE4:1;
5017                 uint16_t INE5:1;
5018                 uint16_t INE6:1;
5019                 uint16_t INE7:1;
5020                 uint16_t INE8:1;
5021                 uint16_t INE9:1;
5022                 uint16_t INE10:1;
5023                 uint16_t INE11:1;
5024                 uint16_t INE12:1;
5025                 uint16_t INE13:1;
5026                 uint16_t INE14:1;
5027                 uint16_t INE15:1;
5028             } B;
5029         } CP1INE;
5030
5031         uint16_t sema4_reserved3[27];   /* {0x80-0x4A}/2 = 0x1B */
5032
5033         union {
5034             uint16_t R;
5035             struct {
5036                 uint16_t GN0:1;
5037                 uint16_t GN1:1;
5038                 uint16_t GN2:1;
5039                 uint16_t GN3:1;
5040                 uint16_t GN4:1;
5041                 uint16_t GN5:1;
5042                 uint16_t GN6:1;
5043                 uint16_t GN7:1;
5044                 uint16_t GN8:1;
5045                 uint16_t GN9:1;
5046                 uint16_t GN10:1;
5047                 uint16_t GN11:1;
5048                 uint16_t GN12:1;
5049                 uint16_t GN13:1;
5050                 uint16_t GN14:1;
5051                 uint16_t GN15:1;
5052             } B;
5053         } CP0NTF;
5054
5055         uint16_t sema4_reserved4[3];    /* {0x88-0x82}/2 = 0x03 */
5056
5057         union {
5058             uint16_t R;
5059             struct {
5060                 uint16_t GN0:1;
5061                 uint16_t GN1:1;
5062                 uint16_t GN2:1;
5063                 uint16_t GN3:1;
5064                 uint16_t GN4:1;
5065                 uint16_t GN5:1;
5066                 uint16_t GN6:1;
5067                 uint16_t GN7:1;
5068                 uint16_t GN8:1;
5069                 uint16_t GN9:1;
5070                 uint16_t GN10:1;
5071                 uint16_t GN11:1;
5072                 uint16_t GN12:1;
5073                 uint16_t GN13:1;
5074                 uint16_t GN14:1;
5075                 uint16_t GN15:1;
5076             } B;
5077         } CP1NTF;
5078
5079         uint16_t sema4_reserved5[59];   /* {0x100-0x8A}/2 = 0x3B */
5080
5081         union {
5082             uint16_t R;
5083             struct {
5084                 uint16_t:2;
5085                 uint16_t RSTGSM:2;
5086                   uint16_t:1;
5087                 uint16_t RSTGMS:3;
5088                 uint16_t RSTGTN:8;
5089             } B;
5090         } RSTGT;
5091
5092         uint16_t sema4_reserved6;
5093
5094         union {
5095             uint16_t R;
5096             struct {
5097                 uint16_t:2;
5098                 uint16_t RSTNSM:2;
5099                   uint16_t:1;
5100                 uint16_t RSTNMS:3;
5101                 uint16_t RSTNTN:8;
5102             } B;
5103         } RSTNTF;
5104     };
5105 /*************************************************************************/
5106 /*                            MODULE : SIU                               */
5107 /*************************************************************************/
5108     struct SIU_tag {
5109
5110         int32_t SIU_reserved0;
5111
5112         union {
5113             uint32_t R;
5114             struct {
5115                 uint32_t PARTNUM:16;
5116                 uint32_t CSP:1;
5117                 uint32_t PKG:5;
5118                   uint32_t:2;
5119                 uint32_t MASKNUM_MAJOR:4;
5120                 uint32_t MASKNUM_MINOR:4;
5121             } B;
5122         } MIDR;                 /* MCU ID Register */
5123
5124         int32_t SIU_reserved1;
5125
5126         union {
5127             uint32_t R;
5128             struct {
5129                 uint32_t PORS:1;
5130                 uint32_t ERS:1;
5131                 uint32_t LLRS:1;
5132                 uint32_t LCRS:1;
5133                 uint32_t WDRS:1;
5134                 uint32_t CRS:1;
5135                   uint32_t:8;
5136                 uint32_t SSRS:1;
5137                   uint32_t:15;
5138                 uint32_t BOOTCFG:1;
5139                   uint32_t:1;
5140             } B;
5141         } RSR;                  /* Reset Status Register */
5142
5143         union {
5144             uint32_t R;
5145             struct {
5146                 uint32_t SSR:1;
5147                   uint32_t:15;
5148                 uint32_t CRE0:1;
5149                 uint32_t CRE1:1;
5150                   uint32_t:6;
5151                 uint32_t SSRL:1;
5152                   uint32_t:7;
5153             } B;
5154         } SRCR;                 /* System Reset Control Register */
5155
5156         union {
5157             uint32_t R;
5158             struct {
5159                 uint32_t NMI0:1;
5160                 uint32_t NMI1:1;
5161                   uint32_t:14;
5162                 uint32_t EIF15:1;
5163                 uint32_t EIF14:1;
5164                 uint32_t EIF13:1;
5165                 uint32_t EIF12:1;
5166                 uint32_t EIF11:1;
5167                 uint32_t EIF10:1;
5168                 uint32_t EIF9:1;
5169                 uint32_t EIF8:1;
5170                 uint32_t EIF7:1;
5171                 uint32_t EIF6:1;
5172                 uint32_t EIF5:1;
5173                 uint32_t EIF4:1;
5174                 uint32_t EIF3:1;
5175                 uint32_t EIF2:1;
5176                 uint32_t EIF1:1;
5177                 uint32_t EIF0:1;
5178             } B;
5179         } EISR;                 /* External Interrupt Status Register */
5180
5181         union SIU_DIRER_tag {
5182             uint32_t R;
5183             struct {
5184                 uint32_t:16;
5185                 uint32_t EIRE15:1;
5186                 uint32_t EIRE14:1;
5187                 uint32_t EIRE13:1;
5188                 uint32_t EIRE12:1;
5189                 uint32_t EIRE11:1;
5190                 uint32_t EIRE10:1;
5191                 uint32_t EIRE9:1;
5192                 uint32_t EIRE8:1;
5193                 uint32_t EIRE7:1;
5194                 uint32_t EIRE6:1;
5195                 uint32_t EIRE5:1;
5196                 uint32_t EIRE4:1;
5197                 uint32_t EIRE3:1;
5198                 uint32_t EIRE2:1;
5199                 uint32_t EIRE1:1;
5200                 uint32_t EIRE0:1;
5201             } B;
5202         } DIRER;                /* DMA/Interrupt Request Enable Register */
5203
5204         union SIU_DIRSR_tag {
5205             uint32_t R;
5206             struct {
5207                 uint32_t:30;
5208                 uint32_t DIRS1:1;
5209                 uint32_t DIRS0:1;
5210             } B;
5211         } DIRSR;                /* DMA/Interrupt Select Register */
5212
5213         union {
5214             uint32_t R;
5215             struct {
5216                 uint32_t:16;
5217                 uint32_t OVF15:1;
5218                 uint32_t OVF14:1;
5219                 uint32_t OVF13:1;
5220                 uint32_t OVF12:1;
5221                 uint32_t OVF11:1;
5222                 uint32_t OVF10:1;
5223                 uint32_t OVF9:1;
5224                 uint32_t OVF8:1;
5225                 uint32_t OVF7:1;
5226                 uint32_t OVF6:1;
5227                 uint32_t OVF5:1;
5228                 uint32_t OVF4:1;
5229                 uint32_t OVF3:1;
5230                 uint32_t OVF2:1;
5231                 uint32_t OVF1:1;
5232                 uint32_t OVF0:1;
5233             } B;
5234         } OSR;                  /* Overrun Status Register */
5235
5236         union SIU_ORER_tag {
5237             uint32_t R;
5238             struct {
5239                 uint32_t:16;
5240                 uint32_t ORE15:1;
5241                 uint32_t ORE14:1;
5242                 uint32_t ORE13:1;
5243                 uint32_t ORE12:1;
5244                 uint32_t ORE11:1;
5245                 uint32_t ORE10:1;
5246                 uint32_t ORE9:1;
5247                 uint32_t ORE8:1;
5248                 uint32_t ORE7:1;
5249                 uint32_t ORE6:1;
5250                 uint32_t ORE5:1;
5251                 uint32_t ORE4:1;
5252                 uint32_t ORE3:1;
5253                 uint32_t ORE2:1;
5254                 uint32_t ORE1:1;
5255                 uint32_t ORE0:1;
5256             } B;
5257         } ORER;                 /* Overrun Request Enable Register */
5258
5259         union SIU_IREER_tag {
5260             uint32_t R;
5261             struct {
5262                 uint32_t NREE0:1;
5263                 uint32_t NREE1:1;
5264                   uint32_t:14;
5265                 uint32_t IREE15:1;
5266                 uint32_t IREE14:1;
5267                 uint32_t IREE13:1;
5268                 uint32_t IREE12:1;
5269                 uint32_t IREE11:1;
5270                 uint32_t IREE10:1;
5271                 uint32_t IREE9:1;
5272                 uint32_t IREE8:1;
5273                 uint32_t IREE7:1;
5274                 uint32_t IREE6:1;
5275                 uint32_t IREE5:1;
5276                 uint32_t IREE4:1;
5277                 uint32_t IREE3:1;
5278                 uint32_t IREE2:1;
5279                 uint32_t IREE1:1;
5280                 uint32_t IREE0:1;
5281             } B;
5282         } IREER;                /* External IRQ Rising-Edge Event Enable Register */
5283
5284         union SIU_IFEER_tag {
5285             uint32_t R;
5286             struct {
5287                 uint32_t NFEE0:1;
5288                 uint32_t NFEE1:1;
5289                   uint32_t:14;
5290                 uint32_t IFEE15:1;
5291                 uint32_t IFEE14:1;
5292                 uint32_t IFEE13:1;
5293                 uint32_t IFEE12:1;
5294                 uint32_t IFEE11:1;
5295                 uint32_t IFEE10:1;
5296                 uint32_t IFEE9:1;
5297                 uint32_t IFEE8:1;
5298                 uint32_t IFEE7:1;
5299                 uint32_t IFEE6:1;
5300                 uint32_t IFEE5:1;
5301                 uint32_t IFEE4:1;
5302                 uint32_t IFEE3:1;
5303                 uint32_t IFEE2:1;
5304                 uint32_t IFEE1:1;
5305                 uint32_t IFEE0:1;
5306             } B;
5307         } IFEER;                /* External IRQ Falling-Edge Event Enable Register */
5308
5309         union SIU_IDFR_tag {
5310             uint32_t R;
5311             struct {
5312                 uint32_t:28;
5313                 uint32_t DFL:4;
5314             } B;
5315         } IDFR;                 /* External IRQ Digital Filter Register */
5316
5317         union {
5318             uint32_t R;
5319             struct {
5320                 uint32_t FNMI0:1;
5321                 uint32_t FNMI1:1;
5322                   uint32_t:14;
5323                 uint32_t FI15:1;
5324                 uint32_t FI14:1;
5325                 uint32_t FI13:1;
5326                 uint32_t FI12:1;
5327                 uint32_t FI11:1;
5328                 uint32_t FI10:1;
5329                 uint32_t FI9:1;
5330                 uint32_t FI8:1;
5331                 uint32_t FI7:1;
5332                 uint32_t FI6:1;
5333                 uint32_t FI5:1;
5334                 uint32_t FI4:1;
5335                 uint32_t FI3:1;
5336                 uint32_t FI2:1;
5337                 uint32_t FI1:1;
5338                 uint32_t FI0:1;
5339             } B;
5340         } IFIR;                 /* External IRQ Filtered Input Register */
5341
5342         int32_t SIU_reserved2[2];
5343
5344         union SIU_PCR_tag {
5345             uint16_t R;
5346             struct {
5347                 uint16_t:4;
5348                 uint16_t PA:2;
5349                 uint16_t OBE:1;
5350                 uint16_t IBE:1;
5351                 uint16_t DSC:2;
5352                 uint16_t ODE:1;
5353                 uint16_t HYS:1;
5354                 uint16_t SRC:2;
5355                 uint16_t WPE:1;
5356                 uint16_t WPS:1;
5357             } B;
5358         } PCR[155];             /* Pad Configuration Registers */
5359
5360         int32_t SIU_reserved3[290];
5361
5362         union {
5363             uint8_t R;
5364             struct {
5365                 uint8_t:7;
5366                 uint8_t PDO:1;
5367             } B;
5368         } GPDO[155];            /* GPIO Pin Data Output Registers */
5369
5370         int8_t SIU_reserved4[357];
5371
5372         union {
5373             uint8_t R;
5374             struct {
5375                 uint8_t:7;
5376                 uint8_t PDI:1;
5377             } B;
5378         } GPDI[155];            /* GPIO Pin Data Input Registers */
5379
5380         int32_t SIU_reserved5[26];
5381
5382         union {
5383             uint32_t R;
5384             struct {
5385                 uint32_t ESEL15:2;
5386                 uint32_t ESEL14:2;
5387                 uint32_t ESEL13:2;
5388                 uint32_t ESEL12:2;
5389                 uint32_t ESEL11:2;
5390                 uint32_t ESEL10:2;
5391                 uint32_t ESEL9:2;
5392                 uint32_t ESEL8:2;
5393                 uint32_t ESEL7:2;
5394                 uint32_t ESEL6:2;
5395                 uint32_t ESEL5:2;
5396                 uint32_t ESEL4:2;
5397                 uint32_t ESEL3:2;
5398                 uint32_t ESEL2:2;
5399                 uint32_t ESEL1:2;
5400                 uint32_t ESEL0:2;
5401             } B;
5402         } ISEL1;                /* IMUX Register */
5403
5404         union {
5405             uint32_t R;
5406             struct {
5407                 uint32_t ESEL15:2;
5408                 uint32_t ESEL14:2;
5409                 uint32_t ESEL13:2;
5410                 uint32_t ESEL12:2;
5411                 uint32_t ESEL11:2;
5412                 uint32_t ESEL10:2;
5413                 uint32_t ESEL9:2;
5414                 uint32_t ESEL8:2;
5415                 uint32_t ESEL7:2;
5416                 uint32_t ESEL6:2;
5417                 uint32_t ESEL5:2;
5418                 uint32_t ESEL4:2;
5419                 uint32_t ESEL3:2;
5420                 uint32_t ESEL2:2;
5421                 uint32_t ESEL1:2;
5422                 uint32_t ESEL0:2;
5423             } B;
5424         } ISEL2;                /* IMUX Register */
5425
5426         int32_t SIU_reserved6;
5427
5428         union {
5429             uint32_t R;
5430             struct {
5431                 uint32_t:17;
5432                 uint32_t TSEL1:7;
5433                   uint32_t:1;
5434                 uint32_t TSEL0:7;
5435             } B;
5436         } ISEL4;                /* IMUX Register */
5437
5438         int32_t SIU_reserved7[27];
5439
5440         union {
5441             uint32_t R;
5442             struct {
5443                 uint32_t:14;
5444                 uint32_t MATCH:1;
5445                 uint32_t DISNEX:1;
5446                   uint32_t:8;
5447                 uint32_t TESTLOCK:1;
5448                   uint32_t:7;
5449             } B;
5450         } CCR;                  /* Chip Configuration Register Register */
5451
5452         union {
5453             uint32_t R;
5454             struct {
5455                 uint32_t:28;
5456                 uint32_t ECEN:1;
5457                   uint32_t:1;
5458                 uint32_t ECDF:2;
5459             } B;
5460         } ECCR;                 /* External Clock Configuration Register Register */
5461
5462         union {
5463             uint32_t R;
5464         } GPR0;                 /* General Purpose Register 0 */
5465
5466         union {
5467             uint32_t R;
5468         } GPR1;                 /* General Purpose Register 1 */
5469
5470         union {
5471             uint32_t R;
5472         } GPR2;                 /* General Purpose Register 2 */
5473
5474         union {
5475             uint32_t R;
5476         } GPR3;                 /* General Purpose Register 3 */
5477
5478         int32_t SIU_reserved8[2];
5479
5480         union {
5481             uint32_t R;
5482             struct {
5483                 uint32_t SYSCLKSEL:2;
5484                 uint32_t SYSCLKDIV:3;
5485                   uint32_t:19;
5486                 uint32_t LPCLKDIV3:2;
5487                 uint32_t LPCLKDIV2:2;
5488                 uint32_t LPCLKDIV1:2;
5489                 uint32_t LPCLKDIV0:2;
5490             } B;
5491         } SYSCLK;               /* System CLock Register */
5492
5493         union {
5494             uint32_t R;
5495             struct {
5496                 uint32_t:6;
5497                 uint32_t HLT6:1;
5498                 uint32_t HLT7:1;
5499                   uint32_t:1;
5500                 uint32_t HLT9:1;
5501                 uint32_t HLT10:1;
5502                 uint32_t HLT11:1;
5503                 uint32_t HLT12:1;
5504                 uint32_t HLT13:1;
5505                 uint32_t HLT14:1;
5506                 uint32_t HLT15:1;
5507                 uint32_t HLT16:1;
5508                 uint32_t HLT17:1;
5509                 uint32_t HLT18:1;
5510                 uint32_t HLT19:1;
5511                 uint32_t HLT20:1;
5512                 uint32_t HLT21:1;
5513                 uint32_t HLT22:1;
5514                 uint32_t HLT23:1;
5515                   uint32_t:2;
5516                 uint32_t HLT26:1;
5517                 uint32_t HLT27:1;
5518                 uint32_t HLT28:1;
5519                 uint32_t HLT29:1;
5520                   uint32_t:1;
5521                 uint32_t HLT31:1;
5522             } B;
5523         } HLT0;                 /* Halt Register 0 */
5524
5525         union {
5526             uint32_t R;
5527             struct {
5528                 uint32_t:3;
5529                 uint32_t HLT3:1;
5530                 uint32_t HLT4:1;
5531                   uint32_t:15;
5532                 uint32_t HLT20:1;
5533                 uint32_t HLT21:1;
5534                 uint32_t HLT22:1;
5535                 uint32_t HLT23:1;
5536                   uint32_t:2;
5537                 uint32_t HLT26:1;
5538                 uint32_t HLT27:1;
5539                 uint32_t HLT28:1;
5540                 uint32_t HLT29:1;
5541                   uint32_t:2;
5542             } B;
5543         } HLT1;                 /* Halt Register 1 */
5544
5545         union {
5546             uint32_t R;
5547             struct {
5548                 uint32_t:6;
5549                 uint32_t HLTACK6:1;
5550                 uint32_t HLTACK7:1;
5551                   uint32_t:1;
5552                 uint32_t HLTACK9:1;
5553                 uint32_t HLTACK10:1;
5554                 uint32_t HLTACK11:1;
5555                 uint32_t HLTACK12:1;
5556                 uint32_t HLTACK13:1;
5557                 uint32_t HLTACK14:1;
5558                 uint32_t HLTACK15:1;
5559                 uint32_t HLTACK16:1;
5560                 uint32_t HLTACK17:1;
5561                 uint32_t HLTACK18:1;
5562                 uint32_t HLTACK19:1;
5563                 uint32_t HLTACK20:1;
5564                 uint32_t HLTACK21:1;
5565                 uint32_t HLTACK22:1;
5566                 uint32_t HLTACK23:1;
5567                   uint32_t:2;
5568                 uint32_t HLTACK26:1;
5569                 uint32_t HLTACK27:1;
5570                 uint32_t HLTACK28:1;
5571                 uint32_t HLTACK29:1;
5572                   uint32_t:1;
5573                 uint32_t HLTACK31:1;
5574             } B;
5575         } HLTACK0;              /* Halt Acknowledge Register 0 */
5576
5577         union {
5578             uint32_t R;
5579             struct {
5580                 uint32_t HLTACK0:1;
5581                 uint32_t HLTACK1:1;
5582                   uint32_t:1;
5583                 uint32_t HLTACK3:1;
5584                 uint32_t HLTACK4:1;
5585                   uint32_t:11;
5586                 uint32_t HLTACK20:1;
5587                 uint32_t HLTACK21:1;
5588                 uint32_t HLTACK22:1;
5589                 uint32_t HLTACK23:1;
5590                   uint32_t:2;
5591                 uint32_t HLTACK26:1;
5592                 uint32_t HLTACK27:1;
5593                 uint32_t HLTACK28:1;
5594                 uint32_t HLTACK29:1;
5595                   uint32_t:2;
5596             } B;
5597         } HLTACK1;              /* Halt Acknowledge Register 0 */
5598
5599         union {
5600             uint32_t R;
5601             struct {
5602                 uint32_t EMIOSSEL31:4;
5603                 uint32_t EMIOSSEL30:4;
5604                 uint32_t EMIOSSEL29:4;
5605                 uint32_t EMIOSSEL28:4;
5606                 uint32_t EMIOSSEL27:4;
5607                 uint32_t EMIOSSEL26:4;
5608                 uint32_t EMIOSSEL25:4;
5609                 uint32_t EMIOSSEL24:4;
5610             } B;
5611         } EMIOS_SEL0;           /* eMIOS Select Register 0 */
5612
5613         union {
5614             uint32_t R;
5615             struct {
5616                 uint32_t EMIOSSEL23:4;
5617                 uint32_t EMIOSSEL22:4;
5618                 uint32_t EMIOSSEL21:4;
5619                 uint32_t EMIOSSEL20:4;
5620                 uint32_t EMIOSSEL19:4;
5621                 uint32_t EMIOSSEL18:4;
5622                 uint32_t EMIOSSEL17:4;
5623                 uint32_t EMIOSSEL16:4;
5624             } B;
5625         } EMIOS_SEL1;           /* eMIOS Select Register 1 */
5626
5627         union {
5628             uint32_t R;
5629             struct {
5630                 uint32_t EMIOSSEL15:4;
5631                 uint32_t EMIOSSEL14:4;
5632                 uint32_t EMIOSSEL13:4;
5633                 uint32_t EMIOSSEL12:4;
5634                 uint32_t EMIOSSEL11:4;
5635                 uint32_t EMIOSSEL10:4;
5636                 uint32_t EMIOSSEL9:4;
5637                 uint32_t EMIOSSEL8:4;
5638             } B;
5639         } EMIOS_SEL2;           /* eMIOS Select Register 2 */
5640
5641         union {
5642             uint32_t R;
5643             struct {
5644                 uint32_t EMIOSSEL7:4;
5645                 uint32_t EMIOSSEL6:4;
5646                 uint32_t EMIOSSEL5:4;
5647                 uint32_t EMIOSSEL4:4;
5648                 uint32_t EMIOSSEL3:4;
5649                 uint32_t EMIOSSEL2:4;
5650                 uint32_t EMIOSSEL1:4;
5651                 uint32_t EMIOSSEL0:4;
5652             } B;
5653         } EMIOS_SEL3;           /* eMIOS Select Register 3 */
5654
5655         union {
5656             uint32_t R;
5657             struct {
5658                 uint32_t ESEL15:2;
5659                 uint32_t ESEL14:2;
5660                 uint32_t ESEL13:2;
5661                 uint32_t ESEL12:2;
5662                 uint32_t ESEL11:2;
5663                 uint32_t ESEL10:2;
5664                 uint32_t ESEL9:2;
5665                 uint32_t ESEL8:2;
5666                 uint32_t ESEL7:2;
5667                 uint32_t ESEL6:2;
5668                 uint32_t ESEL5:2;
5669                 uint32_t ESEL4:2;
5670                 uint32_t ESEL3:2;
5671                 uint32_t ESEL2:2;
5672                 uint32_t ESEL1:2;
5673                 uint32_t ESEL0:2;
5674             } B;
5675         } ISEL2A;               /* External Interrupt Select Register 2A */
5676
5677         int32_t SIU_reserved9[142];
5678
5679         union {
5680             uint32_t R;
5681             struct {
5682                 uint32_t:16;
5683                 uint32_t PB:16;
5684             } B;
5685         } PGPDO0;               /* Parallel GPIO Pin Data Output Register */
5686
5687         union {
5688             uint32_t R;
5689             struct {
5690                 uint32_t PC:16;
5691                 uint32_t PD:16;
5692             } B;
5693         } PGPDO1;               /* Parallel GPIO Pin Data Output Register */
5694
5695         union {
5696             uint32_t R;
5697             struct {
5698                 uint32_t PE:16;
5699                 uint32_t PF:16;
5700             } B;
5701         } PGPDO2;               /* Parallel GPIO Pin Data Output Register */
5702
5703         union {
5704             uint32_t R;
5705             struct {
5706                 uint32_t PG:16;
5707                 uint32_t PH:16;
5708             } B;
5709         } PGPDO3;               /* Parallel GPIO Pin Data Output Register */
5710
5711         union {
5712             uint32_t R;
5713             struct {
5714                 uint32_t PJ:16;
5715                 uint32_t PK:11;
5716                   uint32_t:5;
5717             } B;
5718         } PGPDO4;               /* Parallel GPIO Pin Data Output Register */
5719
5720         int32_t SIU_reserved10[11];
5721
5722         union {
5723             uint32_t R;
5724             struct {
5725                 uint32_t PA:16;
5726                 uint32_t PB:16;
5727             } B;
5728         } PGPDI0;               /* Parallel GPIO Pin Data Input Register */
5729
5730         union {
5731             uint32_t R;
5732             struct {
5733                 uint32_t PC:16;
5734                 uint32_t PD:16;
5735             } B;
5736         } PGPDI1;               /* Parallel GPIO Pin Data Input Register */
5737
5738         union {
5739             uint32_t R;
5740             struct {
5741                 uint32_t PE:16;
5742                 uint32_t PF:16;
5743             } B;
5744         } PGPDI2;               /* Parallel GPIO Pin Data Input Register */
5745
5746         union {
5747             uint32_t R;
5748             struct {
5749                 uint32_t PG:16;
5750                 uint32_t PH:16;
5751             } B;
5752         } PGPDI3;               /* Parallel GPIO Pin Data Input Register */
5753
5754         union {
5755             uint32_t R;
5756             struct {
5757                 uint32_t PJ:16;
5758                 uint32_t PK:11;
5759                   uint32_t:5;
5760             } B;
5761         } PGPDI4;               /* Parallel GPIO Pin Data Input Register */
5762
5763         int32_t SIU_reserved11[12];
5764
5765         union {
5766             uint32_t R;
5767             struct {
5768                 uint32_t PB_MASK:16;
5769                 uint32_t PB:16;
5770             } B;
5771         } MPGPDO1;              /* Masked Parallel GPIO Pin Data Input Register */
5772
5773         union {
5774             uint32_t R;
5775             struct {
5776                 uint32_t PC_MASK:16;
5777                 uint32_t PC:16;
5778             } B;
5779         } MPGPDO2;              /* Masked Parallel GPIO Pin Data Input Register */
5780
5781         union {
5782             uint32_t R;
5783             struct {
5784                 uint32_t PD_MASK:16;
5785                 uint32_t PD:16;
5786             } B;
5787         } MPGPDO3;              /* Masked Parallel GPIO Pin Data Input Register */
5788
5789         union {
5790             uint32_t R;
5791             struct {
5792                 uint32_t PE_MASK:16;
5793                 uint32_t PE:16;
5794             } B;
5795         } MPGPDO4;              /* Masked Parallel GPIO Pin Data Input Register */
5796
5797         union {
5798             uint32_t R;
5799             struct {
5800                 uint32_t PF_MASK:16;
5801                 uint32_t PF:16;
5802             } B;
5803         } MPGPDO5;              /* Masked Parallel GPIO Pin Data Input Register */
5804
5805         union {
5806             uint32_t R;
5807             struct {
5808                 uint32_t PG_MASK:16;
5809                 uint32_t PG:16;
5810             } B;
5811         } MPGPDO6;              /* Masked Parallel GPIO Pin Data Input Register */
5812
5813         union {
5814             uint32_t R;
5815             struct {
5816                 uint32_t PH_MASK:16;
5817                 uint32_t PH:16;
5818             } B;
5819         } MPGPDO7;              /* Masked Parallel GPIO Pin Data Input Register */
5820
5821         union {
5822             uint32_t R;
5823             struct {
5824                 uint32_t PJ_MASK:16;
5825                 uint32_t PJ:16;
5826             } B;
5827         } MPGPDO8;              /* Masked Parallel GPIO Pin Data Input Register */
5828
5829         union {
5830             uint32_t R;
5831             struct {
5832                 uint32_t PK_MASK:11;
5833                   uint32_t:5;
5834                 uint32_t PK:11;
5835                   uint32_t:5;
5836             } B;
5837         } MPGPDO9;              /* Masked Parallel GPIO Pin Data Input Register */
5838
5839         int32_t SIU_reserved12[22];
5840
5841         union {
5842             uint32_t R;
5843             struct {
5844                 uint32_t MASK31:1;
5845                 uint32_t MASK30:1;
5846                 uint32_t MASK29:1;
5847                 uint32_t MASK28:1;
5848                 uint32_t MASK27:1;
5849                 uint32_t MASK26:1;
5850                 uint32_t MASK25:1;
5851                 uint32_t MASK24:1;
5852                 uint32_t MASK23:1;
5853                 uint32_t MASK22:1;
5854                 uint32_t MASK21:1;
5855                 uint32_t MASK20:1;
5856                 uint32_t MASK19:1;
5857                 uint32_t MASK18:1;
5858                 uint32_t MASK17:1;
5859                 uint32_t MASK16:1;
5860                 uint32_t DATA31:1;
5861                 uint32_t DATA30:1;
5862                 uint32_t DATA29:1;
5863                 uint32_t DATA28:1;
5864                 uint32_t DATA27:1;
5865                 uint32_t DATA26:1;
5866                 uint32_t DATA25:1;
5867                 uint32_t DATA24:1;
5868                 uint32_t DATA23:1;
5869                 uint32_t DATA22:1;
5870                 uint32_t DATA21:1;
5871                 uint32_t DATA20:1;
5872                 uint32_t DATA19:1;
5873                 uint32_t DATA18:1;
5874                 uint32_t DATA17:1;
5875                 uint32_t DATA16:1;
5876             } B;
5877         } DSPIAH;               /* Masked Serial GPO for DSPI_A High Register */
5878
5879         union {
5880             uint32_t R;
5881             struct {
5882                 uint32_t MASK15:1;
5883                 uint32_t MASK14:1;
5884                 uint32_t MASK13:1;
5885                 uint32_t MASK12:1;
5886                 uint32_t MASK11:1;
5887                 uint32_t MASK10:1;
5888                 uint32_t MASK9:1;
5889                 uint32_t MASK8:1;
5890                 uint32_t MASK7:1;
5891                 uint32_t MASK6:1;
5892                 uint32_t MASK5:1;
5893                 uint32_t MASK4:1;
5894                 uint32_t MASK3:1;
5895                 uint32_t MASK2:1;
5896                 uint32_t MASK1:1;
5897                 uint32_t MASK0:1;
5898                 uint32_t DATA15:1;
5899                 uint32_t DATA14:1;
5900                 uint32_t DATA13:1;
5901                 uint32_t DATA12:1;
5902                 uint32_t DATA11:1;
5903                 uint32_t DATA10:1;
5904                 uint32_t DATA9:1;
5905                 uint32_t DATA8:1;
5906                 uint32_t DATA7:1;
5907                 uint32_t DATA6:1;
5908                 uint32_t DATA5:1;
5909                 uint32_t DATA4:1;
5910                 uint32_t DATA3:1;
5911                 uint32_t DATA2:1;
5912                 uint32_t DATA1:1;
5913                 uint32_t DATA0:1;
5914             } B;
5915         } DSPIAL;               /* Masked Serial GPO for DSPI_A Low Register */
5916
5917         union {
5918             uint32_t R;
5919             struct {
5920                 uint32_t MASK31:1;
5921                 uint32_t MASK30:1;
5922                 uint32_t MASK29:1;
5923                 uint32_t MASK28:1;
5924                 uint32_t MASK27:1;
5925                 uint32_t MASK26:1;
5926                 uint32_t MASK25:1;
5927                 uint32_t MASK24:1;
5928                 uint32_t MASK23:1;
5929                 uint32_t MASK22:1;
5930                 uint32_t MASK21:1;
5931                 uint32_t MASK20:1;
5932                 uint32_t MASK19:1;
5933                 uint32_t MASK18:1;
5934                 uint32_t MASK17:1;
5935                 uint32_t MASK16:1;
5936                 uint32_t DATA31:1;
5937                 uint32_t DATA30:1;
5938                 uint32_t DATA29:1;
5939                 uint32_t DATA28:1;
5940                 uint32_t DATA27:1;
5941                 uint32_t DATA26:1;
5942                 uint32_t DATA25:1;
5943                 uint32_t DATA24:1;
5944                 uint32_t DATA23:1;
5945                 uint32_t DATA22:1;
5946                 uint32_t DATA21:1;
5947                 uint32_t DATA20:1;
5948                 uint32_t DATA19:1;
5949                 uint32_t DATA18:1;
5950                 uint32_t DATA17:1;
5951                 uint32_t DATA16:1;
5952             } B;
5953         } DSPIBH;               /* Masked Serial GPO for DSPI_B High Register */
5954
5955         union {
5956             uint32_t R;
5957             struct {
5958                 uint32_t MASK15:1;
5959                 uint32_t MASK14:1;
5960                 uint32_t MASK13:1;
5961                 uint32_t MASK12:1;
5962                 uint32_t MASK11:1;
5963                 uint32_t MASK10:1;
5964                 uint32_t MASK9:1;
5965                 uint32_t MASK8:1;
5966                 uint32_t MASK7:1;
5967                 uint32_t MASK6:1;
5968                 uint32_t MASK5:1;
5969                 uint32_t MASK4:1;
5970                 uint32_t MASK3:1;
5971                 uint32_t MASK2:1;
5972                 uint32_t MASK1:1;
5973                 uint32_t MASK0:1;
5974                 uint32_t DATA15:1;
5975                 uint32_t DATA14:1;
5976                 uint32_t DATA13:1;
5977                 uint32_t DATA12:1;
5978                 uint32_t DATA11:1;
5979                 uint32_t DATA10:1;
5980                 uint32_t DATA9:1;
5981                 uint32_t DATA8:1;
5982                 uint32_t DATA7:1;
5983                 uint32_t DATA6:1;
5984                 uint32_t DATA5:1;
5985                 uint32_t DATA4:1;
5986                 uint32_t DATA3:1;
5987                 uint32_t DATA2:1;
5988                 uint32_t DATA1:1;
5989                 uint32_t DATA0:1;
5990             } B;
5991         } DSPIBL;               /* Masked Serial GPO for DSPI_B Low Register */
5992
5993         union {
5994             uint32_t R;
5995             struct {
5996                 uint32_t MASK31:1;
5997                 uint32_t MASK30:1;
5998                 uint32_t MASK29:1;
5999                 uint32_t MASK28:1;
6000                 uint32_t MASK27:1;
6001                 uint32_t MASK26:1;
6002                 uint32_t MASK25:1;
6003                 uint32_t MASK24:1;
6004                 uint32_t MASK23:1;
6005                 uint32_t MASK22:1;
6006                 uint32_t MASK21:1;
6007                 uint32_t MASK20:1;
6008                 uint32_t MASK19:1;
6009                 uint32_t MASK18:1;
6010                 uint32_t MASK17:1;
6011                 uint32_t MASK16:1;
6012                 uint32_t DATA31:1;
6013                 uint32_t DATA30:1;
6014                 uint32_t DATA29:1;
6015                 uint32_t DATA28:1;
6016                 uint32_t DATA27:1;
6017                 uint32_t DATA26:1;
6018                 uint32_t DATA25:1;
6019                 uint32_t DATA24:1;
6020                 uint32_t DATA23:1;
6021                 uint32_t DATA22:1;
6022                 uint32_t DATA21:1;
6023                 uint32_t DATA20:1;
6024                 uint32_t DATA19:1;
6025                 uint32_t DATA18:1;
6026                 uint32_t DATA17:1;
6027                 uint32_t DATA16:1;
6028             } B;
6029         } DSPICH;               /* Masked Serial GPO for DSPI_C High Register */
6030
6031         union {
6032             uint32_t R;
6033             struct {
6034                 uint32_t MASK15:1;
6035                 uint32_t MASK14:1;
6036                 uint32_t MASK13:1;
6037                 uint32_t MASK12:1;
6038                 uint32_t MASK11:1;
6039                 uint32_t MASK10:1;
6040                 uint32_t MASK9:1;
6041                 uint32_t MASK8:1;
6042                 uint32_t MASK7:1;
6043                 uint32_t MASK6:1;
6044                 uint32_t MASK5:1;
6045                 uint32_t MASK4:1;
6046                 uint32_t MASK3:1;
6047                 uint32_t MASK2:1;
6048                 uint32_t MASK1:1;
6049                 uint32_t MASK0:1;
6050                 uint32_t DATA15:1;
6051                 uint32_t DATA14:1;
6052                 uint32_t DATA13:1;
6053                 uint32_t DATA12:1;
6054                 uint32_t DATA11:1;
6055                 uint32_t DATA10:1;
6056                 uint32_t DATA9:1;
6057                 uint32_t DATA8:1;
6058                 uint32_t DATA7:1;
6059                 uint32_t DATA6:1;
6060                 uint32_t DATA5:1;
6061                 uint32_t DATA4:1;
6062                 uint32_t DATA3:1;
6063                 uint32_t DATA2:1;
6064                 uint32_t DATA1:1;
6065                 uint32_t DATA0:1;
6066             } B;
6067         } DSPICL;               /* Masked Serial GPO for DSPI_C Low Register */
6068
6069         union {
6070             uint32_t R;
6071             struct {
6072                 uint32_t MASK31:1;
6073                 uint32_t MASK30:1;
6074                 uint32_t MASK29:1;
6075                 uint32_t MASK28:1;
6076                 uint32_t MASK27:1;
6077                 uint32_t MASK26:1;
6078                 uint32_t MASK25:1;
6079                 uint32_t MASK24:1;
6080                 uint32_t MASK23:1;
6081                 uint32_t MASK22:1;
6082                 uint32_t MASK21:1;
6083                 uint32_t MASK20:1;
6084                 uint32_t MASK19:1;
6085                 uint32_t MASK18:1;
6086                 uint32_t MASK17:1;
6087                 uint32_t MASK16:1;
6088                 uint32_t DATA31:1;
6089                 uint32_t DATA30:1;
6090                 uint32_t DATA29:1;
6091                 uint32_t DATA28:1;
6092                 uint32_t DATA27:1;
6093                 uint32_t DATA26:1;
6094                 uint32_t DATA25:1;
6095                 uint32_t DATA24:1;
6096                 uint32_t DATA23:1;
6097                 uint32_t DATA22:1;
6098                 uint32_t DATA21:1;
6099                 uint32_t DATA20:1;
6100                 uint32_t DATA19:1;
6101                 uint32_t DATA18:1;
6102                 uint32_t DATA17:1;
6103                 uint32_t DATA16:1;
6104             } B;
6105         } DSPIDH;               /* Masked Serial GPO for DSPI_D High Register */
6106
6107         union {
6108             uint32_t R;
6109             struct {
6110                 uint32_t MASK15:1;
6111                 uint32_t MASK14:1;
6112                 uint32_t MASK13:1;
6113                 uint32_t MASK12:1;
6114                 uint32_t MASK11:1;
6115                 uint32_t MASK10:1;
6116                 uint32_t MASK9:1;
6117                 uint32_t MASK8:1;
6118                 uint32_t MASK7:1;
6119                 uint32_t MASK6:1;
6120                 uint32_t MASK5:1;
6121                 uint32_t MASK4:1;
6122                 uint32_t MASK3:1;
6123                 uint32_t MASK2:1;
6124                 uint32_t MASK1:1;
6125                 uint32_t MASK0:1;
6126                 uint32_t DATA15:1;
6127                 uint32_t DATA14:1;
6128                 uint32_t DATA13:1;
6129                 uint32_t DATA12:1;
6130                 uint32_t DATA11:1;
6131                 uint32_t DATA10:1;
6132                 uint32_t DATA9:1;
6133                 uint32_t DATA8:1;
6134                 uint32_t DATA7:1;
6135                 uint32_t DATA6:1;
6136                 uint32_t DATA5:1;
6137                 uint32_t DATA4:1;
6138                 uint32_t DATA3:1;
6139                 uint32_t DATA2:1;
6140                 uint32_t DATA1:1;
6141                 uint32_t DATA0:1;
6142             } B;
6143         } DSPIDL;               /* Masked Serial GPO for DSPI_D Low Register */
6144
6145         int32_t SIU_reserved13[9];
6146
6147         union {
6148             uint32_t R;
6149             struct {
6150                 uint32_t EMIOS31:1;
6151                 uint32_t EMIOS30:1;
6152                 uint32_t EMIOS29:1;
6153                 uint32_t EMIOS28:1;
6154                 uint32_t EMIOS27:1;
6155                 uint32_t EMIOS26:1;
6156                 uint32_t EMIOS25:1;
6157                 uint32_t EMIOS24:1;
6158                 uint32_t EMIOS23:1;
6159                 uint32_t EMIOS22:1;
6160                 uint32_t EMIOS21:1;
6161                 uint32_t EMIOS20:1;
6162                 uint32_t EMIOS19:1;
6163                 uint32_t EMIOS18:1;
6164                 uint32_t EMIOS17:1;
6165                 uint32_t EMIOS16:1;
6166                 uint32_t EMIOS15:1;
6167                 uint32_t EMIOS14:1;
6168                 uint32_t EMIOS13:1;
6169                 uint32_t EMIOS12:1;
6170                 uint32_t EMIOS11:1;
6171                 uint32_t EMIOS10:1;
6172                 uint32_t EMIOS9:1;
6173                 uint32_t EMIOS8:1;
6174                 uint32_t EMIOS7:1;
6175                 uint32_t EMIOS6:1;
6176                 uint32_t EMIOS5:1;
6177                 uint32_t EMIOS4:1;
6178                 uint32_t EMIOS3:1;
6179                 uint32_t EMIOS2:1;
6180                 uint32_t EMIOS1:1;
6181                 uint32_t EMIOS0:1;
6182             } B;
6183         } EMIOSA;               /* EMIOS A Select Register */
6184
6185         union {
6186             uint32_t R;
6187             struct {
6188                 uint32_t DSPIAH31:1;
6189                 uint32_t DSPIAH30:1;
6190                 uint32_t DSPIAH29:1;
6191                 uint32_t DSPIAH28:1;
6192                 uint32_t DSPIAH27:1;
6193                 uint32_t DSPIAH26:1;
6194                 uint32_t DSPIAH25:1;
6195                 uint32_t DSPIAH24:1;
6196                 uint32_t DSPIAH23:1;
6197                 uint32_t DSPIAH22:1;
6198                 uint32_t DSPIAH21:1;
6199                 uint32_t DSPIAH20:1;
6200                 uint32_t DSPIAH19:1;
6201                 uint32_t DSPIAH18:1;
6202                 uint32_t DSPIAH17:1;
6203                 uint32_t DSPIAH16:1;
6204                 uint32_t DSPIAL15:1;
6205                 uint32_t DSPIAL14:1;
6206                 uint32_t DSPIAL13:1;
6207                 uint32_t DSPIAL12:1;
6208                 uint32_t DSPIAL11:1;
6209                 uint32_t DSPIAL10:1;
6210                 uint32_t DSPIAL9:1;
6211                 uint32_t DSPIAL8:1;
6212                 uint32_t DSPIAL7:1;
6213                 uint32_t DSPIAL6:1;
6214                 uint32_t DSPIAL5:1;
6215                 uint32_t DSPIAL4:1;
6216                 uint32_t DSPIAL3:1;
6217                 uint32_t DSPIAL2:1;
6218                 uint32_t DSPIAL1:1;
6219                 uint32_t DSPIAL0:1;
6220             } B;
6221         } DSPIAHLA;             /* DSPIAH/L Select Register for DSPI A */
6222
6223         int32_t SIU_reserved14[2];
6224
6225         union {
6226             uint32_t R;
6227             struct {
6228                 uint32_t EMIOS31:1;
6229                 uint32_t EMIOS30:1;
6230                 uint32_t EMIOS29:1;
6231                 uint32_t EMIOS28:1;
6232                 uint32_t EMIOS27:1;
6233                 uint32_t EMIOS26:1;
6234                 uint32_t EMIOS25:1;
6235                 uint32_t EMIOS24:1;
6236                 uint32_t EMIOS23:1;
6237                 uint32_t EMIOS22:1;
6238                 uint32_t EMIOS21:1;
6239                 uint32_t EMIOS20:1;
6240                 uint32_t EMIOS19:1;
6241                 uint32_t EMIOS18:1;
6242                 uint32_t EMIOS17:1;
6243                 uint32_t EMIOS16:1;
6244                 uint32_t EMIOS15:1;
6245                 uint32_t EMIOS14:1;
6246                 uint32_t EMIOS13:1;
6247                 uint32_t EMIOS12:1;
6248                 uint32_t EMIOS11:1;
6249                 uint32_t EMIOS10:1;
6250                 uint32_t EMIOS9:1;
6251                 uint32_t EMIOS8:1;
6252                 uint32_t EMIOS7:1;
6253                 uint32_t EMIOS6:1;
6254                 uint32_t EMIOS5:1;
6255                 uint32_t EMIOS4:1;
6256                 uint32_t EMIOS3:1;
6257                 uint32_t EMIOS2:1;
6258                 uint32_t EMIOS1:1;
6259                 uint32_t EMIOS0:1;
6260             } B;
6261         } EMIOSB;               /* EMIOS B Select Register */
6262
6263         union {
6264             uint32_t R;
6265             struct {
6266                 uint32_t DSPIBH31:1;
6267                 uint32_t DSPIBH30:1;
6268                 uint32_t DSPIBH29:1;
6269                 uint32_t DSPIBH28:1;
6270                 uint32_t DSPIBH27:1;
6271                 uint32_t DSPIBH26:1;
6272                 uint32_t DSPIBH25:1;
6273                 uint32_t DSPIBH24:1;
6274                 uint32_t DSPIBH23:1;
6275                 uint32_t DSPIBH22:1;
6276                 uint32_t DSPIBH21:1;
6277                 uint32_t DSPIBH20:1;
6278                 uint32_t DSPIBH19:1;
6279                 uint32_t DSPIBH18:1;
6280                 uint32_t DSPIBH17:1;
6281                 uint32_t DSPIBH16:1;
6282                 uint32_t DSPIBL15:1;
6283                 uint32_t DSPIBL14:1;
6284                 uint32_t DSPIBL13:1;
6285                 uint32_t DSPIBL12:1;
6286                 uint32_t DSPIBL11:1;
6287                 uint32_t DSPIBL10:1;
6288                 uint32_t DSPIBL9:1;
6289                 uint32_t DSPIBL8:1;
6290                 uint32_t DSPIBL7:1;
6291                 uint32_t DSPIBL6:1;
6292                 uint32_t DSPIBL5:1;
6293                 uint32_t DSPIBL4:1;
6294                 uint32_t DSPIBL3:1;
6295                 uint32_t DSPIBL2:1;
6296                 uint32_t DSPIBL1:1;
6297                 uint32_t DSPIBL0:1;
6298             } B;
6299         } DSPIBHLB;             /* DSPIBH/L Select Register for DSPI B */
6300
6301         int32_t SIU_reserved115[2];
6302
6303         union {
6304             uint32_t R;
6305             struct {
6306                 uint32_t EMIOS31:1;
6307                 uint32_t EMIOS30:1;
6308                 uint32_t EMIOS29:1;
6309                 uint32_t EMIOS28:1;
6310                 uint32_t EMIOS27:1;
6311                 uint32_t EMIOS26:1;
6312                 uint32_t EMIOS25:1;
6313                 uint32_t EMIOS24:1;
6314                 uint32_t EMIOS23:1;
6315                 uint32_t EMIOS22:1;
6316                 uint32_t EMIOS21:1;
6317                 uint32_t EMIOS20:1;
6318                 uint32_t EMIOS19:1;
6319                 uint32_t EMIOS18:1;
6320                 uint32_t EMIOS17:1;
6321                 uint32_t EMIOS16:1;
6322                 uint32_t EMIOS15:1;
6323                 uint32_t EMIOS14:1;
6324                 uint32_t EMIOS13:1;
6325                 uint32_t EMIOS12:1;
6326                 uint32_t EMIOS11:1;
6327                 uint32_t EMIOS10:1;
6328                 uint32_t EMIOS9:1;
6329                 uint32_t EMIOS8:1;
6330                 uint32_t EMIOS7:1;
6331                 uint32_t EMIOS6:1;
6332                 uint32_t EMIOS5:1;
6333                 uint32_t EMIOS4:1;
6334                 uint32_t EMIOS3:1;
6335                 uint32_t EMIOS2:1;
6336                 uint32_t EMIOS1:1;
6337                 uint32_t EMIOS0:1;
6338             } B;
6339         } EMIOSC;               /* EMIOS C Select Register */
6340
6341         union {
6342             uint32_t R;
6343             struct {
6344                 uint32_t DSPICH31:1;
6345                 uint32_t DSPICH30:1;
6346                 uint32_t DSPICH29:1;
6347                 uint32_t DSPICH28:1;
6348                 uint32_t DSPICH27:1;
6349                 uint32_t DSPICH26:1;
6350                 uint32_t DSPICH25:1;
6351                 uint32_t DSPICH24:1;
6352                 uint32_t DSPICH23:1;
6353                 uint32_t DSPICH22:1;
6354                 uint32_t DSPICH21:1;
6355                 uint32_t DSPICH20:1;
6356                 uint32_t DSPICH19:1;
6357                 uint32_t DSPICH18:1;
6358                 uint32_t DSPICH17:1;
6359                 uint32_t DSPICH16:1;
6360                 uint32_t DSPICL15:1;
6361                 uint32_t DSPICL14:1;
6362                 uint32_t DSPICL13:1;
6363                 uint32_t DSPICL12:1;
6364                 uint32_t DSPICL11:1;
6365                 uint32_t DSPICL10:1;
6366                 uint32_t DSPICL9:1;
6367                 uint32_t DSPICL8:1;
6368                 uint32_t DSPICL7:1;
6369                 uint32_t DSPICL6:1;
6370                 uint32_t DSPICL5:1;
6371                 uint32_t DSPICL4:1;
6372                 uint32_t DSPICL3:1;
6373                 uint32_t DSPICL2:1;
6374                 uint32_t DSPICL1:1;
6375                 uint32_t DSPICL0:1;
6376             } B;
6377         } DSPICHLC;             /* DSPIAH/L Select Register for DSPI C */
6378
6379         int32_t SIU_reserved16[2];
6380
6381         union {
6382             uint32_t R;
6383             struct {
6384                 uint32_t EMIOS31:1;
6385                 uint32_t EMIOS30:1;
6386                 uint32_t EMIOS29:1;
6387                 uint32_t EMIOS28:1;
6388                 uint32_t EMIOS27:1;
6389                 uint32_t EMIOS26:1;
6390                 uint32_t EMIOS25:1;
6391                 uint32_t EMIOS24:1;
6392                 uint32_t EMIOS23:1;
6393                 uint32_t EMIOS22:1;
6394                 uint32_t EMIOS21:1;
6395                 uint32_t EMIOS20:1;
6396                 uint32_t EMIOS19:1;
6397                 uint32_t EMIOS18:1;
6398                 uint32_t EMIOS17:1;
6399                 uint32_t EMIOS16:1;
6400                 uint32_t EMIOS15:1;
6401                 uint32_t EMIOS14:1;
6402                 uint32_t EMIOS13:1;
6403                 uint32_t EMIOS12:1;
6404                 uint32_t EMIOS11:1;
6405                 uint32_t EMIOS10:1;
6406                 uint32_t EMIOS9:1;
6407                 uint32_t EMIOS8:1;
6408                 uint32_t EMIOS7:1;
6409                 uint32_t EMIOS6:1;
6410                 uint32_t EMIOS5:1;
6411                 uint32_t EMIOS4:1;
6412                 uint32_t EMIOS3:1;
6413                 uint32_t EMIOS2:1;
6414                 uint32_t EMIOS1:1;
6415                 uint32_t EMIOS0:1;
6416             } B;
6417         } EMIOSD;               /* EMIOS D Select Register */
6418
6419         union {
6420             uint32_t R;
6421             struct {
6422                 uint32_t DSPIDH31:1;
6423                 uint32_t DSPIDH30:1;
6424                 uint32_t DSPIDH29:1;
6425                 uint32_t DSPIDH28:1;
6426                 uint32_t DSPIDH27:1;
6427                 uint32_t DSPIDH26:1;
6428                 uint32_t DSPIDH25:1;
6429                 uint32_t DSPIDH24:1;
6430                 uint32_t DSPIDH23:1;
6431                 uint32_t DSPIDH22:1;
6432                 uint32_t DSPIDH21:1;
6433                 uint32_t DSPIDH20:1;
6434                 uint32_t DSPIDH19:1;
6435                 uint32_t DSPIDH18:1;
6436                 uint32_t DSPIDH17:1;
6437                 uint32_t DSPIDH16:1;
6438                 uint32_t DSPIDL15:1;
6439                 uint32_t DSPIDL14:1;
6440                 uint32_t DSPIDL13:1;
6441                 uint32_t DSPIDL12:1;
6442                 uint32_t DSPIDL11:1;
6443                 uint32_t DSPIDL10:1;
6444                 uint32_t DSPIDL9:1;
6445                 uint32_t DSPIDL8:1;
6446                 uint32_t DSPIDL7:1;
6447                 uint32_t DSPIDL6:1;
6448                 uint32_t DSPIDL5:1;
6449                 uint32_t DSPIDL4:1;
6450                 uint32_t DSPIDL3:1;
6451                 uint32_t DSPIDL2:1;
6452                 uint32_t DSPIDL1:1;
6453                 uint32_t DSPIDL0:1;
6454             } B;
6455         } DSPIDHLD;             /* DSPIAH/L Select Register for DSPI D */
6456
6457     };                          /* end of SIU_tag */
6458 /**************************************************************************/
6459 /*                          MODULE : STM                                  */
6460 /**************************************************************************/
6461     struct STM_tag {
6462
6463         union {
6464             uint32_t R;
6465             struct {
6466                 uint32_t:16;
6467                 uint32_t CPS:8;
6468                   uint32_t:6;
6469                 uint32_t FRZ:1;
6470                 uint32_t TEN:1;
6471             } B;
6472         } CR;                   /* STM Control Register */
6473
6474         union {
6475             uint32_t R;
6476         } CNT;                  /* STM Count Register */
6477
6478         int32_t STM_reserved[2];
6479
6480         union {
6481             uint32_t R;
6482             struct {
6483                 uint32_t:31;
6484                 uint32_t CEN:1;
6485             } B;
6486         } CCR0;                 /* STM Channel Control Register 0 */
6487
6488         union {
6489             uint32_t R;
6490             struct {
6491                 uint32_t:31;
6492                 uint32_t CIF:1;
6493             } B;
6494         } CIR0;                 /* STM Channel Interrupt Register 0 */
6495
6496         union {
6497             uint32_t R;
6498         } CMP0;                 /* STM Channel Compare Register 0 */
6499
6500         int32_t STM_reserved1;
6501
6502         union {
6503             uint32_t R;
6504             struct {
6505                 uint32_t:31;
6506                 uint32_t CEN:1;
6507             } B;
6508         } CCR1;                 /* STM Channel Control Register 1 */
6509
6510         union {
6511             uint32_t R;
6512             struct {
6513                 uint32_t:31;
6514                 uint32_t CIF:1;
6515             } B;
6516         } CIR1;                 /* STM Channel Interrupt Register 1 */
6517
6518         union {
6519             uint32_t R;
6520         } CMP1;                 /* STM Channel Compare Register 1 */
6521
6522         int32_t STM_reserved2;
6523
6524         union {
6525             uint32_t R;
6526             struct {
6527                 uint32_t:31;
6528                 uint32_t CEN:1;
6529             } B;
6530         } CCR2;                 /* STM Channel Control Register 2 */
6531
6532         union {
6533             uint32_t R;
6534             struct {
6535                 uint32_t:31;
6536                 uint32_t CIF:1;
6537             } B;
6538         } CIR2;                 /* STM Channel Interrupt Register 2 */
6539
6540         union {
6541             uint32_t R;
6542         } CMP2;                 /* STM Channel Compare Register 2 */
6543
6544         int32_t STM_reserved3;
6545
6546         union {
6547             uint32_t R;
6548             struct {
6549                 uint32_t:31;
6550                 uint32_t CEN:1;
6551             } B;
6552         } CCR3;                 /* STM Channel Control Register 3 */
6553
6554         union {
6555             uint32_t R;
6556             struct {
6557                 uint32_t:31;
6558                 uint32_t CIF:1;
6559             } B;
6560         } CIR3;                 /* STM Channel Interrupt Register 3 */
6561
6562         union {
6563             uint32_t R;
6564         } CMP3;                 /* STM Channel Compare Register 3 */
6565
6566     };                          /* end of STM_tag */
6567 /**************************************************************************/
6568 /*                          MODULE : SWT                                  */
6569 /**************************************************************************/
6570     struct SWT_tag {
6571         union {
6572             uint32_t R;
6573             struct {
6574                 uint32_t MAP0:1;
6575                 uint32_t MAP1:1;
6576                 uint32_t MAP2:1;
6577                 uint32_t MAP3:1;
6578                 uint32_t MAP4:1;
6579                 uint32_t MAP5:1;
6580                 uint32_t MAP6:1;
6581                 uint32_t MAP7:1;
6582                   uint32_t:14;
6583                 uint32_t KEY:1;
6584                 uint32_t RIA:1;
6585                 uint32_t WND:1;
6586                 uint32_t ITR:1;
6587                 uint32_t HLK:1;
6588                 uint32_t SLK:1;
6589                   uint32_t:2;
6590                 uint32_t FRZ:1;
6591                 uint32_t WEN:1;
6592             } B;
6593         } CR;                   /* SWT Control Register */
6594
6595         union {
6596             uint32_t R;
6597             struct {
6598                 uint32_t:31;
6599                 uint32_t TIF:1;
6600             } B;
6601         } IR;                   /* SWT Interrupt Register */
6602
6603         union {
6604             uint32_t R;
6605             struct {
6606                 uint32_t WTO:32;
6607             } B;
6608         } TO;                   /* SWT Time-Out Register */
6609
6610         union {
6611             uint32_t R;
6612             struct {
6613                 uint32_t WST:32;
6614             } B;
6615         } WN;                   /* SWT Window Register */
6616
6617         union {
6618             uint32_t R;
6619             struct {
6620                 uint32_t:16;
6621                 uint32_t WSC:16;
6622             } B;
6623         } SR;                   /* SWT Service Register */
6624
6625         union {
6626             uint32_t R;
6627             struct {
6628                 uint32_t CNT:32;
6629             } B;
6630         } CO;                   /* SWT Counter Output Register */
6631
6632         union {
6633             uint32_t R;
6634             struct {
6635                 uint32_t:16;
6636                 uint32_t SK:16;
6637             } B;
6638         } SK;                   /* SWT Service Key Register */
6639
6640     };                          /* end of SWT_tag */
6641
6642 /* Define memories */
6643
6644 #define SRAM0_START   0x40000000UL
6645 #define SRAM0_SIZE       0x80000UL
6646 #define SRAM0_END     0x4007FFFFUL
6647
6648 #define SRAM1_START   0x40080000UL
6649 #define SRAM1_SIZE       0x14000UL
6650 #define SRAM1_END     0x40093FFFUL
6651
6652 #define FLASH_START         0x0UL
6653 #define FLASH_SIZE     0x200000UL
6654 #define FLASH_END      0x1FFFFFUL
6655
6656 /* Define instances of modules AIPS_A */
6657 #define MLB       (*(volatile struct MLB_tag *)       0xC3F84000UL)
6658 #define I2C_C     (*(volatile struct I2C_tag *)       0xC3F88000UL)
6659 #define I2C_D     (*(volatile struct I2C_tag *)       0xC3F8C000UL)
6660 #define DSPI_C    (*(volatile struct DSPI_tag *)      0xC3F90000UL)
6661 #define DSPI_D    (*(volatile struct DSPI_tag *)      0xC3F94000UL)
6662 #define ESCI_J    (*(volatile struct ESCI_tag *)      0xC3FA0000UL)
6663 #define ESCI_K    (*(volatile struct ESCI_tag *)      0xC3FA4000UL)
6664 #define ESCI_L    (*(volatile struct ESCI_tag *)      0xC3FA8000UL)
6665 #define ESCI_M    (*(volatile struct ESCI_tag *)      0xC3FAC000UL)
6666 #define FR        (*(volatile struct FR_tag *)        0xC3FDC000UL)
6667
6668 /* Define instances of modules AIPS_B */
6669 #define XBAR      (*(volatile struct XBAR_tag *)      0xFFF04000UL)
6670 #define SEMA4     (*(volatile struct SEMA4_tag *)     0xFFF10000UL)
6671 #define MPU       (*(volatile struct MPU_tag *)       0xFFF14000UL)
6672 #define SWT       (*(volatile struct SWT_tag *)       0xFFF38000UL)
6673 #define STM       (*(volatile struct STM_tag *)       0xFFF3C000UL)
6674 #define ECSM      (*(volatile struct ECSM_tag *)      0xFFF40000UL)
6675 #define EDMA      (*(volatile struct EDMA_tag *)      0xFFF44000UL)
6676 #define INTC      (*(volatile struct INTC_tag *)      0xFFF48000UL)
6677 #define FEC       (*(volatile struct FEC_tag *)       0xFFF4C000UL)
6678 #define ADC       (*(volatile struct ADC_tag *)       0xFFF80000UL)
6679 #define I2C_A     (*(volatile struct I2C_tag *)       0xFFF88000UL)
6680 #define I2C_B     (*(volatile struct I2C_tag *)       0xFFF8C000UL)
6681 #define DSPI_A    (*(volatile struct DSPI_tag *)      0xFFF90000UL)
6682 #define DSPI_B    (*(volatile struct DSPI_tag *)      0xFFF94000UL)
6683 #define ESCI_A    (*(volatile struct ESCI_tag *)      0xFFFA0000UL)
6684 #define ESCI_B    (*(volatile struct ESCI_tag *)      0xFFFA4000UL)
6685 #define ESCI_C    (*(volatile struct ESCI_tag *)      0xFFFA8000UL)
6686 #define ESCI_D    (*(volatile struct ESCI_tag *)      0xFFFAC000UL)
6687 #define ESCI_E    (*(volatile struct ESCI_tag *)      0xFFFB0000UL)
6688 #define ESCI_F    (*(volatile struct ESCI_tag *)      0xFFFB4000UL)
6689 #define ESCI_G    (*(volatile struct ESCI_tag *)      0xFFFB8000UL)
6690 #define ESCI_H    (*(volatile struct ESCI_tag *)      0xFFFBC000UL)
6691 #define CAN_A     (*(volatile struct FLEXCAN_tag *)   0xFFFC0000UL)
6692 #define CAN_B     (*(volatile struct FLEXCAN_tag *)   0xFFFC4000UL)
6693 #define CAN_C     (*(volatile struct FLEXCAN_tag *)   0xFFFC8000UL)
6694 #define CAN_D     (*(volatile struct FLEXCAN_tag *)   0xFFFCC000UL)
6695 #define CAN_E     (*(volatile struct FLEXCAN_tag *)   0xFFFD0000UL)
6696 #define CAN_F     (*(volatile struct FLEXCAN_tag *)   0xFFFD4000UL)
6697 #define CTU       (*(volatile struct CTU_tag *)       0xFFFD8000UL)
6698 #define DMAMUX    (*(volatile struct DMAMUX_tag *)    0xFFFDC000UL)
6699 #define PIT       (*(volatile struct PIT_tag *)       0xFFFE0000UL)
6700 #define PIT_RTI   (*(volatile struct PIT_tag *)       0xFFFE0000UL)
6701 #define EMIOS     (*(volatile struct EMIOS_tag *)     0xFFFE4000UL)
6702 #define SIU       (*(volatile struct SIU_tag *)       0xFFFE8000UL)
6703 #define CRP       (*(volatile struct CRP_tag *)       0xFFFEC000UL)
6704 #define FMPLL     (*(volatile struct FMPLL_tag *)     0xFFFF0000UL)
6705 #define FLASH     (*(volatile struct FLASH_tag *)     0xFFFF8000UL)
6706
6707 #ifdef __MWERKS__
6708 #pragma pop
6709 #endif
6710
6711 #ifdef  __cplusplus
6712 }
6713 #endif
6714 #endif /* ASM */
6715 #endif                          /* ifdef _MPC5668_H */