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File indexing completed on 2025-05-11 08:23:55
0001 /* 0002 * Modifications of the original file provided by Freescale Semiconductor and 0003 * ST Microelectronics are: 0004 * 0005 * Copyright (c) 2011 embedded brains GmbH & Co. KG 0006 * 0007 * Redistribution and use in source and binary forms, with or without 0008 * modification, are permitted provided that the following conditions 0009 * are met: 0010 * 1. Redistributions of source code must retain the above copyright 0011 * notice, this list of conditions and the following disclaimer. 0012 * 2. Redistributions in binary form must reproduce the above copyright 0013 * notice, this list of conditions and the following disclaimer in the 0014 * documentation and/or other materials provided with the distribution. 0015 * 0016 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 0017 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 0018 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 0019 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 0020 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 0021 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 0022 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 0023 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 0024 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 0025 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 0026 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0027 */ 0028 0029 /****************************************************************************\ 0030 * PROJECT : MPC5643L 0031 * FILE : mpc5643l.h 0032 * 0033 * DESCRIPTION : This is the header file describing the register 0034 * set for the named projects. 0035 * 0036 * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics 0037 * 0038 * VERSION : 1.04 0039 * RELEASE DATE : Tue Dec 1 2009 0040 * CREATION DATE : Thu Oct 8 13:53:51 CEST 2009 0041 * AUTHOR : generated from IP-XACT database 0042 * HISTORY : Preliminary release. 0043 \****************************************************************************/ 0044 0045 /* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */ 0046 0047 /****************************************************************************\ 0048 * Example instantiation and use: 0049 * 0050 * <MODULE>.<REGISTER>.B.<BIT> = 1; 0051 * <MODULE>.<REGISTER>.R = 0x10000000; 0052 * 0053 \****************************************************************************/ 0054 0055 /* 0056 * LICENSE: 0057 * Copyright (c) 2006 Freescale Semiconductor 0058 * 0059 * Permission is hereby granted, free of charge, to any person 0060 * obtaining a copy of this software and associated documentation 0061 * files (the "Software"), to deal in the Software without 0062 * restriction, including without limitation the rights to use, 0063 * copy, modify, merge, publish, distribute, sublicense, and/or 0064 * sell copies of the Software, and to permit persons to whom the 0065 * Software is furnished to do so, subject to the following 0066 * conditions: 0067 * 0068 * The above copyright notice and this permission notice 0069 * shall be included in all copies or substantial portions 0070 * of the Software. 0071 * 0072 * THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 0073 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 0074 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 0075 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 0076 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 0077 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 0078 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 0079 * DEALINGS IN THE SOFTWARE. 0080 * 0081 */ 0082 0083 #ifndef _leopard_H_ /* prevents multiple inclusions of this file */ 0084 #define _leopard_H_ 0085 0086 #ifndef ASM 0087 0088 #include <stdint.h> 0089 0090 #include <mpc55xx/regs-edma.h> 0091 0092 #ifdef __cplusplus 0093 extern "C" { 0094 #endif 0095 0096 #ifdef __MWERKS__ 0097 #pragma push 0098 #pragma ANSI_strict off 0099 #endif 0100 0101 //#define USE_FIELD_ALIASES_CFLASH 0102 //#define USE_FIELD_ALIASES_SIUL 0103 //#define USE_FIELD_ALIASES_SSCM 0104 //#define USE_FIELD_ALIASES_ME 0105 //#define USE_FIELD_ALIASES_RGM 0106 //#define USE_FIELD_ALIASES_ADC 0107 //#define USE_FIELD_ALIASES_CTU 0108 //#define USE_FIELD_ALIASES_mcTIMER 0109 //#define USE_FIELD_ALIASES_mcPWM 0110 //#define USE_FIELD_ALIASES_LINFLEX 0111 //#define USE_FIELD_ALIASES_SPP_MCM 0112 #define USE_FIELD_ALIASES_INTC 0113 #define USE_FIELD_ALIASES_DSPI 0114 //#define USE_FIELD_ALIASES_FLEXCAN 0115 //#define USE_FIELD_ALIASES_FR 0116 //#define USE_FIELD_ALIASES_CMU 0117 //#define USE_FIELD_ALIASES_PLLD 0118 //#define USE_FIELD_ALIASES_SPP_DMA2 0119 0120 /* Define memories */ 0121 0122 #define SRAM_START 0x40000000 0123 #define SRAM_SIZE 0x20000 0124 #define SRAM_END 0x4001FFFF 0125 0126 #define FLASH_START 0x0 0127 #define FLASH_SIZE 0xC0000 0128 #define FLASH_END 0xBFFFF 0129 0130 /****************************************************************/ 0131 /* */ 0132 /* Global definitions and aliases */ 0133 /* */ 0134 /****************************************************************/ 0135 0136 /* 0137 Platform blocks that are only accessible by the second core (core 1) when 0138 the device is in DPM mode. The block definition is equivalent to the one 0139 for the first core (core 0) and reuses the related block structure. 0140 0141 NOTE: the <block_name>_1 defines are the preferred method for programming 0142 */ 0143 #define PBRIDGE_1 (*(volatile PBRIDGE_tag*) 0x8FF00000UL) 0144 #define MAX_1 (*(volatile MAX_tag*) 0x8FF04000UL) 0145 #define MPU_1 (*(volatile MPU_tag*) 0x8FF10000UL) 0146 #define SEMA4_1 (*(volatile SEMA4_tag*) 0x8FF24000UL) 0147 #define SWT_1 (*(volatile SWT_tag*) 0x8FF38000UL) 0148 #define STM_1 (*(volatile STM_tag*) 0x8FF3C000UL) 0149 #define SPP_MCM_1 (*(volatile SPP_MCM_tag*) 0x8FF40000UL) 0150 #define SPP_DMA2_1 (*(volatile SPP_DMA2_tag*) 0x8FF44000UL) 0151 #define INTC_1 (*(volatile INTC_tag*) 0x8FF48000UL) 0152 0153 /* 0154 Platform blocks that are only accessible by the second core (core 1) when 0155 the device is in DPM mode. The block definition is equivalent to the one 0156 for the first core (core 0) and reuses the related block structure. 0157 0158 NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for 0159 programming the corresponding blocks for new code instead. 0160 */ 0161 #define PBRIDGE_DPM PBRIDGE_1 0162 #define MAX_DPM MAX_1 0163 #define MPU_DPM MPU_1 0164 #define SEMA4_DPM SEMA4_1 0165 #define SWT_DPM SWT_1 0166 #define STM_DPM STM_1 0167 #define SPP_MCM_DPM SPP_MCM_1 0168 #define SPP_DMA2_DPM SPP_DMA2_1 0169 #define INTC_DPM INTC_1 0170 0171 /* Aliases for Pictus Module names */ 0172 #define CAN_0 FLEXCAN_A 0173 #define CAN_1 FLEXCAN_B 0174 #define CTU_0 CTU 0175 #define DFLASH CRC 0176 #define DMAMUX DMA_CH_MUX 0177 #define DSPI_0 DSPI_A 0178 #define DSPI_1 DSPI_B 0179 #define DSPI_2 DSPI_C 0180 #define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) 0181 #define ETIMER_0 mcTIMER0 0182 #define ETIMER_1 mcTIMER1 0183 #define FLEXPWM_0 mcPWM_A 0184 #define FLEXPWM_1 mcPWM_B 0185 #define LINFLEX_0 LINFLEX0 0186 #define LINFLEX_1 LINFLEX1 0187 #define MCM_ SPP_MCM 0188 #define PIT PIT_RTI 0189 #define SIU SIUL 0190 #define WKUP WKPU 0191 #define ADC_0 ADC0 0192 #define ADC_1 ADC1 0193 0194 /* Other Aliases */ 0195 #define AIPS_DPM PBRIDGE_1 0196 #define AIPS_1 PBRIDGE_1 0197 #define AIPS PBRIDGE 0198 0199 /****************************************************************/ 0200 /* */ 0201 /* Module: CFLASH_SHADOW */ 0202 /* */ 0203 /****************************************************************/ 0204 0205 0206 /* Register layout for all registers NVPWD... */ 0207 0208 typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ 0209 uint32_t R; 0210 struct { 0211 uint32_t PWD:32; /* PassWorD */ 0212 } B; 0213 } CFLASH_SHADOW_NVPWD_32B_tag; 0214 0215 0216 /* Register layout for all registers NVSCI... */ 0217 0218 typedef union { /* NVSCI - Non Volatile System Censoring Information Register */ 0219 uint32_t R; 0220 struct { 0221 uint32_t SC:16; /* Serial Censorship Control Word */ 0222 uint32_t CW:16; /* Censorship Control Word */ 0223 } B; 0224 } CFLASH_SHADOW_NVSCI_32B_tag; 0225 0226 typedef union { /* Non Volatile LML Default Value */ 0227 uint32_t R; 0228 } CFLASH_SHADOW_NVLML_32B_tag; 0229 0230 typedef union { /* Non Volatile HBL Default Value */ 0231 uint32_t R; 0232 } CFLASH_SHADOW_NVHBL_32B_tag; 0233 0234 typedef union { /* Non Volatile SLL Default Value */ 0235 uint32_t R; 0236 } CFLASH_SHADOW_NVSLL_32B_tag; 0237 0238 0239 /* Register layout for all registers NVBIU... */ 0240 0241 typedef union { /* Non Volatile Bus Interface Unit Register */ 0242 uint32_t R; 0243 struct { 0244 uint32_t BI:32; /* Bus interface Unit */ 0245 } B; 0246 } CFLASH_SHADOW_NVBIU_32B_tag; 0247 0248 typedef union { /* NVUSRO - Non Volatile USeR Options Register */ 0249 uint32_t R; 0250 struct { 0251 uint32_t UO:32; /* User Options */ 0252 } B; 0253 } CFLASH_SHADOW_NVUSRO_32B_tag; 0254 0255 0256 typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag { 0257 0258 /* Non Volatile Bus Interface Unit Register */ 0259 CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */ 0260 int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4]; 0261 0262 } CFLASH_SHADOW_BIU_DEFAULTS_tag; 0263 0264 0265 typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */ 0266 int8_t CFLASH_SHADOW_reserved_0000_C[15832]; 0267 union { 0268 /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ 0269 CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */ 0270 0271 struct { 0272 /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ 0273 CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */ 0274 CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */ 0275 }; 0276 0277 }; 0278 union { 0279 /* NVSCI - Non Volatile System Censoring Information Register */ 0280 CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */ 0281 0282 struct { 0283 /* NVSCI - Non Volatile System Censoring Information Register */ 0284 CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */ 0285 CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */ 0286 }; 0287 0288 }; 0289 /* Non Volatile LML Default Value */ 0290 CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */ 0291 int8_t CFLASH_SHADOW_reserved_3DEC[4]; 0292 /* Non Volatile HBL Default Value */ 0293 CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */ 0294 int8_t CFLASH_SHADOW_reserved_3DF4[4]; 0295 /* Non Volatile SLL Default Value */ 0296 CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */ 0297 int8_t CFLASH_SHADOW_reserved_3DFC_C[4]; 0298 union { 0299 /* Register set BIU_DEFAULTS */ 0300 CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */ 0301 0302 struct { 0303 /* Non Volatile Bus Interface Unit Register */ 0304 CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */ 0305 int8_t CFLASH_SHADOW_reserved_3E04_I1[4]; 0306 CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */ 0307 int8_t CFLASH_SHADOW_reserved_3E0C_I1[4]; 0308 CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */ 0309 int8_t CFLASH_SHADOW_reserved_3E14_E1[4]; 0310 }; 0311 0312 }; 0313 /* NVUSRO - Non Volatile USeR Options Register */ 0314 CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */ 0315 } CFLASH_SHADOW_tag; 0316 0317 0318 #define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL) 0319 0320 0321 0322 /****************************************************************/ 0323 /* */ 0324 /* Module: CFLASH */ 0325 /* */ 0326 /****************************************************************/ 0327 0328 typedef union { /* MCR - Module Configuration Register */ 0329 uint32_t R; 0330 struct { 0331 uint32_t:5; 0332 uint32_t SIZE:3; /* Array Space Size */ 0333 uint32_t:1; 0334 uint32_t LAS:3; /* Low Address Space */ 0335 uint32_t:3; 0336 uint32_t MAS:1; /* Mid Address Space Configuration */ 0337 uint32_t EER:1; /* ECC Event Error */ 0338 uint32_t RWE:1; /* Read-while-Write Event Error */ 0339 uint32_t SBC:1; /* Single Bit Correction */ 0340 uint32_t:1; 0341 uint32_t PEAS:1; /* Program/Erase Access Space */ 0342 uint32_t DONE:1; /* modify operation DONE */ 0343 uint32_t PEG:1; /* Program/Erase Good */ 0344 uint32_t:4; 0345 uint32_t PGM:1; /* Program Bit */ 0346 uint32_t PSUS:1; /* Program Suspend */ 0347 uint32_t ERS:1; /* Erase Bit */ 0348 uint32_t ESUS:1; /* Erase Suspend */ 0349 uint32_t EHV:1; /* Enable High Voltage */ 0350 } B; 0351 } CFLASH_MCR_32B_tag; 0352 0353 typedef union { /* LML - Low/Mid Address Space Block Locking Register */ 0354 uint32_t R; 0355 struct { 0356 uint32_t LME:1; /* Low/Mid Address Space Block Enable */ 0357 uint32_t:10; 0358 #ifndef USE_FIELD_ALIASES_CFLASH 0359 uint32_t SLOCK:1; /* Shadow Address Space Block Lock */ 0360 #else 0361 uint32_t TSLK:1; /* deprecated name - please avoid */ 0362 #endif 0363 uint32_t:2; 0364 #ifndef USE_FIELD_ALIASES_CFLASH 0365 uint32_t MLOCK:2; /* Mid Address Space Block Lock */ 0366 #else 0367 uint32_t MLK:2; /* deprecated name - please avoid */ 0368 #endif 0369 uint32_t:6; 0370 uint32_t LLOCK:10; /* Low Address Space Block Lock */ 0371 } B; 0372 } CFLASH_LML_32B_tag; 0373 0374 typedef union { /* HBL - High Address Space Block Locking Register */ 0375 uint32_t R; 0376 struct { 0377 uint32_t HBE:1; /* High Address Space Block Enable */ 0378 uint32_t:25; 0379 uint32_t HLOCK:6; /* High Address Space Block Lock */ 0380 } B; 0381 } CFLASH_HBL_32B_tag; 0382 0383 typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */ 0384 uint32_t R; 0385 struct { 0386 uint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */ 0387 uint32_t:10; 0388 #ifndef USE_FIELD_ALIASES_CFLASH 0389 uint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */ 0390 #else 0391 uint32_t STSLK:1; /* deprecated name - please avoid */ 0392 #endif 0393 uint32_t:2; 0394 #ifndef USE_FIELD_ALIASES_CFLASH 0395 uint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */ 0396 #else 0397 uint32_t SMK:2; /* deprecated name - please avoid */ 0398 #endif 0399 uint32_t:6; 0400 uint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */ 0401 } B; 0402 } CFLASH_SLL_32B_tag; 0403 0404 typedef union { /* LMS - Low/Mid Address Space Block Select Register */ 0405 uint32_t R; 0406 struct { 0407 uint32_t:14; 0408 uint32_t MSL:2; /* Mid Address Space Block Select */ 0409 uint32_t:6; 0410 uint32_t LSL:10; /* Low Address Space Block Select */ 0411 } B; 0412 } CFLASH_LMS_32B_tag; 0413 0414 typedef union { /* HBS - High Address Space Block Select Register */ 0415 uint32_t R; 0416 struct { 0417 uint32_t:26; 0418 uint32_t HSL:6; /* High Address Space Block Select */ 0419 } B; 0420 } CFLASH_HBS_32B_tag; 0421 0422 typedef union { /* ADR - Address Register */ 0423 uint32_t R; 0424 struct { 0425 uint32_t SAD:1; /* Shadow Address */ 0426 uint32_t:10; 0427 uint32_t ADDR:18; /* Address */ 0428 uint32_t:3; 0429 } B; 0430 } CFLASH_ADR_32B_tag; 0431 0432 typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ 0433 uint32_t R; 0434 struct { 0435 #ifndef USE_FIELD_ALIASES_CFLASH 0436 uint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */ 0437 #else 0438 uint32_t BK0_APC:5; /* deprecated name - please avoid */ 0439 #endif 0440 #ifndef USE_FIELD_ALIASES_CFLASH 0441 uint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */ 0442 #else 0443 uint32_t BK0_WWSC:5; /* deprecated name - please avoid */ 0444 #endif 0445 #ifndef USE_FIELD_ALIASES_CFLASH 0446 uint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */ 0447 #else 0448 uint32_t BK0_RWSC:5; /* deprecated name - please avoid */ 0449 #endif 0450 #ifndef USE_FIELD_ALIASES_CFLASH 0451 uint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */ 0452 #else 0453 uint32_t BK0_RWWC2:1; /* deprecated name - please avoid */ 0454 #endif 0455 #ifndef USE_FIELD_ALIASES_CFLASH 0456 uint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */ 0457 #else 0458 uint32_t BK0_RWWC1:1; /* deprecated name - please avoid */ 0459 #endif 0460 #ifndef USE_FIELD_ALIASES_CFLASH 0461 uint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */ 0462 #else 0463 uint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */ 0464 #endif 0465 #ifndef USE_FIELD_ALIASES_CFLASH 0466 uint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */ 0467 #else 0468 uint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */ 0469 #endif 0470 #ifndef USE_FIELD_ALIASES_CFLASH 0471 uint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */ 0472 #else 0473 uint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */ 0474 #endif 0475 #ifndef USE_FIELD_ALIASES_CFLASH 0476 uint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */ 0477 #else 0478 uint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */ 0479 #endif 0480 #ifndef USE_FIELD_ALIASES_CFLASH 0481 uint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */ 0482 #else 0483 uint32_t B0_P1_BFE:1; /* deprecated name - please avoid */ 0484 #endif 0485 #ifndef USE_FIELD_ALIASES_CFLASH 0486 uint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */ 0487 #else 0488 uint32_t BK0_RWWC0:1; /* deprecated name - please avoid */ 0489 #endif 0490 #ifndef USE_FIELD_ALIASES_CFLASH 0491 uint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */ 0492 #else 0493 uint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */ 0494 #endif 0495 #ifndef USE_FIELD_ALIASES_CFLASH 0496 uint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */ 0497 #else 0498 uint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */ 0499 #endif 0500 #ifndef USE_FIELD_ALIASES_CFLASH 0501 uint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */ 0502 #else 0503 uint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */ 0504 #endif 0505 #ifndef USE_FIELD_ALIASES_CFLASH 0506 uint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */ 0507 #else 0508 uint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */ 0509 #endif 0510 #ifndef USE_FIELD_ALIASES_CFLASH 0511 uint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */ 0512 #else 0513 uint32_t B0_P0_BFE:1; /* deprecated name - please avoid */ 0514 #endif 0515 } B; 0516 } CFLASH_PFCR0_32B_tag; 0517 0518 0519 /* Register layout for all registers BIU... */ 0520 0521 typedef union { /* Bus Interface Unit Register */ 0522 uint32_t R; 0523 } CFLASH_BIU_32B_tag; 0524 0525 typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ 0526 uint32_t R; 0527 struct { 0528 #ifndef USE_FIELD_ALIASES_CFLASH 0529 uint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */ 0530 uint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */ 0531 uint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */ 0532 uint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */ 0533 uint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */ 0534 uint32_t:6; 0535 uint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */ 0536 uint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */ 0537 uint32_t:6; 0538 uint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */ 0539 #else 0540 uint32_t BK1_APC:5; 0541 uint32_t BK1_WWSC:5; 0542 uint32_t BK1_RWSC:5; 0543 uint32_t BK1_RWWC2:1; 0544 uint32_t BK1_RWWC1:1; 0545 uint32_t:6; 0546 uint32_t B0_P1_BFE:1; 0547 uint32_t BK1_RWWC0:1; 0548 uint32_t:6; 0549 uint32_t B1_P0_BFE:1; 0550 #endif 0551 } B; 0552 } CFLASH_PFCR1_32B_tag; 0553 0554 typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ 0555 uint32_t R; 0556 struct { 0557 uint32_t:6; 0558 uint32_t ARBM:2; /* Arbitration Mode */ 0559 uint32_t M7PFD:1; /* Master x Prefetch Disable */ 0560 uint32_t M6PFD:1; /* Master x Prefetch Disable */ 0561 uint32_t M5PFD:1; /* Master x Prefetch Disable */ 0562 uint32_t M4PFD:1; /* Master x Prefetch Disable */ 0563 uint32_t M3PFD:1; /* Master x Prefetch Disable */ 0564 uint32_t M2PFD:1; /* Master x Prefetch Disable */ 0565 uint32_t M1PFD:1; /* Master x Prefetch Disable */ 0566 uint32_t M0PFD:1; /* Master x Prefetch Disable */ 0567 uint32_t M7AP:2; /* Master 7 Access Protection */ 0568 uint32_t M6AP:2; /* Master 6 Access Protection */ 0569 uint32_t M5AP:2; /* Master 5 Access Protection */ 0570 uint32_t M4AP:2; /* Master 4 Access Protection */ 0571 uint32_t M3AP:2; /* Master 3 Access Protection */ 0572 uint32_t M2AP:2; /* Master 2 Access Protection */ 0573 uint32_t M1AP:2; /* Master 1 Access Protection */ 0574 uint32_t M0AP:2; /* Master 0 Access Protection */ 0575 } B; 0576 } CFLASH_PFAPR_32B_tag; 0577 0578 typedef union { /* UT0 - User Test Register */ 0579 uint32_t R; 0580 struct { 0581 uint32_t UTE:1; /* User Test Enable */ 0582 uint32_t SBCE:1; /* Single Bit Correction Enable */ 0583 uint32_t:6; 0584 uint32_t DSI:8; /* Data Syndrome Input */ 0585 uint32_t:10; 0586 uint32_t MRE:1; /* Margin Read Enable */ 0587 uint32_t MRV:1; /* Margin Read Value */ 0588 uint32_t EIE:1; /* ECC Data Input Enable */ 0589 uint32_t AIS:1; /* Array Integrity Sequence */ 0590 uint32_t AIE:1; /* Array Integrity Enable */ 0591 uint32_t AID:1; /* Array Integrity Done */ 0592 } B; 0593 } CFLASH_UT0_32B_tag; 0594 0595 typedef union { /* UT1 - User Test Register */ 0596 uint32_t R; 0597 } CFLASH_UT1_32B_tag; 0598 0599 typedef union { /* UT2 - User Test Register */ 0600 uint32_t R; 0601 } CFLASH_UT2_32B_tag; 0602 0603 0604 /* Register layout for all registers UM... */ 0605 0606 typedef union { /* UM - User Multiple Input Signature Register */ 0607 uint32_t R; 0608 struct { 0609 #ifndef USE_FIELD_ALIASES_CFLASH 0610 uint32_t MISR:32; /* Multiple Input Signature */ 0611 #else 0612 uint32_t MS:32; /* deprecated - please avoid */ 0613 #endif 0614 } B; 0615 } CFLASH_UM_32B_tag; 0616 0617 0618 /* Register layout for generated register(s) UT... */ 0619 0620 typedef union { /* */ 0621 uint32_t R; 0622 } CFLASH_UT_32B_tag; 0623 0624 0625 /* Register layout for generated register(s) PFCR... */ 0626 0627 typedef union { /* */ 0628 uint32_t R; 0629 } CFLASH_PFCR_32B_tag; 0630 0631 0632 0633 typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */ 0634 /* MCR - Module Configuration Register */ 0635 CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ 0636 /* LML - Low/Mid Address Space Block Locking Register */ 0637 CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */ 0638 /* HBL - High Address Space Block Locking Register */ 0639 CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */ 0640 /* SLL - Secondary Low/Mid Address Space Block Locking Register */ 0641 CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */ 0642 /* LMS - Low/Mid Address Space Block Select Register */ 0643 CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */ 0644 /* HBS - High Address Space Block Select Register */ 0645 CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */ 0646 /* ADR - Address Register */ 0647 CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */ 0648 union { 0649 struct { 0650 /* */ 0651 CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */ 0652 int8_t CFLASH_reserved_0024_E0[12]; 0653 }; 0654 0655 /* Bus Interface Unit Register */ 0656 CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */ 0657 0658 struct { 0659 /* Bus Interface Unit Register */ 0660 CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */ 0661 CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */ 0662 CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */ 0663 CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */ 0664 CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */ 0665 }; 0666 0667 struct { 0668 int8_t CFLASH_reserved_001C_I3[8]; 0669 CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */ 0670 int8_t CFLASH_reserved_0028_E3[8]; 0671 }; 0672 0673 struct { 0674 /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ 0675 CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */ 0676 /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ 0677 CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */ 0678 /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ 0679 CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */ 0680 int8_t CFLASH_reserved_0028_E4[8]; 0681 }; 0682 0683 }; 0684 int8_t CFLASH_reserved_0030_C[12]; 0685 union { 0686 CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */ 0687 0688 struct { 0689 /* UT0 - User Test Register */ 0690 CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */ 0691 /* UT1 - User Test Register */ 0692 CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */ 0693 /* UT2 - User Test Register */ 0694 CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */ 0695 }; 0696 0697 }; 0698 union { 0699 CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */ 0700 0701 /* UM - User Multiple Input Signature Register */ 0702 CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */ 0703 0704 struct { 0705 /* UM - User Multiple Input Signature Register */ 0706 CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */ 0707 CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */ 0708 CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */ 0709 CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */ 0710 CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */ 0711 }; 0712 0713 }; 0714 } CFLASH_tag; 0715 0716 0717 #define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL) 0718 0719 0720 0721 /****************************************************************/ 0722 /* */ 0723 /* Module: SIUL */ 0724 /* */ 0725 /****************************************************************/ 0726 0727 typedef union { /* MIDR1 - MCU ID Register #1 */ 0728 uint32_t R; 0729 struct { 0730 uint32_t PARTNUM:16; /* MCU Part Number */ 0731 uint32_t CSP:1; /* CSP Package */ 0732 uint32_t PKG:5; /* Package Settings */ 0733 uint32_t:2; 0734 #ifndef USE_FIELD_ALIASES_SIUL 0735 uint32_t MAJOR_MASK:4; /* Major Mask Revision */ 0736 #else 0737 uint32_t MAJORMASK:4; /* deprecated name - please avoid */ 0738 #endif 0739 #ifndef USE_FIELD_ALIASES_SIUL 0740 uint32_t MINOR_MASK:4; /* Minor Mask Revision */ 0741 #else 0742 uint32_t MINORMASK:4; /* deprecated name - please avoid */ 0743 #endif 0744 } B; 0745 } SIUL_MIDR1_32B_tag; 0746 0747 typedef union { /* MIDR2 - MCU ID Register #2 */ 0748 uint32_t R; 0749 struct { 0750 uint32_t SF:1; /* Manufacturer */ 0751 uint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */ 0752 uint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */ 0753 uint32_t:7; 0754 #ifndef USE_FIELD_ALIASES_SIUL 0755 uint32_t PARTNUM2:8; /* MCU Part Number */ 0756 #else 0757 uint32_t PARTNUM:8; /* deprecated name - please avoid */ 0758 #endif 0759 uint32_t TBD:1; /* Optional Bit */ 0760 uint32_t:2; 0761 uint32_t EE:1; /* Data Flash Present */ 0762 uint32_t:3; 0763 uint32_t FR:1; /* Flexray Present */ 0764 } B; 0765 } SIUL_MIDR2_32B_tag; 0766 0767 typedef union { /* ISR - Interrupt Status Flag Register */ 0768 uint32_t R; 0769 struct { 0770 uint32_t EIF31:1; /* External Interrupt Status Flag */ 0771 uint32_t EIF30:1; /* External Interrupt Status Flag */ 0772 uint32_t EIF29:1; /* External Interrupt Status Flag */ 0773 uint32_t EIF28:1; /* External Interrupt Status Flag */ 0774 uint32_t EIF27:1; /* External Interrupt Status Flag */ 0775 uint32_t EIF26:1; /* External Interrupt Status Flag */ 0776 uint32_t EIF25:1; /* External Interrupt Status Flag */ 0777 uint32_t EIF24:1; /* External Interrupt Status Flag */ 0778 uint32_t EIF23:1; /* External Interrupt Status Flag */ 0779 uint32_t EIF22:1; /* External Interrupt Status Flag */ 0780 uint32_t EIF21:1; /* External Interrupt Status Flag */ 0781 uint32_t EIF20:1; /* External Interrupt Status Flag */ 0782 uint32_t EIF19:1; /* External Interrupt Status Flag */ 0783 uint32_t EIF18:1; /* External Interrupt Status Flag */ 0784 uint32_t EIF17:1; /* External Interrupt Status Flag */ 0785 uint32_t EIF16:1; /* External Interrupt Status Flag */ 0786 uint32_t EIF15:1; /* External Interrupt Status Flag */ 0787 uint32_t EIF14:1; /* External Interrupt Status Flag */ 0788 uint32_t EIF13:1; /* External Interrupt Status Flag */ 0789 uint32_t EIF12:1; /* External Interrupt Status Flag */ 0790 uint32_t EIF11:1; /* External Interrupt Status Flag */ 0791 uint32_t EIF10:1; /* External Interrupt Status Flag */ 0792 uint32_t EIF9:1; /* External Interrupt Status Flag */ 0793 uint32_t EIF8:1; /* External Interrupt Status Flag */ 0794 uint32_t EIF7:1; /* External Interrupt Status Flag */ 0795 uint32_t EIF6:1; /* External Interrupt Status Flag */ 0796 uint32_t EIF5:1; /* External Interrupt Status Flag */ 0797 uint32_t EIF4:1; /* External Interrupt Status Flag */ 0798 uint32_t EIF3:1; /* External Interrupt Status Flag */ 0799 uint32_t EIF2:1; /* External Interrupt Status Flag */ 0800 uint32_t EIF1:1; /* External Interrupt Status Flag */ 0801 uint32_t EIF0:1; /* External Interrupt Status Flag */ 0802 } B; 0803 } SIUL_ISR_32B_tag; 0804 0805 typedef union { /* IRER - Interrupt Request Enable Register */ 0806 uint32_t R; 0807 struct { 0808 uint32_t EIRE31:1; /* Enable External Interrupt Requests */ 0809 uint32_t EIRE30:1; /* Enable External Interrupt Requests */ 0810 uint32_t EIRE29:1; /* Enable External Interrupt Requests */ 0811 uint32_t EIRE28:1; /* Enable External Interrupt Requests */ 0812 uint32_t EIRE27:1; /* Enable External Interrupt Requests */ 0813 uint32_t EIRE26:1; /* Enable External Interrupt Requests */ 0814 uint32_t EIRE25:1; /* Enable External Interrupt Requests */ 0815 uint32_t EIRE24:1; /* Enable External Interrupt Requests */ 0816 uint32_t EIRE23:1; /* Enable External Interrupt Requests */ 0817 uint32_t EIRE22:1; /* Enable External Interrupt Requests */ 0818 uint32_t EIRE21:1; /* Enable External Interrupt Requests */ 0819 uint32_t EIRE20:1; /* Enable External Interrupt Requests */ 0820 uint32_t EIRE19:1; /* Enable External Interrupt Requests */ 0821 uint32_t EIRE18:1; /* Enable External Interrupt Requests */ 0822 uint32_t EIRE17:1; /* Enable External Interrupt Requests */ 0823 uint32_t EIRE16:1; /* Enable External Interrupt Requests */ 0824 uint32_t EIRE15:1; /* Enable External Interrupt Requests */ 0825 uint32_t EIRE14:1; /* Enable External Interrupt Requests */ 0826 uint32_t EIRE13:1; /* Enable External Interrupt Requests */ 0827 uint32_t EIRE12:1; /* Enable External Interrupt Requests */ 0828 uint32_t EIRE11:1; /* Enable External Interrupt Requests */ 0829 uint32_t EIRE10:1; /* Enable External Interrupt Requests */ 0830 uint32_t EIRE9:1; /* Enable External Interrupt Requests */ 0831 uint32_t EIRE8:1; /* Enable External Interrupt Requests */ 0832 uint32_t EIRE7:1; /* Enable External Interrupt Requests */ 0833 uint32_t EIRE6:1; /* Enable External Interrupt Requests */ 0834 uint32_t EIRE5:1; /* Enable External Interrupt Requests */ 0835 uint32_t EIRE4:1; /* Enable External Interrupt Requests */ 0836 uint32_t EIRE3:1; /* Enable External Interrupt Requests */ 0837 uint32_t EIRE2:1; /* Enable External Interrupt Requests */ 0838 uint32_t EIRE1:1; /* Enable External Interrupt Requests */ 0839 uint32_t EIRE0:1; /* Enable External Interrupt Requests */ 0840 } B; 0841 } SIUL_IRER_32B_tag; 0842 0843 typedef union { /* IREER - Interrupt Rising Edge Event Enable */ 0844 uint32_t R; 0845 struct { 0846 uint32_t IREE31:1; /* Enable rising-edge events */ 0847 uint32_t IREE30:1; /* Enable rising-edge events */ 0848 uint32_t IREE29:1; /* Enable rising-edge events */ 0849 uint32_t IREE28:1; /* Enable rising-edge events */ 0850 uint32_t IREE27:1; /* Enable rising-edge events */ 0851 uint32_t IREE26:1; /* Enable rising-edge events */ 0852 uint32_t IREE25:1; /* Enable rising-edge events */ 0853 uint32_t IREE24:1; /* Enable rising-edge events */ 0854 uint32_t IREE23:1; /* Enable rising-edge events */ 0855 uint32_t IREE22:1; /* Enable rising-edge events */ 0856 uint32_t IREE21:1; /* Enable rising-edge events */ 0857 uint32_t IREE20:1; /* Enable rising-edge events */ 0858 uint32_t IREE19:1; /* Enable rising-edge events */ 0859 uint32_t IREE18:1; /* Enable rising-edge events */ 0860 uint32_t IREE17:1; /* Enable rising-edge events */ 0861 uint32_t IREE16:1; /* Enable rising-edge events */ 0862 uint32_t IREE15:1; /* Enable rising-edge events */ 0863 uint32_t IREE14:1; /* Enable rising-edge events */ 0864 uint32_t IREE13:1; /* Enable rising-edge events */ 0865 uint32_t IREE12:1; /* Enable rising-edge events */ 0866 uint32_t IREE11:1; /* Enable rising-edge events */ 0867 uint32_t IREE10:1; /* Enable rising-edge events */ 0868 uint32_t IREE9:1; /* Enable rising-edge events */ 0869 uint32_t IREE8:1; /* Enable rising-edge events */ 0870 uint32_t IREE7:1; /* Enable rising-edge events */ 0871 uint32_t IREE6:1; /* Enable rising-edge events */ 0872 uint32_t IREE5:1; /* Enable rising-edge events */ 0873 uint32_t IREE4:1; /* Enable rising-edge events */ 0874 uint32_t IREE3:1; /* Enable rising-edge events */ 0875 uint32_t IREE2:1; /* Enable rising-edge events */ 0876 uint32_t IREE1:1; /* Enable rising-edge events */ 0877 uint32_t IREE0:1; /* Enable rising-edge events */ 0878 } B; 0879 } SIUL_IREER_32B_tag; 0880 0881 typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */ 0882 uint32_t R; 0883 struct { 0884 uint32_t IFEE31:1; /* Enable Falling Edge Events */ 0885 uint32_t IFEE30:1; /* Enable Falling Edge Events */ 0886 uint32_t IFEE29:1; /* Enable Falling Edge Events */ 0887 uint32_t IFEE28:1; /* Enable Falling Edge Events */ 0888 uint32_t IFEE27:1; /* Enable Falling Edge Events */ 0889 uint32_t IFEE26:1; /* Enable Falling Edge Events */ 0890 uint32_t IFEE25:1; /* Enable Falling Edge Events */ 0891 uint32_t IFEE24:1; /* Enable Falling Edge Events */ 0892 uint32_t IFEE23:1; /* Enable Falling Edge Events */ 0893 uint32_t IFEE22:1; /* Enable Falling Edge Events */ 0894 uint32_t IFEE21:1; /* Enable Falling Edge Events */ 0895 uint32_t IFEE20:1; /* Enable Falling Edge Events */ 0896 uint32_t IFEE19:1; /* Enable Falling Edge Events */ 0897 uint32_t IFEE18:1; /* Enable Falling Edge Events */ 0898 uint32_t IFEE17:1; /* Enable Falling Edge Events */ 0899 uint32_t IFEE16:1; /* Enable Falling Edge Events */ 0900 uint32_t IFEE15:1; /* Enable Falling Edge Events */ 0901 uint32_t IFEE14:1; /* Enable Falling Edge Events */ 0902 uint32_t IFEE13:1; /* Enable Falling Edge Events */ 0903 uint32_t IFEE12:1; /* Enable Falling Edge Events */ 0904 uint32_t IFEE11:1; /* Enable Falling Edge Events */ 0905 uint32_t IFEE10:1; /* Enable Falling Edge Events */ 0906 uint32_t IFEE9:1; /* Enable Falling Edge Events */ 0907 uint32_t IFEE8:1; /* Enable Falling Edge Events */ 0908 uint32_t IFEE7:1; /* Enable Falling Edge Events */ 0909 uint32_t IFEE6:1; /* Enable Falling Edge Events */ 0910 uint32_t IFEE5:1; /* Enable Falling Edge Events */ 0911 uint32_t IFEE4:1; /* Enable Falling Edge Events */ 0912 uint32_t IFEE3:1; /* Enable Falling Edge Events */ 0913 uint32_t IFEE2:1; /* Enable Falling Edge Events */ 0914 uint32_t IFEE1:1; /* Enable Falling Edge Events */ 0915 uint32_t IFEE0:1; /* Enable Falling Edge Events */ 0916 } B; 0917 } SIUL_IFEER_32B_tag; 0918 0919 typedef union { /* IFER Interrupt Filter Enable Register */ 0920 uint32_t R; 0921 struct { 0922 uint32_t IFE31:1; /* Enable Digital Glitch Filter */ 0923 uint32_t IFE30:1; /* Enable Digital Glitch Filter */ 0924 uint32_t IFE29:1; /* Enable Digital Glitch Filter */ 0925 uint32_t IFE28:1; /* Enable Digital Glitch Filter */ 0926 uint32_t IFE27:1; /* Enable Digital Glitch Filter */ 0927 uint32_t IFE26:1; /* Enable Digital Glitch Filter */ 0928 uint32_t IFE25:1; /* Enable Digital Glitch Filter */ 0929 uint32_t IFE24:1; /* Enable Digital Glitch Filter */ 0930 uint32_t IFE23:1; /* Enable Digital Glitch Filter */ 0931 uint32_t IFE22:1; /* Enable Digital Glitch Filter */ 0932 uint32_t IFE21:1; /* Enable Digital Glitch Filter */ 0933 uint32_t IFE20:1; /* Enable Digital Glitch Filter */ 0934 uint32_t IFE19:1; /* Enable Digital Glitch Filter */ 0935 uint32_t IFE18:1; /* Enable Digital Glitch Filter */ 0936 uint32_t IFE17:1; /* Enable Digital Glitch Filter */ 0937 uint32_t IFE16:1; /* Enable Digital Glitch Filter */ 0938 uint32_t IFE15:1; /* Enable Digital Glitch Filter */ 0939 uint32_t IFE14:1; /* Enable Digital Glitch Filter */ 0940 uint32_t IFE13:1; /* Enable Digital Glitch Filter */ 0941 uint32_t IFE12:1; /* Enable Digital Glitch Filter */ 0942 uint32_t IFE11:1; /* Enable Digital Glitch Filter */ 0943 uint32_t IFE10:1; /* Enable Digital Glitch Filter */ 0944 uint32_t IFE9:1; /* Enable Digital Glitch Filter */ 0945 uint32_t IFE8:1; /* Enable Digital Glitch Filter */ 0946 uint32_t IFE7:1; /* Enable Digital Glitch Filter */ 0947 uint32_t IFE6:1; /* Enable Digital Glitch Filter */ 0948 uint32_t IFE5:1; /* Enable Digital Glitch Filter */ 0949 uint32_t IFE4:1; /* Enable Digital Glitch Filter */ 0950 uint32_t IFE3:1; /* Enable Digital Glitch Filter */ 0951 uint32_t IFE2:1; /* Enable Digital Glitch Filter */ 0952 uint32_t IFE1:1; /* Enable Digital Glitch Filter */ 0953 uint32_t IFE0:1; /* Enable Digital Glitch Filter */ 0954 } B; 0955 } SIUL_IFER_32B_tag; 0956 0957 0958 /* Register layout for all registers PCR... */ 0959 0960 typedef union SIU_PCR_tag { /* PCR - Pad Configuration Register */ 0961 uint16_t R; 0962 struct { 0963 uint16_t:1; 0964 #ifndef USE_FIELD_ALIASES_SIUL 0965 uint16_t SMC:1; /* Safe Mode Control */ 0966 #else 0967 uint16_t SME:1; /* deprecated name - please avoid */ 0968 #endif 0969 uint16_t APC:1; /* Analog Pad Control */ 0970 uint16_t:1; 0971 uint16_t PA:2; /* Pad Output Assignment */ 0972 uint16_t OBE:1; /* Output Buffer Enable */ 0973 uint16_t IBE:1; /* Input Buffer Enable */ 0974 #ifndef USE_FIELD_ALIASES_SIUL 0975 uint16_t DSC:2; /* Drive Strength Control */ 0976 #else 0977 uint16_t DCS:2; /* deprecated name - please avoid */ 0978 #endif 0979 uint16_t ODE:1; /* Open Drain Output Enable */ 0980 uint16_t HYS:1; /* Input Hysteresis */ 0981 uint16_t SRC:2; /* Slew Rate Control */ 0982 uint16_t WPE:1; /* Weak Pull Up/Down Enable */ 0983 uint16_t WPS:1; /* Weak Pull Up/Down Select */ 0984 } B; 0985 } SIU_PCR_tag; 0986 0987 0988 /* Register layout for all registers PSMI... */ 0989 0990 typedef union SIUL_PSMI_8B_tag { /* PSMI - Pad Selection for Multiplexed Inputs */ 0991 uint8_t R; 0992 struct { 0993 uint8_t:4; 0994 uint8_t PADSEL:4; /* Pad selection for pin */ 0995 } B; 0996 } SIUL_PSMI_8B_tag; 0997 0998 0999 /* Register layout for all registers PSMI... */ 1000 1001 typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */ 1002 uint32_t R; 1003 struct { 1004 uint32_t:4; 1005 uint32_t PADSEL0:4; /* Pad selection for pin */ 1006 uint32_t:4; 1007 uint32_t PADSEL1:4; /* Pad selection for pin */ 1008 uint32_t:4; 1009 uint32_t PADSEL2:4; /* Pad selection for pin */ 1010 uint32_t:4; 1011 uint32_t PADSEL3:4; /* Pad selection for pin */ 1012 } B; 1013 } SIUL_PSMI_32B_tag; 1014 1015 1016 /* Register layout for all registers GPDO... */ 1017 1018 typedef union { /* GPDO - GPIO Pad Data Output Register */ 1019 uint8_t R; 1020 struct { 1021 uint8_t:7; 1022 uint8_t PDO:1; /* Pad Data Out */ 1023 } B; 1024 } SIUL_GPDO_8B_tag; 1025 1026 1027 /* Register layout for all registers GPDO... */ 1028 1029 typedef union { /* GPDO - GPIO Pad Data Output Register */ 1030 uint32_t R; 1031 struct { 1032 uint32_t:7; 1033 uint32_t PDO0:1; /* Pad Data Out */ 1034 uint32_t:7; 1035 uint32_t PDO1:1; /* Pad Data Out */ 1036 uint32_t:7; 1037 uint32_t PDO2:1; /* Pad Data Out */ 1038 uint32_t:7; 1039 uint32_t PDO3:1; /* Pad Data Out */ 1040 } B; 1041 } SIUL_GPDO_32B_tag; 1042 1043 1044 /* Register layout for all registers GPDI... */ 1045 1046 typedef union { /* GPDI - GPIO Pad Data Input Register */ 1047 uint8_t R; 1048 struct { 1049 uint8_t:7; 1050 uint8_t PDI:1; /* Pad Data In */ 1051 } B; 1052 } SIUL_GPDI_8B_tag; 1053 1054 1055 /* Register layout for all registers GPDI... */ 1056 1057 typedef union { /* GPDI - GPIO Pad Data Input Register */ 1058 uint32_t R; 1059 struct { 1060 uint32_t:7; 1061 uint32_t PDI0:1; /* Pad Data In */ 1062 uint32_t:7; 1063 uint32_t PDI1:1; /* Pad Data In */ 1064 uint32_t:7; 1065 uint32_t PDI2:1; /* Pad Data In */ 1066 uint32_t:7; 1067 uint32_t PDI3:1; /* Pad Data In */ 1068 } B; 1069 } SIUL_GPDI_32B_tag; 1070 1071 1072 /* Register layout for all registers PGPDO... */ 1073 1074 typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */ 1075 uint16_t R; 1076 } SIUL_PGPDO_16B_tag; 1077 1078 1079 /* Register layout for all registers PGPDI... */ 1080 1081 typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */ 1082 uint16_t R; 1083 } SIUL_PGPDI_16B_tag; 1084 1085 1086 /* Register layout for all registers MPGPDO... */ 1087 1088 typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ 1089 uint32_t R; 1090 struct { 1091 uint32_t MASK:16; /* Mask Field */ 1092 uint32_t MPPDO:16; /* Masked Parallel Pad Data Out */ 1093 } B; 1094 } SIUL_MPGPDO_32B_tag; 1095 1096 1097 /* Register layout for all registers IFMC... */ 1098 1099 typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */ 1100 uint32_t R; 1101 struct { 1102 uint32_t:28; 1103 uint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */ 1104 } B; 1105 } SIUL_IFMC_32B_tag; 1106 1107 typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */ 1108 uint32_t R; 1109 struct { 1110 uint32_t:28; 1111 uint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */ 1112 } B; 1113 } SIUL_IFCPR_32B_tag; 1114 1115 1116 1117 typedef struct SIU_tag { /* start of SIUL_tag */ 1118 int8_t SIUL_reserved_0000_C[4]; 1119 union { 1120 SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */ 1121 1122 /* MIDR1 - MCU ID Register #1 */ 1123 SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */ 1124 1125 }; 1126 /* MIDR2 - MCU ID Register #2 */ 1127 SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */ 1128 int8_t SIUL_reserved_000C[8]; 1129 /* ISR - Interrupt Status Flag Register */ 1130 SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */ 1131 /* IRER - Interrupt Request Enable Register */ 1132 SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ 1133 int8_t SIUL_reserved_001C[12]; 1134 /* IREER - Interrupt Rising Edge Event Enable */ 1135 SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */ 1136 /* IFEER - Interrupt Falling-Edge Event Enable */ 1137 SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */ 1138 /* IFER Interrupt Filter Enable Register */ 1139 SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */ 1140 int8_t SIUL_reserved_0034_C[12]; 1141 union { 1142 /* PCR - Pad Configuration Register */ 1143 SIU_PCR_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */ 1144 1145 struct { 1146 /* PCR - Pad Configuration Register */ 1147 SIU_PCR_tag PCR0; /* offset: 0x0040 size: 16 bit */ 1148 SIU_PCR_tag PCR1; /* offset: 0x0042 size: 16 bit */ 1149 SIU_PCR_tag PCR2; /* offset: 0x0044 size: 16 bit */ 1150 SIU_PCR_tag PCR3; /* offset: 0x0046 size: 16 bit */ 1151 SIU_PCR_tag PCR4; /* offset: 0x0048 size: 16 bit */ 1152 SIU_PCR_tag PCR5; /* offset: 0x004A size: 16 bit */ 1153 SIU_PCR_tag PCR6; /* offset: 0x004C size: 16 bit */ 1154 SIU_PCR_tag PCR7; /* offset: 0x004E size: 16 bit */ 1155 SIU_PCR_tag PCR8; /* offset: 0x0050 size: 16 bit */ 1156 SIU_PCR_tag PCR9; /* offset: 0x0052 size: 16 bit */ 1157 SIU_PCR_tag PCR10; /* offset: 0x0054 size: 16 bit */ 1158 SIU_PCR_tag PCR11; /* offset: 0x0056 size: 16 bit */ 1159 SIU_PCR_tag PCR12; /* offset: 0x0058 size: 16 bit */ 1160 SIU_PCR_tag PCR13; /* offset: 0x005A size: 16 bit */ 1161 SIU_PCR_tag PCR14; /* offset: 0x005C size: 16 bit */ 1162 SIU_PCR_tag PCR15; /* offset: 0x005E size: 16 bit */ 1163 SIU_PCR_tag PCR16; /* offset: 0x0060 size: 16 bit */ 1164 SIU_PCR_tag PCR17; /* offset: 0x0062 size: 16 bit */ 1165 SIU_PCR_tag PCR18; /* offset: 0x0064 size: 16 bit */ 1166 SIU_PCR_tag PCR19; /* offset: 0x0066 size: 16 bit */ 1167 SIU_PCR_tag PCR20; /* offset: 0x0068 size: 16 bit */ 1168 SIU_PCR_tag PCR21; /* offset: 0x006A size: 16 bit */ 1169 SIU_PCR_tag PCR22; /* offset: 0x006C size: 16 bit */ 1170 SIU_PCR_tag PCR23; /* offset: 0x006E size: 16 bit */ 1171 SIU_PCR_tag PCR24; /* offset: 0x0070 size: 16 bit */ 1172 SIU_PCR_tag PCR25; /* offset: 0x0072 size: 16 bit */ 1173 SIU_PCR_tag PCR26; /* offset: 0x0074 size: 16 bit */ 1174 SIU_PCR_tag PCR27; /* offset: 0x0076 size: 16 bit */ 1175 SIU_PCR_tag PCR28; /* offset: 0x0078 size: 16 bit */ 1176 SIU_PCR_tag PCR29; /* offset: 0x007A size: 16 bit */ 1177 SIU_PCR_tag PCR30; /* offset: 0x007C size: 16 bit */ 1178 SIU_PCR_tag PCR31; /* offset: 0x007E size: 16 bit */ 1179 SIU_PCR_tag PCR32; /* offset: 0x0080 size: 16 bit */ 1180 SIU_PCR_tag PCR33; /* offset: 0x0082 size: 16 bit */ 1181 SIU_PCR_tag PCR34; /* offset: 0x0084 size: 16 bit */ 1182 SIU_PCR_tag PCR35; /* offset: 0x0086 size: 16 bit */ 1183 SIU_PCR_tag PCR36; /* offset: 0x0088 size: 16 bit */ 1184 SIU_PCR_tag PCR37; /* offset: 0x008A size: 16 bit */ 1185 SIU_PCR_tag PCR38; /* offset: 0x008C size: 16 bit */ 1186 SIU_PCR_tag PCR39; /* offset: 0x008E size: 16 bit */ 1187 SIU_PCR_tag PCR40; /* offset: 0x0090 size: 16 bit */ 1188 SIU_PCR_tag PCR41; /* offset: 0x0092 size: 16 bit */ 1189 SIU_PCR_tag PCR42; /* offset: 0x0094 size: 16 bit */ 1190 SIU_PCR_tag PCR43; /* offset: 0x0096 size: 16 bit */ 1191 SIU_PCR_tag PCR44; /* offset: 0x0098 size: 16 bit */ 1192 SIU_PCR_tag PCR45; /* offset: 0x009A size: 16 bit */ 1193 SIU_PCR_tag PCR46; /* offset: 0x009C size: 16 bit */ 1194 SIU_PCR_tag PCR47; /* offset: 0x009E size: 16 bit */ 1195 SIU_PCR_tag PCR48; /* offset: 0x00A0 size: 16 bit */ 1196 SIU_PCR_tag PCR49; /* offset: 0x00A2 size: 16 bit */ 1197 SIU_PCR_tag PCR50; /* offset: 0x00A4 size: 16 bit */ 1198 SIU_PCR_tag PCR51; /* offset: 0x00A6 size: 16 bit */ 1199 SIU_PCR_tag PCR52; /* offset: 0x00A8 size: 16 bit */ 1200 SIU_PCR_tag PCR53; /* offset: 0x00AA size: 16 bit */ 1201 SIU_PCR_tag PCR54; /* offset: 0x00AC size: 16 bit */ 1202 SIU_PCR_tag PCR55; /* offset: 0x00AE size: 16 bit */ 1203 SIU_PCR_tag PCR56; /* offset: 0x00B0 size: 16 bit */ 1204 SIU_PCR_tag PCR57; /* offset: 0x00B2 size: 16 bit */ 1205 SIU_PCR_tag PCR58; /* offset: 0x00B4 size: 16 bit */ 1206 SIU_PCR_tag PCR59; /* offset: 0x00B6 size: 16 bit */ 1207 SIU_PCR_tag PCR60; /* offset: 0x00B8 size: 16 bit */ 1208 SIU_PCR_tag PCR61; /* offset: 0x00BA size: 16 bit */ 1209 SIU_PCR_tag PCR62; /* offset: 0x00BC size: 16 bit */ 1210 SIU_PCR_tag PCR63; /* offset: 0x00BE size: 16 bit */ 1211 SIU_PCR_tag PCR64; /* offset: 0x00C0 size: 16 bit */ 1212 SIU_PCR_tag PCR65; /* offset: 0x00C2 size: 16 bit */ 1213 SIU_PCR_tag PCR66; /* offset: 0x00C4 size: 16 bit */ 1214 SIU_PCR_tag PCR67; /* offset: 0x00C6 size: 16 bit */ 1215 SIU_PCR_tag PCR68; /* offset: 0x00C8 size: 16 bit */ 1216 SIU_PCR_tag PCR69; /* offset: 0x00CA size: 16 bit */ 1217 SIU_PCR_tag PCR70; /* offset: 0x00CC size: 16 bit */ 1218 SIU_PCR_tag PCR71; /* offset: 0x00CE size: 16 bit */ 1219 SIU_PCR_tag PCR72; /* offset: 0x00D0 size: 16 bit */ 1220 SIU_PCR_tag PCR73; /* offset: 0x00D2 size: 16 bit */ 1221 SIU_PCR_tag PCR74; /* offset: 0x00D4 size: 16 bit */ 1222 SIU_PCR_tag PCR75; /* offset: 0x00D6 size: 16 bit */ 1223 SIU_PCR_tag PCR76; /* offset: 0x00D8 size: 16 bit */ 1224 SIU_PCR_tag PCR77; /* offset: 0x00DA size: 16 bit */ 1225 SIU_PCR_tag PCR78; /* offset: 0x00DC size: 16 bit */ 1226 SIU_PCR_tag PCR79; /* offset: 0x00DE size: 16 bit */ 1227 SIU_PCR_tag PCR80; /* offset: 0x00E0 size: 16 bit */ 1228 SIU_PCR_tag PCR81; /* offset: 0x00E2 size: 16 bit */ 1229 SIU_PCR_tag PCR82; /* offset: 0x00E4 size: 16 bit */ 1230 SIU_PCR_tag PCR83; /* offset: 0x00E6 size: 16 bit */ 1231 SIU_PCR_tag PCR84; /* offset: 0x00E8 size: 16 bit */ 1232 SIU_PCR_tag PCR85; /* offset: 0x00EA size: 16 bit */ 1233 SIU_PCR_tag PCR86; /* offset: 0x00EC size: 16 bit */ 1234 SIU_PCR_tag PCR87; /* offset: 0x00EE size: 16 bit */ 1235 SIU_PCR_tag PCR88; /* offset: 0x00F0 size: 16 bit */ 1236 SIU_PCR_tag PCR89; /* offset: 0x00F2 size: 16 bit */ 1237 SIU_PCR_tag PCR90; /* offset: 0x00F4 size: 16 bit */ 1238 SIU_PCR_tag PCR91; /* offset: 0x00F6 size: 16 bit */ 1239 SIU_PCR_tag PCR92; /* offset: 0x00F8 size: 16 bit */ 1240 SIU_PCR_tag PCR93; /* offset: 0x00FA size: 16 bit */ 1241 SIU_PCR_tag PCR94; /* offset: 0x00FC size: 16 bit */ 1242 SIU_PCR_tag PCR95; /* offset: 0x00FE size: 16 bit */ 1243 SIU_PCR_tag PCR96; /* offset: 0x0100 size: 16 bit */ 1244 SIU_PCR_tag PCR97; /* offset: 0x0102 size: 16 bit */ 1245 SIU_PCR_tag PCR98; /* offset: 0x0104 size: 16 bit */ 1246 SIU_PCR_tag PCR99; /* offset: 0x0106 size: 16 bit */ 1247 SIU_PCR_tag PCR100; /* offset: 0x0108 size: 16 bit */ 1248 SIU_PCR_tag PCR101; /* offset: 0x010A size: 16 bit */ 1249 SIU_PCR_tag PCR102; /* offset: 0x010C size: 16 bit */ 1250 SIU_PCR_tag PCR103; /* offset: 0x010E size: 16 bit */ 1251 SIU_PCR_tag PCR104; /* offset: 0x0110 size: 16 bit */ 1252 SIU_PCR_tag PCR105; /* offset: 0x0112 size: 16 bit */ 1253 SIU_PCR_tag PCR106; /* offset: 0x0114 size: 16 bit */ 1254 SIU_PCR_tag PCR107; /* offset: 0x0116 size: 16 bit */ 1255 SIU_PCR_tag PCR108; /* offset: 0x0118 size: 16 bit */ 1256 SIU_PCR_tag PCR109; /* offset: 0x011A size: 16 bit */ 1257 SIU_PCR_tag PCR110; /* offset: 0x011C size: 16 bit */ 1258 SIU_PCR_tag PCR111; /* offset: 0x011E size: 16 bit */ 1259 SIU_PCR_tag PCR112; /* offset: 0x0120 size: 16 bit */ 1260 SIU_PCR_tag PCR113; /* offset: 0x0122 size: 16 bit */ 1261 SIU_PCR_tag PCR114; /* offset: 0x0124 size: 16 bit */ 1262 SIU_PCR_tag PCR115; /* offset: 0x0126 size: 16 bit */ 1263 SIU_PCR_tag PCR116; /* offset: 0x0128 size: 16 bit */ 1264 SIU_PCR_tag PCR117; /* offset: 0x012A size: 16 bit */ 1265 SIU_PCR_tag PCR118; /* offset: 0x012C size: 16 bit */ 1266 SIU_PCR_tag PCR119; /* offset: 0x012E size: 16 bit */ 1267 SIU_PCR_tag PCR120; /* offset: 0x0130 size: 16 bit */ 1268 SIU_PCR_tag PCR121; /* offset: 0x0132 size: 16 bit */ 1269 SIU_PCR_tag PCR122; /* offset: 0x0134 size: 16 bit */ 1270 SIU_PCR_tag PCR123; /* offset: 0x0136 size: 16 bit */ 1271 SIU_PCR_tag PCR124; /* offset: 0x0138 size: 16 bit */ 1272 SIU_PCR_tag PCR125; /* offset: 0x013A size: 16 bit */ 1273 SIU_PCR_tag PCR126; /* offset: 0x013C size: 16 bit */ 1274 SIU_PCR_tag PCR127; /* offset: 0x013E size: 16 bit */ 1275 SIU_PCR_tag PCR128; /* offset: 0x0140 size: 16 bit */ 1276 SIU_PCR_tag PCR129; /* offset: 0x0142 size: 16 bit */ 1277 SIU_PCR_tag PCR130; /* offset: 0x0144 size: 16 bit */ 1278 SIU_PCR_tag PCR131; /* offset: 0x0146 size: 16 bit */ 1279 SIU_PCR_tag PCR132; /* offset: 0x0148 size: 16 bit */ 1280 SIU_PCR_tag PCR133; /* offset: 0x014A size: 16 bit */ 1281 SIU_PCR_tag PCR134; /* offset: 0x014C size: 16 bit */ 1282 SIU_PCR_tag PCR135; /* offset: 0x014E size: 16 bit */ 1283 SIU_PCR_tag PCR136; /* offset: 0x0150 size: 16 bit */ 1284 SIU_PCR_tag PCR137; /* offset: 0x0152 size: 16 bit */ 1285 SIU_PCR_tag PCR138; /* offset: 0x0154 size: 16 bit */ 1286 SIU_PCR_tag PCR139; /* offset: 0x0156 size: 16 bit */ 1287 SIU_PCR_tag PCR140; /* offset: 0x0158 size: 16 bit */ 1288 SIU_PCR_tag PCR141; /* offset: 0x015A size: 16 bit */ 1289 SIU_PCR_tag PCR142; /* offset: 0x015C size: 16 bit */ 1290 SIU_PCR_tag PCR143; /* offset: 0x015E size: 16 bit */ 1291 SIU_PCR_tag PCR144; /* offset: 0x0160 size: 16 bit */ 1292 SIU_PCR_tag PCR145; /* offset: 0x0162 size: 16 bit */ 1293 SIU_PCR_tag PCR146; /* offset: 0x0164 size: 16 bit */ 1294 SIU_PCR_tag PCR147; /* offset: 0x0166 size: 16 bit */ 1295 SIU_PCR_tag PCR148; /* offset: 0x0168 size: 16 bit */ 1296 SIU_PCR_tag PCR149; /* offset: 0x016A size: 16 bit */ 1297 SIU_PCR_tag PCR150; /* offset: 0x016C size: 16 bit */ 1298 SIU_PCR_tag PCR151; /* offset: 0x016E size: 16 bit */ 1299 SIU_PCR_tag PCR152; /* offset: 0x0170 size: 16 bit */ 1300 SIU_PCR_tag PCR153; /* offset: 0x0172 size: 16 bit */ 1301 SIU_PCR_tag PCR154; /* offset: 0x0174 size: 16 bit */ 1302 SIU_PCR_tag PCR155; /* offset: 0x0176 size: 16 bit */ 1303 SIU_PCR_tag PCR156; /* offset: 0x0178 size: 16 bit */ 1304 SIU_PCR_tag PCR157; /* offset: 0x017A size: 16 bit */ 1305 SIU_PCR_tag PCR158; /* offset: 0x017C size: 16 bit */ 1306 SIU_PCR_tag PCR159; /* offset: 0x017E size: 16 bit */ 1307 SIU_PCR_tag PCR160; /* offset: 0x0180 size: 16 bit */ 1308 SIU_PCR_tag PCR161; /* offset: 0x0182 size: 16 bit */ 1309 SIU_PCR_tag PCR162; /* offset: 0x0184 size: 16 bit */ 1310 SIU_PCR_tag PCR163; /* offset: 0x0186 size: 16 bit */ 1311 SIU_PCR_tag PCR164; /* offset: 0x0188 size: 16 bit */ 1312 SIU_PCR_tag PCR165; /* offset: 0x018A size: 16 bit */ 1313 SIU_PCR_tag PCR166; /* offset: 0x018C size: 16 bit */ 1314 SIU_PCR_tag PCR167; /* offset: 0x018E size: 16 bit */ 1315 SIU_PCR_tag PCR168; /* offset: 0x0190 size: 16 bit */ 1316 SIU_PCR_tag PCR169; /* offset: 0x0192 size: 16 bit */ 1317 SIU_PCR_tag PCR170; /* offset: 0x0194 size: 16 bit */ 1318 SIU_PCR_tag PCR171; /* offset: 0x0196 size: 16 bit */ 1319 SIU_PCR_tag PCR172; /* offset: 0x0198 size: 16 bit */ 1320 SIU_PCR_tag PCR173; /* offset: 0x019A size: 16 bit */ 1321 SIU_PCR_tag PCR174; /* offset: 0x019C size: 16 bit */ 1322 SIU_PCR_tag PCR175; /* offset: 0x019E size: 16 bit */ 1323 SIU_PCR_tag PCR176; /* offset: 0x01A0 size: 16 bit */ 1324 SIU_PCR_tag PCR177; /* offset: 0x01A2 size: 16 bit */ 1325 SIU_PCR_tag PCR178; /* offset: 0x01A4 size: 16 bit */ 1326 SIU_PCR_tag PCR179; /* offset: 0x01A6 size: 16 bit */ 1327 SIU_PCR_tag PCR180; /* offset: 0x01A8 size: 16 bit */ 1328 SIU_PCR_tag PCR181; /* offset: 0x01AA size: 16 bit */ 1329 SIU_PCR_tag PCR182; /* offset: 0x01AC size: 16 bit */ 1330 SIU_PCR_tag PCR183; /* offset: 0x01AE size: 16 bit */ 1331 SIU_PCR_tag PCR184; /* offset: 0x01B0 size: 16 bit */ 1332 SIU_PCR_tag PCR185; /* offset: 0x01B2 size: 16 bit */ 1333 SIU_PCR_tag PCR186; /* offset: 0x01B4 size: 16 bit */ 1334 SIU_PCR_tag PCR187; /* offset: 0x01B6 size: 16 bit */ 1335 SIU_PCR_tag PCR188; /* offset: 0x01B8 size: 16 bit */ 1336 SIU_PCR_tag PCR189; /* offset: 0x01BA size: 16 bit */ 1337 SIU_PCR_tag PCR190; /* offset: 0x01BC size: 16 bit */ 1338 SIU_PCR_tag PCR191; /* offset: 0x01BE size: 16 bit */ 1339 SIU_PCR_tag PCR192; /* offset: 0x01C0 size: 16 bit */ 1340 SIU_PCR_tag PCR193; /* offset: 0x01C2 size: 16 bit */ 1341 SIU_PCR_tag PCR194; /* offset: 0x01C4 size: 16 bit */ 1342 SIU_PCR_tag PCR195; /* offset: 0x01C6 size: 16 bit */ 1343 SIU_PCR_tag PCR196; /* offset: 0x01C8 size: 16 bit */ 1344 SIU_PCR_tag PCR197; /* offset: 0x01CA size: 16 bit */ 1345 SIU_PCR_tag PCR198; /* offset: 0x01CC size: 16 bit */ 1346 SIU_PCR_tag PCR199; /* offset: 0x01CE size: 16 bit */ 1347 SIU_PCR_tag PCR200; /* offset: 0x01D0 size: 16 bit */ 1348 SIU_PCR_tag PCR201; /* offset: 0x01D2 size: 16 bit */ 1349 SIU_PCR_tag PCR202; /* offset: 0x01D4 size: 16 bit */ 1350 SIU_PCR_tag PCR203; /* offset: 0x01D6 size: 16 bit */ 1351 SIU_PCR_tag PCR204; /* offset: 0x01D8 size: 16 bit */ 1352 SIU_PCR_tag PCR205; /* offset: 0x01DA size: 16 bit */ 1353 SIU_PCR_tag PCR206; /* offset: 0x01DC size: 16 bit */ 1354 SIU_PCR_tag PCR207; /* offset: 0x01DE size: 16 bit */ 1355 SIU_PCR_tag PCR208; /* offset: 0x01E0 size: 16 bit */ 1356 SIU_PCR_tag PCR209; /* offset: 0x01E2 size: 16 bit */ 1357 SIU_PCR_tag PCR210; /* offset: 0x01E4 size: 16 bit */ 1358 SIU_PCR_tag PCR211; /* offset: 0x01E6 size: 16 bit */ 1359 SIU_PCR_tag PCR212; /* offset: 0x01E8 size: 16 bit */ 1360 SIU_PCR_tag PCR213; /* offset: 0x01EA size: 16 bit */ 1361 SIU_PCR_tag PCR214; /* offset: 0x01EC size: 16 bit */ 1362 SIU_PCR_tag PCR215; /* offset: 0x01EE size: 16 bit */ 1363 SIU_PCR_tag PCR216; /* offset: 0x01F0 size: 16 bit */ 1364 SIU_PCR_tag PCR217; /* offset: 0x01F2 size: 16 bit */ 1365 SIU_PCR_tag PCR218; /* offset: 0x01F4 size: 16 bit */ 1366 SIU_PCR_tag PCR219; /* offset: 0x01F6 size: 16 bit */ 1367 SIU_PCR_tag PCR220; /* offset: 0x01F8 size: 16 bit */ 1368 SIU_PCR_tag PCR221; /* offset: 0x01FA size: 16 bit */ 1369 SIU_PCR_tag PCR222; /* offset: 0x01FC size: 16 bit */ 1370 SIU_PCR_tag PCR223; /* offset: 0x01FE size: 16 bit */ 1371 SIU_PCR_tag PCR224; /* offset: 0x0200 size: 16 bit */ 1372 SIU_PCR_tag PCR225; /* offset: 0x0202 size: 16 bit */ 1373 SIU_PCR_tag PCR226; /* offset: 0x0204 size: 16 bit */ 1374 SIU_PCR_tag PCR227; /* offset: 0x0206 size: 16 bit */ 1375 SIU_PCR_tag PCR228; /* offset: 0x0208 size: 16 bit */ 1376 SIU_PCR_tag PCR229; /* offset: 0x020A size: 16 bit */ 1377 SIU_PCR_tag PCR230; /* offset: 0x020C size: 16 bit */ 1378 SIU_PCR_tag PCR231; /* offset: 0x020E size: 16 bit */ 1379 SIU_PCR_tag PCR232; /* offset: 0x0210 size: 16 bit */ 1380 SIU_PCR_tag PCR233; /* offset: 0x0212 size: 16 bit */ 1381 SIU_PCR_tag PCR234; /* offset: 0x0214 size: 16 bit */ 1382 SIU_PCR_tag PCR235; /* offset: 0x0216 size: 16 bit */ 1383 SIU_PCR_tag PCR236; /* offset: 0x0218 size: 16 bit */ 1384 SIU_PCR_tag PCR237; /* offset: 0x021A size: 16 bit */ 1385 SIU_PCR_tag PCR238; /* offset: 0x021C size: 16 bit */ 1386 SIU_PCR_tag PCR239; /* offset: 0x021E size: 16 bit */ 1387 SIU_PCR_tag PCR240; /* offset: 0x0220 size: 16 bit */ 1388 SIU_PCR_tag PCR241; /* offset: 0x0222 size: 16 bit */ 1389 SIU_PCR_tag PCR242; /* offset: 0x0224 size: 16 bit */ 1390 SIU_PCR_tag PCR243; /* offset: 0x0226 size: 16 bit */ 1391 SIU_PCR_tag PCR244; /* offset: 0x0228 size: 16 bit */ 1392 SIU_PCR_tag PCR245; /* offset: 0x022A size: 16 bit */ 1393 SIU_PCR_tag PCR246; /* offset: 0x022C size: 16 bit */ 1394 SIU_PCR_tag PCR247; /* offset: 0x022E size: 16 bit */ 1395 SIU_PCR_tag PCR248; /* offset: 0x0230 size: 16 bit */ 1396 SIU_PCR_tag PCR249; /* offset: 0x0232 size: 16 bit */ 1397 SIU_PCR_tag PCR250; /* offset: 0x0234 size: 16 bit */ 1398 SIU_PCR_tag PCR251; /* offset: 0x0236 size: 16 bit */ 1399 SIU_PCR_tag PCR252; /* offset: 0x0238 size: 16 bit */ 1400 SIU_PCR_tag PCR253; /* offset: 0x023A size: 16 bit */ 1401 SIU_PCR_tag PCR254; /* offset: 0x023C size: 16 bit */ 1402 SIU_PCR_tag PCR255; /* offset: 0x023E size: 16 bit */ 1403 SIU_PCR_tag PCR256; /* offset: 0x0240 size: 16 bit */ 1404 SIU_PCR_tag PCR257; /* offset: 0x0242 size: 16 bit */ 1405 SIU_PCR_tag PCR258; /* offset: 0x0244 size: 16 bit */ 1406 SIU_PCR_tag PCR259; /* offset: 0x0246 size: 16 bit */ 1407 SIU_PCR_tag PCR260; /* offset: 0x0248 size: 16 bit */ 1408 SIU_PCR_tag PCR261; /* offset: 0x024A size: 16 bit */ 1409 SIU_PCR_tag PCR262; /* offset: 0x024C size: 16 bit */ 1410 SIU_PCR_tag PCR263; /* offset: 0x024E size: 16 bit */ 1411 SIU_PCR_tag PCR264; /* offset: 0x0250 size: 16 bit */ 1412 SIU_PCR_tag PCR265; /* offset: 0x0252 size: 16 bit */ 1413 SIU_PCR_tag PCR266; /* offset: 0x0254 size: 16 bit */ 1414 SIU_PCR_tag PCR267; /* offset: 0x0256 size: 16 bit */ 1415 SIU_PCR_tag PCR268; /* offset: 0x0258 size: 16 bit */ 1416 SIU_PCR_tag PCR269; /* offset: 0x025A size: 16 bit */ 1417 SIU_PCR_tag PCR270; /* offset: 0x025C size: 16 bit */ 1418 SIU_PCR_tag PCR271; /* offset: 0x025E size: 16 bit */ 1419 SIU_PCR_tag PCR272; /* offset: 0x0260 size: 16 bit */ 1420 SIU_PCR_tag PCR273; /* offset: 0x0262 size: 16 bit */ 1421 SIU_PCR_tag PCR274; /* offset: 0x0264 size: 16 bit */ 1422 SIU_PCR_tag PCR275; /* offset: 0x0266 size: 16 bit */ 1423 SIU_PCR_tag PCR276; /* offset: 0x0268 size: 16 bit */ 1424 SIU_PCR_tag PCR277; /* offset: 0x026A size: 16 bit */ 1425 SIU_PCR_tag PCR278; /* offset: 0x026C size: 16 bit */ 1426 SIU_PCR_tag PCR279; /* offset: 0x026E size: 16 bit */ 1427 SIU_PCR_tag PCR280; /* offset: 0x0270 size: 16 bit */ 1428 SIU_PCR_tag PCR281; /* offset: 0x0272 size: 16 bit */ 1429 SIU_PCR_tag PCR282; /* offset: 0x0274 size: 16 bit */ 1430 SIU_PCR_tag PCR283; /* offset: 0x0276 size: 16 bit */ 1431 SIU_PCR_tag PCR284; /* offset: 0x0278 size: 16 bit */ 1432 SIU_PCR_tag PCR285; /* offset: 0x027A size: 16 bit */ 1433 SIU_PCR_tag PCR286; /* offset: 0x027C size: 16 bit */ 1434 SIU_PCR_tag PCR287; /* offset: 0x027E size: 16 bit */ 1435 SIU_PCR_tag PCR288; /* offset: 0x0280 size: 16 bit */ 1436 SIU_PCR_tag PCR289; /* offset: 0x0282 size: 16 bit */ 1437 SIU_PCR_tag PCR290; /* offset: 0x0284 size: 16 bit */ 1438 SIU_PCR_tag PCR291; /* offset: 0x0286 size: 16 bit */ 1439 SIU_PCR_tag PCR292; /* offset: 0x0288 size: 16 bit */ 1440 SIU_PCR_tag PCR293; /* offset: 0x028A size: 16 bit */ 1441 SIU_PCR_tag PCR294; /* offset: 0x028C size: 16 bit */ 1442 SIU_PCR_tag PCR295; /* offset: 0x028E size: 16 bit */ 1443 SIU_PCR_tag PCR296; /* offset: 0x0290 size: 16 bit */ 1444 SIU_PCR_tag PCR297; /* offset: 0x0292 size: 16 bit */ 1445 SIU_PCR_tag PCR298; /* offset: 0x0294 size: 16 bit */ 1446 SIU_PCR_tag PCR299; /* offset: 0x0296 size: 16 bit */ 1447 SIU_PCR_tag PCR300; /* offset: 0x0298 size: 16 bit */ 1448 SIU_PCR_tag PCR301; /* offset: 0x029A size: 16 bit */ 1449 SIU_PCR_tag PCR302; /* offset: 0x029C size: 16 bit */ 1450 SIU_PCR_tag PCR303; /* offset: 0x029E size: 16 bit */ 1451 SIU_PCR_tag PCR304; /* offset: 0x02A0 size: 16 bit */ 1452 SIU_PCR_tag PCR305; /* offset: 0x02A2 size: 16 bit */ 1453 SIU_PCR_tag PCR306; /* offset: 0x02A4 size: 16 bit */ 1454 SIU_PCR_tag PCR307; /* offset: 0x02A6 size: 16 bit */ 1455 SIU_PCR_tag PCR308; /* offset: 0x02A8 size: 16 bit */ 1456 SIU_PCR_tag PCR309; /* offset: 0x02AA size: 16 bit */ 1457 SIU_PCR_tag PCR310; /* offset: 0x02AC size: 16 bit */ 1458 SIU_PCR_tag PCR311; /* offset: 0x02AE size: 16 bit */ 1459 SIU_PCR_tag PCR312; /* offset: 0x02B0 size: 16 bit */ 1460 SIU_PCR_tag PCR313; /* offset: 0x02B2 size: 16 bit */ 1461 SIU_PCR_tag PCR314; /* offset: 0x02B4 size: 16 bit */ 1462 SIU_PCR_tag PCR315; /* offset: 0x02B6 size: 16 bit */ 1463 SIU_PCR_tag PCR316; /* offset: 0x02B8 size: 16 bit */ 1464 SIU_PCR_tag PCR317; /* offset: 0x02BA size: 16 bit */ 1465 SIU_PCR_tag PCR318; /* offset: 0x02BC size: 16 bit */ 1466 SIU_PCR_tag PCR319; /* offset: 0x02BE size: 16 bit */ 1467 SIU_PCR_tag PCR320; /* offset: 0x02C0 size: 16 bit */ 1468 SIU_PCR_tag PCR321; /* offset: 0x02C2 size: 16 bit */ 1469 SIU_PCR_tag PCR322; /* offset: 0x02C4 size: 16 bit */ 1470 SIU_PCR_tag PCR323; /* offset: 0x02C6 size: 16 bit */ 1471 SIU_PCR_tag PCR324; /* offset: 0x02C8 size: 16 bit */ 1472 SIU_PCR_tag PCR325; /* offset: 0x02CA size: 16 bit */ 1473 SIU_PCR_tag PCR326; /* offset: 0x02CC size: 16 bit */ 1474 SIU_PCR_tag PCR327; /* offset: 0x02CE size: 16 bit */ 1475 SIU_PCR_tag PCR328; /* offset: 0x02D0 size: 16 bit */ 1476 SIU_PCR_tag PCR329; /* offset: 0x02D2 size: 16 bit */ 1477 SIU_PCR_tag PCR330; /* offset: 0x02D4 size: 16 bit */ 1478 SIU_PCR_tag PCR331; /* offset: 0x02D6 size: 16 bit */ 1479 SIU_PCR_tag PCR332; /* offset: 0x02D8 size: 16 bit */ 1480 SIU_PCR_tag PCR333; /* offset: 0x02DA size: 16 bit */ 1481 SIU_PCR_tag PCR334; /* offset: 0x02DC size: 16 bit */ 1482 SIU_PCR_tag PCR335; /* offset: 0x02DE size: 16 bit */ 1483 SIU_PCR_tag PCR336; /* offset: 0x02E0 size: 16 bit */ 1484 SIU_PCR_tag PCR337; /* offset: 0x02E2 size: 16 bit */ 1485 SIU_PCR_tag PCR338; /* offset: 0x02E4 size: 16 bit */ 1486 SIU_PCR_tag PCR339; /* offset: 0x02E6 size: 16 bit */ 1487 SIU_PCR_tag PCR340; /* offset: 0x02E8 size: 16 bit */ 1488 SIU_PCR_tag PCR341; /* offset: 0x02EA size: 16 bit */ 1489 SIU_PCR_tag PCR342; /* offset: 0x02EC size: 16 bit */ 1490 SIU_PCR_tag PCR343; /* offset: 0x02EE size: 16 bit */ 1491 SIU_PCR_tag PCR344; /* offset: 0x02F0 size: 16 bit */ 1492 SIU_PCR_tag PCR345; /* offset: 0x02F2 size: 16 bit */ 1493 SIU_PCR_tag PCR346; /* offset: 0x02F4 size: 16 bit */ 1494 SIU_PCR_tag PCR347; /* offset: 0x02F6 size: 16 bit */ 1495 SIU_PCR_tag PCR348; /* offset: 0x02F8 size: 16 bit */ 1496 SIU_PCR_tag PCR349; /* offset: 0x02FA size: 16 bit */ 1497 SIU_PCR_tag PCR350; /* offset: 0x02FC size: 16 bit */ 1498 SIU_PCR_tag PCR351; /* offset: 0x02FE size: 16 bit */ 1499 SIU_PCR_tag PCR352; /* offset: 0x0300 size: 16 bit */ 1500 SIU_PCR_tag PCR353; /* offset: 0x0302 size: 16 bit */ 1501 SIU_PCR_tag PCR354; /* offset: 0x0304 size: 16 bit */ 1502 SIU_PCR_tag PCR355; /* offset: 0x0306 size: 16 bit */ 1503 SIU_PCR_tag PCR356; /* offset: 0x0308 size: 16 bit */ 1504 SIU_PCR_tag PCR357; /* offset: 0x030A size: 16 bit */ 1505 SIU_PCR_tag PCR358; /* offset: 0x030C size: 16 bit */ 1506 SIU_PCR_tag PCR359; /* offset: 0x030E size: 16 bit */ 1507 SIU_PCR_tag PCR360; /* offset: 0x0310 size: 16 bit */ 1508 SIU_PCR_tag PCR361; /* offset: 0x0312 size: 16 bit */ 1509 SIU_PCR_tag PCR362; /* offset: 0x0314 size: 16 bit */ 1510 SIU_PCR_tag PCR363; /* offset: 0x0316 size: 16 bit */ 1511 SIU_PCR_tag PCR364; /* offset: 0x0318 size: 16 bit */ 1512 SIU_PCR_tag PCR365; /* offset: 0x031A size: 16 bit */ 1513 SIU_PCR_tag PCR366; /* offset: 0x031C size: 16 bit */ 1514 SIU_PCR_tag PCR367; /* offset: 0x031E size: 16 bit */ 1515 SIU_PCR_tag PCR368; /* offset: 0x0320 size: 16 bit */ 1516 SIU_PCR_tag PCR369; /* offset: 0x0322 size: 16 bit */ 1517 SIU_PCR_tag PCR370; /* offset: 0x0324 size: 16 bit */ 1518 SIU_PCR_tag PCR371; /* offset: 0x0326 size: 16 bit */ 1519 SIU_PCR_tag PCR372; /* offset: 0x0328 size: 16 bit */ 1520 SIU_PCR_tag PCR373; /* offset: 0x032A size: 16 bit */ 1521 SIU_PCR_tag PCR374; /* offset: 0x032C size: 16 bit */ 1522 SIU_PCR_tag PCR375; /* offset: 0x032E size: 16 bit */ 1523 SIU_PCR_tag PCR376; /* offset: 0x0330 size: 16 bit */ 1524 SIU_PCR_tag PCR377; /* offset: 0x0332 size: 16 bit */ 1525 SIU_PCR_tag PCR378; /* offset: 0x0334 size: 16 bit */ 1526 SIU_PCR_tag PCR379; /* offset: 0x0336 size: 16 bit */ 1527 SIU_PCR_tag PCR380; /* offset: 0x0338 size: 16 bit */ 1528 SIU_PCR_tag PCR381; /* offset: 0x033A size: 16 bit */ 1529 SIU_PCR_tag PCR382; /* offset: 0x033C size: 16 bit */ 1530 SIU_PCR_tag PCR383; /* offset: 0x033E size: 16 bit */ 1531 SIU_PCR_tag PCR384; /* offset: 0x0340 size: 16 bit */ 1532 SIU_PCR_tag PCR385; /* offset: 0x0342 size: 16 bit */ 1533 SIU_PCR_tag PCR386; /* offset: 0x0344 size: 16 bit */ 1534 SIU_PCR_tag PCR387; /* offset: 0x0346 size: 16 bit */ 1535 SIU_PCR_tag PCR388; /* offset: 0x0348 size: 16 bit */ 1536 SIU_PCR_tag PCR389; /* offset: 0x034A size: 16 bit */ 1537 SIU_PCR_tag PCR390; /* offset: 0x034C size: 16 bit */ 1538 SIU_PCR_tag PCR391; /* offset: 0x034E size: 16 bit */ 1539 SIU_PCR_tag PCR392; /* offset: 0x0350 size: 16 bit */ 1540 SIU_PCR_tag PCR393; /* offset: 0x0352 size: 16 bit */ 1541 SIU_PCR_tag PCR394; /* offset: 0x0354 size: 16 bit */ 1542 SIU_PCR_tag PCR395; /* offset: 0x0356 size: 16 bit */ 1543 SIU_PCR_tag PCR396; /* offset: 0x0358 size: 16 bit */ 1544 SIU_PCR_tag PCR397; /* offset: 0x035A size: 16 bit */ 1545 SIU_PCR_tag PCR398; /* offset: 0x035C size: 16 bit */ 1546 SIU_PCR_tag PCR399; /* offset: 0x035E size: 16 bit */ 1547 SIU_PCR_tag PCR400; /* offset: 0x0360 size: 16 bit */ 1548 SIU_PCR_tag PCR401; /* offset: 0x0362 size: 16 bit */ 1549 SIU_PCR_tag PCR402; /* offset: 0x0364 size: 16 bit */ 1550 SIU_PCR_tag PCR403; /* offset: 0x0366 size: 16 bit */ 1551 SIU_PCR_tag PCR404; /* offset: 0x0368 size: 16 bit */ 1552 SIU_PCR_tag PCR405; /* offset: 0x036A size: 16 bit */ 1553 SIU_PCR_tag PCR406; /* offset: 0x036C size: 16 bit */ 1554 SIU_PCR_tag PCR407; /* offset: 0x036E size: 16 bit */ 1555 SIU_PCR_tag PCR408; /* offset: 0x0370 size: 16 bit */ 1556 SIU_PCR_tag PCR409; /* offset: 0x0372 size: 16 bit */ 1557 SIU_PCR_tag PCR410; /* offset: 0x0374 size: 16 bit */ 1558 SIU_PCR_tag PCR411; /* offset: 0x0376 size: 16 bit */ 1559 SIU_PCR_tag PCR412; /* offset: 0x0378 size: 16 bit */ 1560 SIU_PCR_tag PCR413; /* offset: 0x037A size: 16 bit */ 1561 SIU_PCR_tag PCR414; /* offset: 0x037C size: 16 bit */ 1562 SIU_PCR_tag PCR415; /* offset: 0x037E size: 16 bit */ 1563 SIU_PCR_tag PCR416; /* offset: 0x0380 size: 16 bit */ 1564 SIU_PCR_tag PCR417; /* offset: 0x0382 size: 16 bit */ 1565 SIU_PCR_tag PCR418; /* offset: 0x0384 size: 16 bit */ 1566 SIU_PCR_tag PCR419; /* offset: 0x0386 size: 16 bit */ 1567 SIU_PCR_tag PCR420; /* offset: 0x0388 size: 16 bit */ 1568 SIU_PCR_tag PCR421; /* offset: 0x038A size: 16 bit */ 1569 SIU_PCR_tag PCR422; /* offset: 0x038C size: 16 bit */ 1570 SIU_PCR_tag PCR423; /* offset: 0x038E size: 16 bit */ 1571 SIU_PCR_tag PCR424; /* offset: 0x0390 size: 16 bit */ 1572 SIU_PCR_tag PCR425; /* offset: 0x0392 size: 16 bit */ 1573 SIU_PCR_tag PCR426; /* offset: 0x0394 size: 16 bit */ 1574 SIU_PCR_tag PCR427; /* offset: 0x0396 size: 16 bit */ 1575 SIU_PCR_tag PCR428; /* offset: 0x0398 size: 16 bit */ 1576 SIU_PCR_tag PCR429; /* offset: 0x039A size: 16 bit */ 1577 SIU_PCR_tag PCR430; /* offset: 0x039C size: 16 bit */ 1578 SIU_PCR_tag PCR431; /* offset: 0x039E size: 16 bit */ 1579 SIU_PCR_tag PCR432; /* offset: 0x03A0 size: 16 bit */ 1580 SIU_PCR_tag PCR433; /* offset: 0x03A2 size: 16 bit */ 1581 SIU_PCR_tag PCR434; /* offset: 0x03A4 size: 16 bit */ 1582 SIU_PCR_tag PCR435; /* offset: 0x03A6 size: 16 bit */ 1583 SIU_PCR_tag PCR436; /* offset: 0x03A8 size: 16 bit */ 1584 SIU_PCR_tag PCR437; /* offset: 0x03AA size: 16 bit */ 1585 SIU_PCR_tag PCR438; /* offset: 0x03AC size: 16 bit */ 1586 SIU_PCR_tag PCR439; /* offset: 0x03AE size: 16 bit */ 1587 SIU_PCR_tag PCR440; /* offset: 0x03B0 size: 16 bit */ 1588 SIU_PCR_tag PCR441; /* offset: 0x03B2 size: 16 bit */ 1589 SIU_PCR_tag PCR442; /* offset: 0x03B4 size: 16 bit */ 1590 SIU_PCR_tag PCR443; /* offset: 0x03B6 size: 16 bit */ 1591 SIU_PCR_tag PCR444; /* offset: 0x03B8 size: 16 bit */ 1592 SIU_PCR_tag PCR445; /* offset: 0x03BA size: 16 bit */ 1593 SIU_PCR_tag PCR446; /* offset: 0x03BC size: 16 bit */ 1594 SIU_PCR_tag PCR447; /* offset: 0x03BE size: 16 bit */ 1595 SIU_PCR_tag PCR448; /* offset: 0x03C0 size: 16 bit */ 1596 SIU_PCR_tag PCR449; /* offset: 0x03C2 size: 16 bit */ 1597 SIU_PCR_tag PCR450; /* offset: 0x03C4 size: 16 bit */ 1598 SIU_PCR_tag PCR451; /* offset: 0x03C6 size: 16 bit */ 1599 SIU_PCR_tag PCR452; /* offset: 0x03C8 size: 16 bit */ 1600 SIU_PCR_tag PCR453; /* offset: 0x03CA size: 16 bit */ 1601 SIU_PCR_tag PCR454; /* offset: 0x03CC size: 16 bit */ 1602 SIU_PCR_tag PCR455; /* offset: 0x03CE size: 16 bit */ 1603 SIU_PCR_tag PCR456; /* offset: 0x03D0 size: 16 bit */ 1604 SIU_PCR_tag PCR457; /* offset: 0x03D2 size: 16 bit */ 1605 SIU_PCR_tag PCR458; /* offset: 0x03D4 size: 16 bit */ 1606 SIU_PCR_tag PCR459; /* offset: 0x03D6 size: 16 bit */ 1607 SIU_PCR_tag PCR460; /* offset: 0x03D8 size: 16 bit */ 1608 SIU_PCR_tag PCR461; /* offset: 0x03DA size: 16 bit */ 1609 SIU_PCR_tag PCR462; /* offset: 0x03DC size: 16 bit */ 1610 SIU_PCR_tag PCR463; /* offset: 0x03DE size: 16 bit */ 1611 SIU_PCR_tag PCR464; /* offset: 0x03E0 size: 16 bit */ 1612 SIU_PCR_tag PCR465; /* offset: 0x03E2 size: 16 bit */ 1613 SIU_PCR_tag PCR466; /* offset: 0x03E4 size: 16 bit */ 1614 SIU_PCR_tag PCR467; /* offset: 0x03E6 size: 16 bit */ 1615 SIU_PCR_tag PCR468; /* offset: 0x03E8 size: 16 bit */ 1616 SIU_PCR_tag PCR469; /* offset: 0x03EA size: 16 bit */ 1617 SIU_PCR_tag PCR470; /* offset: 0x03EC size: 16 bit */ 1618 SIU_PCR_tag PCR471; /* offset: 0x03EE size: 16 bit */ 1619 SIU_PCR_tag PCR472; /* offset: 0x03F0 size: 16 bit */ 1620 SIU_PCR_tag PCR473; /* offset: 0x03F2 size: 16 bit */ 1621 SIU_PCR_tag PCR474; /* offset: 0x03F4 size: 16 bit */ 1622 SIU_PCR_tag PCR475; /* offset: 0x03F6 size: 16 bit */ 1623 SIU_PCR_tag PCR476; /* offset: 0x03F8 size: 16 bit */ 1624 SIU_PCR_tag PCR477; /* offset: 0x03FA size: 16 bit */ 1625 SIU_PCR_tag PCR478; /* offset: 0x03FC size: 16 bit */ 1626 SIU_PCR_tag PCR479; /* offset: 0x03FE size: 16 bit */ 1627 SIU_PCR_tag PCR480; /* offset: 0x0400 size: 16 bit */ 1628 SIU_PCR_tag PCR481; /* offset: 0x0402 size: 16 bit */ 1629 SIU_PCR_tag PCR482; /* offset: 0x0404 size: 16 bit */ 1630 SIU_PCR_tag PCR483; /* offset: 0x0406 size: 16 bit */ 1631 SIU_PCR_tag PCR484; /* offset: 0x0408 size: 16 bit */ 1632 SIU_PCR_tag PCR485; /* offset: 0x040A size: 16 bit */ 1633 SIU_PCR_tag PCR486; /* offset: 0x040C size: 16 bit */ 1634 SIU_PCR_tag PCR487; /* offset: 0x040E size: 16 bit */ 1635 SIU_PCR_tag PCR488; /* offset: 0x0410 size: 16 bit */ 1636 SIU_PCR_tag PCR489; /* offset: 0x0412 size: 16 bit */ 1637 SIU_PCR_tag PCR490; /* offset: 0x0414 size: 16 bit */ 1638 SIU_PCR_tag PCR491; /* offset: 0x0416 size: 16 bit */ 1639 SIU_PCR_tag PCR492; /* offset: 0x0418 size: 16 bit */ 1640 SIU_PCR_tag PCR493; /* offset: 0x041A size: 16 bit */ 1641 SIU_PCR_tag PCR494; /* offset: 0x041C size: 16 bit */ 1642 SIU_PCR_tag PCR495; /* offset: 0x041E size: 16 bit */ 1643 SIU_PCR_tag PCR496; /* offset: 0x0420 size: 16 bit */ 1644 SIU_PCR_tag PCR497; /* offset: 0x0422 size: 16 bit */ 1645 SIU_PCR_tag PCR498; /* offset: 0x0424 size: 16 bit */ 1646 SIU_PCR_tag PCR499; /* offset: 0x0426 size: 16 bit */ 1647 SIU_PCR_tag PCR500; /* offset: 0x0428 size: 16 bit */ 1648 SIU_PCR_tag PCR501; /* offset: 0x042A size: 16 bit */ 1649 SIU_PCR_tag PCR502; /* offset: 0x042C size: 16 bit */ 1650 SIU_PCR_tag PCR503; /* offset: 0x042E size: 16 bit */ 1651 SIU_PCR_tag PCR504; /* offset: 0x0430 size: 16 bit */ 1652 SIU_PCR_tag PCR505; /* offset: 0x0432 size: 16 bit */ 1653 SIU_PCR_tag PCR506; /* offset: 0x0434 size: 16 bit */ 1654 SIU_PCR_tag PCR507; /* offset: 0x0436 size: 16 bit */ 1655 SIU_PCR_tag PCR508; /* offset: 0x0438 size: 16 bit */ 1656 SIU_PCR_tag PCR509; /* offset: 0x043A size: 16 bit */ 1657 SIU_PCR_tag PCR510; /* offset: 0x043C size: 16 bit */ 1658 SIU_PCR_tag PCR511; /* offset: 0x043E size: 16 bit */ 1659 }; 1660 1661 }; 1662 int8_t SIUL_reserved_0440_C[192]; 1663 union { 1664 /* PSMI - Pad Selection for Multiplexed Inputs */ 1665 SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */ 1666 1667 /* PSMI - Pad Selection for Multiplexed Inputs */ 1668 SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */ 1669 1670 struct { 1671 /* PSMI - Pad Selection for Multiplexed Inputs */ 1672 SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */ 1673 SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */ 1674 SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */ 1675 SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */ 1676 SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */ 1677 SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */ 1678 SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */ 1679 SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */ 1680 SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */ 1681 SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */ 1682 SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */ 1683 SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */ 1684 SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */ 1685 SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */ 1686 SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */ 1687 SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */ 1688 SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */ 1689 SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */ 1690 SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */ 1691 SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */ 1692 SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */ 1693 SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */ 1694 SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */ 1695 SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */ 1696 SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */ 1697 SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */ 1698 SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */ 1699 SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */ 1700 SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */ 1701 SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */ 1702 SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */ 1703 SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */ 1704 SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */ 1705 SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */ 1706 SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */ 1707 SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */ 1708 SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */ 1709 SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */ 1710 SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */ 1711 SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */ 1712 SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */ 1713 SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */ 1714 SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */ 1715 SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */ 1716 SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */ 1717 SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */ 1718 SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */ 1719 SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */ 1720 SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */ 1721 SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */ 1722 SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */ 1723 SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */ 1724 SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */ 1725 SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */ 1726 SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */ 1727 SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */ 1728 SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */ 1729 SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */ 1730 SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */ 1731 SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */ 1732 SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */ 1733 SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */ 1734 SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */ 1735 SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */ 1736 }; 1737 1738 struct { 1739 /* PSMI - Pad Selection for Multiplexed Inputs */ 1740 SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */ 1741 SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */ 1742 SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */ 1743 SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */ 1744 SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */ 1745 SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */ 1746 SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */ 1747 SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */ 1748 SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */ 1749 SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */ 1750 SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */ 1751 SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */ 1752 SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */ 1753 SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */ 1754 SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */ 1755 SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */ 1756 SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */ 1757 SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */ 1758 SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */ 1759 SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */ 1760 SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */ 1761 SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */ 1762 SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */ 1763 SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */ 1764 SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */ 1765 SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */ 1766 SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */ 1767 SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */ 1768 SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */ 1769 SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */ 1770 SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */ 1771 SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */ 1772 SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */ 1773 SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */ 1774 SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */ 1775 SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */ 1776 SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */ 1777 SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */ 1778 SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */ 1779 SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */ 1780 SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */ 1781 SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */ 1782 SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */ 1783 SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */ 1784 SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */ 1785 SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */ 1786 SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */ 1787 SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */ 1788 SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */ 1789 SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */ 1790 SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */ 1791 SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */ 1792 SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */ 1793 SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */ 1794 SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */ 1795 SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */ 1796 SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */ 1797 SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */ 1798 SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */ 1799 SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */ 1800 SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */ 1801 SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */ 1802 SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */ 1803 SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */ 1804 SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */ 1805 SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */ 1806 SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */ 1807 SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */ 1808 SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */ 1809 SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */ 1810 SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */ 1811 SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */ 1812 SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */ 1813 SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */ 1814 SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */ 1815 SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */ 1816 SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */ 1817 SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */ 1818 SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */ 1819 SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */ 1820 SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */ 1821 SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */ 1822 SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */ 1823 SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */ 1824 SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */ 1825 SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */ 1826 SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */ 1827 SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */ 1828 SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */ 1829 SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */ 1830 SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */ 1831 SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */ 1832 SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */ 1833 SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */ 1834 SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */ 1835 SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */ 1836 SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */ 1837 SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */ 1838 SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */ 1839 SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */ 1840 SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */ 1841 SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */ 1842 SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */ 1843 SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */ 1844 SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */ 1845 SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */ 1846 SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */ 1847 SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */ 1848 SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */ 1849 SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */ 1850 SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */ 1851 SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */ 1852 SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */ 1853 SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */ 1854 SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */ 1855 SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */ 1856 SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */ 1857 SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */ 1858 SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */ 1859 SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */ 1860 SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */ 1861 SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */ 1862 SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */ 1863 SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */ 1864 SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */ 1865 SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */ 1866 SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */ 1867 SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */ 1868 SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */ 1869 SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */ 1870 SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */ 1871 SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */ 1872 SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */ 1873 SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */ 1874 SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */ 1875 SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */ 1876 SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */ 1877 SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */ 1878 SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */ 1879 SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */ 1880 SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */ 1881 SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */ 1882 SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */ 1883 SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */ 1884 SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */ 1885 SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */ 1886 SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */ 1887 SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */ 1888 SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */ 1889 SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */ 1890 SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */ 1891 SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */ 1892 SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */ 1893 SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */ 1894 SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */ 1895 SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */ 1896 SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */ 1897 SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */ 1898 SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */ 1899 SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */ 1900 SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */ 1901 SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */ 1902 SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */ 1903 SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */ 1904 SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */ 1905 SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */ 1906 SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */ 1907 SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */ 1908 SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */ 1909 SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */ 1910 SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */ 1911 SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */ 1912 SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */ 1913 SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */ 1914 SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */ 1915 SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */ 1916 SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */ 1917 SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */ 1918 SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */ 1919 SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */ 1920 SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */ 1921 SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */ 1922 SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */ 1923 SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */ 1924 SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */ 1925 SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */ 1926 SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */ 1927 SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */ 1928 SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */ 1929 SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */ 1930 SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */ 1931 SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */ 1932 SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */ 1933 SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */ 1934 SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */ 1935 SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */ 1936 SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */ 1937 SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */ 1938 SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */ 1939 SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */ 1940 SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */ 1941 SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */ 1942 SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */ 1943 SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */ 1944 SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */ 1945 SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */ 1946 SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */ 1947 SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */ 1948 SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */ 1949 SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */ 1950 SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */ 1951 SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */ 1952 SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */ 1953 SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */ 1954 SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */ 1955 SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */ 1956 SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */ 1957 SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */ 1958 SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */ 1959 SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */ 1960 SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */ 1961 SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */ 1962 SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */ 1963 SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */ 1964 SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */ 1965 SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */ 1966 SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */ 1967 SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */ 1968 SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */ 1969 SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */ 1970 SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */ 1971 SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */ 1972 SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */ 1973 SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */ 1974 SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */ 1975 SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */ 1976 SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */ 1977 SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */ 1978 SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */ 1979 SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */ 1980 SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */ 1981 SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */ 1982 SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */ 1983 SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */ 1984 SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */ 1985 SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */ 1986 SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */ 1987 SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */ 1988 SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */ 1989 SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */ 1990 SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */ 1991 SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */ 1992 SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */ 1993 SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */ 1994 SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */ 1995 SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */ 1996 }; 1997 1998 }; 1999 union { 2000 /* GPDO - GPIO Pad Data Output Register */ 2001 SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */ 2002 2003 /* GPDO - GPIO Pad Data Output Register */ 2004 SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */ 2005 2006 struct { 2007 /* GPDO - GPIO Pad Data Output Register */ 2008 SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */ 2009 SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */ 2010 SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */ 2011 SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */ 2012 SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */ 2013 SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */ 2014 SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */ 2015 SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */ 2016 SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */ 2017 SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */ 2018 SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */ 2019 SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */ 2020 SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */ 2021 SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */ 2022 SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */ 2023 SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */ 2024 SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */ 2025 SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */ 2026 SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */ 2027 SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */ 2028 SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */ 2029 SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */ 2030 SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */ 2031 SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */ 2032 SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */ 2033 SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */ 2034 SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */ 2035 SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */ 2036 SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */ 2037 SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */ 2038 SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */ 2039 SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */ 2040 SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */ 2041 SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */ 2042 SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */ 2043 SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */ 2044 SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */ 2045 SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */ 2046 SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */ 2047 SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */ 2048 SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */ 2049 SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */ 2050 SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */ 2051 SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */ 2052 SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */ 2053 SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */ 2054 SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */ 2055 SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */ 2056 SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */ 2057 SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */ 2058 SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */ 2059 SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */ 2060 SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */ 2061 SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */ 2062 SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */ 2063 SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */ 2064 SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */ 2065 SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */ 2066 SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */ 2067 SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */ 2068 SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */ 2069 SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */ 2070 SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */ 2071 SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */ 2072 SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */ 2073 SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */ 2074 SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */ 2075 SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */ 2076 SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */ 2077 SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */ 2078 SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */ 2079 SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */ 2080 SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */ 2081 SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */ 2082 SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */ 2083 SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */ 2084 SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */ 2085 SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */ 2086 SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */ 2087 SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */ 2088 SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */ 2089 SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */ 2090 SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */ 2091 SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */ 2092 SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */ 2093 SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */ 2094 SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */ 2095 SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */ 2096 SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */ 2097 SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */ 2098 SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */ 2099 SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */ 2100 SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */ 2101 SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */ 2102 SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */ 2103 SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */ 2104 SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */ 2105 SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */ 2106 SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */ 2107 SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */ 2108 SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */ 2109 SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */ 2110 SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */ 2111 SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */ 2112 SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */ 2113 SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */ 2114 SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */ 2115 SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */ 2116 SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */ 2117 SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */ 2118 SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */ 2119 SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */ 2120 SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */ 2121 SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */ 2122 SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */ 2123 SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */ 2124 SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */ 2125 SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */ 2126 SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */ 2127 SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */ 2128 SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */ 2129 SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */ 2130 SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */ 2131 SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */ 2132 SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */ 2133 SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */ 2134 SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */ 2135 SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */ 2136 }; 2137 2138 struct { 2139 /* GPDO - GPIO Pad Data Output Register */ 2140 SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */ 2141 SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */ 2142 SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */ 2143 SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */ 2144 SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */ 2145 SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */ 2146 SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */ 2147 SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */ 2148 SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */ 2149 SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */ 2150 SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */ 2151 SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */ 2152 SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */ 2153 SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */ 2154 SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */ 2155 SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */ 2156 SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */ 2157 SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */ 2158 SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */ 2159 SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */ 2160 SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */ 2161 SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */ 2162 SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */ 2163 SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */ 2164 SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */ 2165 SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */ 2166 SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */ 2167 SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */ 2168 SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */ 2169 SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */ 2170 SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */ 2171 SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */ 2172 SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */ 2173 SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */ 2174 SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */ 2175 SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */ 2176 SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */ 2177 SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */ 2178 SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */ 2179 SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */ 2180 SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */ 2181 SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */ 2182 SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */ 2183 SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */ 2184 SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */ 2185 SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */ 2186 SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */ 2187 SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */ 2188 SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */ 2189 SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */ 2190 SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */ 2191 SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */ 2192 SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */ 2193 SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */ 2194 SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */ 2195 SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */ 2196 SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */ 2197 SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */ 2198 SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */ 2199 SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */ 2200 SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */ 2201 SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */ 2202 SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */ 2203 SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */ 2204 SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */ 2205 SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */ 2206 SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */ 2207 SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */ 2208 SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */ 2209 SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */ 2210 SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */ 2211 SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */ 2212 SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */ 2213 SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */ 2214 SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */ 2215 SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */ 2216 SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */ 2217 SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */ 2218 SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */ 2219 SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */ 2220 SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */ 2221 SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */ 2222 SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */ 2223 SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */ 2224 SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */ 2225 SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */ 2226 SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */ 2227 SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */ 2228 SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */ 2229 SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */ 2230 SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */ 2231 SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */ 2232 SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */ 2233 SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */ 2234 SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */ 2235 SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */ 2236 SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */ 2237 SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */ 2238 SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */ 2239 SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */ 2240 SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */ 2241 SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */ 2242 SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */ 2243 SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */ 2244 SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */ 2245 SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */ 2246 SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */ 2247 SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */ 2248 SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */ 2249 SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */ 2250 SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */ 2251 SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */ 2252 SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */ 2253 SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */ 2254 SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */ 2255 SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */ 2256 SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */ 2257 SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */ 2258 SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */ 2259 SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */ 2260 SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */ 2261 SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */ 2262 SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */ 2263 SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */ 2264 SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */ 2265 SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */ 2266 SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */ 2267 SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */ 2268 SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */ 2269 SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */ 2270 SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */ 2271 SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */ 2272 SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */ 2273 SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */ 2274 SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */ 2275 SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */ 2276 SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */ 2277 SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */ 2278 SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */ 2279 SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */ 2280 SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */ 2281 SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */ 2282 SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */ 2283 SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */ 2284 SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */ 2285 SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */ 2286 SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */ 2287 SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */ 2288 SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */ 2289 SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */ 2290 SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */ 2291 SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */ 2292 SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */ 2293 SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */ 2294 SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */ 2295 SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */ 2296 SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */ 2297 SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */ 2298 SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */ 2299 SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */ 2300 SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */ 2301 SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */ 2302 SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */ 2303 SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */ 2304 SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */ 2305 SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */ 2306 SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */ 2307 SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */ 2308 SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */ 2309 SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */ 2310 SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */ 2311 SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */ 2312 SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */ 2313 SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */ 2314 SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */ 2315 SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */ 2316 SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */ 2317 SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */ 2318 SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */ 2319 SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */ 2320 SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */ 2321 SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */ 2322 SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */ 2323 SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */ 2324 SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */ 2325 SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */ 2326 SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */ 2327 SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */ 2328 SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */ 2329 SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */ 2330 SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */ 2331 SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */ 2332 SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */ 2333 SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */ 2334 SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */ 2335 SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */ 2336 SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */ 2337 SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */ 2338 SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */ 2339 SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */ 2340 SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */ 2341 SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */ 2342 SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */ 2343 SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */ 2344 SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */ 2345 SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */ 2346 SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */ 2347 SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */ 2348 SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */ 2349 SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */ 2350 SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */ 2351 SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */ 2352 SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */ 2353 SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */ 2354 SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */ 2355 SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */ 2356 SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */ 2357 SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */ 2358 SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */ 2359 SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */ 2360 SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */ 2361 SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */ 2362 SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */ 2363 SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */ 2364 SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */ 2365 SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */ 2366 SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */ 2367 SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */ 2368 SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */ 2369 SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */ 2370 SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */ 2371 SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */ 2372 SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */ 2373 SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */ 2374 SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */ 2375 SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */ 2376 SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */ 2377 SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */ 2378 SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */ 2379 SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */ 2380 SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */ 2381 SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */ 2382 SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */ 2383 SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */ 2384 SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */ 2385 SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */ 2386 SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */ 2387 SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */ 2388 SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */ 2389 SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */ 2390 SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */ 2391 SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */ 2392 SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */ 2393 SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */ 2394 SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */ 2395 SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */ 2396 SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */ 2397 SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */ 2398 SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */ 2399 SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */ 2400 SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */ 2401 SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */ 2402 SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */ 2403 SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */ 2404 SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */ 2405 SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */ 2406 SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */ 2407 SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */ 2408 SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */ 2409 SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */ 2410 SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */ 2411 SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */ 2412 SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */ 2413 SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */ 2414 SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */ 2415 SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */ 2416 SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */ 2417 SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */ 2418 SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */ 2419 SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */ 2420 SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */ 2421 SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */ 2422 SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */ 2423 SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */ 2424 SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */ 2425 SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */ 2426 SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */ 2427 SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */ 2428 SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */ 2429 SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */ 2430 SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */ 2431 SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */ 2432 SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */ 2433 SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */ 2434 SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */ 2435 SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */ 2436 SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */ 2437 SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */ 2438 SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */ 2439 SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */ 2440 SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */ 2441 SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */ 2442 SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */ 2443 SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */ 2444 SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */ 2445 SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */ 2446 SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */ 2447 SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */ 2448 SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */ 2449 SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */ 2450 SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */ 2451 SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */ 2452 SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */ 2453 SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */ 2454 SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */ 2455 SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */ 2456 SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */ 2457 SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */ 2458 SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */ 2459 SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */ 2460 SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */ 2461 SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */ 2462 SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */ 2463 SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */ 2464 SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */ 2465 SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */ 2466 SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */ 2467 SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */ 2468 SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */ 2469 SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */ 2470 SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */ 2471 SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */ 2472 SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */ 2473 SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */ 2474 SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */ 2475 SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */ 2476 SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */ 2477 SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */ 2478 SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */ 2479 SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */ 2480 SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */ 2481 SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */ 2482 SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */ 2483 SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */ 2484 SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */ 2485 SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */ 2486 SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */ 2487 SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */ 2488 SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */ 2489 SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */ 2490 SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */ 2491 SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */ 2492 SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */ 2493 SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */ 2494 SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */ 2495 SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */ 2496 SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */ 2497 SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */ 2498 SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */ 2499 SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */ 2500 SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */ 2501 SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */ 2502 SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */ 2503 SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */ 2504 SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */ 2505 SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */ 2506 SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */ 2507 SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */ 2508 SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */ 2509 SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */ 2510 SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */ 2511 SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */ 2512 SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */ 2513 SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */ 2514 SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */ 2515 SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */ 2516 SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */ 2517 SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */ 2518 SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */ 2519 SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */ 2520 SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */ 2521 SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */ 2522 SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */ 2523 SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */ 2524 SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */ 2525 SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */ 2526 SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */ 2527 SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */ 2528 SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */ 2529 SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */ 2530 SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */ 2531 SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */ 2532 SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */ 2533 SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */ 2534 SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */ 2535 SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */ 2536 SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */ 2537 SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */ 2538 SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */ 2539 SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */ 2540 SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */ 2541 SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */ 2542 SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */ 2543 SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */ 2544 SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */ 2545 SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */ 2546 SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */ 2547 SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */ 2548 SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */ 2549 SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */ 2550 SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */ 2551 SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */ 2552 SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */ 2553 SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */ 2554 SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */ 2555 SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */ 2556 SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */ 2557 SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */ 2558 SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */ 2559 SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */ 2560 SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */ 2561 SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */ 2562 SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */ 2563 SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */ 2564 SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */ 2565 SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */ 2566 SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */ 2567 SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */ 2568 SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */ 2569 SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */ 2570 SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */ 2571 SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */ 2572 SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */ 2573 SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */ 2574 SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */ 2575 SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */ 2576 SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */ 2577 SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */ 2578 SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */ 2579 SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */ 2580 SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */ 2581 SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */ 2582 SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */ 2583 SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */ 2584 SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */ 2585 SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */ 2586 SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */ 2587 SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */ 2588 SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */ 2589 SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */ 2590 SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */ 2591 SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */ 2592 SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */ 2593 SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */ 2594 SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */ 2595 SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */ 2596 SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */ 2597 SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */ 2598 SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */ 2599 SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */ 2600 SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */ 2601 SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */ 2602 SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */ 2603 SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */ 2604 SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */ 2605 SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */ 2606 SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */ 2607 SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */ 2608 SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */ 2609 SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */ 2610 SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */ 2611 SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */ 2612 SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */ 2613 SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */ 2614 SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */ 2615 SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */ 2616 SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */ 2617 SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */ 2618 SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */ 2619 SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */ 2620 SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */ 2621 SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */ 2622 SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */ 2623 SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */ 2624 SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */ 2625 SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */ 2626 SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */ 2627 SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */ 2628 SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */ 2629 SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */ 2630 SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */ 2631 SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */ 2632 SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */ 2633 SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */ 2634 SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */ 2635 SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */ 2636 SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */ 2637 SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */ 2638 SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */ 2639 SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */ 2640 SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */ 2641 SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */ 2642 SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */ 2643 SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */ 2644 SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */ 2645 SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */ 2646 SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */ 2647 SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */ 2648 SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */ 2649 SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */ 2650 SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */ 2651 SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */ 2652 }; 2653 2654 }; 2655 union { 2656 /* GPDI - GPIO Pad Data Input Register */ 2657 SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */ 2658 2659 /* GPDI - GPIO Pad Data Input Register */ 2660 SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */ 2661 2662 struct { 2663 /* GPDI - GPIO Pad Data Input Register */ 2664 SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */ 2665 SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */ 2666 SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */ 2667 SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */ 2668 SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */ 2669 SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */ 2670 SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */ 2671 SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */ 2672 SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */ 2673 SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */ 2674 SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */ 2675 SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */ 2676 SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */ 2677 SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */ 2678 SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */ 2679 SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */ 2680 SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */ 2681 SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */ 2682 SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */ 2683 SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */ 2684 SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */ 2685 SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */ 2686 SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */ 2687 SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */ 2688 SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */ 2689 SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */ 2690 SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */ 2691 SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */ 2692 SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */ 2693 SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */ 2694 SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */ 2695 SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */ 2696 SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */ 2697 SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */ 2698 SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */ 2699 SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */ 2700 SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */ 2701 SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */ 2702 SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */ 2703 SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */ 2704 SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */ 2705 SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */ 2706 SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */ 2707 SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */ 2708 SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */ 2709 SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */ 2710 SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */ 2711 SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */ 2712 SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */ 2713 SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */ 2714 SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */ 2715 SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */ 2716 SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */ 2717 SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */ 2718 SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */ 2719 SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */ 2720 SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */ 2721 SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */ 2722 SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */ 2723 SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */ 2724 SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */ 2725 SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */ 2726 SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */ 2727 SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */ 2728 SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */ 2729 SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */ 2730 SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */ 2731 SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */ 2732 SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */ 2733 SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */ 2734 SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */ 2735 SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */ 2736 SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */ 2737 SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */ 2738 SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */ 2739 SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */ 2740 SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */ 2741 SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */ 2742 SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */ 2743 SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */ 2744 SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */ 2745 SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */ 2746 SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */ 2747 SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */ 2748 SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */ 2749 SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */ 2750 SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */ 2751 SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */ 2752 SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */ 2753 SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */ 2754 SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */ 2755 SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */ 2756 SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */ 2757 SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */ 2758 SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */ 2759 SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */ 2760 SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */ 2761 SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */ 2762 SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */ 2763 SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */ 2764 SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */ 2765 SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */ 2766 SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */ 2767 SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */ 2768 SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */ 2769 SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */ 2770 SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */ 2771 SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */ 2772 SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */ 2773 SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */ 2774 SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */ 2775 SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */ 2776 SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */ 2777 SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */ 2778 SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */ 2779 SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */ 2780 SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */ 2781 SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */ 2782 SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */ 2783 SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */ 2784 SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */ 2785 SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */ 2786 SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */ 2787 SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */ 2788 SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */ 2789 SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */ 2790 SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */ 2791 SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */ 2792 }; 2793 2794 struct { 2795 /* GPDI - GPIO Pad Data Input Register */ 2796 SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */ 2797 SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */ 2798 SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */ 2799 SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */ 2800 SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */ 2801 SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */ 2802 SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */ 2803 SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */ 2804 SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */ 2805 SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */ 2806 SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */ 2807 SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */ 2808 SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */ 2809 SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */ 2810 SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */ 2811 SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */ 2812 SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */ 2813 SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */ 2814 SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */ 2815 SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */ 2816 SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */ 2817 SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */ 2818 SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */ 2819 SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */ 2820 SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */ 2821 SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */ 2822 SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */ 2823 SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */ 2824 SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */ 2825 SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */ 2826 SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */ 2827 SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */ 2828 SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */ 2829 SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */ 2830 SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */ 2831 SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */ 2832 SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */ 2833 SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */ 2834 SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */ 2835 SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */ 2836 SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */ 2837 SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */ 2838 SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */ 2839 SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */ 2840 SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */ 2841 SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */ 2842 SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */ 2843 SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */ 2844 SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */ 2845 SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */ 2846 SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */ 2847 SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */ 2848 SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */ 2849 SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */ 2850 SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */ 2851 SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */ 2852 SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */ 2853 SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */ 2854 SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */ 2855 SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */ 2856 SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */ 2857 SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */ 2858 SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */ 2859 SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */ 2860 SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */ 2861 SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */ 2862 SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */ 2863 SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */ 2864 SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */ 2865 SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */ 2866 SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */ 2867 SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */ 2868 SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */ 2869 SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */ 2870 SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */ 2871 SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */ 2872 SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */ 2873 SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */ 2874 SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */ 2875 SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */ 2876 SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */ 2877 SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */ 2878 SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */ 2879 SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */ 2880 SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */ 2881 SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */ 2882 SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */ 2883 SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */ 2884 SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */ 2885 SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */ 2886 SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */ 2887 SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */ 2888 SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */ 2889 SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */ 2890 SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */ 2891 SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */ 2892 SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */ 2893 SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */ 2894 SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */ 2895 SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */ 2896 SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */ 2897 SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */ 2898 SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */ 2899 SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */ 2900 SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */ 2901 SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */ 2902 SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */ 2903 SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */ 2904 SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */ 2905 SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */ 2906 SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */ 2907 SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */ 2908 SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */ 2909 SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */ 2910 SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */ 2911 SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */ 2912 SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */ 2913 SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */ 2914 SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */ 2915 SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */ 2916 SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */ 2917 SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */ 2918 SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */ 2919 SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */ 2920 SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */ 2921 SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */ 2922 SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */ 2923 SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */ 2924 SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */ 2925 SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */ 2926 SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */ 2927 SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */ 2928 SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */ 2929 SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */ 2930 SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */ 2931 SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */ 2932 SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */ 2933 SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */ 2934 SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */ 2935 SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */ 2936 SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */ 2937 SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */ 2938 SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */ 2939 SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */ 2940 SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */ 2941 SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */ 2942 SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */ 2943 SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */ 2944 SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */ 2945 SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */ 2946 SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */ 2947 SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */ 2948 SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */ 2949 SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */ 2950 SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */ 2951 SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */ 2952 SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */ 2953 SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */ 2954 SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */ 2955 SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */ 2956 SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */ 2957 SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */ 2958 SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */ 2959 SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */ 2960 SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */ 2961 SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */ 2962 SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */ 2963 SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */ 2964 SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */ 2965 SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */ 2966 SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */ 2967 SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */ 2968 SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */ 2969 SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */ 2970 SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */ 2971 SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */ 2972 SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */ 2973 SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */ 2974 SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */ 2975 SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */ 2976 SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */ 2977 SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */ 2978 SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */ 2979 SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */ 2980 SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */ 2981 SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */ 2982 SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */ 2983 SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */ 2984 SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */ 2985 SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */ 2986 SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */ 2987 SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */ 2988 SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */ 2989 SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */ 2990 SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */ 2991 SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */ 2992 SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */ 2993 SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */ 2994 SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */ 2995 SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */ 2996 SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */ 2997 SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */ 2998 SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */ 2999 SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */ 3000 SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */ 3001 SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */ 3002 SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */ 3003 SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */ 3004 SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */ 3005 SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */ 3006 SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */ 3007 SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */ 3008 SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */ 3009 SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */ 3010 SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */ 3011 SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */ 3012 SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */ 3013 SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */ 3014 SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */ 3015 SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */ 3016 SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */ 3017 SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */ 3018 SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */ 3019 SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */ 3020 SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */ 3021 SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */ 3022 SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */ 3023 SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */ 3024 SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */ 3025 SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */ 3026 SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */ 3027 SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */ 3028 SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */ 3029 SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */ 3030 SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */ 3031 SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */ 3032 SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */ 3033 SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */ 3034 SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */ 3035 SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */ 3036 SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */ 3037 SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */ 3038 SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */ 3039 SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */ 3040 SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */ 3041 SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */ 3042 SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */ 3043 SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */ 3044 SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */ 3045 SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */ 3046 SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */ 3047 SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */ 3048 SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */ 3049 SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */ 3050 SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */ 3051 SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */ 3052 SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */ 3053 SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */ 3054 SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */ 3055 SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */ 3056 SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */ 3057 SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */ 3058 SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */ 3059 SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */ 3060 SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */ 3061 SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */ 3062 SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */ 3063 SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */ 3064 SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */ 3065 SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */ 3066 SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */ 3067 SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */ 3068 SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */ 3069 SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */ 3070 SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */ 3071 SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */ 3072 SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */ 3073 SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */ 3074 SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */ 3075 SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */ 3076 SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */ 3077 SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */ 3078 SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */ 3079 SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */ 3080 SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */ 3081 SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */ 3082 SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */ 3083 SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */ 3084 SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */ 3085 SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */ 3086 SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */ 3087 SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */ 3088 SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */ 3089 SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */ 3090 SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */ 3091 SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */ 3092 SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */ 3093 SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */ 3094 SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */ 3095 SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */ 3096 SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */ 3097 SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */ 3098 SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */ 3099 SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */ 3100 SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */ 3101 SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */ 3102 SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */ 3103 SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */ 3104 SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */ 3105 SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */ 3106 SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */ 3107 SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */ 3108 SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */ 3109 SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */ 3110 SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */ 3111 SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */ 3112 SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */ 3113 SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */ 3114 SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */ 3115 SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */ 3116 SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */ 3117 SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */ 3118 SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */ 3119 SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */ 3120 SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */ 3121 SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */ 3122 SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */ 3123 SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */ 3124 SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */ 3125 SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */ 3126 SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */ 3127 SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */ 3128 SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */ 3129 SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */ 3130 SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */ 3131 SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */ 3132 SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */ 3133 SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */ 3134 SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */ 3135 SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */ 3136 SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */ 3137 SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */ 3138 SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */ 3139 SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */ 3140 SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */ 3141 SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */ 3142 SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */ 3143 SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */ 3144 SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */ 3145 SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */ 3146 SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */ 3147 SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */ 3148 SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */ 3149 SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */ 3150 SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */ 3151 SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */ 3152 SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */ 3153 SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */ 3154 SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */ 3155 SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */ 3156 SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */ 3157 SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */ 3158 SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */ 3159 SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */ 3160 SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */ 3161 SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */ 3162 SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */ 3163 SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */ 3164 SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */ 3165 SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */ 3166 SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */ 3167 SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */ 3168 SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */ 3169 SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */ 3170 SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */ 3171 SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */ 3172 SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */ 3173 SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */ 3174 SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */ 3175 SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */ 3176 SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */ 3177 SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */ 3178 SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */ 3179 SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */ 3180 SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */ 3181 SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */ 3182 SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */ 3183 SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */ 3184 SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */ 3185 SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */ 3186 SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */ 3187 SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */ 3188 SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */ 3189 SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */ 3190 SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */ 3191 SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */ 3192 SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */ 3193 SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */ 3194 SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */ 3195 SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */ 3196 SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */ 3197 SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */ 3198 SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */ 3199 SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */ 3200 SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */ 3201 SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */ 3202 SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */ 3203 SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */ 3204 SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */ 3205 SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */ 3206 SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */ 3207 SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */ 3208 SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */ 3209 SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */ 3210 SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */ 3211 SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */ 3212 SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */ 3213 SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */ 3214 SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */ 3215 SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */ 3216 SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */ 3217 SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */ 3218 SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */ 3219 SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */ 3220 SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */ 3221 SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */ 3222 SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */ 3223 SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */ 3224 SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */ 3225 SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */ 3226 SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */ 3227 SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */ 3228 SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */ 3229 SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */ 3230 SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */ 3231 SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */ 3232 SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */ 3233 SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */ 3234 SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */ 3235 SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */ 3236 SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */ 3237 SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */ 3238 SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */ 3239 SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */ 3240 SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */ 3241 SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */ 3242 SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */ 3243 SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */ 3244 SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */ 3245 SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */ 3246 SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */ 3247 SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */ 3248 SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */ 3249 SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */ 3250 SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */ 3251 SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */ 3252 SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */ 3253 SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */ 3254 SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */ 3255 SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */ 3256 SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */ 3257 SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */ 3258 SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */ 3259 SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */ 3260 SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */ 3261 SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */ 3262 SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */ 3263 SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */ 3264 SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */ 3265 SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */ 3266 SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */ 3267 SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */ 3268 SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */ 3269 SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */ 3270 SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */ 3271 SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */ 3272 SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */ 3273 SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */ 3274 SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */ 3275 SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */ 3276 SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */ 3277 SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */ 3278 SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */ 3279 SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */ 3280 SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */ 3281 SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */ 3282 SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */ 3283 SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */ 3284 SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */ 3285 SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */ 3286 SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */ 3287 SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */ 3288 SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */ 3289 SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */ 3290 SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */ 3291 SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */ 3292 SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */ 3293 SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */ 3294 SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */ 3295 SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */ 3296 SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */ 3297 SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */ 3298 SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */ 3299 SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */ 3300 SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */ 3301 SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */ 3302 SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */ 3303 SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */ 3304 SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */ 3305 SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */ 3306 SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */ 3307 SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */ 3308 }; 3309 3310 }; 3311 int8_t SIUL_reserved_0A00_C[512]; 3312 union { 3313 /* PGPDO - Parallel GPIO Pad Data Out Register */ 3314 SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */ 3315 3316 struct { 3317 /* PGPDO - Parallel GPIO Pad Data Out Register */ 3318 SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */ 3319 SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */ 3320 SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */ 3321 SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */ 3322 SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */ 3323 SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */ 3324 SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */ 3325 SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */ 3326 SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */ 3327 SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */ 3328 SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */ 3329 SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */ 3330 SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */ 3331 SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */ 3332 SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */ 3333 SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */ 3334 SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */ 3335 SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */ 3336 SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */ 3337 SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */ 3338 SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */ 3339 SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */ 3340 SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */ 3341 SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */ 3342 SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */ 3343 SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */ 3344 SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */ 3345 SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */ 3346 SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */ 3347 SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */ 3348 SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */ 3349 SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */ 3350 }; 3351 3352 }; 3353 union { 3354 /* PGPDI - Parallel GPIO Pad Data In Register */ 3355 SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */ 3356 3357 struct { 3358 /* PGPDI - Parallel GPIO Pad Data In Register */ 3359 SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */ 3360 SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */ 3361 SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */ 3362 SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */ 3363 SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */ 3364 SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */ 3365 SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */ 3366 SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */ 3367 SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */ 3368 SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */ 3369 SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */ 3370 SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */ 3371 SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */ 3372 SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */ 3373 SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */ 3374 SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */ 3375 SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */ 3376 SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */ 3377 SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */ 3378 SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */ 3379 SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */ 3380 SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */ 3381 SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */ 3382 SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */ 3383 SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */ 3384 SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */ 3385 SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */ 3386 SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */ 3387 SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */ 3388 SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */ 3389 SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */ 3390 SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */ 3391 }; 3392 3393 }; 3394 union { 3395 /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ 3396 SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */ 3397 3398 struct { 3399 /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ 3400 SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */ 3401 SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */ 3402 SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */ 3403 SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */ 3404 SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */ 3405 SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */ 3406 SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */ 3407 SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */ 3408 SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */ 3409 SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */ 3410 SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */ 3411 SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */ 3412 SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */ 3413 SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */ 3414 SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */ 3415 SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */ 3416 SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */ 3417 SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */ 3418 SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */ 3419 SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */ 3420 SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */ 3421 SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */ 3422 SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */ 3423 SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */ 3424 SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */ 3425 SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */ 3426 SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */ 3427 SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */ 3428 SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */ 3429 SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */ 3430 SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */ 3431 SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */ 3432 }; 3433 3434 }; 3435 int8_t SIUL_reserved_0D00_C[768]; 3436 union { 3437 /* IFMC - Interrupt Filter Maximum Counter Register */ 3438 SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */ 3439 3440 struct { 3441 /* IFMC - Interrupt Filter Maximum Counter Register */ 3442 SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */ 3443 SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */ 3444 SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */ 3445 SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */ 3446 SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */ 3447 SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */ 3448 SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */ 3449 SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */ 3450 SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */ 3451 SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */ 3452 SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */ 3453 SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */ 3454 SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */ 3455 SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */ 3456 SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */ 3457 SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */ 3458 SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */ 3459 SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */ 3460 SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */ 3461 SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */ 3462 SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */ 3463 SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */ 3464 SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */ 3465 SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */ 3466 SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */ 3467 SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */ 3468 SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */ 3469 SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */ 3470 SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */ 3471 SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */ 3472 SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */ 3473 SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */ 3474 }; 3475 3476 }; 3477 /* IFCPR - Inerrupt Filter Clock Prescaler Register */ 3478 SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */ 3479 } SIU_tag; 3480 3481 3482 #define SIUL (*(volatile SIU_tag *) 0xC3F90000UL) 3483 3484 3485 3486 /****************************************************************/ 3487 /* */ 3488 /* Module: WKPU */ 3489 /* */ 3490 /****************************************************************/ 3491 3492 typedef union { /* WKPU_NSR - NMI Status Flag Register */ 3493 uint32_t R; 3494 struct { 3495 uint32_t NIF0:1; /* NMI Status Flag 0 */ 3496 uint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */ 3497 uint32_t:6; 3498 uint32_t NIF1:1; /* NMI Status Flag 1 */ 3499 uint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */ 3500 uint32_t:6; 3501 uint32_t NIF2:1; /* NMI Status Flag 2 */ 3502 uint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */ 3503 uint32_t:6; 3504 uint32_t NIF3:1; /* NMI Status Flag 3 */ 3505 uint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */ 3506 uint32_t:6; 3507 } B; 3508 } WKPU_NSR_32B_tag; 3509 3510 typedef union { /* WKPU_NCR - NMI Configuration Register */ 3511 uint32_t R; 3512 struct { 3513 uint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */ 3514 uint32_t NDSS0:2; /* NMI Desination Source Select 0 */ 3515 uint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */ 3516 uint32_t:1; 3517 uint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */ 3518 uint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */ 3519 uint32_t NFE0:1; /* NMI Filter Enable 0 */ 3520 uint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */ 3521 uint32_t NDSS1:2; /* NMI Desination Source Select 1 */ 3522 uint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */ 3523 uint32_t:1; 3524 uint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */ 3525 uint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */ 3526 uint32_t NFE1:1; /* NMI Filter Enable 1 */ 3527 uint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */ 3528 uint32_t NDSS2:2; /* NMI Desination Source Select 2 */ 3529 uint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */ 3530 uint32_t:1; 3531 uint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */ 3532 uint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */ 3533 uint32_t NFE2:1; /* NMI Filter Enable 2 */ 3534 uint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */ 3535 uint32_t NDSS3:2; /* NMI Desination Source Select 3 */ 3536 uint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */ 3537 uint32_t:1; 3538 uint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */ 3539 uint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */ 3540 uint32_t NFE3:1; /* NMI Filter Enable 3 */ 3541 } B; 3542 } WKPU_NCR_32B_tag; 3543 3544 typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ 3545 uint32_t R; 3546 struct { 3547 uint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */ 3548 } B; 3549 } WKPU_WISR_32B_tag; 3550 3551 typedef union { /* WKPU_IRER - Interrupt Request Enable Register */ 3552 uint32_t R; 3553 struct { 3554 uint32_t EIRE:32; /* Enable External Interrupt Requests */ 3555 } B; 3556 } WKPU_IRER_32B_tag; 3557 3558 typedef union { /* WKPU_WRER - Wakeup Request Enable Register */ 3559 uint32_t R; 3560 struct { 3561 uint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */ 3562 } B; 3563 } WKPU_WRER_32B_tag; 3564 3565 typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ 3566 uint32_t R; 3567 struct { 3568 uint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */ 3569 } B; 3570 } WKPU_WIREER_32B_tag; 3571 3572 typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ 3573 uint32_t R; 3574 struct { 3575 uint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */ 3576 } B; 3577 } WKPU_WIFEER_32B_tag; 3578 3579 typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ 3580 uint32_t R; 3581 struct { 3582 uint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */ 3583 } B; 3584 } WKPU_WIFER_32B_tag; 3585 3586 typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ 3587 uint32_t R; 3588 struct { 3589 uint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */ 3590 } B; 3591 } WKPU_WIPUER_32B_tag; 3592 3593 3594 3595 typedef struct WKPU_struct_tag { /* start of WKPU_tag */ 3596 /* WKPU_NSR - NMI Status Flag Register */ 3597 WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */ 3598 int8_t WKPU_reserved_0004[4]; 3599 /* WKPU_NCR - NMI Configuration Register */ 3600 WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */ 3601 int8_t WKPU_reserved_000C[8]; 3602 /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ 3603 WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */ 3604 /* WKPU_IRER - Interrupt Request Enable Register */ 3605 WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ 3606 /* WKPU_WRER - Wakeup Request Enable Register */ 3607 WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */ 3608 int8_t WKPU_reserved_0020[8]; 3609 /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ 3610 WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */ 3611 /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ 3612 WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */ 3613 /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ 3614 WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */ 3615 /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ 3616 WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */ 3617 } WKPU_tag; 3618 3619 3620 #define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL) 3621 3622 3623 3624 /****************************************************************/ 3625 /* */ 3626 /* Module: SSCM */ 3627 /* */ 3628 /****************************************************************/ 3629 3630 typedef union { /* SSCM_STATUS - System Status Register */ 3631 uint16_t R; 3632 struct { 3633 uint16_t LSM:1; /* Lock Step Mode */ 3634 uint16_t:2; 3635 uint16_t NXEN1:1; /* Processor 1 Nexus enabled */ 3636 uint16_t NXEN:1; /* Processor 0 Nexus enabled */ 3637 uint16_t PUB:1; /* Public Serial Access Status */ 3638 uint16_t SEC:1; /* Security Status */ 3639 uint16_t:1; 3640 uint16_t BMODE:3; /* Device Boot Mode */ 3641 uint16_t VLE:1; /* Variable Length Instruction Mode */ 3642 uint16_t ABD:1; /* Autobaud detection */ 3643 uint16_t:3; 3644 } B; 3645 } SSCM_STATUS_16B_tag; 3646 3647 typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */ 3648 uint16_t R; 3649 struct { 3650 uint16_t JPIN:10; /* JTAG Part ID Number */ 3651 uint16_t IVLD:1; /* Instruction Flash Valid */ 3652 uint16_t MREV:4; /* Minor Mask Revision */ 3653 uint16_t DVLD:1; /* Data Flash Valid */ 3654 } B; 3655 } SSCM_MEMCONFIG_16B_tag; 3656 3657 typedef union { /* SSCM_ERROR - Error Configuration */ 3658 uint16_t R; 3659 struct { 3660 uint16_t:14; 3661 uint16_t PAE:1; /* Peripheral Bus Abort Enable */ 3662 uint16_t RAE:1; /* Register Bus Abort Enable */ 3663 } B; 3664 } SSCM_ERROR_16B_tag; 3665 3666 typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */ 3667 uint16_t R; 3668 struct { 3669 uint16_t:13; 3670 uint16_t DEBUG_MODE:3; /* Debug Status Port Mode */ 3671 } B; 3672 } SSCM_DEBUGPORT_16B_tag; 3673 3674 typedef union { /* SSCM_PWCMPH - Password Comparison Register High */ 3675 uint32_t R; 3676 struct { 3677 uint32_t PWD_HI:32; /* Password High */ 3678 } B; 3679 } SSCM_PWCMPH_32B_tag; 3680 3681 typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */ 3682 uint32_t R; 3683 struct { 3684 uint32_t PWD_LO:32; /* Password Low */ 3685 } B; 3686 } SSCM_PWCMPL_32B_tag; 3687 3688 typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ 3689 uint32_t R; 3690 struct { 3691 uint32_t P2BOOT:30; /* boot location 2nd processor */ 3692 uint32_t DVLE:1; /* VLE mode for 2nd processor */ 3693 uint32_t:1; 3694 } B; 3695 } SSCM_DPMBOOT_32B_tag; 3696 3697 typedef union { /* SSCM_DPMKEY - Boot Key Register */ 3698 uint32_t R; 3699 struct { 3700 uint32_t KEY:32; /* Boot Control Key */ 3701 } B; 3702 } SSCM_DPMKEY_32B_tag; 3703 3704 typedef union { /* SSCM_UOPS - User Option Status Register */ 3705 uint32_t R; 3706 struct { 3707 uint32_t UOPT:32; /* User Option Bits */ 3708 } B; 3709 } SSCM_UOPS_32B_tag; 3710 3711 typedef union { /* SSCM_SCTR - SSCM Control Register */ 3712 uint32_t R; 3713 struct { 3714 uint32_t:29; 3715 uint32_t TFE:1; /* Test Flash Enable */ 3716 uint32_t DSL:1; /* Disable Software-Controlled MBIST */ 3717 uint32_t DSM:1; /* Disable Software-Controlled LBIST */ 3718 } B; 3719 } SSCM_SCTR_32B_tag; 3720 3721 typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ 3722 uint32_t R; 3723 struct { 3724 uint32_t TINFO0:32; /* General purpose TestFlash word 0 */ 3725 } B; 3726 } SSCM_TF_INFO0_32B_tag; 3727 3728 typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ 3729 uint32_t R; 3730 struct { 3731 uint32_t TINFO1:32; /* General purpose TestFlash word 1 */ 3732 } B; 3733 } SSCM_TF_INFO1_32B_tag; 3734 3735 typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ 3736 uint32_t R; 3737 struct { 3738 uint32_t TINFO2:32; /* General purpose TestFlash word 2 */ 3739 } B; 3740 } SSCM_TF_INFO2_32B_tag; 3741 3742 typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ 3743 uint32_t R; 3744 struct { 3745 uint32_t TINFO3:32; /* General purpose TestFlash word */ 3746 } B; 3747 } SSCM_TF_INFO3_32B_tag; 3748 3749 3750 3751 typedef struct SSCM_struct_tag { /* start of SSCM_tag */ 3752 /* SSCM_STATUS - System Status Register */ 3753 SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */ 3754 /* SSCM_MEMCONFIG - System Memory Configuration Register */ 3755 SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */ 3756 int8_t SSCM_reserved_0004[2]; 3757 /* SSCM_ERROR - Error Configuration */ 3758 SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */ 3759 /* SSCM_DEBUGPORT - Debug Status Port Register */ 3760 SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */ 3761 int8_t SSCM_reserved_000A[2]; 3762 /* SSCM_PWCMPH - Password Comparison Register High */ 3763 SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */ 3764 /* SSCM_PWCMPL - Password Comparison Register Low */ 3765 SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */ 3766 int8_t SSCM_reserved_0014[4]; 3767 /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ 3768 SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */ 3769 /* SSCM_DPMKEY - Boot Key Register */ 3770 SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */ 3771 /* SSCM_UOPS - User Option Status Register */ 3772 SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */ 3773 /* SSCM_SCTR - SSCM Control Register */ 3774 SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */ 3775 /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ 3776 SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */ 3777 /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ 3778 SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */ 3779 /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ 3780 SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */ 3781 /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ 3782 SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */ 3783 } SSCM_tag; 3784 3785 3786 #define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL) 3787 3788 3789 3790 /****************************************************************/ 3791 /* */ 3792 /* Module: ME */ 3793 /* */ 3794 /****************************************************************/ 3795 3796 typedef union { /* ME_GS - Global Status Register */ 3797 uint32_t R; 3798 struct { 3799 #ifndef USE_FIELD_ALIASES_ME 3800 uint32_t S_CURRENT_MODE:4; /* Current device mode status */ 3801 #else 3802 uint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */ 3803 #endif 3804 uint32_t S_MTRANS:1; /* Mode transition status */ 3805 uint32_t:3; 3806 uint32_t S_PDO:1; /* Output power-down status */ 3807 uint32_t:2; 3808 uint32_t S_MVR:1; /* Main voltage regulator status */ 3809 uint32_t:2; 3810 #ifndef USE_FIELD_ALIASES_ME 3811 uint32_t S_FLA:2; /* Flash availability status */ 3812 #else 3813 uint32_t S_CFLA:2; /* deprecated name - please avoid */ 3814 #endif 3815 uint32_t:8; 3816 uint32_t S_PLL1:1; /* Secondary PLL status */ 3817 uint32_t S_PLL0:1; /* System PLL status */ 3818 #ifndef USE_FIELD_ALIASES_ME 3819 uint32_t S_XOSC:1; /* System crystal oscillator status */ 3820 #else 3821 uint32_t S_OSC:1; /* deprecated name - please avoid */ 3822 #endif 3823 #ifndef USE_FIELD_ALIASES_ME 3824 uint32_t S_IRCOSC:1; /* System RC oscillator status */ 3825 #else 3826 uint32_t S_RC:1; /* deprecated name - please avoid */ 3827 #endif 3828 uint32_t S_SYSCLK:4; /* System clock switch status */ 3829 } B; 3830 } ME_GS_32B_tag; 3831 3832 typedef union { /* ME_MCTL - Mode Control Register */ 3833 uint32_t R; 3834 struct { 3835 uint32_t TARGET_MODE:4; /* Target device mode */ 3836 uint32_t:12; 3837 uint32_t KEY:16; /* Control key */ 3838 } B; 3839 } ME_MCTL_32B_tag; 3840 3841 typedef union { /* ME_MEN - Mode Enable Register */ 3842 uint32_t R; 3843 struct { 3844 uint32_t:21; 3845 uint32_t STOP0:1; /* STOP0 mode enable */ 3846 uint32_t:1; 3847 uint32_t HALT0:1; /* HALT0 mode enable */ 3848 uint32_t RUN3:1; /* RUN3 mode enable */ 3849 uint32_t RUN2:1; /* RUN2 mode enable */ 3850 uint32_t RUN1:1; /* RUN1 mode enable */ 3851 uint32_t RUN0:1; /* RUN0 mode enable */ 3852 uint32_t DRUN:1; /* DRUN mode enable */ 3853 uint32_t SAFE:1; /* SAFE mode enable */ 3854 uint32_t:1; 3855 uint32_t RESET:1; /* RESET mode enable */ 3856 } B; 3857 } ME_MEN_32B_tag; 3858 3859 typedef union { /* ME_IS - Interrupt Status Register */ 3860 uint32_t R; 3861 struct { 3862 uint32_t:28; 3863 #ifndef USE_FIELD_ALIASES_ME 3864 uint32_t I_ICONF:1; /* Invalid mode config interrupt */ 3865 #else 3866 uint32_t I_CONF:1; /* deprecated name - please avoid */ 3867 #endif 3868 #ifndef USE_FIELD_ALIASES_ME 3869 uint32_t I_IMODE:1; /* Invalid mode interrupt */ 3870 #else 3871 uint32_t I_MODE:1; /* deprecated name - please avoid */ 3872 #endif 3873 uint32_t I_SAFE:1; /* SAFE mode interrupt */ 3874 #ifndef USE_FIELD_ALIASES_ME 3875 uint32_t I_MTC:1; /* Mode transition complete interrupt */ 3876 #else 3877 uint32_t I_TC:1; /* deprecated name - please avoid */ 3878 #endif 3879 } B; 3880 } ME_IS_32B_tag; 3881 3882 typedef union { /* ME_IM - Interrupt Mask Register */ 3883 uint32_t R; 3884 struct { 3885 uint32_t:28; 3886 #ifndef USE_FIELD_ALIASES_ME 3887 uint32_t M_ICONF:1; /* Invalid mode config interrupt mask */ 3888 #else 3889 uint32_t M_CONF:1; /* deprecated name - please avoid */ 3890 #endif 3891 #ifndef USE_FIELD_ALIASES_ME 3892 uint32_t M_IMODE:1; /* Invalid mode interrupt mask */ 3893 #else 3894 uint32_t M_MODE:1; /* deprecated name - please avoid */ 3895 #endif 3896 uint32_t M_SAFE:1; /* SAFE mode interrupt mask */ 3897 #ifndef USE_FIELD_ALIASES_ME 3898 uint32_t M_MTC:1; /* Mode transition complete interrupt mask */ 3899 #else 3900 uint32_t M_TC:1; /* deprecated name - please avoid */ 3901 #endif 3902 } B; 3903 } ME_IM_32B_tag; 3904 3905 typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */ 3906 uint32_t R; 3907 struct { 3908 uint32_t:27; 3909 uint32_t S_MTI:1; /* Mode Transition Illegal status */ 3910 uint32_t S_MRI:1; /* Mode Request Illegal status */ 3911 uint32_t S_DMA:1; /* Disabled Mode Access status */ 3912 uint32_t S_NMA:1; /* Non-existing Mode Access status */ 3913 uint32_t S_SEA:1; /* Safe Event Active status */ 3914 } B; 3915 } ME_IMTS_32B_tag; 3916 3917 typedef union { /* ME_DMTS - Debug Mode Transition Status Register */ 3918 uint32_t R; 3919 struct { 3920 uint32_t PREVIOUS_MODE:4; /* Previous Device Mode */ 3921 uint32_t:4; 3922 uint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */ 3923 uint32_t:2; 3924 uint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */ 3925 uint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */ 3926 uint32_t:2; 3927 uint32_t SMR:1; /* SAFE Mode Request */ 3928 uint32_t:1; 3929 uint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */ 3930 uint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */ 3931 uint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */ 3932 uint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */ 3933 uint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */ 3934 uint32_t:1; 3935 uint32_t FLASH_SC:1; /* FLASH State Change Indicator */ 3936 uint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */ 3937 uint32_t:4; 3938 uint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */ 3939 uint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */ 3940 uint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */ 3941 } B; 3942 } ME_DMTS_32B_tag; 3943 3944 typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */ 3945 uint32_t R; 3946 struct { 3947 uint32_t:8; 3948 uint32_t PDO:1; /* IOs output power-down control */ 3949 uint32_t:2; 3950 uint32_t MVRON:1; /* Main voltage regulator control */ 3951 uint32_t:2; 3952 uint32_t FLAON:2; /* Flash power-down control */ 3953 uint32_t:8; 3954 #ifndef USE_FIELD_ALIASES_ME 3955 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ 3956 #else 3957 uint32_t PLL2ON:1; /* deprecated name - please avoid */ 3958 #endif 3959 #ifndef USE_FIELD_ALIASES_ME 3960 uint32_t PLL0ON:1; /* System PLL control */ 3961 #else 3962 uint32_t PLL1ON:1; /* deprecated name - please avoid */ 3963 #endif 3964 #ifndef USE_FIELD_ALIASES_ME 3965 uint32_t XOSCON:1; /* System crystal oscillator control */ 3966 #else 3967 uint32_t XOSC0ON:1; /* deprecated name - please avoid */ 3968 #endif 3969 #ifndef USE_FIELD_ALIASES_ME 3970 uint32_t IRCOSCON:1; /* System RC oscillator control */ 3971 #else 3972 uint32_t IRCON:1; /* deprecated name - please avoid */ 3973 #endif 3974 uint32_t SYSCLK:4; /* System clock switch control */ 3975 } B; 3976 } ME_RESET_MC_32B_tag; 3977 3978 typedef union { /* ME_SAFE_MC - Mode Configuration Register */ 3979 uint32_t R; 3980 struct { 3981 uint32_t:8; 3982 uint32_t PDO:1; /* IOs output power-down control */ 3983 uint32_t:2; 3984 uint32_t MVRON:1; /* Main voltage regulator control */ 3985 uint32_t:2; 3986 uint32_t FLAON:2; /* Flash power-down control */ 3987 uint32_t:8; 3988 #ifndef USE_FIELD_ALIASES_ME 3989 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ 3990 #else 3991 uint32_t PLL2ON:1; /* deprecated name - please avoid */ 3992 #endif 3993 #ifndef USE_FIELD_ALIASES_ME 3994 uint32_t PLL0ON:1; /* System PLL control */ 3995 #else 3996 uint32_t PLL1ON:1; /* deprecated name - please avoid */ 3997 #endif 3998 #ifndef USE_FIELD_ALIASES_ME 3999 uint32_t XOSCON:1; /* System crystal oscillator control */ 4000 #else 4001 uint32_t XOSC0ON:1; /* deprecated name - please avoid */ 4002 #endif 4003 #ifndef USE_FIELD_ALIASES_ME 4004 uint32_t IRCOSCON:1; /* System RC oscillator control */ 4005 #else 4006 uint32_t IRCON:1; /* deprecated name - please avoid */ 4007 #endif 4008 uint32_t SYSCLK:4; /* System clock switch control */ 4009 } B; 4010 } ME_SAFE_MC_32B_tag; 4011 4012 typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */ 4013 uint32_t R; 4014 struct { 4015 uint32_t:8; 4016 uint32_t PDO:1; /* IOs output power-down control */ 4017 uint32_t:2; 4018 uint32_t MVRON:1; /* Main voltage regulator control */ 4019 uint32_t:2; 4020 uint32_t FLAON:2; /* Flash power-down control */ 4021 uint32_t:8; 4022 #ifndef USE_FIELD_ALIASES_ME 4023 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ 4024 #else 4025 uint32_t PLL2ON:1; /* deprecated name - please avoid */ 4026 #endif 4027 #ifndef USE_FIELD_ALIASES_ME 4028 uint32_t PLL0ON:1; /* System PLL control */ 4029 #else 4030 uint32_t PLL1ON:1; /* deprecated name - please avoid */ 4031 #endif 4032 #ifndef USE_FIELD_ALIASES_ME 4033 uint32_t XOSCON:1; /* System crystal oscillator control */ 4034 #else 4035 uint32_t XOSC0ON:1; /* deprecated name - please avoid */ 4036 #endif 4037 #ifndef USE_FIELD_ALIASES_ME 4038 uint32_t IRCOSCON:1; /* System RC oscillator control */ 4039 #else 4040 uint32_t IRCON:1; /* deprecated name - please avoid */ 4041 #endif 4042 uint32_t SYSCLK:4; /* System clock switch control */ 4043 } B; 4044 } ME_DRUN_MC_32B_tag; 4045 4046 4047 /* Register layout for all registers RUN_MC... */ 4048 4049 typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ 4050 uint32_t R; 4051 struct { 4052 uint32_t:8; 4053 uint32_t PDO:1; /* IOs output power-down control */ 4054 uint32_t:2; 4055 uint32_t MVRON:1; /* Main voltage regulator control */ 4056 uint32_t:2; 4057 uint32_t FLAON:2; /* Flash power-down control */ 4058 uint32_t:8; 4059 #ifndef USE_FIELD_ALIASES_ME 4060 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ 4061 #else 4062 uint32_t PLL2ON:1; /* deprecated name - please avoid */ 4063 #endif 4064 #ifndef USE_FIELD_ALIASES_ME 4065 uint32_t PLL0ON:1; /* System PLL control */ 4066 #else 4067 uint32_t PLL1ON:1; /* deprecated name - please avoid */ 4068 #endif 4069 #ifndef USE_FIELD_ALIASES_ME 4070 uint32_t XOSCON:1; /* System crystal oscillator control */ 4071 #else 4072 uint32_t XOSC0ON:1; /* deprecated name - please avoid */ 4073 #endif 4074 #ifndef USE_FIELD_ALIASES_ME 4075 uint32_t IRCOSCON:1; /* System RC oscillator control */ 4076 #else 4077 uint32_t IRCON:1; /* deprecated name - please avoid */ 4078 #endif 4079 uint32_t SYSCLK:4; /* System clock switch control */ 4080 } B; 4081 } ME_RUN_MC_32B_tag; 4082 4083 typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */ 4084 uint32_t R; 4085 struct { 4086 uint32_t:8; 4087 uint32_t PDO:1; /* IOs output power-down control */ 4088 uint32_t:2; 4089 uint32_t MVRON:1; /* Main voltage regulator control */ 4090 uint32_t:2; 4091 uint32_t FLAON:2; /* Flash power-down control */ 4092 uint32_t:8; 4093 #ifndef USE_FIELD_ALIASES_ME 4094 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ 4095 #else 4096 uint32_t PLL2ON:1; /* deprecated name - please avoid */ 4097 #endif 4098 #ifndef USE_FIELD_ALIASES_ME 4099 uint32_t PLL0ON:1; /* System PLL control */ 4100 #else 4101 uint32_t PLL1ON:1; /* deprecated name - please avoid */ 4102 #endif 4103 #ifndef USE_FIELD_ALIASES_ME 4104 uint32_t XOSCON:1; /* System crystal oscillator control */ 4105 #else 4106 uint32_t XOSC0ON:1; /* deprecated name - please avoid */ 4107 #endif 4108 #ifndef USE_FIELD_ALIASES_ME 4109 uint32_t IRCOSCON:1; /* System RC oscillator control */ 4110 #else 4111 uint32_t IRCON:1; /* deprecated name - please avoid */ 4112 #endif 4113 uint32_t SYSCLK:4; /* System clock switch control */ 4114 } B; 4115 } ME_HALT0_MC_32B_tag; 4116 4117 typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */ 4118 uint32_t R; 4119 struct { 4120 uint32_t:8; 4121 uint32_t PDO:1; /* IOs output power-down control */ 4122 uint32_t:2; 4123 uint32_t MVRON:1; /* Main voltage regulator control */ 4124 uint32_t:2; 4125 uint32_t FLAON:2; /* Flash power-down control */ 4126 uint32_t:8; 4127 #ifndef USE_FIELD_ALIASES_ME 4128 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ 4129 #else 4130 uint32_t PLL2ON:1; /* deprecated name - please avoid */ 4131 #endif 4132 #ifndef USE_FIELD_ALIASES_ME 4133 uint32_t PLL0ON:1; /* System PLL control */ 4134 #else 4135 uint32_t PLL1ON:1; /* deprecated name - please avoid */ 4136 #endif 4137 #ifndef USE_FIELD_ALIASES_ME 4138 uint32_t XOSCON:1; /* System crystal oscillator control */ 4139 #else 4140 uint32_t XOSC0ON:1; /* deprecated name - please avoid */ 4141 #endif 4142 #ifndef USE_FIELD_ALIASES_ME 4143 uint32_t IRCOSCON:1; /* System RC oscillator control */ 4144 #else 4145 uint32_t IRCON:1; /* deprecated name - please avoid */ 4146 #endif 4147 uint32_t SYSCLK:4; /* System clock switch control */ 4148 } B; 4149 } ME_STOP0_MC_32B_tag; 4150 4151 typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ 4152 uint32_t R; 4153 struct { 4154 uint32_t:8; 4155 uint32_t PDO:1; /* IOs output power-down control */ 4156 uint32_t:2; 4157 uint32_t MVRON:1; /* Main voltage regulator control */ 4158 uint32_t:2; 4159 uint32_t FLAON:2; /* Flash power-down control */ 4160 uint32_t:8; 4161 #ifndef USE_FIELD_ALIASES_ME 4162 uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ 4163 #else 4164 uint32_t PLL2ON:1; /* deprecated name - please avoid */ 4165 #endif 4166 #ifndef USE_FIELD_ALIASES_ME 4167 uint32_t PLL0ON:1; /* System PLL control */ 4168 #else 4169 uint32_t PLL1ON:1; /* deprecated name - please avoid */ 4170 #endif 4171 #ifndef USE_FIELD_ALIASES_ME 4172 uint32_t XOSCON:1; /* System crystal oscillator control */ 4173 #else 4174 uint32_t XOSC0ON:1; /* deprecated name - please avoid */ 4175 #endif 4176 #ifndef USE_FIELD_ALIASES_ME 4177 uint32_t IRCOSCON:1; /* System RC oscillator control */ 4178 #else 4179 uint32_t IRCON:1; /* deprecated name - please avoid */ 4180 #endif 4181 uint32_t SYSCLK:4; /* System clock switch control */ 4182 } B; 4183 } ME_STANDBY0_MC_32B_tag; 4184 4185 typedef union { /* ME_PS0 - Peripheral Status Register 0 */ 4186 uint32_t R; 4187 struct { 4188 uint32_t:7; 4189 uint32_t S_FLEXRAY:1; /* FlexRay status */ 4190 uint32_t:6; 4191 uint32_t S_FLEXCAN1:1; /* FlexCAN1 status */ 4192 uint32_t S_FLEXCAN0:1; /* FlexCAN0 status */ 4193 uint32_t:9; 4194 uint32_t S_DSPI2:1; /* DSPI2 status */ 4195 uint32_t S_DSPI1:1; /* DSPI1 status */ 4196 uint32_t S_DSPI0:1; /* DSPI0 status */ 4197 uint32_t:4; 4198 } B; 4199 } ME_PS0_32B_tag; 4200 4201 typedef union { /* ME_PS1 - Peripheral Status Register 1 */ 4202 uint32_t R; 4203 struct { 4204 uint32_t:1; 4205 uint32_t S_SWG:1; /* SWG status */ 4206 uint32_t:3; 4207 uint32_t S_CRC:1; /* CRC status */ 4208 uint32_t:8; 4209 uint32_t S_LIN_FLEX1:1; /* LinFlex1 status */ 4210 uint32_t S_LIN_FLEX0:1; /* LinFlex0 status */ 4211 uint32_t:5; 4212 uint32_t S_FLEXPWM1:1; /* FlexPWM1 status */ 4213 uint32_t S_FLEXPWM0:1; /* FlexPWM0 status */ 4214 uint32_t S_ETIMER2:1; /* eTimer2 status */ 4215 uint32_t S_ETIMER1:1; /* eTimer1 status */ 4216 uint32_t S_ETIMER0:1; /* eTimer0 status */ 4217 uint32_t:2; 4218 uint32_t S_CTU:1; /* CTU status */ 4219 uint32_t:1; 4220 uint32_t S_ADC1:1; /* ADC1 status */ 4221 uint32_t S_ADC0:1; /* ADC0 status */ 4222 } B; 4223 } ME_PS1_32B_tag; 4224 4225 typedef union { /* ME_PS2 - Peripheral Status Register 2 */ 4226 uint32_t R; 4227 struct { 4228 uint32_t:3; 4229 uint32_t S_PIT:1; /* PIT status */ 4230 uint32_t:28; 4231 } B; 4232 } ME_PS2_32B_tag; 4233 4234 4235 /* Register layout for all registers RUN_PC... */ 4236 4237 typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ 4238 uint32_t R; 4239 struct { 4240 uint32_t:24; 4241 uint32_t RUN3:1; /* Peripheral control during RUN3 */ 4242 uint32_t RUN2:1; /* Peripheral control during RUN2 */ 4243 uint32_t RUN1:1; /* Peripheral control during RUN1 */ 4244 uint32_t RUN0:1; /* Peripheral control during RUN0 */ 4245 uint32_t DRUN:1; /* Peripheral control during DRUN */ 4246 uint32_t SAFE:1; /* Peripheral control during SAFE */ 4247 uint32_t TEST:1; /* Peripheral control during TEST */ 4248 uint32_t RESET:1; /* Peripheral control during RESET */ 4249 } B; 4250 } ME_RUN_PC_32B_tag; 4251 4252 4253 /* Register layout for all registers LP_PC... */ 4254 4255 typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ 4256 uint32_t R; 4257 struct { 4258 uint32_t:21; 4259 uint32_t STOP0:1; /* Peripheral control during STOP0 */ 4260 uint32_t:1; 4261 uint32_t HALT0:1; /* Peripheral control during HALT0 */ 4262 uint32_t:8; 4263 } B; 4264 } ME_LP_PC_32B_tag; 4265 4266 4267 /* Register layout for all registers PCTL... */ 4268 4269 typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */ 4270 uint8_t R; 4271 struct { 4272 uint8_t:1; 4273 uint8_t DBG_F:1; /* Peripheral control in debug mode */ 4274 uint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */ 4275 uint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */ 4276 } B; 4277 } ME_PCTL_8B_tag; 4278 4279 4280 4281 4282 /* Register layout for generated register(s) PS... */ 4283 4284 typedef union { /* */ 4285 uint32_t R; 4286 } ME_PS_32B_tag; 4287 4288 4289 4290 4291 4292 4293 typedef struct ME_struct_tag { /* start of ME_tag */ 4294 /* ME_GS - Global Status Register */ 4295 ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */ 4296 /* ME_MCTL - Mode Control Register */ 4297 ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */ 4298 union { 4299 ME_MEN_32B_tag MER; /* deprecated - please avoid */ 4300 4301 /* ME_MEN - Mode Enable Register */ 4302 ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */ 4303 4304 }; 4305 /* ME_IS - Interrupt Status Register */ 4306 ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */ 4307 /* ME_IM - Interrupt Mask Register */ 4308 ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */ 4309 /* ME_IMTS - Invalid Mode Transition Status Register */ 4310 ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */ 4311 /* ME_DMTS - Debug Mode Transition Status Register */ 4312 ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */ 4313 int8_t ME_reserved_001C_C[4]; 4314 union { 4315 /* ME_RESET_MC - RESET Mode Configuration Register */ 4316 ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */ 4317 4318 ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */ 4319 4320 }; 4321 int8_t ME_reserved_0024_C[4]; 4322 union { 4323 /* ME_SAFE_MC - Mode Configuration Register */ 4324 ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */ 4325 4326 ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */ 4327 4328 }; 4329 union { 4330 /* ME_DRUN_MC - DRUN Mode Configuration Register */ 4331 ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */ 4332 4333 ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */ 4334 4335 }; 4336 union { 4337 /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ 4338 ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */ 4339 4340 ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */ 4341 4342 struct { 4343 /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ 4344 ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */ 4345 ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */ 4346 ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */ 4347 ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */ 4348 }; 4349 4350 }; 4351 union { 4352 /* ME_HALT0_MC - HALT0 Mode Configuration Register */ 4353 ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */ 4354 4355 ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */ 4356 4357 }; 4358 int8_t ME_reserved_0044_C[4]; 4359 union { 4360 /* ME_STOP0_MC - STOP0 Mode Configration Register */ 4361 ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */ 4362 4363 ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */ 4364 4365 }; 4366 int8_t ME_reserved_004C_C[8]; 4367 union { 4368 /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ 4369 ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */ 4370 4371 ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */ 4372 4373 }; 4374 int8_t ME_reserved_0058_C[8]; 4375 union { 4376 ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */ 4377 4378 struct { 4379 /* ME_PS0 - Peripheral Status Register 0 */ 4380 ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */ 4381 /* ME_PS1 - Peripheral Status Register 1 */ 4382 ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */ 4383 /* ME_PS2 - Peripheral Status Register 2 */ 4384 ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */ 4385 }; 4386 4387 }; 4388 int8_t ME_reserved_006C_C[20]; 4389 union { 4390 ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */ 4391 4392 /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ 4393 ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */ 4394 4395 struct { 4396 /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ 4397 ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */ 4398 ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */ 4399 ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */ 4400 ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */ 4401 ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */ 4402 ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */ 4403 ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */ 4404 ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */ 4405 }; 4406 4407 }; 4408 union { 4409 ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */ 4410 4411 /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ 4412 ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */ 4413 4414 struct { 4415 /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ 4416 ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */ 4417 ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */ 4418 ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */ 4419 ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */ 4420 ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */ 4421 ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */ 4422 ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */ 4423 ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */ 4424 }; 4425 4426 }; 4427 union { 4428 /* ME_PCTL[0...143] - Peripheral Control Registers */ 4429 ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */ 4430 4431 struct { 4432 /* ME_PCTL[0...143] - Peripheral Control Registers */ 4433 ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */ 4434 ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */ 4435 ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */ 4436 ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */ 4437 ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */ 4438 ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */ 4439 ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */ 4440 ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */ 4441 ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */ 4442 ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */ 4443 ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */ 4444 ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */ 4445 ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */ 4446 ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */ 4447 ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */ 4448 ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */ 4449 ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */ 4450 ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */ 4451 ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */ 4452 ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */ 4453 ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */ 4454 ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */ 4455 ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */ 4456 ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */ 4457 ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */ 4458 ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */ 4459 ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */ 4460 ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */ 4461 ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */ 4462 ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */ 4463 ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */ 4464 ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */ 4465 ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */ 4466 ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */ 4467 ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */ 4468 ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */ 4469 ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */ 4470 ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */ 4471 ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */ 4472 ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */ 4473 ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */ 4474 ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */ 4475 ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */ 4476 ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */ 4477 ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */ 4478 ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */ 4479 ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */ 4480 ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */ 4481 ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */ 4482 ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */ 4483 ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */ 4484 ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */ 4485 ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */ 4486 ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */ 4487 ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */ 4488 ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */ 4489 ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */ 4490 ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */ 4491 ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */ 4492 ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */ 4493 ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */ 4494 ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */ 4495 ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */ 4496 ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */ 4497 ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */ 4498 ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */ 4499 ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */ 4500 ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */ 4501 ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */ 4502 ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */ 4503 ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */ 4504 ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */ 4505 ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */ 4506 ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */ 4507 ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */ 4508 ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */ 4509 ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */ 4510 ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */ 4511 ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */ 4512 ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */ 4513 ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */ 4514 ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */ 4515 ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */ 4516 ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */ 4517 ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */ 4518 ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */ 4519 ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */ 4520 ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */ 4521 ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */ 4522 ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */ 4523 ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */ 4524 ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */ 4525 ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */ 4526 ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */ 4527 ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */ 4528 ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */ 4529 ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */ 4530 ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */ 4531 ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */ 4532 ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */ 4533 ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */ 4534 ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */ 4535 ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */ 4536 ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */ 4537 ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */ 4538 ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */ 4539 ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */ 4540 ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */ 4541 ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */ 4542 ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */ 4543 ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */ 4544 ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */ 4545 ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */ 4546 ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */ 4547 ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */ 4548 ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */ 4549 ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */ 4550 ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */ 4551 ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */ 4552 ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */ 4553 ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */ 4554 ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */ 4555 ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */ 4556 ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */ 4557 ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */ 4558 ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */ 4559 ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */ 4560 ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */ 4561 ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */ 4562 ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */ 4563 ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */ 4564 ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */ 4565 ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */ 4566 ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */ 4567 ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */ 4568 ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */ 4569 ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */ 4570 ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */ 4571 ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */ 4572 ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */ 4573 ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */ 4574 ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */ 4575 ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */ 4576 ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */ 4577 }; 4578 4579 }; 4580 } ME_tag; 4581 4582 4583 #define ME (*(volatile ME_tag *) 0xC3FDC000UL) 4584 4585 4586 4587 /****************************************************************/ 4588 /* */ 4589 /* Module: OSC */ 4590 /* */ 4591 /****************************************************************/ 4592 4593 typedef union { /* OSC_CTL - Control Register */ 4594 uint32_t R; 4595 struct { 4596 uint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */ 4597 uint32_t:7; 4598 uint32_t EOCV:8; /* End of Count Value */ 4599 uint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */ 4600 uint32_t:2; 4601 uint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */ 4602 uint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */ 4603 uint32_t:5; 4604 uint32_t S_OSC:1; 4605 uint32_t OSCON:1; } B; 4606 } OSC_CTL_32B_tag; 4607 4608 4609 4610 typedef struct OSC_struct_tag { /* start of OSC_tag */ 4611 /* OSC_CTL - Control Register */ 4612 OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ 4613 } OSC_tag; 4614 4615 4616 #define OSC (*(volatile OSC_tag *) 0xC3FE0000UL) 4617 4618 4619 4620 /****************************************************************/ 4621 /* */ 4622 /* Module: RC */ 4623 /* */ 4624 /****************************************************************/ 4625 4626 typedef union { /* RC_CTL - Control Register */ 4627 uint32_t R; 4628 struct { 4629 uint32_t:10; 4630 uint32_t RCTRIM:6; /* Main RC Trimming Bits */ 4631 uint32_t:3; 4632 uint32_t RCDIV:5; /* Main RC Clock Division Factor */ 4633 uint32_t:2; 4634 uint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */ 4635 uint32_t:5; 4636 } B; 4637 } RC_CTL_32B_tag; 4638 4639 4640 4641 typedef struct RC_struct_tag { /* start of RC_tag */ 4642 /* RC_CTL - Control Register */ 4643 RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ 4644 } RC_tag; 4645 4646 4647 #define RC (*(volatile RC_tag *) 0xC3FE0060UL) 4648 4649 4650 4651 /****************************************************************/ 4652 /* */ 4653 /* Module: PLLD */ 4654 /* */ 4655 /****************************************************************/ 4656 4657 typedef union { /* PLLD_CR - Control Register */ 4658 uint32_t R; 4659 struct { 4660 uint32_t:2; 4661 uint32_t IDF:4; /* PLL Input Division Factor */ 4662 uint32_t ODF:2; /* PLL Output Division Factor */ 4663 uint32_t:1; 4664 uint32_t NDIV:7; /* PLL Loop Division Factor */ 4665 uint32_t:7; 4666 uint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */ 4667 uint32_t MODE:1; /* Activate 1:1 Mode */ 4668 uint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */ 4669 uint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */ 4670 uint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */ 4671 uint32_t S_LOCK:1; /* PLL has Aquired Lock */ 4672 uint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */ 4673 uint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */ 4674 uint32_t PLL_ON:1; /* PLL ON Bit */ 4675 } B; 4676 } PLLD_CR_32B_tag; 4677 4678 typedef union { /* PLLD_MR - PLLD Modulation Register */ 4679 uint32_t R; 4680 struct { 4681 uint32_t STRB_BYPASS:1; /* Strobe Bypass */ 4682 uint32_t:1; 4683 uint32_t SPRD_SEL:1; /* Spread Type Selection */ 4684 uint32_t MOD_PERIOD:13; /* Modulation Period */ 4685 #ifndef USE_FIELD_ALIASES_PLLD 4686 uint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */ 4687 #else 4688 uint32_t FM_EN:1; /* deprecated name - please avoid */ 4689 #endif 4690 uint32_t INC_STEP:15; /* Increment Step */ 4691 } B; 4692 } PLLD_MR_32B_tag; 4693 4694 4695 4696 typedef struct PLLD_struct_tag { /* start of PLLD_tag */ 4697 /* PLLD_CR - Control Register */ 4698 PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ 4699 /* PLLD_MR - PLLD Modulation Register */ 4700 PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */ 4701 4702 uint32_t plld_reserved[6]; 4703 } PLLD_tag; 4704 4705 4706 #define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL) 4707 #define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL) 4708 4709 4710 4711 /****************************************************************/ 4712 /* */ 4713 /* Module: CMU */ 4714 /* */ 4715 /****************************************************************/ 4716 4717 typedef union { /* CMU_CSR - Control Status Register */ 4718 uint32_t R; 4719 struct { 4720 uint32_t:8; 4721 uint32_t SFM:1; /* Start Frequency Measure */ 4722 uint32_t:13; 4723 #ifndef USE_FIELD_ALIASES_RGM 4724 uint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */ 4725 #else 4726 uint32_t CLKSEL1:2; /* deprecated name - please avoid */ 4727 #endif 4728 uint32_t:5; 4729 uint32_t RCDIV:2; /* RCfast Clock Division Factor */ 4730 uint32_t CME_A:1; /* PLL_A Clock Monitor Enable */ 4731 } B; 4732 } CMU_CSR_32B_tag; 4733 4734 typedef union { /* CMU_FDR - Frequency Display Register */ 4735 uint32_t R; 4736 struct { 4737 uint32_t:12; 4738 uint32_t FD:20; /* Measured Frequency Bits */ 4739 } B; 4740 } CMU_FDR_32B_tag; 4741 4742 typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */ 4743 uint32_t R; 4744 struct { 4745 uint32_t:20; 4746 uint32_t HFREF_A:12; /* High Frequency Reference Value */ 4747 } B; 4748 } CMU_HFREFR_A_32B_tag; 4749 4750 typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */ 4751 uint32_t R; 4752 struct { 4753 uint32_t:20; 4754 uint32_t LFREF_A:12; /* Low Frequency Reference Value */ 4755 } B; 4756 } CMU_LFREFR_A_32B_tag; 4757 4758 typedef union { /* CMU_ISR - Interrupt Status Register */ 4759 uint32_t R; 4760 struct { 4761 uint32_t:28; 4762 uint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */ 4763 #ifndef USE_FIELD_ALIASES_RGM 4764 uint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */ 4765 #else 4766 uint32_t FHHI_A:1; /* deprecated name - please avoid */ 4767 #endif 4768 uint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */ 4769 uint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */ 4770 } B; 4771 } CMU_ISR_32B_tag; 4772 4773 typedef union { /* CMU_IMR - Interrupt Mask Register */ 4774 uint32_t R; 4775 } CMU_IMR_32B_tag; 4776 4777 typedef union { /* CMU_MDR - Measurement Duration Register */ 4778 uint32_t R; 4779 struct { 4780 uint32_t:12; 4781 uint32_t MD:20; /* Measurment Duration Bits */ 4782 } B; 4783 } CMU_MDR_32B_tag; 4784 4785 4786 4787 typedef struct CMU_struct_tag { /* start of CMU_tag */ 4788 /* CMU_CSR - Control Status Register */ 4789 CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */ 4790 /* CMU_FDR - Frequency Display Register */ 4791 CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */ 4792 /* CMU_HFREFR_A - High Frequency Reference Register */ 4793 CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */ 4794 /* CMU_LFREFR_A - Low Frequency Reference Register */ 4795 CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */ 4796 /* CMU_ISR - Interrupt Status Register */ 4797 CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ 4798 /* CMU_IMR - Interrupt Mask Register */ 4799 CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */ 4800 /* CMU_MDR - Measurement Duration Register */ 4801 CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */ 4802 } CMU_tag; 4803 4804 4805 #define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL) 4806 #define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL) 4807 #define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL) 4808 4809 4810 4811 /****************************************************************/ 4812 /* */ 4813 /* Module: CGM */ 4814 /* */ 4815 /****************************************************************/ 4816 4817 typedef union { /* Output Clock Enable Register */ 4818 uint32_t R; 4819 uint8_t BYTE[4]; /* individual bytes can be accessed */ 4820 uint16_t HALF[2]; /* individual halfwords can be accessed */ 4821 uint32_t WORD; /* individual words can be accessed */ 4822 struct { 4823 uint32_t:31; 4824 uint32_t EN:1; /* Clock Enable Bit */ 4825 } B; 4826 } CGM_OC_EN_32B_tag; 4827 4828 typedef union { /* Output Clock Division Select Register */ 4829 uint32_t R; 4830 uint8_t BYTE[4]; /* individual bytes can be accessed */ 4831 uint16_t HALF[2]; /* individual halfwords can be accessed */ 4832 uint32_t WORD; /* individual words can be accessed */ 4833 struct { 4834 uint32_t:2; 4835 uint32_t SELDIV:2; /* Output Clock Division Select */ 4836 uint32_t SELCTL:4; /* Output Clock Source Selection Control */ 4837 uint32_t:24; 4838 } B; 4839 } CGM_OCDS_SC_32B_tag; 4840 4841 typedef union { /* System Clock Select Status Register */ 4842 uint32_t R; 4843 uint8_t BYTE[4]; /* individual bytes can be accessed */ 4844 uint16_t HALF[2]; /* individual halfwords can be accessed */ 4845 uint32_t WORD; /* individual words can be accessed */ 4846 struct { 4847 uint32_t:4; 4848 uint32_t SELSTAT:4; /* System Clock Source Selection Status */ 4849 uint32_t:24; 4850 } B; 4851 } CGM_SC_SS_32B_tag; 4852 4853 typedef union { /* System Clock Divider Configuration Register */ 4854 uint32_t R; 4855 uint8_t BYTE[4]; /* individual bytes can be accessed */ 4856 uint16_t HALF[2]; /* individual halfwords can be accessed */ 4857 uint32_t WORD; /* individual words can be accessed */ 4858 struct { 4859 uint32_t DE0:1; /* Divider 0 Enable */ 4860 uint32_t:3; 4861 uint32_t DIV0:4; /* Divider 0 Value */ 4862 uint32_t:24; 4863 } B; 4864 } CGM_SC_DC0_3_32B_tag; 4865 4866 4867 /* Register layout for all registers SC_DC... */ 4868 4869 typedef union { /* System Clock Divider Configuration Register */ 4870 uint8_t R; 4871 struct { 4872 uint8_t DE:1; /* Divider Enable */ 4873 uint8_t:3; 4874 uint8_t DIV:4; /* Divider Division Value */ 4875 } B; 4876 } CGM_SC_DC_8B_tag; 4877 4878 4879 /* Register layout for all registers AC_SC... */ 4880 4881 typedef union { /* Auxiliary Clock Select Control Registers */ 4882 uint32_t R; 4883 uint8_t BYTE[4]; /* individual bytes can be accessed */ 4884 uint16_t HALF[2]; /* individual halfwords can be accessed */ 4885 uint32_t WORD; /* individual words can be accessed */ 4886 struct { 4887 uint32_t:4; 4888 uint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */ 4889 uint32_t:24; 4890 } B; 4891 } CGM_AC_SC_32B_tag; 4892 4893 4894 /* Register layout for all registers AC_DC0_3... */ 4895 4896 typedef union { /* Auxiliary Clock Divider Configuration Registers */ 4897 uint32_t R; 4898 struct { 4899 uint32_t DE0:1; /* Divider 0 Enable */ 4900 uint32_t:3; 4901 uint32_t DIV0:4; /* Divider 0 Value */ 4902 uint32_t DE1:1; /* Divider 1 Enable */ 4903 uint32_t:3; 4904 uint32_t DIV1:4; /* Divider 1 Value */ 4905 uint32_t:16; 4906 } B; 4907 } CGM_AC_DC0_3_32B_tag; 4908 4909 4910 typedef struct CGM_AUXCLK_struct_tag { 4911 4912 /* Auxiliary Clock Select Control Registers */ 4913 CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */ 4914 /* Auxiliary Clock Divider Configuration Registers */ 4915 CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */ 4916 4917 } CGM_AUXCLK_tag; 4918 4919 4920 typedef struct CGM_struct_tag { /* start of CGM_tag */ 4921 OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */ 4922 int8_t CGM_reserved_0004[92]; 4923 RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */ 4924 int8_t CGM_reserved_0064[60]; 4925 PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */ 4926 int8_t CGM_reserved_00E0[32]; 4927 CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */ 4928 CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */ 4929 CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */ 4930 CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */ 4931 CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */ 4932 CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */ 4933 CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */ 4934 int8_t CGM_reserved_011C[4]; 4935 CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */ 4936 int8_t CGM_reserved_0124[4]; 4937 CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */ 4938 CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */ 4939 CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */ 4940 int8_t CGM_reserved_0134[572]; 4941 union { 4942 /* Output Clock Enable Register */ 4943 CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */ 4944 4945 CGM_OC_EN_32B_tag OCEN; /* deprecated - please avoid */ 4946 4947 }; 4948 union { 4949 /* Output Clock Division Select Register */ 4950 CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */ 4951 4952 CGM_OCDS_SC_32B_tag OCDSSC; /* deprecated - please avoid */ 4953 4954 }; 4955 union { 4956 /* Output Clock Division Select Register */ 4957 CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */ 4958 4959 CGM_SC_SS_32B_tag SCSS; /* deprecated - please avoid */ 4960 4961 }; /* System Clock Select Status Register */ 4962 union { 4963 struct { 4964 /* System Clock Divider Configuration Register */ 4965 CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */ 4966 int8_t CGM_reserved_037E_E0[2]; 4967 }; 4968 4969 struct { 4970 /* System Clock Divider Configuration Register */ 4971 CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */ 4972 CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */ 4973 int8_t CGM_reserved_037E_E1[2]; 4974 }; 4975 4976 /* System Clock Divider Configuration Register */ 4977 union { 4978 CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */ 4979 CGM_SC_DC0_3_32B_tag SCDC; /* deprecated - please avoid */ 4980 }; 4981 }; 4982 union { 4983 /* Register set AUXCLK */ 4984 CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */ 4985 4986 struct { 4987 union { 4988 /* Auxiliary Clock Select Control Registers */ 4989 CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */ 4990 4991 CGM_AC_SC_32B_tag AC0SC; /* deprecated - please avoid */ 4992 4993 }; 4994 union { 4995 /* Auxiliary Clock Divider Configuration Registers */ 4996 CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */ 4997 4998 CGM_AC_DC0_3_32B_tag AC0DC; /* deprecated - please avoid */ 4999 5000 }; 5001 union { 5002 /* Auxiliary Clock Select Control Registers */ 5003 CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */ 5004 5005 CGM_AC_SC_32B_tag AC1SC; /* deprecated - please avoid */ 5006 5007 }; 5008 union { 5009 /* Auxiliary Clock Divider Configuration Registers */ 5010 CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */ 5011 5012 CGM_AC_DC0_3_32B_tag AC1DC; /* deprecated - please avoid */ 5013 5014 }; 5015 union { 5016 /* Auxiliary Clock Select Control Registers */ 5017 CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */ 5018 5019 CGM_AC_SC_32B_tag AC2SC; /* deprecated - please avoid */ 5020 5021 }; 5022 union { 5023 /* Auxiliary Clock Divider Configuration Registers */ 5024 CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */ 5025 5026 CGM_AC_DC0_3_32B_tag AC2DC; /* deprecated - please avoid */ 5027 5028 }; 5029 union { 5030 /* Auxiliary Clock Select Control Registers */ 5031 CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */ 5032 5033 CGM_AC_SC_32B_tag AC3SC; /* deprecated - please avoid */ 5034 5035 }; 5036 union { 5037 /* Auxiliary Clock Divider Configuration Registers */ 5038 CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */ 5039 5040 CGM_AC_DC0_3_32B_tag AC3DC; /* deprecated - please avoid */ 5041 5042 }; 5043 union { 5044 /* Auxiliary Clock Select Control Registers */ 5045 CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */ 5046 5047 CGM_AC_SC_32B_tag AC4SC; /* deprecated - please avoid */ 5048 5049 }; 5050 union { 5051 /* Auxiliary Clock Divider Configuration Registers */ 5052 CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */ 5053 5054 CGM_AC_DC0_3_32B_tag AC4DC; /* deprecated - please avoid */ 5055 }; 5056 union { 5057 /* Auxiliary Clock Select Control Registers */ 5058 CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */ 5059 5060 CGM_AC_SC_32B_tag AC5SC; /* deprecated - please avoid */ 5061 5062 }; 5063 union { 5064 /* Auxiliary Clock Divider Configuration Registers */ 5065 CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */ 5066 5067 CGM_AC_DC0_3_32B_tag AC5DC; /* deprecated - please avoid */ 5068 5069 }; 5070 }; 5071 5072 }; 5073 } CGM_tag; 5074 5075 5076 #define CGM (*(volatile CGM_tag *) 0xC3FE0000UL) 5077 5078 5079 5080 /****************************************************************/ 5081 /* */ 5082 /* Module: RGM */ 5083 /* */ 5084 /****************************************************************/ 5085 5086 typedef union { /* Functional Event Status Register */ 5087 uint16_t R; 5088 struct { 5089 uint16_t F_EXR:1; /* Flag for External Reset */ 5090 uint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */ 5091 uint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */ 5092 uint16_t F_ST_DONE:1; /* Flag for self-test completed */ 5093 #ifndef USE_FIELD_ALIASES_RGM 5094 uint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */ 5095 #else 5096 uint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */ 5097 #endif 5098 uint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */ 5099 uint16_t F_PLL1:1; /* Flag for PLL1 fail */ 5100 uint16_t F_SWT:1; /* Flag for Software Watchdog Timer */ 5101 uint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */ 5102 uint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */ 5103 uint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */ 5104 uint16_t F_PLL0:1; /* Flag for PLL0 fail */ 5105 uint16_t F_CWD:1; /* Flag for Core Watchdog Reset */ 5106 uint16_t F_SOFT:1; /* Flag for software reset */ 5107 uint16_t F_CORE:1; /* Flag for core reset */ 5108 uint16_t F_JTAG:1; /* Flag for JTAG initiated reset */ 5109 } B; 5110 } RGM_FES_16B_tag; 5111 5112 typedef union { /* Destructive Event Status Register */ 5113 uint16_t R; 5114 struct { 5115 #ifndef USE_FIELD_ALIASES_RGM 5116 uint16_t F_POR:1; /* Flag for Power on Reset */ 5117 #else 5118 uint16_t POR:1; /* deprecated name - please avoid */ 5119 #endif 5120 uint16_t:7; 5121 uint16_t F_COMP:1; /* Flag for comparator error */ 5122 uint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */ 5123 uint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */ 5124 uint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */ 5125 uint16_t:2; 5126 uint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */ 5127 #ifndef USE_FIELD_ALIASES_RGM 5128 uint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */ 5129 #else 5130 uint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */ 5131 #endif 5132 } B; 5133 } RGM_DES_16B_tag; 5134 5135 typedef union { /* Functional Event Reset Disable Register */ 5136 uint16_t R; 5137 struct { 5138 uint16_t D_EXR:1; /* Disable External Pad Event Reset */ 5139 uint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */ 5140 uint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */ 5141 uint16_t D_ST_DONE:1; /* Disable self-test completed */ 5142 #ifndef USE_FIELD_ALIASES_RGM 5143 uint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */ 5144 #else 5145 uint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */ 5146 #endif 5147 uint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */ 5148 uint16_t D_PLL1:1; /* Disable PLL1 fail */ 5149 uint16_t D_SWT:1; /* Disable Software Watchdog Timer */ 5150 uint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */ 5151 uint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */ 5152 uint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */ 5153 uint16_t D_PLL0:1; /* Disable PLL0 fail */ 5154 uint16_t D_CWD:1; /* Disable Core Watchdog Reset */ 5155 uint16_t D_SOFT:1; /* Disable software reset */ 5156 uint16_t D_CORE:1; /* Disable core reset */ 5157 uint16_t D_JTAG:1; /* Disable JTAG initiated reset */ 5158 } B; 5159 } RGM_FERD_16B_tag; 5160 5161 typedef union { /* Destructive Event Reset Disable Register */ 5162 uint16_t R; 5163 struct { 5164 uint16_t:8; 5165 uint16_t D_COMP:1; /* Disable comparator error */ 5166 uint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */ 5167 uint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */ 5168 uint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */ 5169 uint16_t:2; 5170 uint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */ 5171 #ifndef USE_FIELD_ALIASES_RGM 5172 uint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */ 5173 #else 5174 uint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */ 5175 #endif 5176 } B; 5177 } RGM_DERD_16B_tag; 5178 5179 typedef union { /* Functional Event Alternate Request Register */ 5180 uint16_t R; 5181 struct { 5182 uint16_t:4; 5183 #ifndef USE_FIELD_ALIASES_RGM 5184 uint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */ 5185 #else 5186 uint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */ 5187 #endif 5188 uint16_t:1; 5189 uint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */ 5190 uint16_t:1; 5191 uint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */ 5192 uint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq. 5193 too high/low */ 5194 uint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */ 5195 uint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */ 5196 uint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */ 5197 uint16_t:3; 5198 } B; 5199 } RGM_FEAR_16B_tag; 5200 5201 typedef union { /* Functional Event Short Sequence Register */ 5202 uint16_t R; 5203 struct { 5204 uint16_t SS_EXR:1; /* Short Sequence for External Reset */ 5205 uint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */ 5206 uint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */ 5207 uint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */ 5208 #ifndef USE_FIELD_ALIASES_RGM 5209 uint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */ 5210 #else 5211 uint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */ 5212 #endif 5213 uint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */ 5214 uint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */ 5215 uint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */ 5216 uint16_t:1; 5217 uint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */ 5218 uint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */ 5219 uint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */ 5220 uint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */ 5221 uint16_t SS_SOFT:1; /* Short Sequence for software reset */ 5222 uint16_t SS_CORE:1; /* Short Sequence for core reset */ 5223 uint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */ 5224 } B; 5225 } RGM_FESS_16B_tag; 5226 5227 typedef union { /* Functional Bidirectional Reset Enable Register */ 5228 uint16_t R; 5229 struct { 5230 uint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */ 5231 uint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */ 5232 uint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */ 5233 uint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */ 5234 #ifndef USE_FIELD_ALIASES_RGM 5235 uint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */ 5236 #else 5237 uint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */ 5238 #endif 5239 uint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */ 5240 uint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */ 5241 uint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */ 5242 uint16_t:1; 5243 uint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */ 5244 uint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */ 5245 uint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */ 5246 uint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */ 5247 uint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */ 5248 uint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */ 5249 uint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */ 5250 } B; 5251 } RGM_FBRE_16B_tag; 5252 5253 5254 5255 typedef struct RGM_struct_tag { /* start of RGM_tag */ 5256 /* Functional Event Status Register */ 5257 RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */ 5258 /* Destructive Event Status Register */ 5259 RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */ 5260 /* Functional Event Reset Disable Register */ 5261 RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */ 5262 /* Destructive Event Reset Disable Register */ 5263 RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */ 5264 int8_t RGM_reserved_0008[8]; 5265 /* Functional Event Alternate Request Register */ 5266 RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */ 5267 int8_t RGM_reserved_0012[6]; 5268 /* Functional Event Short Sequence Register */ 5269 RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */ 5270 int8_t RGM_reserved_001A[2]; 5271 /* Functional Bidirectional Reset Enable Register */ 5272 RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */ 5273 } RGM_tag; 5274 5275 5276 #define RGM (*(volatile RGM_tag *) 0xC3FE4000UL) 5277 5278 5279 5280 /****************************************************************/ 5281 /* */ 5282 /* Module: PCU */ 5283 /* */ 5284 /****************************************************************/ 5285 5286 5287 /* Register layout for all registers PCONF... */ 5288 5289 typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ 5290 uint32_t R; 5291 struct { 5292 uint32_t:18; 5293 uint32_t STBY0:1; /* Power domain control during STBY0 */ 5294 uint32_t:2; 5295 uint32_t STOP0:1; /* Power domain control during STOP0 */ 5296 uint32_t:1; 5297 uint32_t HALT0:1; /* Power domain control during HALT0 */ 5298 uint32_t RUN3:1; /* Power domain control during RUN3 */ 5299 uint32_t RUN2:1; /* Power domain control during RUN2 */ 5300 uint32_t RUN1:1; /* Power domain control during RUN1 */ 5301 uint32_t RUN0:1; /* Power domain control during RUN0 */ 5302 uint32_t DRUN:1; /* Power domain control during DRUN */ 5303 uint32_t SAFE:1; /* Power domain control during SAFE */ 5304 uint32_t TEST:1; /* Power domain control during TEST */ 5305 uint32_t RST:1; /* Power domain control during RST */ 5306 } B; 5307 } PCU_PCONF_32B_tag; 5308 5309 typedef union { /* PCU_PSTAT - Power Domain Status Register */ 5310 uint32_t R; 5311 struct { 5312 uint32_t:16; 5313 uint32_t PD15:1; /* Power Status for Power Domain 15 */ 5314 uint32_t PD14:1; /* Power Status for Power Domain 14 */ 5315 uint32_t PD13:1; /* Power Status for Power Domain 13 */ 5316 uint32_t PD12:1; /* Power Status for Power Domain 12 */ 5317 uint32_t PD11:1; /* Power Status for Power Domain 11 */ 5318 uint32_t PD10:1; /* Power Status for Power Domain 10 */ 5319 uint32_t PD9:1; /* Power Status for Power Domain 9 */ 5320 uint32_t PD8:1; /* Power Status for Power Domain 8 */ 5321 uint32_t PD7:1; /* Power Status for Power Domain 7 */ 5322 uint32_t PD6:1; /* Power Status for Power Domain 6 */ 5323 uint32_t PD5:1; /* Power Status for Power Domain 5 */ 5324 uint32_t PD4:1; /* Power Status for Power Domain 4 */ 5325 uint32_t PD3:1; /* Power Status for Power Domain 3 */ 5326 uint32_t PD2:1; /* Power Status for Power Domain 2 */ 5327 uint32_t PD1:1; /* Power Status for Power Domain 1 */ 5328 uint32_t PD0:1; /* Power Status for Power Domain 0 */ 5329 } B; 5330 } PCU_PSTAT_32B_tag; 5331 5332 5333 5334 typedef struct PCU_struct_tag { /* start of PCU_tag */ 5335 union { 5336 /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ 5337 PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */ 5338 5339 struct { 5340 /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ 5341 PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */ 5342 PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */ 5343 PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */ 5344 PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */ 5345 PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */ 5346 PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */ 5347 PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */ 5348 PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */ 5349 PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */ 5350 PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */ 5351 PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */ 5352 PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */ 5353 PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */ 5354 PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */ 5355 PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */ 5356 PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */ 5357 }; 5358 5359 }; 5360 /* PCU_PSTAT - Power Domain Status Register */ 5361 PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */ 5362 } PCU_tag; 5363 5364 5365 #define PCU (*(volatile PCU_tag *) 0xC3FE8000UL) 5366 5367 5368 5369 /****************************************************************/ 5370 /* */ 5371 /* Module: PMUCTRL */ 5372 /* */ 5373 /****************************************************************/ 5374 5375 typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */ 5376 uint32_t R; 5377 struct { 5378 uint32_t:11; 5379 uint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */ 5380 uint32_t:6; 5381 uint32_t HVD_M:1; /* High Voltage Detector Main */ 5382 uint32_t HVD_B:1; /* High Voltage Detector Backup */ 5383 uint32_t:4; 5384 uint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */ 5385 } B; 5386 } PMUCTRL_STATHVD_32B_tag; 5387 5388 typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */ 5389 uint32_t R; 5390 struct { 5391 uint32_t:11; 5392 uint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */ 5393 uint32_t:6; 5394 uint32_t LVD_M:1; /* Ligh Voltage Detector Main */ 5395 uint32_t LVD_B:1; /* Ligh Voltage Detector Backup */ 5396 uint32_t:4; 5397 uint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */ 5398 } B; 5399 } PMUCTRL_STATLVD_32B_tag; 5400 5401 typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */ 5402 uint32_t R; 5403 struct { 5404 uint32_t:28; 5405 uint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ 5406 } B; 5407 } PMUCTRL_STATIREG_32B_tag; 5408 5409 typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */ 5410 uint32_t R; 5411 struct { 5412 uint32_t:28; 5413 uint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ 5414 } B; 5415 } PMUCTRL_STATEREG_32B_tag; 5416 5417 typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */ 5418 uint32_t R; 5419 struct { 5420 uint32_t EBMM:1; /* External Ballast Management Mode */ 5421 uint32_t AEBD:1; /* Automatic External Ballast Detection */ 5422 uint32_t ENPN:1; /* External NPN status flag */ 5423 uint32_t:13; 5424 uint32_t CTB:2; /* Configuration Trace Bits */ 5425 uint32_t:6; 5426 uint32_t CBS:4; /* Current BIST Status */ 5427 uint32_t CPCS:4; /* Current Pmu Configuration Status */ 5428 } B; 5429 } PMUCTRL_STATUS_32B_tag; 5430 5431 typedef union { /* PMUCTRL_CTRL - PMU Control Register */ 5432 uint32_t R; 5433 struct { 5434 uint32_t:30; 5435 uint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */ 5436 } B; 5437 } PMUCTRL_CTRL_32B_tag; 5438 5439 typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */ 5440 uint32_t R; 5441 struct { 5442 uint32_t MF_BB:4; /* Mask Fault Bypass Balast */ 5443 uint32_t:28; 5444 } B; 5445 } PMUCTRL_MASKF_32B_tag; 5446 5447 typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */ 5448 uint32_t R; 5449 struct { 5450 uint32_t BB_LV:4; /* Bypass Ballast Low Voltage */ 5451 uint32_t:9; 5452 uint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */ 5453 uint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */ 5454 uint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */ 5455 uint32_t:13; 5456 uint32_t LHCF:1; /* Low High voltage detector Critical Fault */ 5457 uint32_t LNCF:1; /* Low voltage detector Non Critical Fault */ 5458 uint32_t HNCF:1; /* High voltage detector Non Critical Fault */ 5459 } B; 5460 } PMUCTRL_FAULT_32B_tag; 5461 5462 typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ 5463 uint32_t R; 5464 struct { 5465 uint32_t:10; 5466 uint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */ 5467 uint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */ 5468 uint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */ 5469 uint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */ 5470 uint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */ 5471 uint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */ 5472 uint32_t:12; 5473 uint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */ 5474 uint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */ 5475 uint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */ 5476 uint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */ 5477 } B; 5478 } PMUCTRL_IRQS_32B_tag; 5479 5480 typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ 5481 uint32_t R; 5482 struct { 5483 uint32_t:10; 5484 uint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */ 5485 uint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */ 5486 uint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */ 5487 uint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */ 5488 uint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */ 5489 uint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */ 5490 uint32_t:12; 5491 uint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */ 5492 uint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */ 5493 uint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */ 5494 uint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */ 5495 } B; 5496 } PMUCTRL_IRQE_32B_tag; 5497 5498 5499 5500 typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */ 5501 int8_t PMUCTRL_reserved_0000[4]; 5502 /* PMUCTRL_STATHVD - PMU Status Register HVD */ 5503 PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */ 5504 /* PMUCTRL_STATLVD - PMU Status Register LVD */ 5505 PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */ 5506 int8_t PMUCTRL_reserved_000C[20]; 5507 /* PMUCTRL_STATIREG - PMU Status Register IREG */ 5508 PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */ 5509 /* PMUCTRL_STATEREG - PMU Status Register EREG */ 5510 PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */ 5511 int8_t PMUCTRL_reserved_0028[24]; 5512 /* PMUCTRL_STATUS - PMU Status Register STATUS */ 5513 PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */ 5514 /* PMUCTRL_CTRL - PMU Control Register */ 5515 PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */ 5516 int8_t PMUCTRL_reserved_0048[40]; 5517 /* PMUCTRL_MASKF - PMU Mask Fault Register */ 5518 PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */ 5519 /* PMUCTRL_FAULT - PMU Fault Monitor Register */ 5520 PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */ 5521 /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ 5522 PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */ 5523 /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ 5524 PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */ 5525 } PMUCTRL_tag; 5526 5527 5528 #define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL) 5529 5530 5531 5532 /****************************************************************/ 5533 /* */ 5534 /* Module: PIT_RTI */ 5535 /* */ 5536 /****************************************************************/ 5537 5538 typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */ 5539 uint32_t R; 5540 struct { 5541 uint32_t:30; 5542 uint32_t MDIS:1; /* Module Disable. Disable the module clock */ 5543 uint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */ 5544 } B; 5545 } PIT_RTI_PITMCR_32B_tag; 5546 5547 5548 /* Register layout for all registers LDVAL... */ 5549 5550 typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */ 5551 uint32_t R; 5552 struct { 5553 uint32_t TSV:32; /* Time Start Value Bits */ 5554 } B; 5555 } PIT_RTI_LDVAL_32B_tag; 5556 5557 5558 /* Register layout for all registers CVAL... */ 5559 5560 typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */ 5561 uint32_t R; 5562 struct { 5563 uint32_t TVL:32; /* Current Timer Value Bits */ 5564 } B; 5565 } PIT_RTI_CVAL_32B_tag; 5566 5567 5568 /* Register layout for all registers TCTRL... */ 5569 5570 typedef union { /* PIT_RTI_TCTRL - Timer Control Register */ 5571 uint32_t R; 5572 struct { 5573 uint32_t:30; 5574 uint32_t TIE:1; /* Timer Interrupt Enable Bit */ 5575 uint32_t TEN:1; /* Timer Enable Bit */ 5576 } B; 5577 } PIT_RTI_TCTRL_32B_tag; 5578 5579 5580 /* Register layout for all registers TFLG... */ 5581 5582 typedef union { /* PIT_RTI_TFLG - Timer Flag Register */ 5583 uint32_t R; 5584 struct { 5585 uint32_t:31; 5586 uint32_t TIF:1; /* Timer Interrupt Flag Bit */ 5587 } B; 5588 } PIT_RTI_TFLG_32B_tag; 5589 5590 5591 typedef struct PIT_RTI_CHANNEL_struct_tag { 5592 5593 /* PIT_RTI_LDVAL - Timer Load Value Register */ 5594 PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */ 5595 /* PIT_RTI_CVAL - Current Timer Value Register */ 5596 PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */ 5597 /* PIT_RTI_TCTRL - Timer Control Register */ 5598 PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */ 5599 /* PIT_RTI_TFLG - Timer Flag Register */ 5600 PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */ 5601 5602 } PIT_RTI_CHANNEL_tag; 5603 5604 5605 typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */ 5606 /* PIT_RTI_PITMCR - PIT Module Control Register */ 5607 PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */ 5608 int8_t PIT_RTI_reserved_0004_C[252]; 5609 union { 5610 /* Register set CHANNEL */ 5611 PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */ 5612 5613 PIT_RTI_CHANNEL_tag CH[4]; /* offset: 0x0100 (0x0010 x 4) */ 5614 5615 struct { 5616 /* PIT_RTI_LDVAL - Timer Load Value Register */ 5617 PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */ 5618 /* PIT_RTI_CVAL - Current Timer Value Register */ 5619 PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */ 5620 /* PIT_RTI_TCTRL - Timer Control Register */ 5621 PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */ 5622 /* PIT_RTI_TFLG - Timer Flag Register */ 5623 PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */ 5624 /* PIT_RTI_LDVAL - Timer Load Value Register */ 5625 PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */ 5626 /* PIT_RTI_CVAL - Current Timer Value Register */ 5627 PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */ 5628 /* PIT_RTI_TCTRL - Timer Control Register */ 5629 PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */ 5630 /* PIT_RTI_TFLG - Timer Flag Register */ 5631 PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */ 5632 /* PIT_RTI_LDVAL - Timer Load Value Register */ 5633 PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */ 5634 /* PIT_RTI_CVAL - Current Timer Value Register */ 5635 PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */ 5636 /* PIT_RTI_TCTRL - Timer Control Register */ 5637 PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */ 5638 /* PIT_RTI_TFLG - Timer Flag Register */ 5639 PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */ 5640 /* PIT_RTI_LDVAL - Timer Load Value Register */ 5641 PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */ 5642 /* PIT_RTI_CVAL - Current Timer Value Register */ 5643 PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */ 5644 /* PIT_RTI_TCTRL - Timer Control Register */ 5645 PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */ 5646 /* PIT_RTI_TFLG - Timer Flag Register */ 5647 PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */ 5648 }; 5649 5650 }; 5651 } PIT_RTI_tag; 5652 5653 5654 #define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL) 5655 5656 5657 5658 /****************************************************************/ 5659 /* */ 5660 /* Module: ADC */ 5661 /* */ 5662 /****************************************************************/ 5663 5664 typedef union { /* module configuration register */ 5665 uint32_t R; 5666 struct { 5667 uint32_t OWREN:1; /* Overwrite enable */ 5668 uint32_t WLSIDE:1; /* Write Left/right Alligned */ 5669 uint32_t MODE:1; /* One Shot/Scan Mode Selectiom */ 5670 uint32_t EDGLEV:1; /* edge or level selection for external start trigger */ 5671 uint32_t TRGEN:1; /* external trigger enable */ 5672 uint32_t EDGE:1; /* start trigger egde /level detection */ 5673 uint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */ 5674 uint32_t NSTART:1; /* start normal conversion */ 5675 uint32_t:1; 5676 uint32_t JTRGEN:1; /* Injectin External Trigger Enable */ 5677 uint32_t JEDGE:1; /* start trigger egde /level detection for injected */ 5678 uint32_t JSTART:1; /* injected conversion start */ 5679 uint32_t:2; 5680 uint32_t CTUEN:1; /* CTU enabaled */ 5681 uint32_t:8; 5682 uint32_t ADCLKSEL:1; /* Select which clock for device */ 5683 uint32_t ABORTCHAIN:1; /* abort chain conversion */ 5684 uint32_t ABORT:1; /* abort current conversion */ 5685 #ifndef USE_FIELD_ALIASES_ADC 5686 uint32_t ACKO:1; /* Auto Clock Off Enable */ 5687 #else 5688 uint32_t ACK0:1; /* deprecated name - please avoid */ 5689 #endif 5690 uint32_t OFFREFRESH:1; /* offset phase selection */ 5691 uint32_t OFFCANC:1; /* offset phase cancellation selection */ 5692 uint32_t:2; 5693 uint32_t PWDN:1; /* Power Down Enable */ 5694 } B; 5695 } ADC_MCR_32B_tag; 5696 5697 typedef union { /* module status register */ 5698 uint32_t R; 5699 struct { 5700 uint32_t:7; 5701 uint32_t NSTART:1; /* normal conversion status */ 5702 uint32_t JABORT:1; /* Injection chain abort status */ 5703 uint32_t:2; 5704 uint32_t JSTART:1; /* Injection Start status */ 5705 uint32_t:3; 5706 uint32_t CTUSTART:1; /* ctu start status */ 5707 uint32_t CHADDR:7; /* which address conv is goin on */ 5708 uint32_t:3; 5709 #ifndef USE_FIELD_ALIASES_ADC 5710 uint32_t ACKO:1; /* Auto Clock Off Enable status */ 5711 #else 5712 uint32_t ACK0:1; /* deprecated name - please avoid */ 5713 #endif 5714 uint32_t OFFREFRESH:1; /* offset refresh status */ 5715 uint32_t OFFCANC:1; /* offset phase cancellation status */ 5716 uint32_t ADCSTATUS:3; /* status of ADC FSM */ 5717 } B; 5718 } ADC_MSR_32B_tag; 5719 5720 typedef union { /* Interrupt status register */ 5721 uint32_t R; 5722 struct { 5723 uint32_t:25; 5724 uint32_t OFFCANCOVR:1; /* Offset cancellation phase over */ 5725 uint32_t EOFFSET:1; /* error in offset refresh */ 5726 uint32_t EOCTU:1; /* end of CTU channel conversion */ 5727 uint32_t JEOC:1; /* end of injected channel conversion */ 5728 uint32_t JECH:1; /* end ofinjected chain conversion */ 5729 uint32_t EOC:1; /* end of channel conversion */ 5730 uint32_t ECH:1; /* end of chain conversion */ 5731 } B; 5732 } ADC_ISR_32B_tag; 5733 5734 typedef union { /* CHANNEL PENDING REGISTER 0 */ 5735 uint32_t R; 5736 struct { 5737 #ifndef USE_FIELD_ALIASES_ADC 5738 uint32_t EOC_CH31:1; /* Channel 31 conversion over */ 5739 #else 5740 uint32_t EOC31:1; /* deprecated name - please avoid */ 5741 #endif 5742 #ifndef USE_FIELD_ALIASES_ADC 5743 uint32_t EOC_CH30:1; /* Channel 30 conversion over */ 5744 #else 5745 uint32_t EOC30:1; /* deprecated name - please avoid */ 5746 #endif 5747 #ifndef USE_FIELD_ALIASES_ADC 5748 uint32_t EOC_CH29:1; /* Channel 29 conversion over */ 5749 #else 5750 uint32_t EOC29:1; /* deprecated name - please avoid */ 5751 #endif 5752 #ifndef USE_FIELD_ALIASES_ADC 5753 uint32_t EOC_CH28:1; /* Channel 28 conversion over */ 5754 #else 5755 uint32_t EOC28:1; /* deprecated name - please avoid */ 5756 #endif 5757 #ifndef USE_FIELD_ALIASES_ADC 5758 uint32_t EOC_CH27:1; /* Channel 27 conversion over */ 5759 #else 5760 uint32_t EOC27:1; /* deprecated name - please avoid */ 5761 #endif 5762 #ifndef USE_FIELD_ALIASES_ADC 5763 uint32_t EOC_CH26:1; /* Channel 26 conversion over */ 5764 #else 5765 uint32_t EOC26:1; /* deprecated name - please avoid */ 5766 #endif 5767 #ifndef USE_FIELD_ALIASES_ADC 5768 uint32_t EOC_CH25:1; /* Channel 25 conversion over */ 5769 #else 5770 uint32_t EOC25:1; /* deprecated name - please avoid */ 5771 #endif 5772 #ifndef USE_FIELD_ALIASES_ADC 5773 uint32_t EOC_CH24:1; /* Channel 24 conversion over */ 5774 #else 5775 uint32_t EOC24:1; /* deprecated name - please avoid */ 5776 #endif 5777 #ifndef USE_FIELD_ALIASES_ADC 5778 uint32_t EOC_CH23:1; /* Channel 23 conversion over */ 5779 #else 5780 uint32_t EOC23:1; /* deprecated name - please avoid */ 5781 #endif 5782 #ifndef USE_FIELD_ALIASES_ADC 5783 uint32_t EOC_CH22:1; /* Channel 22 conversion over */ 5784 #else 5785 uint32_t EOC22:1; /* deprecated name - please avoid */ 5786 #endif 5787 #ifndef USE_FIELD_ALIASES_ADC 5788 uint32_t EOC_CH21:1; /* Channel 21 conversion over */ 5789 #else 5790 uint32_t EOC21:1; /* deprecated name - please avoid */ 5791 #endif 5792 #ifndef USE_FIELD_ALIASES_ADC 5793 uint32_t EOC_CH20:1; /* Channel 20 conversion over */ 5794 #else 5795 uint32_t EOC20:1; /* deprecated name - please avoid */ 5796 #endif 5797 #ifndef USE_FIELD_ALIASES_ADC 5798 uint32_t EOC_CH19:1; /* Channel 19 conversion over */ 5799 #else 5800 uint32_t EOC19:1; /* deprecated name - please avoid */ 5801 #endif 5802 #ifndef USE_FIELD_ALIASES_ADC 5803 uint32_t EOC_CH18:1; /* Channel 18 conversion over */ 5804 #else 5805 uint32_t EOC18:1; /* deprecated name - please avoid */ 5806 #endif 5807 #ifndef USE_FIELD_ALIASES_ADC 5808 uint32_t EOC_CH17:1; /* Channel 17 conversion over */ 5809 #else 5810 uint32_t EOC17:1; /* deprecated name - please avoid */ 5811 #endif 5812 #ifndef USE_FIELD_ALIASES_ADC 5813 uint32_t EOC_CH16:1; /* Channel 16 conversion over */ 5814 #else 5815 uint32_t EOC16:1; /* deprecated name - please avoid */ 5816 #endif 5817 #ifndef USE_FIELD_ALIASES_ADC 5818 uint32_t EOC_CH15:1; /* Channel 15 conversion over */ 5819 #else 5820 uint32_t EOC15:1; /* deprecated name - please avoid */ 5821 #endif 5822 #ifndef USE_FIELD_ALIASES_ADC 5823 uint32_t EOC_CH14:1; /* Channel 14 conversion over */ 5824 #else 5825 uint32_t EOC14:1; /* deprecated name - please avoid */ 5826 #endif 5827 #ifndef USE_FIELD_ALIASES_ADC 5828 uint32_t EOC_CH13:1; /* Channel 13 conversion over */ 5829 #else 5830 uint32_t EOC13:1; /* deprecated name - please avoid */ 5831 #endif 5832 #ifndef USE_FIELD_ALIASES_ADC 5833 uint32_t EOC_CH12:1; /* Channel 12 conversion over */ 5834 #else 5835 uint32_t EOC12:1; /* deprecated name - please avoid */ 5836 #endif 5837 #ifndef USE_FIELD_ALIASES_ADC 5838 uint32_t EOC_CH11:1; /* Channel 11 conversion over */ 5839 #else 5840 uint32_t EOC11:1; /* deprecated name - please avoid */ 5841 #endif 5842 #ifndef USE_FIELD_ALIASES_ADC 5843 uint32_t EOC_CH10:1; /* Channel 10 conversion over */ 5844 #else 5845 uint32_t EOC10:1; /* deprecated name - please avoid */ 5846 #endif 5847 #ifndef USE_FIELD_ALIASES_ADC 5848 uint32_t EOC_CH9:1; /* Channel 9 conversion over */ 5849 #else 5850 uint32_t EOC9:1; /* deprecated name - please avoid */ 5851 #endif 5852 #ifndef USE_FIELD_ALIASES_ADC 5853 uint32_t EOC_CH8:1; /* Channel 8 conversion over */ 5854 #else 5855 uint32_t EOC8:1; /* deprecated name - please avoid */ 5856 #endif 5857 #ifndef USE_FIELD_ALIASES_ADC 5858 uint32_t EOC_CH7:1; /* Channel 7 conversion over */ 5859 #else 5860 uint32_t EOC7:1; /* deprecated name - please avoid */ 5861 #endif 5862 #ifndef USE_FIELD_ALIASES_ADC 5863 uint32_t EOC_CH6:1; /* Channel 6 conversion over */ 5864 #else 5865 uint32_t EOC6:1; /* deprecated name - please avoid */ 5866 #endif 5867 #ifndef USE_FIELD_ALIASES_ADC 5868 uint32_t EOC_CH5:1; /* Channel 5 conversion over */ 5869 #else 5870 uint32_t EOC5:1; /* deprecated name - please avoid */ 5871 #endif 5872 #ifndef USE_FIELD_ALIASES_ADC 5873 uint32_t EOC_CH4:1; /* Channel 4 conversion over */ 5874 #else 5875 uint32_t EOC4:1; /* deprecated name - please avoid */ 5876 #endif 5877 #ifndef USE_FIELD_ALIASES_ADC 5878 uint32_t EOC_CH3:1; /* Channel 3 conversion over */ 5879 #else 5880 uint32_t EOC3:1; /* deprecated name - please avoid */ 5881 #endif 5882 #ifndef USE_FIELD_ALIASES_ADC 5883 uint32_t EOC_CH2:1; /* Channel 2 conversion over */ 5884 #else 5885 uint32_t EOC2:1; /* deprecated name - please avoid */ 5886 #endif 5887 #ifndef USE_FIELD_ALIASES_ADC 5888 uint32_t EOC_CH1:1; /* Channel 1 conversion over */ 5889 #else 5890 uint32_t EOC1:1; /* deprecated name - please avoid */ 5891 #endif 5892 #ifndef USE_FIELD_ALIASES_ADC 5893 uint32_t EOC_CH0:1; /* Channel 0 conversion over */ 5894 #else 5895 uint32_t EOC0:1; /* deprecated name - please avoid */ 5896 #endif 5897 } B; 5898 } ADC_CEOCFR0_32B_tag; 5899 5900 typedef union { /* CHANNEL PENDING REGISTER 1 */ 5901 uint32_t R; 5902 struct { 5903 uint32_t EOC_CH63:1; /* Channel 63 conversion over */ 5904 uint32_t EOC_CH62:1; /* Channel 62 conversion over */ 5905 uint32_t EOC_CH61:1; /* Channel 61 conversion over */ 5906 uint32_t EOC_CH60:1; /* Channel 60 conversion over */ 5907 uint32_t EOC_CH59:1; /* Channel 59 conversion over */ 5908 uint32_t EOC_CH58:1; /* Channel 58 conversion over */ 5909 uint32_t EOC_CH57:1; /* Channel 57 conversion over */ 5910 uint32_t EOC_CH56:1; /* Channel 56 conversion over */ 5911 uint32_t EOC_CH55:1; /* Channel 55 conversion over */ 5912 uint32_t EOC_CH54:1; /* Channel 54 conversion over */ 5913 uint32_t EOC_CH53:1; /* Channel 53 conversion over */ 5914 uint32_t EOC_CH52:1; /* Channel 52 conversion over */ 5915 uint32_t EOC_CH51:1; /* Channel 51 conversion over */ 5916 uint32_t EOC_CH50:1; /* Channel 50 conversion over */ 5917 uint32_t EOC_CH49:1; /* Channel 49 conversion over */ 5918 uint32_t EOC_CH48:1; /* Channel 48 conversion over */ 5919 uint32_t EOC_CH47:1; /* Channel 47 conversion over */ 5920 uint32_t EOC_CH46:1; /* Channel 46 conversion over */ 5921 uint32_t EOC_CH45:1; /* Channel 45 conversion over */ 5922 uint32_t EOC_CH44:1; /* Channel 44 conversion over */ 5923 uint32_t EOC_CH43:1; /* Channel 43 conversion over */ 5924 uint32_t EOC_CH42:1; /* Channel 42 conversion over */ 5925 uint32_t EOC_CH41:1; /* Channel 41 conversion over */ 5926 uint32_t EOC_CH40:1; /* Channel 40 conversion over */ 5927 uint32_t EOC_CH39:1; /* Channel 39 conversion over */ 5928 uint32_t EOC_CH38:1; /* Channel 38 conversion over */ 5929 uint32_t EOC_CH37:1; /* Channel 37 conversion over */ 5930 uint32_t EOC_CH36:1; /* Channel 36 conversion over */ 5931 uint32_t EOC_CH35:1; /* Channel 35 conversion over */ 5932 uint32_t EOC_CH34:1; /* Channel 34 conversion over */ 5933 uint32_t EOC_CH33:1; /* Channel 33 conversion over */ 5934 uint32_t EOC_CH32:1; /* Channel 32 conversion over */ 5935 } B; 5936 } ADC_CEOCFR1_32B_tag; 5937 5938 typedef union { /* CHANNEL PENDING REGISTER 2 */ 5939 uint32_t R; 5940 struct { 5941 uint32_t EOC_CH95:1; /* Channel 95 conversion over */ 5942 uint32_t EOC_CH94:1; /* Channel 94 conversion over */ 5943 uint32_t EOC_CH93:1; /* Channel 93 conversion over */ 5944 uint32_t EOC_CH92:1; /* Channel 92 conversion over */ 5945 uint32_t EOC_CH91:1; /* Channel 91 conversion over */ 5946 uint32_t EOC_CH90:1; /* Channel 90 conversion over */ 5947 uint32_t EOC_CH89:1; /* Channel 89 conversion over */ 5948 uint32_t EOC_CH88:1; /* Channel 88 conversion over */ 5949 uint32_t EOC_CH87:1; /* Channel 87 conversion over */ 5950 uint32_t EOC_CH86:1; /* Channel 86 conversion over */ 5951 uint32_t EOC_CH85:1; /* Channel 85 conversion over */ 5952 uint32_t EOC_CH84:1; /* Channel 84 conversion over */ 5953 uint32_t EOC_CH83:1; /* Channel 83 conversion over */ 5954 uint32_t EOC_CH82:1; /* Channel 82 conversion over */ 5955 uint32_t EOC_CH81:1; /* Channel 81 conversion over */ 5956 uint32_t EOC_CH80:1; /* Channel 80 conversion over */ 5957 uint32_t EOC_CH79:1; /* Channel 79 conversion over */ 5958 uint32_t EOC_CH78:1; /* Channel 78 conversion over */ 5959 uint32_t EOC_CH77:1; /* Channel 77 conversion over */ 5960 uint32_t EOC_CH76:1; /* Channel 76 conversion over */ 5961 uint32_t EOC_CH75:1; /* Channel 75 conversion over */ 5962 uint32_t EOC_CH74:1; /* Channel 74 conversion over */ 5963 uint32_t EOC_CH73:1; /* Channel 73 conversion over */ 5964 uint32_t EOC_CH72:1; /* Channel 72 conversion over */ 5965 uint32_t EOC_CH71:1; /* Channel 71 conversion over */ 5966 uint32_t EOC_CH70:1; /* Channel 70 conversion over */ 5967 uint32_t EOC_CH69:1; /* Channel 69 conversion over */ 5968 uint32_t EOC_CH68:1; /* Channel 68 conversion over */ 5969 uint32_t EOC_CH67:1; /* Channel 67 conversion over */ 5970 uint32_t EOC_CH66:1; /* Channel 66 conversion over */ 5971 uint32_t EOC_CH65:1; /* Channel 65 conversion over */ 5972 uint32_t EOC_CH64:1; /* Channel 64 conversion over */ 5973 } B; 5974 } ADC_CEOCFR2_32B_tag; 5975 5976 typedef union { /* interrupt mask register */ 5977 uint32_t R; 5978 struct { 5979 uint32_t:25; 5980 uint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */ 5981 uint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */ 5982 uint32_t MSKEOCTU:1; /* mask bit for EOCTU */ 5983 uint32_t MSKJEOC:1; /* mask bit for JEOC */ 5984 uint32_t MSKJECH:1; /* mask bit for JECH */ 5985 uint32_t MSKEOC:1; /* mask bit for EOC */ 5986 uint32_t MSKECH:1; /* mask bit for ECH */ 5987 } B; 5988 } ADC_IMR_32B_tag; 5989 5990 typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */ 5991 uint32_t R; 5992 struct { 5993 uint32_t CIM31:1; /* Channel 31 mask register */ 5994 uint32_t CIM30:1; /* Channel 30 mask register */ 5995 uint32_t CIM29:1; /* Channel 29 mask register */ 5996 uint32_t CIM28:1; /* Channel 28 mask register */ 5997 uint32_t CIM27:1; /* Channel 27 mask register */ 5998 uint32_t CIM26:1; /* Channel 26 mask register */ 5999 uint32_t CIM25:1; /* Channel 25 mask register */ 6000 uint32_t CIM24:1; /* Channel 24 mask register */ 6001 uint32_t CIM23:1; /* Channel 23 mask register */ 6002 uint32_t CIM22:1; /* Channel 22 mask register */ 6003 uint32_t CIM21:1; /* Channel 21 mask register */ 6004 uint32_t CIM20:1; /* Channel 20 mask register */ 6005 uint32_t CIM19:1; /* Channel 19 mask register */ 6006 uint32_t CIM18:1; /* Channel 18 mask register */ 6007 uint32_t CIM17:1; /* Channel 17 mask register */ 6008 uint32_t CIM16:1; /* Channel 16 mask register */ 6009 uint32_t CIM15:1; /* Channel 15 mask register */ 6010 uint32_t CIM14:1; /* Channel 14 mask register */ 6011 uint32_t CIM13:1; /* Channel 13 mask register */ 6012 uint32_t CIM12:1; /* Channel 12 mask register */ 6013 uint32_t CIM11:1; /* Channel 11 mask register */ 6014 uint32_t CIM10:1; /* Channel 10 mask register */ 6015 uint32_t CIM9:1; /* Channel 9 mask register */ 6016 uint32_t CIM8:1; /* Channel 8 mask register */ 6017 uint32_t CIM7:1; /* Channel 7 mask register */ 6018 uint32_t CIM6:1; /* Channel 6 mask register */ 6019 uint32_t CIM5:1; /* Channel 5 mask register */ 6020 uint32_t CIM4:1; /* Channel 4 mask register */ 6021 uint32_t CIM3:1; /* Channel 3 mask register */ 6022 uint32_t CIM2:1; /* Channel 2 mask register */ 6023 uint32_t CIM1:1; /* Channel 1 mask register */ 6024 uint32_t CIM0:1; /* Channel 0 mask register */ 6025 } B; 6026 } ADC_CIMR0_32B_tag; 6027 6028 typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */ 6029 uint32_t R; 6030 struct { 6031 uint32_t CIM63:1; /* Channel 63 mask register */ 6032 uint32_t CIM62:1; /* Channel 62 mask register */ 6033 uint32_t CIM61:1; /* Channel 61 mask register */ 6034 uint32_t CIM60:1; /* Channel 60 mask register */ 6035 uint32_t CIM59:1; /* Channel 59 mask register */ 6036 uint32_t CIM58:1; /* Channel 58 mask register */ 6037 uint32_t CIM57:1; /* Channel 57 mask register */ 6038 uint32_t CIM56:1; /* Channel 56 mask register */ 6039 uint32_t CIM55:1; /* Channel 55 mask register */ 6040 uint32_t CIM54:1; /* Channel 54 mask register */ 6041 uint32_t CIM53:1; /* Channel 53 mask register */ 6042 uint32_t CIM52:1; /* Channel 52 mask register */ 6043 uint32_t CIM51:1; /* Channel 51 mask register */ 6044 uint32_t CIM50:1; /* Channel 50 mask register */ 6045 uint32_t CIM49:1; /* Channel 49 mask register */ 6046 uint32_t CIM48:1; /* Channel 48 mask register */ 6047 uint32_t CIM47:1; /* Channel 47 mask register */ 6048 uint32_t CIM46:1; /* Channel 46 mask register */ 6049 uint32_t CIM45:1; /* Channel 45 mask register */ 6050 uint32_t CIM44:1; /* Channel 44 mask register */ 6051 uint32_t CIM43:1; /* Channel 43 mask register */ 6052 uint32_t CIM42:1; /* Channel 42 mask register */ 6053 uint32_t CIM41:1; /* Channel 41 mask register */ 6054 uint32_t CIM40:1; /* Channel 40 mask register */ 6055 uint32_t CIM39:1; /* Channel 39 mask register */ 6056 uint32_t CIM38:1; /* Channel 38 mask register */ 6057 uint32_t CIM37:1; /* Channel 37 mask register */ 6058 uint32_t CIM36:1; /* Channel 36 mask register */ 6059 uint32_t CIM35:1; /* Channel 35 mask register */ 6060 uint32_t CIM34:1; /* Channel 34 mask register */ 6061 uint32_t CIM33:1; /* Channel 33 mask register */ 6062 uint32_t CIM32:1; /* Channel 32 mask register */ 6063 } B; 6064 } ADC_CIMR1_32B_tag; 6065 6066 typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */ 6067 uint32_t R; 6068 struct { 6069 uint32_t CIM95:1; /* Channel 95 mask register */ 6070 uint32_t CIM94:1; /* Channel 94 mask register */ 6071 uint32_t CIM93:1; /* Channel 93 mask register */ 6072 uint32_t CIM92:1; /* Channel 92 mask register */ 6073 uint32_t CIM91:1; /* Channel 91 mask register */ 6074 uint32_t CIM90:1; /* Channel 90 mask register */ 6075 uint32_t CIM89:1; /* Channel 89 mask register */ 6076 uint32_t CIM88:1; /* Channel 88 mask register */ 6077 uint32_t CIM87:1; /* Channel 87 mask register */ 6078 uint32_t CIM86:1; /* Channel 86 mask register */ 6079 uint32_t CIM85:1; /* Channel 85 mask register */ 6080 uint32_t CIM84:1; /* Channel 84 mask register */ 6081 uint32_t CIM83:1; /* Channel 83 mask register */ 6082 uint32_t CIM82:1; /* Channel 82 mask register */ 6083 uint32_t CIM81:1; /* Channel 81 mask register */ 6084 uint32_t CIM80:1; /* Channel 80 mask register */ 6085 uint32_t CIM79:1; /* Channel 79 mask register */ 6086 uint32_t CIM78:1; /* Channel 78 mask register */ 6087 uint32_t CIM77:1; /* Channel 77 mask register */ 6088 uint32_t CIM76:1; /* Channel 76 mask register */ 6089 uint32_t CIM75:1; /* Channel 75 mask register */ 6090 uint32_t CIM74:1; /* Channel 74 mask register */ 6091 uint32_t CIM73:1; /* Channel 73 mask register */ 6092 uint32_t CIM72:1; /* Channel 72 mask register */ 6093 uint32_t CIM71:1; /* Channel 71 mask register */ 6094 uint32_t CIM70:1; /* Channel 70 mask register */ 6095 uint32_t CIM69:1; /* Channel 69 mask register */ 6096 uint32_t CIM68:1; /* Channel 68 mask register */ 6097 uint32_t CIM67:1; /* Channel 67 mask register */ 6098 uint32_t CIM66:1; /* Channel 66 mask register */ 6099 uint32_t CIM65:1; /* Channel 65 mask register */ 6100 uint32_t CIM64:1; /* Channel 64 mask register */ 6101 } B; 6102 } ADC_CIMR2_32B_tag; 6103 6104 typedef union { /* Watchdog Threshold interrupt status register */ 6105 uint32_t R; 6106 struct { 6107 uint32_t:24; 6108 uint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */ 6109 uint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */ 6110 uint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */ 6111 uint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */ 6112 uint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */ 6113 uint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */ 6114 uint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */ 6115 uint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */ 6116 } B; 6117 } ADC_WTISR_32B_tag; 6118 6119 typedef union { /* Watchdog interrupt MASK register */ 6120 uint32_t R; 6121 struct { 6122 uint32_t:24; 6123 uint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */ 6124 uint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */ 6125 uint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */ 6126 uint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */ 6127 uint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */ 6128 uint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */ 6129 uint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */ 6130 uint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */ 6131 } B; 6132 } ADC_WTIMR_32B_tag; 6133 6134 typedef union { /* DMAE register */ 6135 uint32_t R; 6136 struct { 6137 uint32_t:30; 6138 uint32_t DCLR:1; /* DMA clear sequence enable */ 6139 uint32_t DMAEN:1; /* DMA global enable */ 6140 } B; 6141 } ADC_DMAE_32B_tag; 6142 6143 typedef union { /* DMA REGISTER 0 */ 6144 uint32_t R; 6145 struct { 6146 uint32_t DMA31:1; /* Channel 31 DMA Enable */ 6147 uint32_t DMA30:1; /* Channel 30 DMA Enable */ 6148 uint32_t DMA29:1; /* Channel 29 DMA Enable */ 6149 uint32_t DMA28:1; /* Channel 28 DMA Enable */ 6150 uint32_t DMA27:1; /* Channel 27 DMA Enable */ 6151 uint32_t DMA26:1; /* Channel 26 DMA Enable */ 6152 uint32_t DMA25:1; /* Channel 25 DMA Enable */ 6153 uint32_t DMA24:1; /* Channel 24 DMA Enable */ 6154 uint32_t DMA23:1; /* Channel 23 DMA Enable */ 6155 uint32_t DMA22:1; /* Channel 22 DMA Enable */ 6156 uint32_t DMA21:1; /* Channel 21 DMA Enable */ 6157 uint32_t DMA20:1; /* Channel 20 DMA Enable */ 6158 uint32_t DMA19:1; /* Channel 19 DMA Enable */ 6159 uint32_t DMA18:1; /* Channel 18 DMA Enable */ 6160 uint32_t DMA17:1; /* Channel 17 DMA Enable */ 6161 uint32_t DMA16:1; /* Channel 16 DMA Enable */ 6162 uint32_t DMA15:1; /* Channel 15 DMA Enable */ 6163 uint32_t DMA14:1; /* Channel 14 DMA Enable */ 6164 uint32_t DMA13:1; /* Channel 13 DMA Enable */ 6165 uint32_t DMA12:1; /* Channel 12 DMA Enable */ 6166 uint32_t DMA11:1; /* Channel 11 DMA Enable */ 6167 uint32_t DMA10:1; /* Channel 10 DMA Enable */ 6168 uint32_t DMA9:1; /* Channel 9 DMA Enable */ 6169 uint32_t DMA8:1; /* Channel 8 DMA Enable */ 6170 uint32_t DMA7:1; /* Channel 7 DMA Enable */ 6171 uint32_t DMA6:1; /* Channel 6 DMA Enable */ 6172 uint32_t DMA5:1; /* Channel 5 DMA Enable */ 6173 uint32_t DMA4:1; /* Channel 4 DMA Enable */ 6174 uint32_t DMA3:1; /* Channel 3 DMA Enable */ 6175 uint32_t DMA2:1; /* Channel 2 DMA Enable */ 6176 uint32_t DMA1:1; /* Channel 1 DMA Enable */ 6177 uint32_t DMA0:1; /* Channel 0 DMA Enable */ 6178 } B; 6179 } ADC_DMAR0_32B_tag; 6180 6181 typedef union { /* DMA REGISTER 1 */ 6182 uint32_t R; 6183 struct { 6184 uint32_t DMA63:1; /* Channel 63 DMA Enable */ 6185 uint32_t DMA62:1; /* Channel 62 DMA Enable */ 6186 uint32_t DMA61:1; /* Channel 61 DMA Enable */ 6187 uint32_t DMA60:1; /* Channel 60 DMA Enable */ 6188 uint32_t DMA59:1; /* Channel 59 DMA Enable */ 6189 uint32_t DMA58:1; /* Channel 58 DMA Enable */ 6190 uint32_t DMA57:1; /* Channel 57 DMA Enable */ 6191 uint32_t DMA56:1; /* Channel 56 DMA Enable */ 6192 uint32_t DMA55:1; /* Channel 55 DMA Enable */ 6193 uint32_t DMA54:1; /* Channel 54 DMA Enable */ 6194 uint32_t DMA53:1; /* Channel 53 DMA Enable */ 6195 uint32_t DMA52:1; /* Channel 52 DMA Enable */ 6196 uint32_t DMA51:1; /* Channel 51 DMA Enable */ 6197 uint32_t DMA50:1; /* Channel 50 DMA Enable */ 6198 uint32_t DMA49:1; /* Channel 49 DMA Enable */ 6199 uint32_t DMA48:1; /* Channel 48 DMA Enable */ 6200 uint32_t DMA47:1; /* Channel 47 DMA Enable */ 6201 uint32_t DMA46:1; /* Channel 46 DMA Enable */ 6202 uint32_t DMA45:1; /* Channel 45 DMA Enable */ 6203 uint32_t DMA44:1; /* Channel 44 DMA Enable */ 6204 uint32_t DMA43:1; /* Channel 43 DMA Enable */ 6205 uint32_t DMA42:1; /* Channel 42 DMA Enable */ 6206 uint32_t DMA41:1; /* Channel 41 DMA Enable */ 6207 uint32_t DMA40:1; /* Channel 40 DMA Enable */ 6208 uint32_t DMA39:1; /* Channel 39 DMA Enable */ 6209 uint32_t DMA38:1; /* Channel 38 DMA Enable */ 6210 uint32_t DMA37:1; /* Channel 37 DMA Enable */ 6211 uint32_t DMA36:1; /* Channel 36 DMA Enable */ 6212 uint32_t DMA35:1; /* Channel 35 DMA Enable */ 6213 uint32_t DMA34:1; /* Channel 34 DMA Enable */ 6214 uint32_t DMA33:1; /* Channel 33 DMA Enable */ 6215 uint32_t DMA32:1; /* Channel 32 DMA Enable */ 6216 } B; 6217 } ADC_DMAR1_32B_tag; 6218 6219 typedef union { /* DMA REGISTER 2 */ 6220 uint32_t R; 6221 struct { 6222 uint32_t DMA95:1; /* Channel 95 DMA Enable */ 6223 uint32_t DMA94:1; /* Channel 94 DMA Enable */ 6224 uint32_t DMA93:1; /* Channel 93 DMA Enable */ 6225 uint32_t DMA92:1; /* Channel 92 DMA Enable */ 6226 uint32_t DMA91:1; /* Channel 91 DMA Enable */ 6227 uint32_t DMA90:1; /* Channel 90 DMA Enable */ 6228 uint32_t DMA89:1; /* Channel 89 DMA Enable */ 6229 uint32_t DMA88:1; /* Channel 88 DMA Enable */ 6230 uint32_t DMA87:1; /* Channel 87 DMA Enable */ 6231 uint32_t DMA86:1; /* Channel 86 DMA Enable */ 6232 uint32_t DMA85:1; /* Channel 85 DMA Enable */ 6233 uint32_t DMA84:1; /* Channel 84 DMA Enable */ 6234 uint32_t DMA83:1; /* Channel 83 DMA Enable */ 6235 uint32_t DMA82:1; /* Channel 82 DMA Enable */ 6236 uint32_t DMA81:1; /* Channel 81 DMA Enable */ 6237 uint32_t DMA80:1; /* Channel 80 DMA Enable */ 6238 uint32_t DMA79:1; /* Channel 79 DMA Enable */ 6239 uint32_t DMA78:1; /* Channel 78 DMA Enable */ 6240 uint32_t DMA77:1; /* Channel 77 DMA Enable */ 6241 uint32_t DMA76:1; /* Channel 76 DMA Enable */ 6242 uint32_t DMA75:1; /* Channel 75 DMA Enable */ 6243 uint32_t DMA74:1; /* Channel 74 DMA Enable */ 6244 uint32_t DMA73:1; /* Channel 73 DMA Enable */ 6245 uint32_t DMA72:1; /* Channel 72 DMA Enable */ 6246 uint32_t DMA71:1; /* Channel 71 DMA Enable */ 6247 uint32_t DMA70:1; /* Channel 70 DMA Enable */ 6248 uint32_t DMA69:1; /* Channel 69 DMA Enable */ 6249 uint32_t DMA68:1; /* Channel 68 DMA Enable */ 6250 uint32_t DMA67:1; /* Channel 67 DMA Enable */ 6251 uint32_t DMA66:1; /* Channel 66 DMA Enable */ 6252 uint32_t DMA65:1; /* Channel 65 DMA Enable */ 6253 uint32_t DMA64:1; /* Channel 64 DMA Enable */ 6254 } B; 6255 } ADC_DMAR2_32B_tag; 6256 6257 6258 /* Register layout for all registers TRC... */ 6259 6260 typedef union { /* Threshold Control register C */ 6261 uint32_t R; 6262 struct { 6263 uint32_t:16; 6264 uint32_t THREN:1; /* Threshold enable */ 6265 uint32_t THRINV:1; /* invert the output pin */ 6266 uint32_t THROP:1; /* output pin register */ 6267 uint32_t:6; 6268 uint32_t THRCH:7; /* Choose channel for threshold register */ 6269 } B; 6270 } ADC_TRC_32B_tag; 6271 6272 6273 /* Register layout for all registers THRHLR... */ 6274 6275 typedef union { /* Upper Threshold register */ 6276 uint32_t R; 6277 struct { 6278 uint32_t:4; 6279 uint32_t THRH:12; /* high threshold value s */ 6280 uint32_t:4; 6281 uint32_t THRL:12; /* low threshold value s */ 6282 } B; 6283 } ADC_THRHLR_32B_tag; 6284 6285 6286 /* Register layout for all registers THRALT... */ 6287 6288 typedef union { /* alternate Upper Threshold register */ 6289 uint32_t R; 6290 struct { 6291 uint32_t:6; 6292 uint32_t THRH:10; /* high threshold value s */ 6293 uint32_t:6; 6294 uint32_t THRL:10; /* low threshold value s */ 6295 } B; 6296 } ADC_THRALT_32B_tag; 6297 6298 typedef union { /* PRESAMPLING CONTROL REGISTER */ 6299 uint32_t R; 6300 struct { 6301 uint32_t:25; 6302 uint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */ 6303 uint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */ 6304 uint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */ 6305 #ifndef USE_FIELD_ALIASES_ADC 6306 uint32_t PRECONV:1; /* Presampled value */ 6307 #else 6308 uint32_t PREONCE:1; /* deprecated name - please avoid */ 6309 #endif 6310 } B; 6311 } ADC_PSCR_32B_tag; 6312 6313 typedef union { /* Presampling Register 0 */ 6314 uint32_t R; 6315 struct { 6316 uint32_t PRES31:1; /* Channel 31 Presampling Enable */ 6317 uint32_t PRES30:1; /* Channel 30 Presampling Enable */ 6318 uint32_t PRES29:1; /* Channel 29 Presampling Enable */ 6319 uint32_t PRES28:1; /* Channel 28 Presampling Enable */ 6320 uint32_t PRES27:1; /* Channel 27 Presampling Enable */ 6321 uint32_t PRES26:1; /* Channel 26 Presampling Enable */ 6322 uint32_t PRES25:1; /* Channel 25 Presampling Enable */ 6323 uint32_t PRES24:1; /* Channel 24 Presampling Enable */ 6324 uint32_t PRES23:1; /* Channel 23 Presampling Enable */ 6325 uint32_t PRES22:1; /* Channel 22 Presampling Enable */ 6326 uint32_t PRES21:1; /* Channel 21 Presampling Enable */ 6327 uint32_t PRES20:1; /* Channel 20 Presampling Enable */ 6328 uint32_t PRES19:1; /* Channel 19 Presampling Enable */ 6329 uint32_t PRES18:1; /* Channel 18 Presampling Enable */ 6330 uint32_t PRES17:1; /* Channel 17 Presampling Enable */ 6331 uint32_t PRES16:1; /* Channel 16 Presampling Enable */ 6332 uint32_t PRES15:1; /* Channel 15 Presampling Enable */ 6333 uint32_t PRES14:1; /* Channel 14 Presampling Enable */ 6334 uint32_t PRES13:1; /* Channel 13 Presampling Enable */ 6335 uint32_t PRES12:1; /* Channel 12 Presampling Enable */ 6336 uint32_t PRES11:1; /* Channel 11 Presampling Enable */ 6337 uint32_t PRES10:1; /* Channel 10 Presampling Enable */ 6338 uint32_t PRES9:1; /* Channel 9 Presampling Enable */ 6339 uint32_t PRES8:1; /* Channel 8 Presampling Enable */ 6340 uint32_t PRES7:1; /* Channel 7 Presampling Enable */ 6341 uint32_t PRES6:1; /* Channel 6 Presampling Enable */ 6342 uint32_t PRES5:1; /* Channel 5 Presampling Enable */ 6343 uint32_t PRES4:1; /* Channel 4 Presampling Enable */ 6344 uint32_t PRES3:1; /* Channel 3 Presampling Enable */ 6345 uint32_t PRES2:1; /* Channel 2 Presampling Enable */ 6346 uint32_t PRES1:1; /* Channel 1presampling Enable */ 6347 uint32_t PRES0:1; /* Channel 0 Presampling Enable */ 6348 } B; 6349 } ADC_PSR0_32B_tag; 6350 6351 typedef union { /* Presampling REGISTER 1 */ 6352 uint32_t R; 6353 struct { 6354 uint32_t PRES63:1; /* Channel 63 Presampling Enable */ 6355 uint32_t PRES62:1; /* Channel 62 Presampling Enable */ 6356 uint32_t PRES61:1; /* Channel 61 Presampling Enable */ 6357 uint32_t PRES60:1; /* Channel 60 Presampling Enable */ 6358 uint32_t PRES59:1; /* Channel 59 Presampling Enable */ 6359 uint32_t PRES58:1; /* Channel 58 Presampling Enable */ 6360 uint32_t PRES57:1; /* Channel 57 Presampling Enable */ 6361 uint32_t PRES56:1; /* Channel 56 Presampling Enable */ 6362 uint32_t PRES55:1; /* Channel 55 Presampling Enable */ 6363 uint32_t PRES54:1; /* Channel 54 Presampling Enable */ 6364 uint32_t PRES53:1; /* Channel 53 Presampling Enable */ 6365 uint32_t PRES52:1; /* Channel 52 Presampling Enable */ 6366 uint32_t PRES51:1; /* Channel 51 Presampling Enable */ 6367 uint32_t PRES50:1; /* Channel 50 Presampling Enable */ 6368 uint32_t PRES49:1; /* Channel 49 Presampling Enable */ 6369 uint32_t PRES48:1; /* Channel 48 Presampling Enable */ 6370 uint32_t PRES47:1; /* Channel 47 Presampling Enable */ 6371 uint32_t PRES46:1; /* Channel 46 Presampling Enable */ 6372 uint32_t PRES45:1; /* Channel 45 Presampling Enable */ 6373 uint32_t PRES44:1; /* Channel 44 Presampling Enable */ 6374 uint32_t PRES43:1; /* Channel 43 Presampling Enable */ 6375 uint32_t PRES42:1; /* Channel 42 Presampling Enable */ 6376 uint32_t PRES41:1; /* Channel 41 Presampling Enable */ 6377 uint32_t PRES40:1; /* Channel 40 Presampling Enable */ 6378 uint32_t PRES39:1; /* Channel 39 Presampling Enable */ 6379 uint32_t PRES38:1; /* Channel 38 Presampling Enable */ 6380 uint32_t PRES37:1; /* Channel 37 Presampling Enable */ 6381 uint32_t PRES36:1; /* Channel 36 Presampling Enable */ 6382 uint32_t PRES35:1; /* Channel 35 Presampling Enable */ 6383 uint32_t PRES34:1; /* Channel 34 Presampling Enable */ 6384 uint32_t PRES33:1; /* Channel 33 Presampling Enable */ 6385 uint32_t PRES32:1; /* Channel 32 Presampling Enable */ 6386 } B; 6387 } ADC_PSR1_32B_tag; 6388 6389 typedef union { /* Presampling REGISTER 2 */ 6390 uint32_t R; 6391 struct { 6392 uint32_t PRES95:1; /* Channel 95 Presampling Enable */ 6393 uint32_t PRES94:1; /* Channel 94 Presampling Enable */ 6394 uint32_t PRES93:1; /* Channel 93 Presampling Enable */ 6395 uint32_t PRES92:1; /* Channel 92 Presampling Enable */ 6396 uint32_t PRES91:1; /* Channel 91 Presampling Enable */ 6397 uint32_t PRES90:1; /* Channel 90 Presampling Enable */ 6398 uint32_t PRES89:1; /* Channel 89 Presampling Enable */ 6399 uint32_t PRES88:1; /* Channel 88 Presampling Enable */ 6400 uint32_t PRES87:1; /* Channel 87 Presampling Enable */ 6401 uint32_t PRES86:1; /* Channel 86 Presampling Enable */ 6402 uint32_t PRES85:1; /* Channel 85 Presampling Enable */ 6403 uint32_t PRES84:1; /* Channel 84 Presampling Enable */ 6404 uint32_t PRES83:1; /* Channel 83 Presampling Enable */ 6405 uint32_t PRES82:1; /* Channel 82 Presampling Enable */ 6406 uint32_t PRES81:1; /* Channel 81 Presampling Enable */ 6407 uint32_t PRES80:1; /* Channel 80 Presampling Enable */ 6408 uint32_t PRES79:1; /* Channel 79 Presampling Enable */ 6409 uint32_t PRES78:1; /* Channel 78 Presampling Enable */ 6410 uint32_t PRES77:1; /* Channel 77 Presampling Enable */ 6411 uint32_t PRES76:1; /* Channel 76 Presampling Enable */ 6412 uint32_t PRES75:1; /* Channel 75 Presampling Enable */ 6413 uint32_t PRES74:1; /* Channel 74 Presampling Enable */ 6414 uint32_t PRES73:1; /* Channel 73 Presampling Enable */ 6415 uint32_t PRES72:1; /* Channel 72 Presampling Enable */ 6416 uint32_t PRES71:1; /* Channel 71 Presampling Enable */ 6417 uint32_t PRES70:1; /* Channel 70 Presampling Enable */ 6418 uint32_t PRES69:1; /* Channel 69 Presampling Enable */ 6419 uint32_t PRES68:1; /* Channel 68 Presampling Enable */ 6420 uint32_t PRES67:1; /* Channel 67 Presampling Enable */ 6421 uint32_t PRES66:1; /* Channel 66 Presampling Enable */ 6422 uint32_t PRES65:1; /* Channel 65 Presampling Enable */ 6423 uint32_t PRES64:1; /* Channel 64 Presampling Enable */ 6424 } B; 6425 } ADC_PSR2_32B_tag; 6426 6427 6428 /* Register layout for all registers CTR... */ 6429 6430 typedef union { /* conversion timing register */ 6431 uint32_t R; 6432 struct { 6433 uint32_t:16; 6434 uint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */ 6435 uint32_t:1; 6436 uint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */ 6437 uint32_t:1; 6438 uint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */ 6439 uint32_t:1; 6440 #ifndef USE_FIELD_ALIASES_ADC 6441 uint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */ 6442 #else 6443 uint32_t INPSAMP:8; 6444 #endif 6445 } B; 6446 } ADC_CTR_32B_tag; 6447 6448 typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */ 6449 uint32_t R; 6450 struct { 6451 uint32_t CH31:1; /* Channel 31 Normal Sampling Enable */ 6452 uint32_t CH30:1; /* Channel 30 Normal Sampling Enable */ 6453 uint32_t CH29:1; /* Channel 29 Normal Sampling Enable */ 6454 uint32_t CH28:1; /* Channel 28 Normal Sampling Enable */ 6455 uint32_t CH27:1; /* Channel 27 Normal Sampling Enable */ 6456 uint32_t CH26:1; /* Channel 26 Normal Sampling Enable */ 6457 uint32_t CH25:1; /* Channel 25 Normal Sampling Enable */ 6458 uint32_t CH24:1; /* Channel 24 Normal Sampling Enable */ 6459 uint32_t CH23:1; /* Channel 23 Normal Sampling Enable */ 6460 uint32_t CH22:1; /* Channel 22 Normal Sampling Enable */ 6461 uint32_t CH21:1; /* Channel 21 Normal Sampling Enable */ 6462 uint32_t CH20:1; /* Channel 20 Normal Sampling Enable */ 6463 uint32_t CH19:1; /* Channel 19 Normal Sampling Enable */ 6464 uint32_t CH18:1; /* Channel 18 Normal Sampling Enable */ 6465 uint32_t CH17:1; /* Channel 17 Normal Sampling Enable */ 6466 uint32_t CH16:1; /* Channel 16 Normal Sampling Enable */ 6467 uint32_t CH15:1; /* Channel 15 Normal Sampling Enable */ 6468 uint32_t CH14:1; /* Channel 14 Normal Sampling Enable */ 6469 uint32_t CH13:1; /* Channel 13 Normal Sampling Enable */ 6470 uint32_t CH12:1; /* Channel 12 Normal Sampling Enable */ 6471 uint32_t CH11:1; /* Channel 11 Normal Sampling Enable */ 6472 uint32_t CH10:1; /* Channel 10 Normal Sampling Enable */ 6473 uint32_t CH9:1; /* Channel 9 Normal Sampling Enable */ 6474 uint32_t CH8:1; /* Channel 8 Normal Sampling Enable */ 6475 uint32_t CH7:1; /* Channel 7 Normal Sampling Enable */ 6476 uint32_t CH6:1; /* Channel 6 Normal Sampling Enable */ 6477 uint32_t CH5:1; /* Channel 5 Normal Sampling Enable */ 6478 uint32_t CH4:1; /* Channel 4 Normal Sampling Enable */ 6479 uint32_t CH3:1; /* Channel 3 Normal Sampling Enable */ 6480 uint32_t CH2:1; /* Channel 2 Normal Sampling Enable */ 6481 uint32_t CH1:1; /* Channel 1 Normal Sampling Enable */ 6482 uint32_t CH0:1; /* Channel 0 Normal Sampling Enable */ 6483 } B; 6484 } ADC_NCMR0_32B_tag; 6485 6486 typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */ 6487 uint32_t R; 6488 struct { 6489 uint32_t CH63:1; /* Channel 63 Normal Sampling Enable */ 6490 uint32_t CH62:1; /* Channel 62 Normal Sampling Enable */ 6491 uint32_t CH61:1; /* Channel 61 Normal Sampling Enable */ 6492 uint32_t CH60:1; /* Channel 60 Normal Sampling Enable */ 6493 uint32_t CH59:1; /* Channel 59 Normal Sampling Enable */ 6494 uint32_t CH58:1; /* Channel 58 Normal Sampling Enable */ 6495 uint32_t CH57:1; /* Channel 57 Normal Sampling Enable */ 6496 uint32_t CH56:1; /* Channel 56 Normal Sampling Enable */ 6497 uint32_t CH55:1; /* Channel 55 Normal Sampling Enable */ 6498 uint32_t CH54:1; /* Channel 54 Normal Sampling Enable */ 6499 uint32_t CH53:1; /* Channel 53 Normal Sampling Enable */ 6500 uint32_t CH52:1; /* Channel 52 Normal Sampling Enable */ 6501 uint32_t CH51:1; /* Channel 51 Normal Sampling Enable */ 6502 uint32_t CH50:1; /* Channel 50 Normal Sampling Enable */ 6503 uint32_t CH49:1; /* Channel 49 Normal Sampling Enable */ 6504 uint32_t CH48:1; /* Channel 48 Normal Sampling Enable */ 6505 uint32_t CH47:1; /* Channel 47 Normal Sampling Enable */ 6506 uint32_t CH46:1; /* Channel 46 Normal Sampling Enable */ 6507 uint32_t CH45:1; /* Channel 45 Normal Sampling Enable */ 6508 uint32_t CH44:1; /* Channel 44 Normal Sampling Enable */ 6509 uint32_t CH43:1; /* Channel 43 Normal Sampling Enable */ 6510 uint32_t CH42:1; /* Channel 42 Normal Sampling Enable */ 6511 uint32_t CH41:1; /* Channel 41 Normal Sampling Enable */ 6512 uint32_t CH40:1; /* Channel 40 Normal Sampling Enable */ 6513 uint32_t CH39:1; /* Channel 39 Normal Sampling Enable */ 6514 uint32_t CH38:1; /* Channel 38 Normal Sampling Enable */ 6515 uint32_t CH37:1; /* Channel 37 Normal Sampling Enable */ 6516 uint32_t CH36:1; /* Channel 36 Normal Sampling Enable */ 6517 uint32_t CH35:1; /* Channel 35 Normal Sampling Enable */ 6518 uint32_t CH34:1; /* Channel 34 Normal Sampling Enable */ 6519 uint32_t CH33:1; /* Channel 33 Normal Sampling Enable */ 6520 uint32_t CH32:1; /* Channel 32 Normal Sampling Enable */ 6521 } B; 6522 } ADC_NCMR1_32B_tag; 6523 6524 typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */ 6525 uint32_t R; 6526 struct { 6527 uint32_t CH95:1; /* Channel 95 Normal Sampling Enable */ 6528 uint32_t CH94:1; /* Channel 94 Normal Sampling Enable */ 6529 uint32_t CH93:1; /* Channel 93 Normal Sampling Enable */ 6530 uint32_t CH92:1; /* Channel 92 Normal Sampling Enable */ 6531 uint32_t CH91:1; /* Channel 91 Normal Sampling Enable */ 6532 uint32_t CH90:1; /* Channel 90 Normal Sampling Enable */ 6533 uint32_t CH89:1; /* Channel 89 Normal Sampling Enable */ 6534 uint32_t CH88:1; /* Channel 88 Normal Sampling Enable */ 6535 uint32_t CH87:1; /* Channel 87 Normal Sampling Enable */ 6536 uint32_t CH86:1; /* Channel 86 Normal Sampling Enable */ 6537 uint32_t CH85:1; /* Channel 85 Normal Sampling Enable */ 6538 uint32_t CH84:1; /* Channel 84 Normal Sampling Enable */ 6539 uint32_t CH83:1; /* Channel 83 Normal Sampling Enable */ 6540 uint32_t CH82:1; /* Channel 82 Normal Sampling Enable */ 6541 uint32_t CH81:1; /* Channel 81 Normal Sampling Enable */ 6542 uint32_t CH80:1; /* Channel 80 Normal Sampling Enable */ 6543 uint32_t CH79:1; /* Channel 79 Normal Sampling Enable */ 6544 uint32_t CH78:1; /* Channel 78 Normal Sampling Enable */ 6545 uint32_t CH77:1; /* Channel 77 Normal Sampling Enable */ 6546 uint32_t CH76:1; /* Channel 76 Normal Sampling Enable */ 6547 uint32_t CH75:1; /* Channel 75 Normal Sampling Enable */ 6548 uint32_t CH74:1; /* Channel 74 Normal Sampling Enable */ 6549 uint32_t CH73:1; /* Channel 73 Normal Sampling Enable */ 6550 uint32_t CH72:1; /* Channel 72 Normal Sampling Enable */ 6551 uint32_t CH71:1; /* Channel 71 Normal Sampling Enable */ 6552 uint32_t CH70:1; /* Channel 70 Normal Sampling Enable */ 6553 uint32_t CH69:1; /* Channel 69 Normal Sampling Enable */ 6554 uint32_t CH68:1; /* Channel 68 Normal Sampling Enable */ 6555 uint32_t CH67:1; /* Channel 67 Normal Sampling Enable */ 6556 uint32_t CH66:1; /* Channel 66 Normal Sampling Enable */ 6557 uint32_t CH65:1; /* Channel 65 Normal Sampling Enable */ 6558 uint32_t CH64:1; /* Channel 64 Normal Sampling Enable */ 6559 } B; 6560 } ADC_NCMR2_32B_tag; 6561 6562 typedef union { /* Injected Conversion Mask Register 0 */ 6563 uint32_t R; 6564 struct { 6565 uint32_t CH31:1; /* Channel 31 Injected Sampling Enable */ 6566 uint32_t CH30:1; /* Channel 30 Injected Sampling Enable */ 6567 uint32_t CH29:1; /* Channel 29 Injected Sampling Enable */ 6568 uint32_t CH28:1; /* Channel 28 Injected Sampling Enable */ 6569 uint32_t CH27:1; /* Channel 27 Injected Sampling Enable */ 6570 uint32_t CH26:1; /* Channel 26 Injected Sampling Enable */ 6571 uint32_t CH25:1; /* Channel 25 Injected Sampling Enable */ 6572 uint32_t CH24:1; /* Channel 24 Injected Sampling Enable */ 6573 uint32_t CH23:1; /* Channel 23 Injected Sampling Enable */ 6574 uint32_t CH22:1; /* Channel 22 Injected Sampling Enable */ 6575 uint32_t CH21:1; /* Channel 21 Injected Sampling Enable */ 6576 uint32_t CH20:1; /* Channel 20 Injected Sampling Enable */ 6577 uint32_t CH19:1; /* Channel 19 Injected Sampling Enable */ 6578 uint32_t CH18:1; /* Channel 18 Injected Sampling Enable */ 6579 uint32_t CH17:1; /* Channel 17 Injected Sampling Enable */ 6580 uint32_t CH16:1; /* Channel 16 Injected Sampling Enable */ 6581 uint32_t CH15:1; /* Channel 15 Injected Sampling Enable */ 6582 uint32_t CH14:1; /* Channel 14 Injected Sampling Enable */ 6583 uint32_t CH13:1; /* Channel 13 Injected Sampling Enable */ 6584 uint32_t CH12:1; /* Channel 12 Injected Sampling Enable */ 6585 uint32_t CH11:1; /* Channel 11 Injected Sampling Enable */ 6586 uint32_t CH10:1; /* Channel 10 Injected Sampling Enable */ 6587 uint32_t CH9:1; /* Channel 9 Injected Sampling Enable */ 6588 uint32_t CH8:1; /* Channel 8 Injected Sampling Enable */ 6589 uint32_t CH7:1; /* Channel 7 Injected Sampling Enable */ 6590 uint32_t CH6:1; /* Channel 6 Injected Sampling Enable */ 6591 uint32_t CH5:1; /* Channel 5 Injected Sampling Enable */ 6592 uint32_t CH4:1; /* Channel 4 Injected Sampling Enable */ 6593 uint32_t CH3:1; /* Channel 3 Injected Sampling Enable */ 6594 uint32_t CH2:1; /* Channel 2 Injected Sampling Enable */ 6595 uint32_t CH1:1; /* Channel 1 injected Sampling Enable */ 6596 uint32_t CH0:1; /* Channel 0 injected Sampling Enable */ 6597 } B; 6598 } ADC_JCMR0_32B_tag; 6599 6600 typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */ 6601 uint32_t R; 6602 struct { 6603 uint32_t CH63:1; /* Channel 63 Injected Sampling Enable */ 6604 uint32_t CH62:1; /* Channel 62 Injected Sampling Enable */ 6605 uint32_t CH61:1; /* Channel 61 Injected Sampling Enable */ 6606 uint32_t CH60:1; /* Channel 60 Injected Sampling Enable */ 6607 uint32_t CH59:1; /* Channel 59 Injected Sampling Enable */ 6608 uint32_t CH58:1; /* Channel 58 Injected Sampling Enable */ 6609 uint32_t CH57:1; /* Channel 57 Injected Sampling Enable */ 6610 uint32_t CH56:1; /* Channel 56 Injected Sampling Enable */ 6611 uint32_t CH55:1; /* Channel 55 Injected Sampling Enable */ 6612 uint32_t CH54:1; /* Channel 54 Injected Sampling Enable */ 6613 uint32_t CH53:1; /* Channel 53 Injected Sampling Enable */ 6614 uint32_t CH52:1; /* Channel 52 Injected Sampling Enable */ 6615 uint32_t CH51:1; /* Channel 51 Injected Sampling Enable */ 6616 uint32_t CH50:1; /* Channel 50 Injected Sampling Enable */ 6617 uint32_t CH49:1; /* Channel 49 Injected Sampling Enable */ 6618 uint32_t CH48:1; /* Channel 48 Injected Sampling Enable */ 6619 uint32_t CH47:1; /* Channel 47 Injected Sampling Enable */ 6620 uint32_t CH46:1; /* Channel 46 Injected Sampling Enable */ 6621 uint32_t CH45:1; /* Channel 45 Injected Sampling Enable */ 6622 uint32_t CH44:1; /* Channel 44 Injected Sampling Enable */ 6623 uint32_t CH43:1; /* Channel 43 Injected Sampling Enable */ 6624 uint32_t CH42:1; /* Channel 42 Injected Sampling Enable */ 6625 uint32_t CH41:1; /* Channel 41 Injected Sampling Enable */ 6626 uint32_t CH40:1; /* Channel 40 Injected Sampling Enable */ 6627 uint32_t CH39:1; /* Channel 39 Injected Sampling Enable */ 6628 uint32_t CH38:1; /* Channel 38 Injected Sampling Enable */ 6629 uint32_t CH37:1; /* Channel 37 Injected Sampling Enable */ 6630 uint32_t CH36:1; /* Channel 36 Injected Sampling Enable */ 6631 uint32_t CH35:1; /* Channel 35 Injected Sampling Enable */ 6632 uint32_t CH34:1; /* Channel 34 Injected Sampling Enable */ 6633 uint32_t CH33:1; /* Channel 33 Injected Sampling Enable */ 6634 uint32_t CH32:1; /* Channel 32 Injected Sampling Enable */ 6635 } B; 6636 } ADC_JCMR1_32B_tag; 6637 6638 typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */ 6639 uint32_t R; 6640 struct { 6641 uint32_t CH95:1; /* Channel 95 Injected Sampling Enable */ 6642 uint32_t CH94:1; /* Channel 94 Injected Sampling Enable */ 6643 uint32_t CH93:1; /* Channel 93 Injected Sampling Enable */ 6644 uint32_t CH92:1; /* Channel 92 Injected Sampling Enable */ 6645 uint32_t CH91:1; /* Channel 91 Injected Sampling Enable */ 6646 uint32_t CH90:1; /* Channel 90 Injected Sampling Enable */ 6647 uint32_t CH89:1; /* Channel 89 Injected Sampling Enable */ 6648 uint32_t CH88:1; /* Channel 88 Injected Sampling Enable */ 6649 uint32_t CH87:1; /* Channel 87 Injected Sampling Enable */ 6650 uint32_t CH86:1; /* Channel 86 Injected Sampling Enable */ 6651 uint32_t CH85:1; /* Channel 85 Injected Sampling Enable */ 6652 uint32_t CH84:1; /* Channel 84 Injected Sampling Enable */ 6653 uint32_t CH83:1; /* Channel 83 Injected Sampling Enable */ 6654 uint32_t CH82:1; /* Channel 82 Injected Sampling Enable */ 6655 uint32_t CH81:1; /* Channel 81 Injected Sampling Enable */ 6656 uint32_t CH80:1; /* Channel 80 Injected Sampling Enable */ 6657 uint32_t CH79:1; /* Channel 79 Injected Sampling Enable */ 6658 uint32_t CH78:1; /* Channel 78 Injected Sampling Enable */ 6659 uint32_t CH77:1; /* Channel 77 Injected Sampling Enable */ 6660 uint32_t CH76:1; /* Channel 76 Injected Sampling Enable */ 6661 uint32_t CH75:1; /* Channel 75 Injected Sampling Enable */ 6662 uint32_t CH74:1; /* Channel 74 Injected Sampling Enable */ 6663 uint32_t CH73:1; /* Channel 73 Injected Sampling Enable */ 6664 uint32_t CH72:1; /* Channel 72 Injected Sampling Enable */ 6665 uint32_t CH71:1; /* Channel 71 Injected Sampling Enable */ 6666 uint32_t CH70:1; /* Channel 70 Injected Sampling Enable */ 6667 uint32_t CH69:1; /* Channel 69 Injected Sampling Enable */ 6668 uint32_t CH68:1; /* Channel 68 Injected Sampling Enable */ 6669 uint32_t CH67:1; /* Channel 67 Injected Sampling Enable */ 6670 uint32_t CH66:1; /* Channel 66 Injected Sampling Enable */ 6671 uint32_t CH65:1; /* Channel 65 Injected Sampling Enable */ 6672 uint32_t CH64:1; /* Channel 64 Injected Sampling Enable */ 6673 } B; 6674 } ADC_JCMR2_32B_tag; 6675 6676 typedef union { /* Offset Word Regsiter */ 6677 uint32_t R; 6678 struct { 6679 uint32_t:15; 6680 uint32_t OFFSETLOAD:1; /* load_offset */ 6681 uint32_t:8; 6682 #ifndef USE_FIELD_ALIASES_ADC 6683 uint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */ 6684 #else 6685 uint32_t OFFSETWORD:8; 6686 #endif 6687 } B; 6688 } ADC_OFFWR_32B_tag; 6689 6690 typedef union { /* Decode Signal Delay Register */ 6691 uint32_t R; 6692 struct { 6693 uint32_t:24; 6694 uint32_t DSD:8; /* take into account the settling time of the external mux */ 6695 } B; 6696 } ADC_DSDR_32B_tag; 6697 6698 typedef union { /* Power Down Dealy Register */ 6699 uint32_t R; 6700 struct { 6701 uint32_t:24; 6702 uint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */ 6703 } B; 6704 } ADC_PDEDR_32B_tag; 6705 6706 6707 /* Register layout for all registers CDR... */ 6708 6709 typedef union { /* CHANNEL DATA REGS */ 6710 uint32_t R; 6711 struct { 6712 uint32_t:12; 6713 uint32_t VALID:1; /* validity of data */ 6714 uint32_t OVERW:1; /* overwrite data */ 6715 uint32_t RESULT:2; /* reflects mode conversion */ 6716 uint32_t:6; 6717 uint32_t CDATA:10; /* Channel 0 converted data */ 6718 } B; 6719 } ADC_CDR_32B_tag; 6720 6721 typedef union { /* Upper Threshold register 4 is not contiguous to 3 */ 6722 uint32_t R; 6723 struct { 6724 uint32_t:4; 6725 uint32_t THRH:12; /* high threshold value s */ 6726 uint32_t:4; 6727 uint32_t THRL:12; /* low threshold value s */ 6728 } B; 6729 } ADC_THRHLR4_32B_tag; 6730 6731 typedef union { /* Upper Threshold register 5 */ 6732 uint32_t R; 6733 struct { 6734 uint32_t:4; 6735 uint32_t THRH:12; /* high threshold value s */ 6736 uint32_t:4; 6737 uint32_t THRL:12; /* low threshold value s */ 6738 } B; 6739 } ADC_THRHLR5_32B_tag; 6740 6741 typedef union { /* Upper Threshold register 6 */ 6742 uint32_t R; 6743 struct { 6744 uint32_t:4; 6745 uint32_t THRH:12; /* high threshold value s */ 6746 uint32_t:4; 6747 uint32_t THRL:12; /* low threshold value s */ 6748 } B; 6749 } ADC_THRHLR6_32B_tag; 6750 6751 typedef union { /* Upper Threshold register 7 */ 6752 uint32_t R; 6753 struct { 6754 uint32_t:4; 6755 uint32_t THRH:12; /* high threshold value s */ 6756 uint32_t:4; 6757 uint32_t THRL:12; /* low threshold value s */ 6758 } B; 6759 } ADC_THRHLR7_32B_tag; 6760 6761 typedef union { /* Upper Threshold register 8 */ 6762 uint32_t R; 6763 struct { 6764 uint32_t:4; 6765 uint32_t THRH:12; /* high threshold value s */ 6766 uint32_t:4; 6767 uint32_t THRL:12; /* low threshold value s */ 6768 } B; 6769 } ADC_THRHLR8_32B_tag; 6770 6771 typedef union { /* Upper Threshold register 9 */ 6772 uint32_t R; 6773 struct { 6774 uint32_t:4; 6775 uint32_t THRH:12; /* high threshold value s */ 6776 uint32_t:4; 6777 uint32_t THRL:12; /* low threshold value s */ 6778 } B; 6779 } ADC_THRHLR9_32B_tag; 6780 6781 typedef union { /* Upper Threshold register 10 */ 6782 uint32_t R; 6783 struct { 6784 uint32_t:4; 6785 uint32_t THRH:12; /* high threshold value s */ 6786 uint32_t:4; 6787 uint32_t THRL:12; /* low threshold value s */ 6788 } B; 6789 } ADC_THRHLR10_32B_tag; 6790 6791 typedef union { /* Upper Threshold register 11 */ 6792 uint32_t R; 6793 struct { 6794 uint32_t:4; 6795 uint32_t THRH:12; /* high threshold value s */ 6796 uint32_t:4; 6797 uint32_t THRL:12; /* low threshold value s */ 6798 } B; 6799 } ADC_THRHLR11_32B_tag; 6800 6801 typedef union { /* Upper Threshold register 12 */ 6802 uint32_t R; 6803 struct { 6804 uint32_t:4; 6805 uint32_t THRH:12; /* high threshold value s */ 6806 uint32_t:4; 6807 uint32_t THRL:12; /* low threshold value s */ 6808 } B; 6809 } ADC_THRHLR12_32B_tag; 6810 6811 typedef union { /* Upper Threshold register 13 */ 6812 uint32_t R; 6813 struct { 6814 uint32_t:4; 6815 uint32_t THRH:12; /* high threshold value s */ 6816 uint32_t:4; 6817 uint32_t THRL:12; /* low threshold value s */ 6818 } B; 6819 } ADC_THRHLR13_32B_tag; 6820 6821 typedef union { /* Upper Threshold register 14 */ 6822 uint32_t R; 6823 struct { 6824 uint32_t:4; 6825 uint32_t THRH:12; /* high threshold value s */ 6826 uint32_t:4; 6827 uint32_t THRL:12; /* low threshold value s */ 6828 } B; 6829 } ADC_THRHLR14_32B_tag; 6830 6831 typedef union { /* Upper Threshold register 15 */ 6832 uint32_t R; 6833 struct { 6834 uint32_t:4; 6835 uint32_t THRH:12; /* high threshold value s */ 6836 uint32_t:4; 6837 uint32_t THRL:12; /* low threshold value s */ 6838 } B; 6839 } ADC_THRHLR15_32B_tag; 6840 6841 6842 /* Register layout for all registers CWSELR... */ 6843 6844 typedef union { /* Channel Watchdog Select register */ 6845 uint32_t R; 6846 struct { 6847 uint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */ 6848 uint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */ 6849 uint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */ 6850 uint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */ 6851 uint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */ 6852 uint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */ 6853 uint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */ 6854 uint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */ 6855 } B; 6856 } ADC_CWSELR_32B_tag; 6857 6858 6859 /* Register layout for all registers CWENR... */ 6860 6861 typedef union { /* Channel Watchdog Enable Register */ 6862 uint32_t R; 6863 struct { 6864 uint32_t:16; 6865 uint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6866 uint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6867 uint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6868 uint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6869 uint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6870 uint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6871 uint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6872 uint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6873 uint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6874 uint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6875 uint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6876 uint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6877 uint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6878 uint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6879 uint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6880 uint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */ 6881 } B; 6882 } ADC_CWENR_32B_tag; 6883 6884 6885 /* Register layout for all registers AWORR... */ 6886 6887 typedef union { /* Analog Watchdog Out of Range Register */ 6888 uint32_t R; 6889 struct { 6890 uint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */ 6891 uint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */ 6892 uint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */ 6893 uint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */ 6894 uint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */ 6895 uint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */ 6896 uint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */ 6897 uint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */ 6898 uint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */ 6899 uint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */ 6900 uint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */ 6901 uint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */ 6902 uint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */ 6903 uint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */ 6904 uint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */ 6905 uint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */ 6906 uint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */ 6907 uint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */ 6908 uint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */ 6909 uint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */ 6910 uint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */ 6911 uint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */ 6912 uint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */ 6913 uint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */ 6914 uint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */ 6915 uint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */ 6916 uint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */ 6917 uint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */ 6918 uint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */ 6919 uint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */ 6920 uint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */ 6921 uint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */ 6922 } B; 6923 } ADC_AWORR_32B_tag; 6924 6925 typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */ 6926 uint32_t R; 6927 struct { 6928 uint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */ 6929 uint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */ 6930 uint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */ 6931 uint32_t:5; 6932 uint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */ 6933 uint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */ 6934 } B; 6935 } ADC_STCR1_32B_tag; 6936 6937 typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */ 6938 uint32_t R; 6939 struct { 6940 uint32_t:5; 6941 uint32_t SERR:1; /* Error fault injection bit (write only) */ 6942 uint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */ 6943 uint32_t:1; 6944 uint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */ 6945 uint32_t:4; 6946 uint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */ 6947 uint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */ 6948 uint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */ 6949 uint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */ 6950 uint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */ 6951 uint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */ 6952 uint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */ 6953 uint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */ 6954 uint32_t:3; 6955 uint32_t EN:1; /* Self testing channel enable */ 6956 uint32_t:4; 6957 uint32_t FMA_C:1; /* Fault mapping for the algorithm C */ 6958 uint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */ 6959 uint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */ 6960 } B; 6961 } ADC_STCR2_32B_tag; 6962 6963 typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */ 6964 uint32_t R; 6965 struct { 6966 uint32_t:22; 6967 uint32_t ALG:2; /* Algorithm scheduling */ 6968 uint32_t:8; 6969 } B; 6970 } ADC_STCR3_32B_tag; 6971 6972 typedef union { /* SELF TEST BAUD RATE REGISTER */ 6973 uint32_t R; 6974 struct { 6975 uint32_t:13; 6976 uint32_t WDT:3; /* Watchdog timer value */ 6977 uint32_t:8; 6978 uint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */ 6979 } B; 6980 } ADC_STBRR_32B_tag; 6981 6982 typedef union { /* SELF TEST STATUS REGISTER 1 */ 6983 uint32_t R; 6984 struct { 6985 uint32_t:6; 6986 uint32_t WDTERR:1; /* Watchdog timer error */ 6987 uint32_t OVERWR:1; /* Overwrite error */ 6988 uint32_t ST_EOC:1; /* Self test EOC bit */ 6989 uint32_t:4; 6990 uint32_t WDG_EOA_C:1; /* Algorithm C completed without error */ 6991 uint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */ 6992 uint32_t WDG_EOA_S:1; /* Algorithm S completed without error */ 6993 uint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */ 6994 uint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */ 6995 uint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */ 6996 uint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */ 6997 uint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */ 6998 uint32_t:1; 6999 uint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */ 7000 uint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */ 7001 } B; 7002 } ADC_STSR1_32B_tag; 7003 7004 typedef union { /* SELF TEST STATUS REGISTER 2 */ 7005 uint32_t R; 7006 struct { 7007 uint32_t OVFL:1; /* Overflow bit */ 7008 uint32_t:3; 7009 uint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */ 7010 uint32_t:4; 7011 uint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */ 7012 } B; 7013 } ADC_STSR2_32B_tag; 7014 7015 typedef union { /* SELF TEST STATUS REGISTER 3 */ 7016 uint32_t R; 7017 struct { 7018 uint32_t:4; 7019 uint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */ 7020 uint32_t:4; 7021 uint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */ 7022 } B; 7023 } ADC_STSR3_32B_tag; 7024 7025 typedef union { /* SELF TEST STATUS REGISTER 4 */ 7026 uint32_t R; 7027 struct { 7028 uint32_t:4; 7029 uint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */ 7030 uint32_t:4; 7031 uint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */ 7032 } B; 7033 } ADC_STSR4_32B_tag; 7034 7035 typedef union { /* SELF TEST DATA REGISTER 1 */ 7036 uint32_t R; 7037 struct { 7038 uint32_t:12; 7039 uint32_t VALID:1; /* Valid data */ 7040 uint32_t OVERWR:1; /* Overwrite data */ 7041 uint32_t:6; 7042 uint32_t TCDATA:12; /* Test channel converted data */ 7043 } B; 7044 } ADC_STDR1_32B_tag; 7045 7046 typedef union { /* SELF TEST DATA REGISTER 2 */ 7047 uint32_t R; 7048 struct { 7049 uint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */ 7050 uint32_t VALID:1; /* Valid data */ 7051 uint32_t OVERWR:1; /* Overwrite data */ 7052 uint32_t:6; 7053 uint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */ 7054 } B; 7055 } ADC_STDR2_32B_tag; 7056 7057 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ 7058 uint32_t R; 7059 struct { 7060 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ 7061 uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */ 7062 uint32_t:2; 7063 uint32_t THRH:12; /* High threshold value for channel 0 */ 7064 uint32_t:4; 7065 uint32_t THRL:12; /* Low threshold value for channel 0 */ 7066 } B; 7067 } ADC_STAW0R_32B_tag; 7068 7069 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ 7070 uint32_t R; 7071 struct { 7072 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ 7073 uint32_t:3; 7074 uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ 7075 uint32_t:4; 7076 uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ 7077 } B; 7078 } ADC_STAW1AR_32B_tag; 7079 7080 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ 7081 uint32_t R; 7082 struct { 7083 uint32_t:4; 7084 uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ 7085 uint32_t:4; 7086 uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ 7087 } B; 7088 } ADC_STAW1BR_32B_tag; 7089 7090 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ 7091 uint32_t R; 7092 struct { 7093 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ 7094 uint32_t:19; 7095 uint32_t THRL:12; /* Low threshold value for channel */ 7096 } B; 7097 } ADC_STAW2R_32B_tag; 7098 7099 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ 7100 uint32_t R; 7101 struct { 7102 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */ 7103 uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */ 7104 uint32_t:2; 7105 uint32_t THRH:12; /* High threshold value for channel 3 */ 7106 uint32_t:4; 7107 uint32_t THRL:12; /* Low threshold value for channel 3 */ 7108 } B; 7109 } ADC_STAW3R_32B_tag; 7110 7111 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ 7112 uint32_t R; 7113 struct { 7114 uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */ 7115 uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */ 7116 uint32_t:2; 7117 uint32_t THRH:12; /* High threshold value for channel 4 */ 7118 uint32_t:4; 7119 uint32_t THRL:12; /* Low threshold value for channel 4 */ 7120 } B; 7121 } ADC_STAW4R_32B_tag; 7122 7123 typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ 7124 uint32_t R; 7125 struct { 7126 uint32_t:4; 7127 uint32_t THRH:12; /* High threshold value for algorithm C */ 7128 uint32_t:4; 7129 uint32_t THRL:12; /* Low threshold value for algorithm C */ 7130 } B; 7131 } ADC_STAW5R_32B_tag; 7132 7133 7134 7135 typedef struct ADC_struct_tag { /* start of ADC_tag */ 7136 /* module configuration register */ 7137 ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ 7138 /* module status register */ 7139 ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */ 7140 int8_t ADC_reserved_0008[8]; 7141 /* Interrupt status register */ 7142 ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ 7143 union { 7144 ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */ 7145 7146 struct { 7147 /* CHANNEL PENDING REGISTER 0 */ 7148 ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */ 7149 /* CHANNEL PENDING REGISTER 1 */ 7150 ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */ 7151 /* CHANNEL PENDING REGISTER 2 */ 7152 ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */ 7153 }; 7154 7155 }; 7156 /* interrupt mask register */ 7157 ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */ 7158 union { 7159 ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */ 7160 7161 struct { 7162 /* CHANNEL INTERRUPT MASK REGISTER 0 */ 7163 ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */ 7164 /* CHANNEL INTERRUPT MASK REGISTER 1 */ 7165 ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */ 7166 /* CHANNEL INTERRUPT MASK REGISTER 2 */ 7167 ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */ 7168 }; 7169 7170 }; 7171 /* Watchdog Threshold interrupt status register */ 7172 ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */ 7173 /* Watchdog interrupt MASK register */ 7174 ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */ 7175 int8_t ADC_reserved_0038[8]; 7176 /* DMAE register */ 7177 ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */ 7178 union { 7179 ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */ 7180 7181 struct { 7182 /* DMA REGISTER 0 */ 7183 ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */ 7184 /* DMA REGISTER 1 */ 7185 ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */ 7186 /* DMA REGISTER 2 */ 7187 ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */ 7188 }; 7189 7190 }; 7191 union { 7192 /* Threshold Control register C */ 7193 ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */ 7194 7195 struct { 7196 /* Threshold Control register C */ 7197 ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */ 7198 ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */ 7199 ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */ 7200 ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */ 7201 }; 7202 7203 }; 7204 union { 7205 /* Upper Threshold register */ 7206 ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */ 7207 7208 struct { 7209 /* Upper Threshold register */ 7210 ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */ 7211 ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */ 7212 ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */ 7213 ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */ 7214 }; 7215 7216 }; 7217 union { 7218 /* alternate Upper Threshold register */ 7219 ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */ 7220 7221 struct { 7222 /* alternate Upper Threshold register */ 7223 ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */ 7224 ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */ 7225 ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */ 7226 ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */ 7227 }; 7228 7229 }; 7230 /* PRESAMPLING CONTROL REGISTER */ 7231 ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */ 7232 union { 7233 ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */ 7234 7235 struct { 7236 /* Presampling Register 0 */ 7237 ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */ 7238 /* Presampling REGISTER 1 */ 7239 ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */ 7240 /* Presampling REGISTER 2 */ 7241 ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */ 7242 }; 7243 7244 }; 7245 int8_t ADC_reserved_0090_C[4]; 7246 union { 7247 /* conversion timing register */ 7248 ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */ 7249 7250 struct { 7251 /* conversion timing register */ 7252 ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */ 7253 ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */ 7254 ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */ 7255 }; 7256 7257 }; 7258 int8_t ADC_reserved_00A0_C[4]; 7259 union { 7260 ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */ 7261 7262 struct { 7263 /* NORMAL CONVERSION MASK REGISTER 0 */ 7264 ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */ 7265 /* NORMAL CONVERSION MASK REGISTER 1 */ 7266 ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */ 7267 /* NORMAL CONVERSION MASK REGISTER 2 */ 7268 ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */ 7269 }; 7270 7271 }; 7272 int8_t ADC_reserved_00B0_C[4]; 7273 union { 7274 ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */ 7275 7276 struct { 7277 /* Injected Conversion Mask Register 0 */ 7278 ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */ 7279 /* INJECTED CONVERSION MASK REGISTER 1 */ 7280 ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */ 7281 /* INJECTED CONVERSION MASK REGISTER 2 */ 7282 ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */ 7283 }; 7284 7285 }; 7286 /* Offset Word Regsiter */ 7287 ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */ 7288 /* Decode Signal Delay Register */ 7289 ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */ 7290 /* Power Down Dealy Register */ 7291 ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */ 7292 int8_t ADC_reserved_00CC_C[52]; 7293 union { 7294 /* CHANNEL DATA REGS */ 7295 ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */ 7296 7297 struct { 7298 /* CHANNEL DATA REGS */ 7299 ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */ 7300 ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */ 7301 ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */ 7302 ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */ 7303 ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */ 7304 ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */ 7305 ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */ 7306 ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */ 7307 ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */ 7308 ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */ 7309 ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */ 7310 ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */ 7311 ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */ 7312 ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */ 7313 ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */ 7314 ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */ 7315 ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */ 7316 ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */ 7317 ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */ 7318 ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */ 7319 ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */ 7320 ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */ 7321 ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */ 7322 ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */ 7323 ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */ 7324 ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */ 7325 ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */ 7326 ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */ 7327 ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */ 7328 ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */ 7329 ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */ 7330 ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */ 7331 ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */ 7332 ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */ 7333 ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */ 7334 ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */ 7335 ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */ 7336 ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */ 7337 ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */ 7338 ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */ 7339 ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */ 7340 ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */ 7341 ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */ 7342 ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */ 7343 ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */ 7344 ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */ 7345 ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */ 7346 ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */ 7347 ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */ 7348 ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */ 7349 ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */ 7350 ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */ 7351 ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */ 7352 ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */ 7353 ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */ 7354 ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */ 7355 ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */ 7356 ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */ 7357 ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */ 7358 ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */ 7359 ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */ 7360 ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */ 7361 ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */ 7362 ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */ 7363 ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */ 7364 ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */ 7365 ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */ 7366 ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */ 7367 ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */ 7368 ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */ 7369 ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */ 7370 ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */ 7371 ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */ 7372 ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */ 7373 ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */ 7374 ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */ 7375 ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */ 7376 ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */ 7377 ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */ 7378 ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */ 7379 ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */ 7380 ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */ 7381 ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */ 7382 ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */ 7383 ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */ 7384 ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */ 7385 ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */ 7386 ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */ 7387 ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */ 7388 ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */ 7389 ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */ 7390 ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */ 7391 ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */ 7392 ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */ 7393 ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */ 7394 ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */ 7395 }; 7396 7397 }; 7398 /* Upper Threshold register 4 is not contiguous to 3 */ 7399 ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */ 7400 /* Upper Threshold register 5 */ 7401 ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */ 7402 /* Upper Threshold register 6 */ 7403 ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */ 7404 /* Upper Threshold register 7 */ 7405 ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */ 7406 /* Upper Threshold register 8 */ 7407 ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */ 7408 /* Upper Threshold register 9 */ 7409 ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */ 7410 /* Upper Threshold register 10 */ 7411 ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */ 7412 /* Upper Threshold register 11 */ 7413 ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */ 7414 /* Upper Threshold register 12 */ 7415 ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */ 7416 /* Upper Threshold register 13 */ 7417 ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */ 7418 /* Upper Threshold register 14 */ 7419 ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */ 7420 /* Upper Threshold register 15 */ 7421 ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */ 7422 union { 7423 /* Channel Watchdog Select register */ 7424 ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */ 7425 7426 struct { 7427 /* Channel Watchdog Select register */ 7428 ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */ 7429 ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */ 7430 ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */ 7431 ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */ 7432 ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */ 7433 ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */ 7434 ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */ 7435 ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */ 7436 ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */ 7437 ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */ 7438 ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */ 7439 ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */ 7440 }; 7441 7442 }; 7443 union { 7444 /* Channel Watchdog Enable Register */ 7445 ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */ 7446 7447 struct { 7448 /* Channel Watchdog Enable Register */ 7449 ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */ 7450 ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */ 7451 ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */ 7452 }; 7453 7454 }; 7455 int8_t ADC_reserved_02EC_C[4]; 7456 union { 7457 /* Analog Watchdog Out of Range Register */ 7458 ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */ 7459 7460 struct { 7461 /* Analog Watchdog Out of Range Register */ 7462 ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */ 7463 ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */ 7464 ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */ 7465 }; 7466 7467 }; 7468 int8_t ADC_reserved_02FC[68]; 7469 /* SELF TEST CONFIGURATION REGISTER 1 */ 7470 ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */ 7471 /* SELF TEST CONFIGURATION REGISTER 2 */ 7472 ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */ 7473 /* SELF TEST CONFIGURATION REGISTER 3 */ 7474 ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */ 7475 /* SELF TEST BAUD RATE REGISTER */ 7476 ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */ 7477 /* SELF TEST STATUS REGISTER 1 */ 7478 ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */ 7479 /* SELF TEST STATUS REGISTER 2 */ 7480 ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */ 7481 /* SELF TEST STATUS REGISTER 3 */ 7482 ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */ 7483 /* SELF TEST STATUS REGISTER 4 */ 7484 ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */ 7485 int8_t ADC_reserved_0360[16]; 7486 /* SELF TEST DATA REGISTER 1 */ 7487 ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */ 7488 /* SELF TEST DATA REGISTER 2 */ 7489 ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */ 7490 int8_t ADC_reserved_0378[8]; 7491 /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ 7492 ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */ 7493 /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ 7494 ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */ 7495 /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ 7496 ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */ 7497 /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ 7498 ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */ 7499 /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ 7500 ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */ 7501 /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ 7502 ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */ 7503 /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ 7504 ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */ 7505 } ADC_tag; 7506 7507 7508 #define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL) 7509 #define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL) 7510 7511 7512 7513 /****************************************************************/ 7514 /* */ 7515 /* Module: CTU */ 7516 /* */ 7517 /****************************************************************/ 7518 7519 typedef union { /* Trigger Generator Subunit Input Selection register */ 7520 uint32_t R; 7521 struct { 7522 uint32_t I15_FE:1; /* ext_signal Falling Edge */ 7523 uint32_t I15_RE:1; /* ext_signal Rising Edge */ 7524 uint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */ 7525 uint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */ 7526 uint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */ 7527 uint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */ 7528 uint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */ 7529 uint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */ 7530 uint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */ 7531 uint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */ 7532 uint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */ 7533 uint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */ 7534 uint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */ 7535 uint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */ 7536 uint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */ 7537 uint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */ 7538 uint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */ 7539 uint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */ 7540 uint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */ 7541 uint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */ 7542 uint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */ 7543 uint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */ 7544 uint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */ 7545 uint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */ 7546 uint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */ 7547 uint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */ 7548 uint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */ 7549 uint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */ 7550 uint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */ 7551 uint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */ 7552 uint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */ 7553 uint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */ 7554 } B; 7555 } CTU_TGSISR_32B_tag; 7556 7557 typedef union { /* Trigger Generator Subunit Control Register */ 7558 uint16_t R; 7559 struct { 7560 uint16_t:7; 7561 #ifndef USE_FIELD_ALIASES_CTU 7562 uint16_t ET_TM:1; /* Toggle Mode Enable */ 7563 #else 7564 uint16_t ETTM:1; /* deprecated name - please avoid */ 7565 #endif 7566 uint16_t PRES:2; /* TGS Prescaler Selection */ 7567 #ifndef USE_FIELD_ALIASES_CTU 7568 uint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */ 7569 #else 7570 uint16_t MRSSM:5; /* deprecated name - please avoid */ 7571 #endif 7572 #ifndef USE_FIELD_ALIASES_CTU 7573 uint16_t TGS_M:1; /* Trigger Generator Subunit Mode */ 7574 #else 7575 uint16_t TGSM:1; /* deprecated name - please avoid */ 7576 #endif 7577 } B; 7578 } CTU_TGSCR_16B_tag; 7579 7580 typedef union { /* */ 7581 uint16_t R; 7582 } CTU_TCR_16B_tag; 7583 7584 typedef union { /* TGS Counter Compare Register */ 7585 uint16_t R; 7586 #ifndef USE_FIELD_ALIASES_CTU 7587 struct { 7588 uint16_t TGSCCV:16; /* deprecated field -- do not use */ 7589 } B; 7590 #endif 7591 } CTU_TGSCCR_16B_tag; 7592 7593 typedef union { /* TGS Counter Reload Register */ 7594 uint16_t R; 7595 #ifndef USE_FIELD_ALIASES_CTU 7596 struct { 7597 uint16_t TGSCRV:16; /* deprecated field -- do not use */ 7598 } B; 7599 #endif 7600 } CTU_TGSCRR_16B_tag; 7601 7602 typedef union { /* Commands List Control Register 1 */ 7603 uint32_t R; 7604 struct { 7605 uint32_t:3; 7606 uint32_t T3INDEX:5; /* Trigger 3 First Command address */ 7607 uint32_t:3; 7608 uint32_t T2INDEX:5; /* Trigger 2 First Command address */ 7609 uint32_t:3; 7610 uint32_t T1INDEX:5; /* Trigger 1 First Command address */ 7611 uint32_t:3; 7612 uint32_t T0INDEX:5; /* Trigger 0 First Command address */ 7613 } B; 7614 } CTU_CLCR1_32B_tag; 7615 7616 typedef union { /* Commands List Control Register 2 */ 7617 uint32_t R; 7618 struct { 7619 uint32_t:3; 7620 uint32_t T7INDEX:5; /* Trigger 7 First Command address */ 7621 uint32_t:3; 7622 uint32_t T6INDEX:5; /* Trigger 6 First Command address */ 7623 uint32_t:3; 7624 uint32_t T5INDEX:5; /* Trigger 5 First Command address */ 7625 uint32_t:3; 7626 uint32_t T4INDEX:5; /* Trigger 4 First Command address */ 7627 } B; 7628 } CTU_CLCR2_32B_tag; 7629 7630 typedef union { /* Trigger Handler Control Register 1 */ 7631 uint32_t R; 7632 struct { 7633 uint32_t:1; 7634 uint32_t T3_E:1; /* Trigger 3 enable */ 7635 uint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */ 7636 uint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */ 7637 uint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */ 7638 uint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */ 7639 uint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */ 7640 uint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */ 7641 uint32_t:1; 7642 uint32_t T2_E:1; /* Trigger 2 enable */ 7643 uint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */ 7644 uint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */ 7645 uint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */ 7646 uint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */ 7647 uint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */ 7648 uint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */ 7649 uint32_t:1; 7650 uint32_t T1_E:1; /* Trigger 1 enable */ 7651 uint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */ 7652 uint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */ 7653 uint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */ 7654 uint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */ 7655 uint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */ 7656 uint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */ 7657 uint32_t:1; 7658 uint32_t T0_E:1; /* Trigger 0 enable */ 7659 uint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */ 7660 uint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */ 7661 uint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */ 7662 uint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */ 7663 uint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */ 7664 uint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */ 7665 } B; 7666 } CTU_THCR1_32B_tag; 7667 7668 typedef union { /* Trigger Handler Control Register 2 */ 7669 uint32_t R; 7670 struct { 7671 uint32_t:1; 7672 uint32_t T7_E:1; /* Trigger 7 enable */ 7673 uint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */ 7674 uint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */ 7675 uint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */ 7676 uint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */ 7677 uint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */ 7678 uint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */ 7679 uint32_t:1; 7680 uint32_t T6_E:1; /* Trigger 6 enable */ 7681 uint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */ 7682 uint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */ 7683 uint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */ 7684 uint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */ 7685 uint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */ 7686 uint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */ 7687 uint32_t:1; 7688 uint32_t T5_E:1; /* Trigger 5 enable */ 7689 uint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */ 7690 uint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */ 7691 uint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */ 7692 uint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */ 7693 uint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */ 7694 uint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */ 7695 uint32_t:1; 7696 uint32_t T4_E:1; /* Trigger 4 enable */ 7697 uint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */ 7698 uint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */ 7699 uint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */ 7700 uint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */ 7701 uint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */ 7702 uint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */ 7703 } B; 7704 } CTU_THCR2_32B_tag; 7705 7706 7707 /* Register layout for all registers CLR_DCM... */ 7708 7709 typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ 7710 uint16_t R; 7711 struct { 7712 uint16_t CIR:1; /* Command Interrupt Request */ 7713 uint16_t LC:1; /* Last Command */ 7714 uint16_t CMS:1; /* Conversion Mode Selection */ 7715 uint16_t FIFO:3; /* FIFO for ADC A/B */ 7716 uint16_t:1; 7717 uint16_t CHB:4; /* ADC unit B channel number */ 7718 uint16_t:1; 7719 uint16_t CHA:4; /* ADC unit A channel number */ 7720 } B; 7721 } CTU_CLR_DCM_16B_tag; 7722 7723 7724 /* Register layout for all registers CLR_SCM... */ 7725 7726 typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ 7727 uint16_t R; 7728 struct { 7729 uint16_t CIR:1; /* Command Interrupt Request */ 7730 uint16_t LC:1; /* Last Command */ 7731 uint16_t CMS:1; /* Conversion Mode Selection */ 7732 uint16_t FIFO:3; /* FIFO for ADC A/B */ 7733 uint16_t:4; 7734 uint16_t SU:1; /* Selection ADC Unit */ 7735 uint16_t:1; 7736 uint16_t CH:4; /* ADC unit channel number */ 7737 } B; 7738 } CTU_CLR_SCM_16B_tag; 7739 7740 7741 /* Register layout for all registers CLR... */ 7742 7743 7744 typedef union { /* Control Register */ 7745 uint16_t R; 7746 struct { 7747 uint16_t EMPTY_CLR7:1; /* Empty Clear 7 */ 7748 uint16_t EMPTY_CLR6:1; /* Empty Clear 6 */ 7749 uint16_t EMPTY_CLR5:1; /* Empty Clear 5 */ 7750 uint16_t EMPTY_CLR4:1; /* Empty Clear 4 */ 7751 uint16_t EMPTY_CLR3:1; /* Empty Clear 3 */ 7752 uint16_t EMPTY_CLR2:1; /* Empty Clear 2 */ 7753 uint16_t EMPTY_CLR1:1; /* Empty Clear 1 */ 7754 uint16_t EMPTY_CLR0:1; /* Empty Clear 0 */ 7755 #ifndef USE_FIELD_ALIASES_CTU 7756 uint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */ 7757 #else 7758 uint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */ 7759 #endif 7760 #ifndef USE_FIELD_ALIASES_CTU 7761 uint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */ 7762 #else 7763 uint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */ 7764 #endif 7765 #ifndef USE_FIELD_ALIASES_CTU 7766 uint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */ 7767 #else 7768 uint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */ 7769 #endif 7770 #ifndef USE_FIELD_ALIASES_CTU 7771 uint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */ 7772 #else 7773 uint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */ 7774 #endif 7775 #ifndef USE_FIELD_ALIASES_CTU 7776 uint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */ 7777 #else 7778 uint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */ 7779 #endif 7780 #ifndef USE_FIELD_ALIASES_CTU 7781 uint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */ 7782 #else 7783 uint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */ 7784 #endif 7785 #ifndef USE_FIELD_ALIASES_CTU 7786 uint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */ 7787 #else 7788 uint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */ 7789 #endif 7790 #ifndef USE_FIELD_ALIASES_CTU 7791 uint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */ 7792 #else 7793 uint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */ 7794 #endif 7795 } B; 7796 } CTU_CR_16B_tag; 7797 7798 typedef union { /* Control Register FIFO */ 7799 uint32_t R; 7800 struct { 7801 uint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */ 7802 uint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */ 7803 uint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */ 7804 uint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */ 7805 uint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */ 7806 uint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */ 7807 uint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */ 7808 uint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */ 7809 uint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */ 7810 uint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */ 7811 uint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */ 7812 uint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */ 7813 uint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */ 7814 uint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */ 7815 uint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */ 7816 uint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */ 7817 uint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */ 7818 uint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */ 7819 uint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */ 7820 uint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */ 7821 uint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */ 7822 uint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */ 7823 uint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */ 7824 uint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */ 7825 uint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */ 7826 uint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */ 7827 uint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */ 7828 uint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */ 7829 uint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */ 7830 uint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */ 7831 uint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */ 7832 uint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */ 7833 } B; 7834 } CTU_FCR_32B_tag; 7835 7836 typedef union { /* Threshold 1 Register */ 7837 uint32_t R; 7838 struct { 7839 uint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */ 7840 uint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */ 7841 uint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */ 7842 uint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */ 7843 } B; 7844 } CTU_TH1_32B_tag; 7845 7846 typedef union { /* Threshold 2 Register */ 7847 uint32_t R; 7848 struct { 7849 uint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */ 7850 uint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */ 7851 uint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */ 7852 uint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */ 7853 } B; 7854 } CTU_TH2_32B_tag; 7855 7856 typedef union { /* Status Register */ 7857 uint32_t R; 7858 struct { 7859 uint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */ 7860 uint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */ 7861 uint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */ 7862 uint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */ 7863 uint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */ 7864 uint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */ 7865 uint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */ 7866 uint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */ 7867 uint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */ 7868 uint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */ 7869 uint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */ 7870 uint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */ 7871 uint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */ 7872 uint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */ 7873 uint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */ 7874 uint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */ 7875 uint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */ 7876 uint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */ 7877 uint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */ 7878 uint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */ 7879 uint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */ 7880 uint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */ 7881 uint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */ 7882 uint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */ 7883 uint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */ 7884 uint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */ 7885 uint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */ 7886 uint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */ 7887 uint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */ 7888 uint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */ 7889 uint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */ 7890 uint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */ 7891 } B; 7892 } CTU_STS_32B_tag; 7893 7894 7895 /* Register layout for all registers FR... */ 7896 7897 typedef union { /* FIFO Right Aligned register */ 7898 uint32_t R; 7899 struct { 7900 uint32_t:11; 7901 uint32_t ADC:1; /* ADC Unit */ 7902 uint32_t N_CH:4; /* Number Channel */ 7903 uint32_t:4; 7904 uint32_t DATA:12; /* Data Fifo */ 7905 } B; 7906 } CTU_FR_32B_tag; 7907 7908 7909 /* Register layout for all registers FL... */ 7910 7911 typedef union { /* FIFO Left Aligned register */ 7912 uint32_t R; 7913 struct { 7914 uint32_t:11; 7915 uint32_t ADC:1; /* ADC Unit */ 7916 uint32_t N_CH:4; /* Number Channel */ 7917 uint32_t:1; 7918 uint32_t DATA:12; /* Data Fifo */ 7919 uint32_t:3; 7920 } B; 7921 } CTU_FL_32B_tag; 7922 7923 typedef union { /* CTU Error Flag Register */ 7924 uint16_t R; 7925 struct { 7926 uint16_t:3; 7927 uint16_t CS:1; /* Counter Status */ 7928 uint16_t ET_OE:1; /* ExtTrigger Generation Overrun */ 7929 uint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */ 7930 uint16_t T4_OE:1; /* Timer4 Generation Overrun */ 7931 uint16_t T3_OE:1; /* Timer3 Generation Overrun */ 7932 uint16_t T2_OE:1; /* Timer2 Generation Overrun */ 7933 uint16_t T1_OE:1; /* Timer1 Generation Overrun */ 7934 #ifndef USE_FIELD_ALIASES_CTU 7935 uint16_t ADC_OE:1; /* ADC Command Generation Overrun */ 7936 #else 7937 uint16_t ADCOE:1; /* ADC Command Generation Overrun */ 7938 #endif 7939 #ifndef USE_FIELD_ALIASES_CTU 7940 uint16_t TGS_OSM:1; /* TGS Overrun */ 7941 #else 7942 uint16_t TGSOSM:1; /* TGS Overrun */ 7943 #endif 7944 #ifndef USE_FIELD_ALIASES_CTU 7945 uint16_t MRS_O:1; /* MRS Overrun */ 7946 #else 7947 uint16_t MRSO:1; /* TGS Overrun */ 7948 #endif 7949 uint16_t ICE:1; /* Invalid Command Error */ 7950 #ifndef USE_FIELD_ALIASES_CTU 7951 uint16_t SM_TO:1; /* Trigger Overrun */ 7952 #else 7953 uint16_t SMTO:1; /* Trigger Overrun */ 7954 #endif 7955 #ifndef USE_FIELD_ALIASES_CTU 7956 uint16_t MRS_RE:1; /* MRS Reload Error */ 7957 #else 7958 uint16_t MRSRE:1; /* MRS Reload Error */ 7959 #endif 7960 } B; 7961 } CTU_CTUEFR_16B_tag; 7962 7963 typedef union { /* CTU Interrupt Flag Register */ 7964 uint16_t R; 7965 struct { 7966 uint16_t:4; 7967 uint16_t S_E_B:1; /* Slice time OK */ 7968 uint16_t S_E_A:1; /* Slice time OK */ 7969 #ifndef USE_FIELD_ALIASES_CTU 7970 uint16_t ADC_I:1; /* ADC Command Interrupt Flag */ 7971 #else 7972 uint16_t ADC:1; 7973 #endif 7974 #ifndef USE_FIELD_ALIASES_CTU 7975 uint16_t T7_I:1; /* Trigger 7 Interrupt Flag */ 7976 #else 7977 uint16_t T7:1; 7978 #endif 7979 #ifndef USE_FIELD_ALIASES_CTU 7980 uint16_t T6_I:1; /* Trigger 6 Interrupt Flag */ 7981 #else 7982 uint16_t T6:1; 7983 #endif 7984 #ifndef USE_FIELD_ALIASES_CTU 7985 uint16_t T5_I:1; /* Trigger 5 Interrupt Flag */ 7986 #else 7987 uint16_t T5:1; 7988 #endif 7989 #ifndef USE_FIELD_ALIASES_CTU 7990 uint16_t T4_I:1; /* Trigger 4 Interrupt Flag */ 7991 #else 7992 uint16_t T4:1; 7993 #endif 7994 #ifndef USE_FIELD_ALIASES_CTU 7995 uint16_t T3_I:1; /* Trigger 3 Interrupt Flag */ 7996 #else 7997 uint16_t T3:1; 7998 #endif 7999 #ifndef USE_FIELD_ALIASES_CTU 8000 uint16_t T2_I:1; /* Trigger 2 Interrupt Flag */ 8001 #else 8002 uint16_t T2:1; 8003 #endif 8004 #ifndef USE_FIELD_ALIASES_CTU 8005 uint16_t T1_I:1; /* Trigger 1 Interrupt Flag */ 8006 #else 8007 uint16_t T1:1; 8008 #endif 8009 #ifndef USE_FIELD_ALIASES_CTU 8010 uint16_t T0_I:1; /* Trigger 0 Interrupt Flag */ 8011 #else 8012 uint16_t T0:1; 8013 #endif 8014 #ifndef USE_FIELD_ALIASES_CTU 8015 uint16_t MRS_I:1; /* MRS Interrupt Flag */ 8016 #else 8017 uint16_t MRS:1; 8018 #endif 8019 } B; 8020 } CTU_CTUIFR_16B_tag; 8021 8022 typedef union { /* CTU Interrupt/DMA Register */ 8023 uint16_t R; 8024 struct { 8025 #ifndef USE_FIELD_ALIASES_CTU 8026 uint16_t T7_I:1; /* Trigger 7 Interrupt Enable */ 8027 #else 8028 uint16_t T7IE:1; 8029 #endif 8030 #ifndef USE_FIELD_ALIASES_CTU 8031 uint16_t T6_I:1; /* Trigger 6 Interrupt Enable */ 8032 #else 8033 uint16_t T6IE:1; 8034 #endif 8035 #ifndef USE_FIELD_ALIASES_CTU 8036 uint16_t T5_I:1; /* Trigger 5 Interrupt Enable */ 8037 #else 8038 uint16_t T5IE:1; 8039 #endif 8040 #ifndef USE_FIELD_ALIASES_CTU 8041 uint16_t T4_I:1; /* Trigger 4 Interrupt Enable */ 8042 #else 8043 uint16_t T4IE:1; 8044 #endif 8045 #ifndef USE_FIELD_ALIASES_CTU 8046 uint16_t T3_I:1; /* Trigger 3 Interrupt Enable */ 8047 #else 8048 uint16_t T3IE:1; 8049 #endif 8050 #ifndef USE_FIELD_ALIASES_CTU 8051 uint16_t T2_I:1; /* Trigger 2 Interrupt Enable */ 8052 #else 8053 uint16_t T2IE:1; 8054 #endif 8055 #ifndef USE_FIELD_ALIASES_CTU 8056 uint16_t T1_I:1; /* Trigger 1 Interrupt Enable */ 8057 #else 8058 uint16_t T1IE:1; 8059 #endif 8060 #ifndef USE_FIELD_ALIASES_CTU 8061 uint16_t T0_I:1; /* Trigger 0 Interrupt Enable */ 8062 #else 8063 uint16_t T0IE:1; 8064 #endif 8065 uint16_t:2; 8066 uint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */ 8067 uint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */ 8068 uint16_t DMA_DE:1; /* DMA and gre bit */ 8069 #ifndef USE_FIELD_ALIASES_CTU 8070 uint16_t MRS_DMAE:1; /* DMA Transfer Enable */ 8071 #else 8072 uint16_t MRSDMAE:1; 8073 #endif 8074 #ifndef USE_FIELD_ALIASES_CTU 8075 uint16_t MRS_IE:1; /* MRS Interrupt Enable */ 8076 #else 8077 uint16_t MRSIE:1; 8078 #endif 8079 uint16_t IEE:1; /* Interrupt Error Enable */ 8080 } B; 8081 } CTU_CTUIR_16B_tag; 8082 8083 typedef union { /* Control On-Time Register */ 8084 uint16_t R; 8085 struct { 8086 uint16_t:8; 8087 #ifndef USE_FIELD_ALIASES_CTU 8088 uint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */ 8089 #else 8090 uint16_t COTR:8; 8091 #endif 8092 } B; 8093 } CTU_COTR_16B_tag; 8094 8095 typedef union { /* CTU Control Register */ 8096 uint16_t R; 8097 struct { 8098 #ifndef USE_FIELD_ALIASES_CTU 8099 uint16_t T7_SG:1; /* Trigger 7 Software Generated */ 8100 #else 8101 uint16_t T7SG:1; 8102 #endif 8103 #ifndef USE_FIELD_ALIASES_CTU 8104 uint16_t T6_SG:1; /* Trigger 6 Software Generated */ 8105 #else 8106 uint16_t T6SG:1; 8107 #endif 8108 #ifndef USE_FIELD_ALIASES_CTU 8109 uint16_t T5_SG:1; /* Trigger 5 Software Generated */ 8110 #else 8111 uint16_t T5SG:1; 8112 #endif 8113 #ifndef USE_FIELD_ALIASES_CTU 8114 uint16_t T4_SG:1; /* Trigger 4 Software Generated */ 8115 #else 8116 uint16_t T4SG:1; 8117 #endif 8118 #ifndef USE_FIELD_ALIASES_CTU 8119 uint16_t T3_SG:1; /* Trigger 3 Software Generated */ 8120 #else 8121 uint16_t T3SG:1; 8122 #endif 8123 #ifndef USE_FIELD_ALIASES_CTU 8124 uint16_t T2_SG:1; /* Trigger 2 Software Generated */ 8125 #else 8126 uint16_t T2SG:1; 8127 #endif 8128 #ifndef USE_FIELD_ALIASES_CTU 8129 uint16_t T1_SG:1; /* Trigger 1 Software Generated */ 8130 #else 8131 uint16_t T1SG:1; 8132 #endif 8133 #ifndef USE_FIELD_ALIASES_CTU 8134 uint16_t T0_SG:1; /* Trigger 0 Software Generated */ 8135 #else 8136 uint16_t T0SG:1; 8137 #endif 8138 #ifndef USE_FIELD_ALIASES_CTU 8139 uint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */ 8140 #else 8141 uint16_t CTUADCRESET:1; 8142 #endif 8143 #ifndef USE_FIELD_ALIASES_CTU 8144 uint16_t CTU_ODIS:1; /* CTU Output Disable */ 8145 #else 8146 uint16_t CTUODIS:1; 8147 #endif 8148 #ifndef USE_FIELD_ALIASES_CTU 8149 uint16_t FILTER_EN:1; /* Synchronize Filter Register value */ 8150 #else 8151 uint16_t FILTERENABLE:1; 8152 #endif 8153 uint16_t CGRE:1; /* Clear GRE */ 8154 uint16_t FGRE:1; /* GRE Flag */ 8155 #ifndef USE_FIELD_ALIASES_CTU 8156 uint16_t MRS_SG:1; /* MRS Software Generated */ 8157 #else 8158 uint16_t MRSSG:1; 8159 #endif 8160 uint16_t GRE:1; /* General Reload Enable */ 8161 #ifndef USE_FIELD_ALIASES_CTU 8162 uint16_t TGSISR_RE:1; /* TGSISR Reload Enable */ 8163 #else 8164 uint16_t TGSISRRE:1; 8165 #endif 8166 } B; 8167 } CTU_CTUCR_16B_tag; 8168 8169 typedef union { /* CTU Digital Filter Register */ 8170 uint16_t R; 8171 struct { 8172 uint16_t:8; 8173 #ifndef USE_FIELD_ALIASES_CTU 8174 uint16_t FILTER_VALUE:8; /* Filter Value */ 8175 #else 8176 uint16_t FILTERVALUE:8; /* deprecated name - please avoid */ 8177 #endif 8178 } B; 8179 } CTU_FILTER_16B_tag; 8180 8181 typedef union { /* CTU Expected A Value Register */ 8182 uint16_t R; 8183 struct { 8184 uint16_t EXPECTED_A_VALUE:16; /* Expected A Value */ 8185 } B; 8186 } CTU_EXPECTED_A_16B_tag; 8187 8188 typedef union { /* CTU Expected B Value Register */ 8189 uint16_t R; 8190 struct { 8191 uint16_t EXPECTED_B_VALUE:16; /* Expected B Value */ 8192 } B; 8193 } CTU_EXPECTED_B_16B_tag; 8194 8195 typedef union { /* CTU Counter Range Register */ 8196 uint16_t R; 8197 struct { 8198 uint16_t:8; 8199 uint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */ 8200 } B; 8201 } CTU_CNT_RANGE_16B_tag; 8202 8203 8204 /* Register layout for generated register(s) FRA... */ 8205 8206 typedef union { /* */ 8207 uint32_t R; 8208 } CTU_FRA_32B_tag; 8209 8210 8211 /* Register layout for generated register(s) FLA... */ 8212 8213 typedef union { /* */ 8214 uint32_t R; 8215 } CTU_FLA_32B_tag; 8216 8217 8218 8219 typedef struct CTU_struct_tag { /* start of CTU_tag */ 8220 /* Trigger Generator Subunit Input Selection register */ 8221 CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */ 8222 /* Trigger Generator Subunit Control Register */ 8223 CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */ 8224 union { 8225 CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */ 8226 8227 struct { 8228 CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */ 8229 CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */ 8230 CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */ 8231 CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */ 8232 CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */ 8233 CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */ 8234 CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */ 8235 CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */ 8236 }; 8237 8238 }; 8239 /* TGS Counter Compare Register */ 8240 CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */ 8241 /* TGS Counter Reload Register */ 8242 CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */ 8243 int8_t CTU_reserved_001A[2]; 8244 /* Commands List Control Register 1 */ 8245 CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */ 8246 /* Commands List Control Register 2 */ 8247 CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */ 8248 /* Trigger Handler Control Register 1 */ 8249 CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */ 8250 /* Trigger Handler Control Register 2 */ 8251 CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */ 8252 union { 8253 /* Command List Register. View: BIT13, BIT9 */ 8254 CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */ 8255 8256 /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ 8257 CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */ 8258 8259 /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ 8260 CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */ 8261 8262 struct { 8263 /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ 8264 CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */ 8265 CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */ 8266 CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */ 8267 CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */ 8268 CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */ 8269 CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */ 8270 CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */ 8271 CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */ 8272 CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */ 8273 CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */ 8274 CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */ 8275 CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */ 8276 CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */ 8277 CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */ 8278 CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */ 8279 CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */ 8280 CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */ 8281 CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */ 8282 CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */ 8283 CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */ 8284 CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */ 8285 CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */ 8286 CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */ 8287 CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */ 8288 }; 8289 8290 struct { 8291 /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ 8292 CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */ 8293 CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */ 8294 CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */ 8295 CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */ 8296 CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */ 8297 CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */ 8298 CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */ 8299 CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */ 8300 CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */ 8301 CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */ 8302 CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */ 8303 CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */ 8304 CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */ 8305 CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */ 8306 CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */ 8307 CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */ 8308 CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */ 8309 CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */ 8310 CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */ 8311 CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */ 8312 CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */ 8313 CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */ 8314 CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */ 8315 CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */ 8316 }; 8317 8318 }; 8319 int8_t CTU_reserved_005C[16]; 8320 /* Control Register */ 8321 CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */ 8322 int8_t CTU_reserved_006E[2]; 8323 /* Control Register FIFO */ 8324 CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */ 8325 /* Threshold 1 Register */ 8326 CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */ 8327 /* Threshold 2 Register */ 8328 CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */ 8329 union { 8330 /* Status Register */ 8331 CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */ 8332 8333 CTU_STS_32B_tag STATUS; /* deprecated - please avoid */ 8334 8335 }; 8336 union { 8337 CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */ 8338 8339 /* FIFO Right Aligned register */ 8340 CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */ 8341 8342 struct { 8343 /* FIFO Right Aligned register */ 8344 CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */ 8345 CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */ 8346 CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */ 8347 CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */ 8348 CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */ 8349 CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */ 8350 CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */ 8351 CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */ 8352 }; 8353 8354 }; 8355 union { 8356 CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */ 8357 8358 /* FIFO Left Aligned register */ 8359 CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */ 8360 8361 struct { 8362 /* FIFO Left Aligned register */ 8363 CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */ 8364 CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */ 8365 CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */ 8366 CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */ 8367 CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */ 8368 CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */ 8369 CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */ 8370 CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */ 8371 }; 8372 8373 }; 8374 /* CTU Error Flag Register */ 8375 CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */ 8376 /* CTU Interrupt Flag Register */ 8377 CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */ 8378 /* CTU Interrupt/DMA Register */ 8379 CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */ 8380 /* Control On-Time Register */ 8381 CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */ 8382 /* CTU Control Register */ 8383 CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */ 8384 union { 8385 /* CTU Digital Filter Register */ 8386 CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */ 8387 8388 CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */ 8389 8390 }; 8391 /* CTU Expected A Value Register */ 8392 CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */ 8393 8394 /* CTU Expected B Value Register */ 8395 CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */ 8396 /* CTU Counter Range Register */ 8397 CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */ 8398 } CTU_tag; 8399 8400 8401 #define CTU (*(volatile CTU_tag *) 0xFFE0C000UL) 8402 8403 8404 8405 /****************************************************************/ 8406 /* */ 8407 /* Module: mcTIMER */ 8408 /* */ 8409 /****************************************************************/ 8410 8411 8412 /* Register layout for all registers COMP1... */ 8413 8414 typedef union { /* Compare Register 1 */ 8415 uint16_t R; 8416 struct { 8417 uint16_t COMP1:16; /* deprecated definition -- do not use */ 8418 } B; 8419 } mcTIMER_COMP1_16B_tag; 8420 8421 8422 /* Register layout for all registers COMP2... */ 8423 8424 typedef union { /* Compare Register 2 */ 8425 uint16_t R; 8426 struct { 8427 uint16_t COMP2:16; /* deprecated definition -- do not use */ 8428 } B; 8429 } mcTIMER_COMP2_16B_tag; 8430 8431 8432 /* Register layout for all registers CAPT1... */ 8433 8434 typedef union { /* Capture Register 1 */ 8435 uint16_t R; 8436 struct { 8437 uint16_t CAPT1:16; /* deprecated definition -- do not use */ 8438 } B; 8439 } mcTIMER_CAPT1_16B_tag; 8440 8441 8442 /* Register layout for all registers CAPT2... */ 8443 8444 typedef union { /* Capture Register 2 */ 8445 uint16_t R; 8446 struct { 8447 uint16_t CAPT2:16; /* deprecated definition -- do not use */ 8448 } B; 8449 } mcTIMER_CAPT2_16B_tag; 8450 8451 8452 /* Register layout for all registers LOAD... */ 8453 8454 typedef union { /* Load Register */ 8455 uint16_t R; 8456 struct { 8457 uint16_t LOAD:16; /* deprecated definition -- do not use */ 8458 } B; 8459 } mcTIMER_LOAD_16B_tag; 8460 8461 8462 /* Register layout for all registers HOLD... */ 8463 8464 typedef union { /* Hold Register */ 8465 uint16_t R; 8466 struct { 8467 uint16_t HOLD:16; /* deprecated definition -- do not use */ 8468 } B; 8469 } mcTIMER_HOLD_16B_tag; 8470 8471 8472 /* Register layout for all registers CNTR... */ 8473 8474 typedef union { /* Counter Register */ 8475 uint16_t R; 8476 struct { 8477 uint16_t CNTR:16; /* deprecated definition -- do not use */ 8478 } B; 8479 } mcTIMER_CNTR_16B_tag; 8480 8481 8482 /* Register layout for all registers CTRL1... */ 8483 8484 typedef union { /* Control Register */ 8485 uint16_t R; 8486 struct { 8487 uint16_t CNTMODE:3; /* Count Mode */ 8488 uint16_t PRISRC:5; /* Primary Count Source */ 8489 uint16_t ONCE:1; /* Count Once */ 8490 uint16_t LENGTH:1; /* Count Length */ 8491 uint16_t DIR:1; /* Count Direction */ 8492 uint16_t SECSRC:5; /* Secondary Count Source */ 8493 } B; 8494 } mcTIMER_CTRL1_16B_tag; 8495 8496 8497 /* Register layout for all registers CTRL2... */ 8498 8499 typedef union { /* Control Register 2 */ 8500 uint16_t R; 8501 struct { 8502 uint16_t OEN:1; /* Output Enable */ 8503 uint16_t RDNT:1; /* Redundant Channel Enable */ 8504 uint16_t INPUT:1; /* External Input Signal */ 8505 uint16_t VAL:1; /* Forced OFLAG Value */ 8506 uint16_t FORCE:1; /* Force the OFLAG output */ 8507 uint16_t COFRC:1; /* Co-channel OFLAG Force */ 8508 uint16_t COINIT:2; /* Co-channel Initialization */ 8509 uint16_t SIPS:1; /* Secondary Source Input Polarity Select */ 8510 uint16_t PIPS:1; /* Primary Source Input Polarity Select */ 8511 uint16_t OPS:1; /* Output Polarity Select */ 8512 uint16_t MSTR:1; /* Master Mode */ 8513 uint16_t OUTMODE:4; /* Output Mode */ 8514 } B; 8515 } mcTIMER_CTRL2_16B_tag; 8516 8517 8518 /* Register layout for all registers CTRL3... */ 8519 8520 typedef union { /* Control Register 3 */ 8521 uint16_t R; 8522 struct { 8523 uint16_t STPEN:1; /* Stop Action Enable */ 8524 uint16_t ROC:2; /* Reload On Capture */ 8525 uint16_t FMODE:1; /* Fault Safing Mode */ 8526 uint16_t FDIS:4; /* Fault Disable Mask */ 8527 uint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */ 8528 uint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */ 8529 uint16_t DBGEN:2; /* Debug Actions Enable */ 8530 } B; 8531 } mcTIMER_CTRL3_16B_tag; 8532 8533 8534 /* Register layout for all registers STS... */ 8535 8536 typedef union { /* Status Register */ 8537 uint16_t R; 8538 struct { 8539 uint16_t:6; 8540 uint16_t WDF:1; /* Watchdog Time-out Flag */ 8541 uint16_t RCF:1; /* Redundant Channel Flag */ 8542 uint16_t ICF2:1; /* Input Capture 2 Flag */ 8543 uint16_t ICF1:1; /* Input Capture 1 Flag */ 8544 uint16_t IEHF:1; /* Input Edge High Flag */ 8545 uint16_t IELF:1; /* Input Edge Low Flag */ 8546 uint16_t TOF:1; /* Timer Overflow Flag */ 8547 uint16_t TCF2:1; /* Timer Compare 2 Flag */ 8548 uint16_t TCF1:1; /* Timer Compare 1 Flag */ 8549 uint16_t TCF:1; /* Timer Compare Flag */ 8550 } B; 8551 } mcTIMER_STS_16B_tag; 8552 8553 8554 /* Register layout for all registers INTDMA... */ 8555 8556 typedef union { /* Interrupt and DMA Enable Register */ 8557 uint16_t R; 8558 struct { 8559 uint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */ 8560 uint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */ 8561 uint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */ 8562 uint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */ 8563 uint16_t:2; 8564 uint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */ 8565 uint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */ 8566 uint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */ 8567 uint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */ 8568 uint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */ 8569 uint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */ 8570 uint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */ 8571 uint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */ 8572 uint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */ 8573 uint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */ 8574 } B; 8575 } mcTIMER_INTDMA_16B_tag; 8576 8577 8578 /* Register layout for all registers CMPLD1... */ 8579 8580 typedef union { /* Comparator Load Register 1 */ 8581 uint16_t R; 8582 struct { 8583 uint16_t CMPLD1:16; /* deprecated definition -- do not use */ 8584 } B; 8585 } mcTIMER_CMPLD1_16B_tag; 8586 8587 8588 /* Register layout for all registers CMPLD2... */ 8589 8590 typedef union { /* Comparator Load Register 2 */ 8591 uint16_t R; 8592 struct { 8593 uint16_t CMPLD2:16; /* deprecated definition -- do not use */ 8594 } B; 8595 } mcTIMER_CMPLD2_16B_tag; 8596 8597 8598 /* Register layout for all registers CCCTRL... */ 8599 8600 typedef union { /* Compare and Capture Control Register */ 8601 uint16_t R; 8602 struct { 8603 uint16_t CLC2:3; /* Compare Load Control 2 */ 8604 uint16_t CLC1:3; /* Compare Load Control 1 */ 8605 uint16_t CMPMODE:2; /* Compare Mode */ 8606 uint16_t CPT2MODE:2; /* Capture 2 Mode Control */ 8607 uint16_t CPT1MODE:2; /* Capture 1 Mode Control */ 8608 uint16_t CFWM:2; /* Capture FIFO Water Mark */ 8609 uint16_t ONESHOT:1; /* One Shot Capture Mode */ 8610 uint16_t ARM:1; /* Arm Capture */ 8611 } B; 8612 } mcTIMER_CCCTRL_16B_tag; 8613 8614 8615 /* Register layout for all registers FILT... */ 8616 8617 typedef union { /* Input Filter Register */ 8618 uint16_t R; 8619 struct { 8620 uint16_t:5; 8621 #ifndef USE_FIELD_ALIASES_mcTIMER 8622 uint16_t FILT_CNT:3; /* Input Filter Sample Count */ 8623 #else 8624 uint16_t FILTCNT:3; /* deprecated name - please avoid */ 8625 #endif 8626 #ifndef USE_FIELD_ALIASES_mcTIMER 8627 uint16_t FILT_PER:8; /* Input Filter Sample Period */ 8628 #else 8629 uint16_t FILTPER:8; /* deprecated name - please avoid */ 8630 #endif 8631 } B; 8632 } mcTIMER_FILT_16B_tag; 8633 8634 typedef union { /* Watchdog Time-out Register */ 8635 uint16_t R; 8636 struct { 8637 uint16_t WDTOL:16; /* deprecated definition -- do not use */ 8638 } B; 8639 } mcTIMER_WDTOL_16B_tag; 8640 8641 typedef union { /* Watchdog Time-out Register */ 8642 uint16_t R; 8643 struct { 8644 uint16_t WDTOH:16; /* deprecated definition -- do not use */ 8645 } B; 8646 } mcTIMER_WDTOH_16B_tag; 8647 8648 typedef union { /* Fault Control Register */ 8649 uint16_t R; 8650 struct { 8651 uint16_t:3; 8652 uint16_t FTEST:1; /* Fault Test */ 8653 uint16_t FIE:4; /* Fault Interrupt Enable */ 8654 uint16_t:4; 8655 uint16_t FLVL:4; /* Fault Active Logic Level */ 8656 } B; 8657 } mcTIMER_FCTRL_16B_tag; 8658 8659 typedef union { /* Fault Status Register */ 8660 uint16_t R; 8661 struct { 8662 uint16_t:4; 8663 uint16_t FFPIN:4; /* Filtered Fault Pin */ 8664 uint16_t:4; 8665 uint16_t FFLAG:4; /* Fault Flag */ 8666 } B; 8667 } mcTIMER_FSTS_16B_tag; 8668 8669 typedef union { /* Fault Filter Registers */ 8670 uint16_t R; 8671 struct { 8672 uint16_t:5; 8673 #ifndef USE_FIELD_ALIASES_mcTIMER 8674 uint16_t FFPIN:3; /* Fault Filter Sample Count */ 8675 #else 8676 uint16_t FFILTCNT:3; /* deprecated name - please avoid */ 8677 #endif 8678 #ifndef USE_FIELD_ALIASES_mcTIMER 8679 uint16_t FFILT_PER:8; /* Fault Filter Sample Period */ 8680 #else 8681 uint16_t FFILTPER:8; /* deprecated name - please avoid */ 8682 #endif 8683 } B; 8684 } mcTIMER_FFILT_16B_tag; 8685 8686 typedef union { /* Channel Enable Registers */ 8687 uint16_t R; 8688 struct { 8689 uint16_t:8; 8690 uint16_t ENBL:8; /* Timer Channel Enable */ 8691 } B; 8692 } mcTIMER_ENBL_16B_tag; 8693 8694 typedef union { /* DMA Request 0 Select Registers */ 8695 uint16_t R; 8696 struct { 8697 uint16_t:11; 8698 uint16_t DREQ0V:5; /* DMA Request Select */ 8699 } B; 8700 } mcTIMER_DREQ0_16B_tag; 8701 8702 typedef union { /* DMA Request 1 Select Registers */ 8703 uint16_t R; 8704 struct { 8705 uint16_t:11; 8706 uint16_t DREQ1V:5; /* DMA Request Select */ 8707 } B; 8708 } mcTIMER_DREQ1_16B_tag; 8709 8710 typedef union { /* DMA Request 2 Select Registers */ 8711 uint16_t R; 8712 struct { 8713 uint16_t:11; 8714 uint16_t DREQ2V:5; /* DMA Request Select */ 8715 } B; 8716 } mcTIMER_DREQ2_16B_tag; 8717 8718 typedef union { /* DMA Request 3 Select Registers */ 8719 uint16_t R; 8720 struct { 8721 uint16_t:11; 8722 uint16_t DREQ3V:5; /* DMA Request Select */ 8723 } B; 8724 } mcTIMER_DREQ3_16B_tag; 8725 8726 8727 /* Register layout for generated register(s) DREQ... */ 8728 8729 typedef union { /* */ 8730 uint16_t R; 8731 } mcTIMER_DREQ_16B_tag; 8732 8733 8734 typedef struct mcTIMER_CHANNEL_struct_tag { 8735 8736 /* Compare Register 1 */ 8737 mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */ 8738 /* Compare Register 2 */ 8739 mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */ 8740 /* Capture Register 1 */ 8741 mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */ 8742 /* Capture Register 2 */ 8743 mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */ 8744 /* Load Register */ 8745 mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */ 8746 /* Hold Register */ 8747 mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */ 8748 /* Counter Register */ 8749 mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */ 8750 union { 8751 /* Control Register */ 8752 mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */ 8753 mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ 8754 }; 8755 /* Control Register 2 */ 8756 mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */ 8757 /* Control Register 3 */ 8758 mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */ 8759 /* Status Register */ 8760 mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */ 8761 /* Interrupt and DMA Enable Register */ 8762 mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */ 8763 /* Comparator Load Register 1 */ 8764 mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */ 8765 /* Comparator Load Register 2 */ 8766 mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */ 8767 /* Compare and Capture Control Register */ 8768 mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */ 8769 /* Input Filter Register */ 8770 mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */ 8771 8772 } mcTIMER_CHANNEL_tag; 8773 8774 8775 typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */ 8776 union { 8777 /* Register set CHANNEL */ 8778 mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */ 8779 8780 struct { 8781 /* Compare Register 1 */ 8782 mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */ 8783 /* Compare Register 2 */ 8784 mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */ 8785 /* Capture Register 1 */ 8786 mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */ 8787 /* Capture Register 2 */ 8788 mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */ 8789 /* Load Register */ 8790 mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */ 8791 /* Hold Register */ 8792 mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */ 8793 /* Counter Register */ 8794 mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */ 8795 /* Control Register */ 8796 mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */ 8797 /* Control Register 2 */ 8798 mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */ 8799 /* Control Register 3 */ 8800 mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */ 8801 /* Status Register */ 8802 mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */ 8803 /* Interrupt and DMA Enable Register */ 8804 mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */ 8805 /* Comparator Load Register 1 */ 8806 mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */ 8807 /* Comparator Load Register 2 */ 8808 mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */ 8809 /* Compare and Capture Control Register */ 8810 mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */ 8811 /* Input Filter Register */ 8812 mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */ 8813 /* Compare Register 1 */ 8814 mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */ 8815 /* Compare Register 2 */ 8816 mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */ 8817 /* Capture Register 1 */ 8818 mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */ 8819 /* Capture Register 2 */ 8820 mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */ 8821 /* Load Register */ 8822 mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */ 8823 /* Hold Register */ 8824 mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */ 8825 /* Counter Register */ 8826 mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */ 8827 /* Control Register */ 8828 mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */ 8829 /* Control Register 2 */ 8830 mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */ 8831 /* Control Register 3 */ 8832 mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */ 8833 /* Status Register */ 8834 mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */ 8835 /* Interrupt and DMA Enable Register */ 8836 mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */ 8837 /* Comparator Load Register 1 */ 8838 mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */ 8839 /* Comparator Load Register 2 */ 8840 mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */ 8841 /* Compare and Capture Control Register */ 8842 mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */ 8843 /* Input Filter Register */ 8844 mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */ 8845 /* Compare Register 1 */ 8846 mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */ 8847 /* Compare Register 2 */ 8848 mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */ 8849 /* Capture Register 1 */ 8850 mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */ 8851 /* Capture Register 2 */ 8852 mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */ 8853 /* Load Register */ 8854 mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */ 8855 /* Hold Register */ 8856 mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */ 8857 /* Counter Register */ 8858 mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */ 8859 /* Control Register */ 8860 mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */ 8861 /* Control Register 2 */ 8862 mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */ 8863 /* Control Register 3 */ 8864 mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */ 8865 /* Status Register */ 8866 mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */ 8867 /* Interrupt and DMA Enable Register */ 8868 mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */ 8869 /* Comparator Load Register 1 */ 8870 mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */ 8871 /* Comparator Load Register 2 */ 8872 mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */ 8873 /* Compare and Capture Control Register */ 8874 mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */ 8875 /* Input Filter Register */ 8876 mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */ 8877 /* Compare Register 1 */ 8878 mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */ 8879 /* Compare Register 2 */ 8880 mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */ 8881 /* Capture Register 1 */ 8882 mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */ 8883 /* Capture Register 2 */ 8884 mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */ 8885 /* Load Register */ 8886 mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */ 8887 /* Hold Register */ 8888 mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */ 8889 /* Counter Register */ 8890 mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */ 8891 /* Control Register */ 8892 mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */ 8893 /* Control Register 2 */ 8894 mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */ 8895 /* Control Register 3 */ 8896 mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */ 8897 /* Status Register */ 8898 mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */ 8899 /* Interrupt and DMA Enable Register */ 8900 mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */ 8901 /* Comparator Load Register 1 */ 8902 mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */ 8903 /* Comparator Load Register 2 */ 8904 mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */ 8905 /* Compare and Capture Control Register */ 8906 mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */ 8907 /* Input Filter Register */ 8908 mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */ 8909 /* Compare Register 1 */ 8910 mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */ 8911 /* Compare Register 2 */ 8912 mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */ 8913 /* Capture Register 1 */ 8914 mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */ 8915 /* Capture Register 2 */ 8916 mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */ 8917 /* Load Register */ 8918 mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */ 8919 /* Hold Register */ 8920 mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */ 8921 /* Counter Register */ 8922 mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */ 8923 /* Control Register */ 8924 mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */ 8925 /* Control Register 2 */ 8926 mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */ 8927 /* Control Register 3 */ 8928 mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */ 8929 /* Status Register */ 8930 mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */ 8931 /* Interrupt and DMA Enable Register */ 8932 mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */ 8933 /* Comparator Load Register 1 */ 8934 mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */ 8935 /* Comparator Load Register 2 */ 8936 mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */ 8937 /* Compare and Capture Control Register */ 8938 mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */ 8939 /* Input Filter Register */ 8940 mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */ 8941 /* Compare Register 1 */ 8942 mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */ 8943 /* Compare Register 2 */ 8944 mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */ 8945 /* Capture Register 1 */ 8946 mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */ 8947 /* Capture Register 2 */ 8948 mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */ 8949 /* Load Register */ 8950 mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */ 8951 /* Hold Register */ 8952 mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */ 8953 /* Counter Register */ 8954 mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */ 8955 /* Control Register */ 8956 mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */ 8957 /* Control Register 2 */ 8958 mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */ 8959 /* Control Register 3 */ 8960 mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */ 8961 /* Status Register */ 8962 mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */ 8963 /* Interrupt and DMA Enable Register */ 8964 mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */ 8965 /* Comparator Load Register 1 */ 8966 mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */ 8967 /* Comparator Load Register 2 */ 8968 mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */ 8969 /* Compare and Capture Control Register */ 8970 mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */ 8971 /* Input Filter Register */ 8972 mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */ 8973 }; 8974 8975 }; 8976 int8_t mcTIMER_reserved_00C0[64]; 8977 /* Watchdog Time-out Register */ 8978 mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */ 8979 /* Watchdog Time-out Register */ 8980 mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */ 8981 /* Fault Control Register */ 8982 mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */ 8983 /* Fault Status Register */ 8984 mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */ 8985 /* Fault Filter Registers */ 8986 mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */ 8987 int8_t mcTIMER_reserved_010A[2]; 8988 /* Channel Enable Registers */ 8989 mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */ 8990 int8_t mcTIMER_reserved_010E_C[2]; 8991 union { 8992 mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */ 8993 8994 struct { 8995 /* DMA Request 0 Select Registers */ 8996 mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */ 8997 /* DMA Request 1 Select Registers */ 8998 mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */ 8999 /* DMA Request 2 Select Registers */ 9000 mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */ 9001 /* DMA Request 3 Select Registers */ 9002 mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */ 9003 }; 9004 9005 }; 9006 } mcTIMER_tag; 9007 9008 9009 #define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL) 9010 #define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL) 9011 #define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL) 9012 9013 9014 9015 /****************************************************************/ 9016 /* */ 9017 /* Module: mcPWM */ 9018 /* */ 9019 /****************************************************************/ 9020 9021 9022 /* Register layout for all registers CNT... */ 9023 9024 typedef union { /* Counter Register */ 9025 uint16_t R; 9026 } mcPWM_CNT_16B_tag; 9027 9028 9029 /* Register layout for all registers INIT... */ 9030 9031 typedef union { /* Initial Counter Register */ 9032 uint16_t R; 9033 } mcPWM_INIT_16B_tag; 9034 9035 9036 /* Register layout for all registers CTRL2... */ 9037 9038 typedef union { /* Control 2 Register */ 9039 uint16_t R; 9040 struct { 9041 uint16_t DBGEN:1; /* Debug Enable */ 9042 uint16_t WAITEN:1; /* Wait Enable */ 9043 uint16_t INDEP:1; /* Independent or Complementary Pair Operation */ 9044 #ifndef USE_FIELD_ALIASES_mcPWM 9045 uint16_t PWM23_INIT:1; /* PWM23 Initial Value */ 9046 #else 9047 uint16_t PWMA_INIT:1; /* deprecated name - please avoid */ 9048 #endif 9049 #ifndef USE_FIELD_ALIASES_mcPWM 9050 uint16_t PWM45_INIT:1; /* PWM23 Initial Value */ 9051 #else 9052 uint16_t PWMB_INIT:1; /* deprecated name - please avoid */ 9053 #endif 9054 uint16_t PWMX_INIT:1; /* PWMX Initial Value */ 9055 uint16_t INIT_SEL:2; /* Initialization Control Select */ 9056 uint16_t FRCEN:1; /* Force Initialization enable */ 9057 uint16_t FORCE:1; /* Force Initialization */ 9058 uint16_t FORCE_SEL:3; /* Force Source Select */ 9059 uint16_t RELOAD_SEL:1; /* Reload Source Select */ 9060 uint16_t CLK_SEL:2; /* Clock Source Select */ 9061 } B; 9062 } mcPWM_CTRL2_16B_tag; 9063 9064 9065 /* Register layout for all registers CTRL1... */ 9066 9067 typedef union { /* Control Register */ 9068 uint16_t R; 9069 struct { 9070 uint16_t LDFQ:4; /* Load Frequency */ 9071 uint16_t HALF:1; /* Half Cycle Reload */ 9072 uint16_t FULL:1; /* Full Cycle Reload */ 9073 uint16_t DT:2; /* Deadtime */ 9074 uint16_t:1; 9075 uint16_t PRSC:3; /* Prescaler */ 9076 uint16_t:1; 9077 uint16_t LDMOD:1; /* Load Mode Select */ 9078 uint16_t:1; 9079 #ifndef USE_FIELD_ALIASES_mcPWM 9080 uint16_t DBL_EN:1; /* Double Switching Enable */ 9081 #else 9082 uint16_t DBLEN:1; /* deprecated name - please avoid */ 9083 #endif 9084 } B; 9085 } mcPWM_CTRL1_16B_tag; 9086 9087 9088 /* Register layout for all registers VAL_0... */ 9089 9090 typedef union { /* Value Register 0 */ 9091 uint16_t R; 9092 } mcPWM_VAL_0_16B_tag; 9093 9094 9095 /* Register layout for all registers VAL_1... */ 9096 9097 typedef union { /* Value Register 1 */ 9098 uint16_t R; 9099 } mcPWM_VAL_1_16B_tag; 9100 9101 9102 /* Register layout for all registers VAL_2... */ 9103 9104 typedef union { /* Value Register 2 */ 9105 uint16_t R; 9106 } mcPWM_VAL_2_16B_tag; 9107 9108 9109 /* Register layout for all registers VAL_3... */ 9110 9111 typedef union { /* Value Register 3 */ 9112 uint16_t R; 9113 } mcPWM_VAL_3_16B_tag; 9114 9115 9116 /* Register layout for all registers VAL_4... */ 9117 9118 typedef union { /* Value Register 4 */ 9119 uint16_t R; 9120 } mcPWM_VAL_4_16B_tag; 9121 9122 9123 /* Register layout for all registers VAL_5... */ 9124 9125 typedef union { /* Value Register 5 */ 9126 uint16_t R; 9127 } mcPWM_VAL_5_16B_tag; 9128 9129 /* Register layout for all registers OCTRL... */ 9130 9131 typedef union { /* Output Control Register */ 9132 uint16_t R; 9133 struct { 9134 uint16_t PWMA_IN:1; /* PWMA Input */ 9135 uint16_t PWMB_IN:1; /* PWMB Input */ 9136 uint16_t PWMX_IN:1; /* PWMX Input */ 9137 uint16_t:2; 9138 uint16_t POLA:1; /* PWMA Output Polarity */ 9139 uint16_t POLB:1; /* PWMB Output Polarity */ 9140 uint16_t POLX:1; /* PWMX Output Polarity */ 9141 uint16_t:2; 9142 uint16_t PWMAFS:2; /* PWMA Fault State */ 9143 uint16_t PWMBFS:2; /* PWMB Fault State */ 9144 uint16_t PWMXFS:2; /* PWMX Fault State */ 9145 } B; 9146 } mcPWM_OCTRL_16B_tag; 9147 9148 9149 /* Register layout for all registers STS... */ 9150 9151 typedef union { /* Status Register */ 9152 uint16_t R; 9153 struct { 9154 uint16_t:1; 9155 uint16_t RUF:1; /* Registers Updated Flag */ 9156 uint16_t REF:1; /* Reload Error Flag */ 9157 uint16_t RF:1; /* Reload Flag */ 9158 uint16_t CFA1:1; /* Capture Flag A1 */ 9159 uint16_t CFA0:1; /* Capture Flag A0 */ 9160 uint16_t CFB1:1; /* Capture Flag B1 */ 9161 uint16_t CFB0:1; /* Capture Flag B0 */ 9162 uint16_t CFX1:1; /* Capture Flag X1 */ 9163 uint16_t CFX0:1; /* Capture Flag X0 */ 9164 uint16_t CMPF:6; /* Compare Flags */ 9165 } B; 9166 } mcPWM_STS_16B_tag; 9167 9168 9169 /* Register layout for all registers INTEN... */ 9170 9171 typedef union { /* Interrupt Enable Registers */ 9172 uint16_t R; 9173 struct { 9174 uint16_t:2; 9175 uint16_t REIE:1; /* Reload Error Interrupt Enable */ 9176 uint16_t RIE:1; /* Reload Interrupt Enable */ 9177 uint16_t CA1IE:1; /* Capture A1 Interrupt Enable */ 9178 uint16_t CA0IE:1; /* Capture A0 Interrupt Enable */ 9179 uint16_t CB1IE:1; /* Capture B1 Interrupt Enable */ 9180 uint16_t CB0IE:1; /* Capture B0 Interrupt Enable */ 9181 uint16_t CX1IE:1; /* Capture X1 Interrupt Enable */ 9182 uint16_t CX0IE:1; /* Capture X0 Interrupt Enable */ 9183 uint16_t CMPIE:6; /* Compare Interrupt Enables */ 9184 } B; 9185 } mcPWM_INTEN_16B_tag; 9186 9187 9188 /* Register layout for all registers DMAEN... */ 9189 9190 typedef union { /* DMA Enable Registers */ 9191 uint16_t R; 9192 struct { 9193 uint16_t:6; 9194 uint16_t VALDE:1; /* Value Register DMA Enable */ 9195 uint16_t FAND:1; /* FIFO Watermark AND Control */ 9196 uint16_t CAPTDE:2; /* Capture DMA Enable Source Select */ 9197 uint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */ 9198 uint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */ 9199 uint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */ 9200 uint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */ 9201 uint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */ 9202 uint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */ 9203 } B; 9204 } mcPWM_DMAEN_16B_tag; 9205 9206 9207 /* Register layout for all registers TCTRL... */ 9208 9209 typedef union { /* Output Trigger Control Registers */ 9210 uint16_t R; 9211 struct { 9212 uint16_t:10; 9213 uint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */ 9214 } B; 9215 } mcPWM_TCTRL_16B_tag; 9216 9217 9218 /* Register layout for all registers DISMAP... */ 9219 9220 typedef union { /* Fault Disable Mapping Registers */ 9221 uint16_t R; 9222 struct { 9223 uint16_t:4; 9224 uint16_t DISX:4; /* PWMX Fault Disable Mask */ 9225 uint16_t DISB:4; /* PWMB Fault Disable Mask */ 9226 uint16_t DISA:4; /* PWMA Fault Disable Mask */ 9227 } B; 9228 } mcPWM_DISMAP_16B_tag; 9229 9230 9231 /* Register layout for all registers DTCNT0... */ 9232 9233 typedef union { /* Deadtime Count Register 0 */ 9234 uint16_t R; 9235 struct { 9236 uint16_t:5; 9237 uint16_t DTCNT0:11; /* Deadtime Count Register 0 */ 9238 } B; 9239 } mcPWM_DTCNT0_16B_tag; 9240 9241 9242 /* Register layout for all registers DTCNT1... */ 9243 9244 typedef union { /* Deadtime Count Register 1 */ 9245 uint16_t R; 9246 struct { 9247 uint16_t:5; 9248 uint16_t DTCNT1:11; /* Deadtime Count Register 1 */ 9249 } B; 9250 } mcPWM_DTCNT1_16B_tag; 9251 9252 /* Register layout for all registers CAPTCTRLX... */ 9253 9254 typedef union { /* Capture Control X Register */ 9255 uint16_t R; 9256 struct { 9257 uint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */ 9258 uint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */ 9259 uint16_t CFXWM:2; /* Capture X FIFOs Water Mark */ 9260 #ifndef USE_FIELD_ALIASES_mcPWM 9261 uint16_t EDGCNTXEN:1; /* Edge Counter X Enable */ 9262 #else 9263 uint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */ 9264 #endif 9265 #ifndef USE_FIELD_ALIASES_mcPWM 9266 uint16_t INPSELX:1; /* Input Select X */ 9267 #else 9268 uint16_t INP_SELX:1; /* deprecated name - please avoid */ 9269 #endif 9270 uint16_t EDGX1:2; /* Edge X 1 */ 9271 uint16_t EDGX0:2; /* Edge X 0 */ 9272 uint16_t ONESHOTX:1; /* One Shot Mode X */ 9273 uint16_t ARMX:1; /* Arm X */ 9274 } B; 9275 } mcPWM_CAPTCTRLX_16B_tag; 9276 9277 9278 /* Register layout for all registers CAPTCMPX... */ 9279 9280 typedef union { /* Capture Compare X Register */ 9281 uint16_t R; 9282 struct { 9283 uint16_t EDGCNTX:8; /* Edge Counter X */ 9284 uint16_t EDGCMPX:8; /* Edge Compare X */ 9285 } B; 9286 } mcPWM_CAPTCMPX_16B_tag; 9287 9288 9289 /* Register layout for all registers CVAL0... */ 9290 9291 typedef union { /* Capture Value 0 Register */ 9292 uint16_t R; 9293 struct { 9294 uint16_t CAPTVAL0:16; /* Captured value from submodule counter */ 9295 } B; 9296 } mcPWM_CVAL0_16B_tag; 9297 9298 9299 /* Register layout for all registers CVAL0CYC... */ 9300 9301 typedef union { /* Capture Value 0 Cycle Register */ 9302 uint16_t R; 9303 struct { 9304 uint16_t:12; 9305 uint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */ 9306 } B; 9307 } mcPWM_CVAL0CYC_16B_tag; 9308 9309 9310 /* Register layout for all registers CVAL1... */ 9311 9312 typedef union { /* Capture Value 1 Register */ 9313 uint16_t R; 9314 struct { 9315 uint16_t CAPTVAL1:16; /* Captured value from submodule counter */ 9316 } B; 9317 } mcPWM_CVAL1_16B_tag; 9318 9319 9320 /* Register layout for all registers CVAL1CYC... */ 9321 9322 typedef union { /* Capture Value 1 Cycle Register */ 9323 uint16_t R; 9324 struct { 9325 uint16_t:12; 9326 uint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */ 9327 } B; 9328 } mcPWM_CVAL1CYC_16B_tag; 9329 9330 9331 /* Register layout for all registers CVAL3... */ 9332 9333 typedef union { /* Capture Value 3 Register */ 9334 uint16_t R; 9335 struct { 9336 uint16_t CAPTVAL3:16; /* Captured value from submodule counter */ 9337 } B; 9338 } mcPWM_CVAL3_16B_tag; 9339 9340 9341 /* Register layout for all registers CVAL3CYC... */ 9342 9343 typedef union { /* Capture Value 3 Cycle Register */ 9344 uint16_t R; 9345 struct { 9346 uint16_t:12; 9347 uint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */ 9348 } B; 9349 } mcPWM_CVAL3CYC_16B_tag; 9350 9351 9352 /* Register layout for all registers CVAL4... */ 9353 9354 typedef union { /* Capture Value 4 Register */ 9355 uint16_t R; 9356 struct { 9357 uint16_t CAPTVAL4:16; /* Captured value from submodule counter */ 9358 } B; 9359 } mcPWM_CVAL4_16B_tag; 9360 9361 9362 /* Register layout for all registers CVAL4CYC... */ 9363 9364 typedef union { /* Capture Value 4 Cycle Register */ 9365 uint16_t R; 9366 struct { 9367 uint16_t:12; 9368 uint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */ 9369 } B; 9370 } mcPWM_CVAL4CYC_16B_tag; 9371 9372 9373 /* Register layout for all registers CVAL5... */ 9374 9375 typedef union { /* Capture Value 5 Register */ 9376 uint16_t R; 9377 struct { 9378 uint16_t CAPTVAL5:16; /* Captured value from submodule counter */ 9379 } B; 9380 } mcPWM_CVAL5_16B_tag; 9381 9382 9383 /* Register layout for all registers CVAL5CYC... */ 9384 9385 typedef union { /* Capture Value 5 Cycle Register */ 9386 uint16_t R; 9387 struct { 9388 uint16_t:12; 9389 uint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */ 9390 } B; 9391 } mcPWM_CVAL5CYC_16B_tag; 9392 9393 typedef union { /* Output Enable Register */ 9394 uint16_t R; 9395 struct { 9396 uint16_t:4; 9397 uint16_t PWMA_EN:4; /* PWMA Output Enables */ 9398 uint16_t PWMB_EN:4; /* PWMB Output Enables */ 9399 uint16_t PWMX_EN:4; /* PWMX Output Enables */ 9400 } B; 9401 } mcPWM_OUTEN_16B_tag; 9402 9403 typedef union { /* Mask Register */ 9404 uint16_t R; 9405 struct { 9406 uint16_t:4; 9407 uint16_t MASKA:4; /* PWMA Masks */ 9408 uint16_t MASKB:4; /* PWMB Masks */ 9409 uint16_t MASKX:4; /* PWMX Masks */ 9410 } B; 9411 } mcPWM_MASK_16B_tag; 9412 9413 typedef union { /* Software Controlled Output Register */ 9414 uint16_t R; 9415 struct { 9416 uint16_t:8; 9417 #ifndef USE_FIELD_ALIASES_mcPWM 9418 uint16_t OUT23_3:1; /* Software Controlled Output 23_3 */ 9419 #else 9420 uint16_t OUTA_3:1; /* deprecated name - please avoid */ 9421 #endif 9422 #ifndef USE_FIELD_ALIASES_mcPWM 9423 uint16_t OUT45_3:1; /* Software Controlled Output 45_3 */ 9424 #else 9425 uint16_t OUTB_3:1; /* deprecated name - please avoid */ 9426 #endif 9427 #ifndef USE_FIELD_ALIASES_mcPWM 9428 uint16_t OUT23_2:1; /* Software Controlled Output 23_2 */ 9429 #else 9430 uint16_t OUTA_2:1; /* deprecated name - please avoid */ 9431 #endif 9432 #ifndef USE_FIELD_ALIASES_mcPWM 9433 uint16_t OUT45_2:1; /* Software Controlled Output 45_2 */ 9434 #else 9435 uint16_t OUTB_2:1; /* deprecated name - please avoid */ 9436 #endif 9437 #ifndef USE_FIELD_ALIASES_mcPWM 9438 uint16_t OUT23_1:1; /* Software Controlled Output 23_1 */ 9439 #else 9440 uint16_t OUTA_1:1; /* deprecated name - please avoid */ 9441 #endif 9442 #ifndef USE_FIELD_ALIASES_mcPWM 9443 uint16_t OUT45_1:1; /* Software Controlled Output 45_1 */ 9444 #else 9445 uint16_t OUTB_1:1; /* deprecated name - please avoid */ 9446 #endif 9447 #ifndef USE_FIELD_ALIASES_mcPWM 9448 uint16_t OUT23_0:1; /* Software Controlled Output 23_0 */ 9449 #else 9450 uint16_t OUTA_0:1; /* deprecated name - please avoid */ 9451 #endif 9452 #ifndef USE_FIELD_ALIASES_mcPWM 9453 uint16_t OUT45_0:1; /* Software Controlled Output 45_0 */ 9454 #else 9455 uint16_t OUTB_0:1; /* deprecated name - please avoid */ 9456 #endif 9457 } B; 9458 } mcPWM_SWCOUT_16B_tag; 9459 9460 typedef union { /* Deadtime Source Select Register */ 9461 uint16_t R; 9462 struct { 9463 #ifndef USE_FIELD_ALIASES_mcPWM 9464 uint16_t SEL23_3:2; /* PWM23_3 Control Select */ 9465 #else 9466 uint16_t SELA_3:2; /* deprecated name - please avoid */ 9467 #endif 9468 #ifndef USE_FIELD_ALIASES_mcPWM 9469 uint16_t SEL45_3:2; /* PWM45_3 Control Select */ 9470 #else 9471 uint16_t SELB_3:2; /* deprecated name - please avoid */ 9472 #endif 9473 #ifndef USE_FIELD_ALIASES_mcPWM 9474 uint16_t SEL23_2:2; /* PWM23_2 Control Select */ 9475 #else 9476 uint16_t SELA_2:2; /* deprecated name - please avoid */ 9477 #endif 9478 #ifndef USE_FIELD_ALIASES_mcPWM 9479 uint16_t SEL45_2:2; /* PWM45_2 Control Select */ 9480 #else 9481 uint16_t SELB_2:2; /* deprecated name - please avoid */ 9482 #endif 9483 #ifndef USE_FIELD_ALIASES_mcPWM 9484 uint16_t SEL23_1:2; /* PWM23_1 Control Select */ 9485 #else 9486 uint16_t SELA_1:2; /* deprecated name - please avoid */ 9487 #endif 9488 #ifndef USE_FIELD_ALIASES_mcPWM 9489 uint16_t SEL45_1:2; /* PWM45_1 Control Select */ 9490 #else 9491 uint16_t SELB_1:2; /* deprecated name - please avoid */ 9492 #endif 9493 #ifndef USE_FIELD_ALIASES_mcPWM 9494 uint16_t SEL23_0:2; /* PWM23_0 Control Select */ 9495 #else 9496 uint16_t SELA_0:2; /* deprecated name - please avoid */ 9497 #endif 9498 #ifndef USE_FIELD_ALIASES_mcPWM 9499 uint16_t SEL45_0:2; /* PWM45_0 Control Select */ 9500 #else 9501 uint16_t SELB_0:2; /* deprecated name - please avoid */ 9502 #endif 9503 } B; 9504 } mcPWM_DTSRCSEL_16B_tag; 9505 9506 typedef union { /* Master Control Register */ 9507 uint16_t R; 9508 struct { 9509 uint16_t IPOL:4; /* Current Polarity */ 9510 uint16_t RUN:4; /* Run */ 9511 #ifndef USE_FIELD_ALIASES_mcPWM 9512 uint16_t CLOK:4; /* Clear Load Okay */ 9513 #else 9514 uint16_t CLDOK:4; /* deprecated name - please avoid */ 9515 #endif 9516 uint16_t LDOK:4; /* Load Okay */ 9517 } B; 9518 } mcPWM_MCTRL_16B_tag; 9519 9520 typedef union { /* Fault Control Register */ 9521 uint16_t R; 9522 struct { 9523 uint16_t FLVL:4; /* Fault Level */ 9524 uint16_t FAUTO:4; /* Automatic Fault Clearing */ 9525 uint16_t FSAFE:4; /* Fault Safety Mode */ 9526 uint16_t FIE:4; /* Fault Interrupt Enables */ 9527 } B; 9528 } mcPWM_FCTRL_16B_tag; 9529 9530 typedef union { /* Fault Status Register */ 9531 uint16_t R; 9532 struct { 9533 uint16_t:3; 9534 uint16_t FTEST:1; /* Fault Test */ 9535 uint16_t FFPIN:4; /* Filtered Fault Pins */ 9536 uint16_t:4; 9537 uint16_t FFLAG:4; /* Fault Flags */ 9538 } B; 9539 } mcPWM_FSTS_16B_tag; 9540 9541 typedef union { /* Fault Filter Register */ 9542 uint16_t R; 9543 struct { 9544 uint16_t:5; 9545 uint16_t FILT_CNT:3; /* Fault Filter Count */ 9546 uint16_t FILT_PER:8; /* Fault Filter Period */ 9547 } B; 9548 } mcPWM_FFILT_16B_tag; 9549 9550 9551 /* Register layout for generated register(s) VAL... */ 9552 9553 typedef union { /* */ 9554 uint16_t R; 9555 } mcPWM_VAL_16B_tag; 9556 9557 9558 typedef struct mcPWM_SUBMOD_struct_tag { 9559 9560 /* Counter Register */ 9561 mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */ 9562 /* Initial Counter Register */ 9563 mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */ 9564 /* Control 2 Register */ 9565 mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */ 9566 union { 9567 /* Control Register */ 9568 mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */ 9569 mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ 9570 }; 9571 /* Value Register 0 */ 9572 9573 union { 9574 9575 struct { 9576 9577 mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */ 9578 /* Value Register 1 */ 9579 mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */ 9580 /* Value Register 2 */ 9581 mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */ 9582 /* Value Register 3 */ 9583 mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */ 9584 /* Value Register 4 */ 9585 mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */ 9586 /* Value Register 5 */ 9587 mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */ 9588 9589 }; 9590 9591 mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */ 9592 9593 }; 9594 int8_t mcPWM_reserved_0014[4]; 9595 /* Output Control Register */ 9596 mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */ 9597 /* Status Register */ 9598 mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */ 9599 /* Interrupt Enable Registers */ 9600 mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */ 9601 /* DMA Enable Registers */ 9602 mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */ 9603 /* Output Trigger Control Registers */ 9604 mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */ 9605 /* Fault Disable Mapping Registers */ 9606 mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */ 9607 /* Deadtime Count Register 0 */ 9608 mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */ 9609 /* Deadtime Count Register 1 */ 9610 mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */ 9611 /* Capture Control A Register */ 9612 int8_t mcPWM_reserved_0028[8]; 9613 /* Capture Control X Register */ 9614 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */ 9615 union { 9616 /* Capture Compare X Register */ 9617 mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */ 9618 mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */ 9619 }; 9620 /* Capture Value 0 Register */ 9621 mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */ 9622 union { 9623 /* Capture Value 0 Cycle Register */ 9624 mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */ 9625 mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */ 9626 }; 9627 /* Capture Value 1 Register */ 9628 mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */ 9629 union { 9630 /* Capture Value 1 Cycle Register */ 9631 mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */ 9632 mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */ 9633 }; 9634 /* Capture Value 2 Register */ 9635 int8_t mcPWM_SUBMOD_reserved_003C[16]; 9636 int8_t mcPWM_SUBMOD_reserved_004C[4]; 9637 9638 } mcPWM_SUBMOD_tag; 9639 9640 9641 typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */ 9642 union { 9643 /* Register set SUBMOD */ 9644 mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */ 9645 9646 mcPWM_SUBMOD_tag SUB[4]; /* offset: 0x0000 (0x0050 x 4) */ 9647 9648 struct { 9649 /* Counter Register */ 9650 mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */ 9651 /* Initial Counter Register */ 9652 mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */ 9653 /* Control 2 Register */ 9654 mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */ 9655 /* Control Register */ 9656 mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */ 9657 /* Value Register 0 */ 9658 mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */ 9659 /* Value Register 1 */ 9660 mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */ 9661 /* Value Register 2 */ 9662 mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */ 9663 /* Value Register 3 */ 9664 mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */ 9665 /* Value Register 4 */ 9666 mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */ 9667 /* Value Register 5 */ 9668 mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */ 9669 int8_t mcPWM_reserved_0014[4]; 9670 /* Output Control Register */ 9671 mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */ 9672 /* Status Register */ 9673 mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */ 9674 /* Interrupt Enable Registers */ 9675 mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */ 9676 /* DMA Enable Registers */ 9677 mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */ 9678 /* Output Trigger Control Registers */ 9679 mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */ 9680 /* Fault Disable Mapping Registers */ 9681 mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */ 9682 /* Deadtime Count Register 0 */ 9683 mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */ 9684 /* Deadtime Count Register 1 */ 9685 mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */ 9686 int8_t mcPWM_reserved_0028[8]; 9687 /* Capture Control X Register */ 9688 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */ 9689 /* Capture Compare X Register */ 9690 mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */ 9691 /* Capture Value 0 Register */ 9692 mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */ 9693 /* Capture Value 0 Cycle Register */ 9694 mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */ 9695 /* Capture Value 1 Register */ 9696 mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */ 9697 /* Capture Value 1 Cycle Register */ 9698 mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */ 9699 int8_t mcPWM_reserved_003c[16]; 9700 int8_t mcPWM_reserved_004C_I2[4]; 9701 /* Counter Register */ 9702 mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */ 9703 /* Initial Counter Register */ 9704 mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */ 9705 /* Control 2 Register */ 9706 mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */ 9707 /* Control Register */ 9708 mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */ 9709 /* Value Register 0 */ 9710 mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */ 9711 /* Value Register 1 */ 9712 mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */ 9713 /* Value Register 2 */ 9714 mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */ 9715 /* Value Register 3 */ 9716 mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */ 9717 /* Value Register 4 */ 9718 mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */ 9719 /* Value Register 5 */ 9720 mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */ 9721 int8_t mcPWM_reserved_0064[4]; 9722 /* Output Control Register */ 9723 mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */ 9724 /* Status Register */ 9725 mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */ 9726 /* Interrupt Enable Registers */ 9727 mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */ 9728 /* DMA Enable Registers */ 9729 mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */ 9730 /* Output Trigger Control Registers */ 9731 mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */ 9732 /* Fault Disable Mapping Registers */ 9733 mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */ 9734 /* Deadtime Count Register 0 */ 9735 mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */ 9736 /* Deadtime Count Register 1 */ 9737 mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */ 9738 /* Capture Control A Register */ 9739 int8_t mcPWM_reserved_0078[8]; 9740 /* Capture Control X Register */ 9741 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */ 9742 /* Capture Compare X Register */ 9743 mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */ 9744 /* Capture Value 0 Register */ 9745 mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */ 9746 /* Capture Value 0 Cycle Register */ 9747 mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */ 9748 /* Capture Value 1 Register */ 9749 mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */ 9750 /* Capture Value 1 Cycle Register */ 9751 mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */ 9752 int8_t mcPWM_reserved_008c[16]; 9753 int8_t mcPWM_reserved_009C_I2[4]; 9754 /* Counter Register */ 9755 mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */ 9756 /* Initial Counter Register */ 9757 mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */ 9758 /* Control 2 Register */ 9759 mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */ 9760 /* Control Register */ 9761 mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */ 9762 /* Value Register 0 */ 9763 mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */ 9764 /* Value Register 1 */ 9765 mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */ 9766 /* Value Register 2 */ 9767 mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */ 9768 /* Value Register 3 */ 9769 mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */ 9770 /* Value Register 4 */ 9771 mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */ 9772 /* Value Register 5 */ 9773 mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */ 9774 int8_t mcPWM_reserved_00b4[4]; 9775 /* Output Control Register */ 9776 mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */ 9777 /* Status Register */ 9778 mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */ 9779 /* Interrupt Enable Registers */ 9780 mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */ 9781 /* DMA Enable Registers */ 9782 mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */ 9783 /* Output Trigger Control Registers */ 9784 mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */ 9785 /* Fault Disable Mapping Registers */ 9786 mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */ 9787 /* Deadtime Count Register 0 */ 9788 mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */ 9789 /* Deadtime Count Register 1 */ 9790 mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */ 9791 /* Capture Control A Register */ 9792 int8_t mcPWM_reserved_00c8[8]; 9793 /* Capture Control X Register */ 9794 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */ 9795 /* Capture Compare X Register */ 9796 mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */ 9797 /* Capture Value 0 Register */ 9798 mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */ 9799 /* Capture Value 0 Cycle Register */ 9800 mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */ 9801 /* Capture Value 1 Register */ 9802 mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */ 9803 /* Capture Value 1 Cycle Register */ 9804 mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */ 9805 int8_t mcPWM_reserved_00dc[16]; 9806 int8_t mcPWM_reserved_00EC_I2[4]; 9807 /* Counter Register */ 9808 mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */ 9809 /* Initial Counter Register */ 9810 mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */ 9811 /* Control 2 Register */ 9812 mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */ 9813 /* Control Register */ 9814 mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */ 9815 /* Value Register 0 */ 9816 mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */ 9817 /* Value Register 1 */ 9818 mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */ 9819 /* Value Register 2 */ 9820 mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */ 9821 /* Value Register 3 */ 9822 mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */ 9823 /* Value Register 4 */ 9824 mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */ 9825 /* Value Register 5 */ 9826 mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */ 9827 int8_t mcPWM_reserved_00104[4]; 9828 /* Output Control Register */ 9829 mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */ 9830 /* Status Register */ 9831 mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */ 9832 /* Interrupt Enable Registers */ 9833 mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */ 9834 /* DMA Enable Registers */ 9835 mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */ 9836 /* Output Trigger Control Registers */ 9837 mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */ 9838 /* Fault Disable Mapping Registers */ 9839 mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */ 9840 /* Deadtime Count Register 0 */ 9841 mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */ 9842 /* Deadtime Count Register 1 */ 9843 mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */ 9844 /* Capture Control A Register */ 9845 int8_t mcPWM_reserved_00118[8]; 9846 /* Capture Control X Register */ 9847 mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */ 9848 /* Capture Compare X Register */ 9849 mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */ 9850 /* Capture Value 0 Register */ 9851 mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */ 9852 /* Capture Value 0 Cycle Register */ 9853 mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */ 9854 /* Capture Value 1 Register */ 9855 mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */ 9856 /* Capture Value 1 Cycle Register */ 9857 mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */ 9858 int8_t mcPWM_reserved_0012c[16]; 9859 int8_t mcPWM_reserved_013C_E2[4]; 9860 }; 9861 9862 }; 9863 /* Output Enable Register */ 9864 mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */ 9865 /* Mask Register */ 9866 mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */ 9867 /* Software Controlled Output Register */ 9868 mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */ 9869 /* Deadtime Source Select Register */ 9870 mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */ 9871 /* Master Control Register */ 9872 mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */ 9873 int8_t mcPWM_reserved_014A[2]; 9874 /* Fault Control Register */ 9875 mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */ 9876 /* Fault Status Register */ 9877 mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */ 9878 /* Fault Filter Register */ 9879 mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */ 9880 } mcPWM_tag; 9881 9882 9883 #define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL) 9884 #define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL) 9885 9886 9887 9888 /****************************************************************/ 9889 /* */ 9890 /* Module: LINFLEX */ 9891 /* */ 9892 /****************************************************************/ 9893 9894 typedef union { /* LIN Control Register */ 9895 uint32_t R; 9896 struct { 9897 uint32_t:16; 9898 uint32_t CCD:1; /* Checksum Calculation Disable */ 9899 uint32_t CFD:1; /* Checksum Field Disable */ 9900 uint32_t LASE:1; /* LIN Auto Synchronization Enable */ 9901 #ifndef USE_FIELD_ALIASES_LINFLEX 9902 uint32_t AUTOWU:1; /* Auto Wake Up */ 9903 #else 9904 uint32_t AWUM:1; /* deprecated name - please avoid */ 9905 #endif 9906 uint32_t MBL:4; /* Master Break Length */ 9907 uint32_t BF:1; /* By-Pass Filter */ 9908 #ifndef USE_FIELD_ALIASES_LINFLEX 9909 uint32_t SLFM:1; /* Selftest Mode */ 9910 #else 9911 uint32_t SFTM:1; /* deprecated name - please avoid */ 9912 #endif 9913 uint32_t LBKM:1; /* Loopback Mode */ 9914 uint32_t MME:1; /* Master Mode Enable */ 9915 #ifndef USE_FIELD_ALIASES_LINFLEX 9916 uint32_t SSBL:1; /* Slave Mode Synch Break Length */ 9917 #else 9918 uint32_t SSDT:1; /* deprecated name - please avoid */ 9919 #endif 9920 uint32_t RBLM:1; /* Receiver Buffer Locked Mode */ 9921 uint32_t SLEEP:1; /* Sleep Mode Request */ 9922 uint32_t INIT:1; /* Initialization Mode Request */ 9923 } B; 9924 } LINFLEX_LINCR1_32B_tag; 9925 9926 typedef union { /* LIN Interrupt Enable Register */ 9927 uint32_t R; 9928 struct { 9929 uint32_t:16; 9930 uint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */ 9931 uint32_t OCIE:1; /* Output Compare Interrupt Enable */ 9932 uint32_t BEIE:1; /* Bit Error Interrupt Enable */ 9933 uint32_t CEIE:1; /* Checksum Error Interrupt Enable */ 9934 uint32_t HEIE:1; /* Header Error Interrupt Enable */ 9935 uint32_t:2; 9936 uint32_t FEIE:1; /* Frame Error Interrupt Enable */ 9937 uint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */ 9938 uint32_t LSIE:1; /* LIN State Interrupt Enable */ 9939 uint32_t WUIE:1; /* Wakeup Interrupt Enable */ 9940 uint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */ 9941 #ifndef USE_FIELD_ALIASES_LINFLEX 9942 uint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */ 9943 #else 9944 uint32_t DBEIE:1; /* deprecated name - please avoid */ 9945 #endif 9946 uint32_t DRIE:1; /* Data Reception complete Interrupt Enable */ 9947 uint32_t DTIE:1; /* Data Transmitted Interrupt Enable */ 9948 uint32_t HRIE:1; /* Header Received Interrupt Enable */ 9949 } B; 9950 } LINFLEX_LINIER_32B_tag; 9951 9952 typedef union { /* LIN Status Register */ 9953 uint32_t R; 9954 struct { 9955 uint32_t:16; 9956 uint32_t LINS:4; /* LIN State */ 9957 uint32_t:2; 9958 uint32_t RMB:1; /* Release Message Buffer */ 9959 uint32_t:1; 9960 #ifndef USE_FIELD_ALIASES_LINFLEX 9961 uint32_t RXBUSY:1; /* Receiver Busy Flag */ 9962 #else 9963 uint32_t RBSY:1; /* deprecated name - please avoid */ 9964 #endif 9965 #ifndef USE_FIELD_ALIASES_LINFLEX 9966 uint32_t RDI:1; /* LIN Receive Signal */ 9967 #else 9968 uint32_t RPS:1; /* deprecated name - please avoid */ 9969 #endif 9970 uint32_t WUF:1; /* Wake Up Flag */ 9971 uint32_t DBFF:1; /* Data Buffer Full Flag */ 9972 uint32_t DBEF:1; /* Data Buffer Empty Flag */ 9973 uint32_t DRF:1; /* Data Reception Completed Flag */ 9974 uint32_t DTF:1; /* Data Transmission Completed Flag */ 9975 uint32_t HRF:1; /* Header Received Flag */ 9976 } B; 9977 } LINFLEX_LINSR_32B_tag; 9978 9979 typedef union { /* LIN Error Status Register */ 9980 uint32_t R; 9981 struct { 9982 uint32_t:16; 9983 uint32_t SZF:1; /* Stuck at Zero Flag */ 9984 uint32_t OCF:1; /* Output Compare Flag */ 9985 uint32_t BEF:1; /* Bit Error Flag */ 9986 uint32_t CEF:1; /* Checksum Error Flag */ 9987 uint32_t SFEF:1; /* Sync Field Error Flag */ 9988 #ifndef USE_FIELD_ALIASES_LINFLEX 9989 uint32_t SDEF:1; /* Sync Delimiter Error Flag */ 9990 #else 9991 uint32_t BDEF:1; /* deprecated name - please avoid */ 9992 #endif 9993 uint32_t IDPEF:1; /* ID Parity Error Flag */ 9994 uint32_t FEF:1; /* Framing Error Flag */ 9995 uint32_t BOF:1; /* Buffer Overrun Flag */ 9996 uint32_t:6; 9997 uint32_t NF:1; /* Noise Flag */ 9998 } B; 9999 } LINFLEX_LINESR_32B_tag; 10000 10001 typedef union { /* UART Mode Control Register */ 10002 uint32_t R; 10003 struct { 10004 uint32_t:16; 10005 uint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */ 10006 uint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */ 10007 uint32_t RFBM:1; /* RX FIFO/ Buffer Mode */ 10008 uint32_t TFBM:1; /* TX FIFO/ Buffer Mode */ 10009 uint32_t WL1:1; /* Word Length in UART mode - bit 1 */ 10010 uint32_t PC1:1; /* Parity Check - bit 1 */ 10011 uint32_t RXEN:1; /* Receiver Enable */ 10012 uint32_t TXEN:1; /* Transmitter Enable */ 10013 #ifndef USE_FIELD_ALIASES_LINFLEX 10014 uint32_t PC0:1; /* Parity Check - bit 0 */ 10015 #else 10016 uint32_t OP:1; /* deprecated name - please avoid */ 10017 #endif 10018 uint32_t PCE:1; /* Parity Control Enable */ 10019 #ifndef USE_FIELD_ALIASES_LINFLEX 10020 uint32_t WL0:1; /* Word Length in UART Mode - bit 0 */ 10021 #else 10022 uint32_t WL:1; /* deprecated name - please avoid */ 10023 #endif 10024 uint32_t UART:1; /* UART Mode */ 10025 } B; 10026 } LINFLEX_UARTCR_32B_tag; 10027 10028 typedef union { /* UART Mode Status Register */ 10029 uint32_t R; 10030 struct { 10031 uint32_t:16; 10032 uint32_t SZF:1; /* Stuck at Zero Flag */ 10033 uint32_t OCF:1; /* Output Compare Flag */ 10034 uint32_t PE:4; /* Parity Error Flag */ 10035 uint32_t RMB:1; /* Release Message Buffer */ 10036 uint32_t FEF:1; /* Framing Error Flag */ 10037 uint32_t BOF:1; /* Buffer Overrun Flag */ 10038 uint32_t RDI:1; /* Receiver Data Input Signal */ 10039 uint32_t WUF:1; /* Wakeup Flag */ 10040 uint32_t:1; 10041 uint32_t TO:1; /* Time Out */ 10042 #ifndef USE_FIELD_ALIASES_LINFLEX 10043 uint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */ 10044 #else 10045 uint32_t DRF:1; /* deprecated name - please avoid */ 10046 #endif 10047 #ifndef USE_FIELD_ALIASES_LINFLEX 10048 uint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */ 10049 #else 10050 uint32_t DTF:1; /* deprecated name - please avoid */ 10051 #endif 10052 uint32_t NF:1; /* Noise Flag */ 10053 } B; 10054 } LINFLEX_UARTSR_32B_tag; 10055 10056 typedef union { /* LIN Time-Out Control Status Register */ 10057 uint32_t R; 10058 struct { 10059 uint32_t:21; 10060 #ifndef USE_FIELD_ALIASES_LINFLEX 10061 uint32_t MODE:1; /* Time-out Counter Mode */ 10062 #else 10063 uint32_t LTOM:1; /* deprecated name - please avoid */ 10064 #endif 10065 uint32_t IOT:1; /* Idle on Timeout */ 10066 uint32_t TOCE:1; /* Time-Out Counter Enable */ 10067 uint32_t CNT:8; /* Counter Value */ 10068 } B; 10069 } LINFLEX_LINTCSR_32B_tag; 10070 10071 typedef union { /* LIN Output Compare Register */ 10072 uint32_t R; 10073 struct { 10074 uint32_t:16; 10075 uint32_t OC2:8; /* Output Compare Value 2 */ 10076 uint32_t OC1:8; /* Output Compare Value 1 */ 10077 } B; 10078 } LINFLEX_LINOCR_32B_tag; 10079 10080 typedef union { /* LIN Time-Out Control Register */ 10081 uint32_t R; 10082 struct { 10083 uint32_t:20; 10084 uint32_t RTO:4; /* Response Time-Out Value */ 10085 uint32_t:1; 10086 uint32_t HTO:7; /* Header Time-Out Value */ 10087 } B; 10088 } LINFLEX_LINTOCR_32B_tag; 10089 10090 typedef union { /* LIN Fractional Baud Rate Register */ 10091 uint32_t R; 10092 struct { 10093 uint32_t:28; 10094 #ifndef USE_FIELD_ALIASES_LINFLEX 10095 uint32_t FBR:4; /* Fractional Baud Rates */ 10096 #else 10097 uint32_t DIV_F:4; /* deprecated name - please avoid */ 10098 #endif 10099 } B; 10100 } LINFLEX_LINFBRR_32B_tag; 10101 10102 typedef union { /* LIN Integer Baud Rate Register */ 10103 uint32_t R; 10104 struct { 10105 uint32_t:13; 10106 #ifndef USE_FIELD_ALIASES_LINFLEX 10107 uint32_t IBR:19; /* Integer Baud Rates */ 10108 #else 10109 uint32_t DIV_M:19; /* deprecated name - please avoid */ 10110 #endif 10111 } B; 10112 } LINFLEX_LINIBRR_32B_tag; 10113 10114 typedef union { /* LIN Checksum Field Register */ 10115 uint32_t R; 10116 struct { 10117 uint32_t:24; 10118 uint32_t CF:8; /* Checksum Bits */ 10119 } B; 10120 } LINFLEX_LINCFR_32B_tag; 10121 10122 typedef union { /* LIN Control Register 2 */ 10123 uint32_t R; 10124 struct { 10125 uint32_t:17; 10126 uint32_t IOBE:1; /* Idle on Bit Error */ 10127 uint32_t IOPE:1; /* Idle on Identifier Parity Error */ 10128 uint32_t WURQ:1; /* Wakeup Generate Request */ 10129 uint32_t DDRQ:1; /* Data Discard Request */ 10130 uint32_t DTRQ:1; /* Data Transmission Request */ 10131 uint32_t ABRQ:1; /* Abort Request */ 10132 uint32_t HTRQ:1; /* Header Transmission Request */ 10133 uint32_t:8; 10134 } B; 10135 } LINFLEX_LINCR2_32B_tag; 10136 10137 typedef union { /* Buffer Identifier Register */ 10138 uint32_t R; 10139 struct { 10140 uint32_t:16; 10141 uint32_t DFL:6; /* Data Field Length */ 10142 uint32_t DIR:1; /* Direction */ 10143 uint32_t CCS:1; /* Classic Checksum */ 10144 uint32_t:2; 10145 uint32_t ID:6; /* Identifier */ 10146 } B; 10147 } LINFLEX_BIDR_32B_tag; 10148 10149 typedef union { /* Buffer Data Register Least Significant */ 10150 uint32_t R; 10151 struct { 10152 uint32_t DATA3:8; /* Data3 */ 10153 uint32_t DATA2:8; /* Data2 */ 10154 uint32_t DATA1:8; /* Data1 */ 10155 uint32_t DATA0:8; /* Data0 */ 10156 } B; 10157 } LINFLEX_BDRL_32B_tag; 10158 10159 typedef union { /* Buffer Data Register Most Significant */ 10160 uint32_t R; 10161 struct { 10162 uint32_t DATA7:8; /* Data7 */ 10163 uint32_t DATA6:8; /* Data6 */ 10164 uint32_t DATA5:8; /* Data5 */ 10165 uint32_t DATA4:8; /* Data4 */ 10166 } B; 10167 } LINFLEX_BDRM_32B_tag; 10168 10169 typedef union { /* Identifier Filter Enable Register */ 10170 uint32_t R; 10171 struct { 10172 uint32_t:24; 10173 uint32_t FACT:8; /* Filter Active */ 10174 } B; 10175 } LINFLEX_IFER_32B_tag; 10176 10177 typedef union { /* Identifier Filter Match Index */ 10178 uint32_t R; 10179 struct { 10180 uint32_t:28; 10181 uint32_t IFMI_IFMI:4; /* Filter Match Index */ 10182 } B; 10183 } LINFLEX_IFMI_32B_tag; 10184 10185 typedef union { /* Identifier Filter Mode Register */ 10186 uint32_t R; 10187 struct { 10188 uint32_t:28; 10189 uint32_t IFM:4; /* Filter Mode */ 10190 } B; 10191 } LINFLEX_IFMR_32B_tag; 10192 10193 10194 /* Register layout for all registers IFCR... */ 10195 10196 typedef union { /* Identifier Filter Control Register */ 10197 uint32_t R; 10198 struct { 10199 uint32_t:16; 10200 uint32_t DFL:6; /* Data Field Length */ 10201 uint32_t DIR:1; /* Direction */ 10202 uint32_t CCS:1; /* Classic Checksum */ 10203 uint32_t:2; 10204 uint32_t ID:6; /* Identifier */ 10205 } B; 10206 } LINFLEX_IFCR_32B_tag; 10207 10208 typedef union { /* Global Control Register */ 10209 uint32_t R; 10210 struct { 10211 uint32_t:26; 10212 uint32_t TDFBM:1; /* Transmit Data First Bit MSB */ 10213 uint32_t RDFBM:1; /* Received Data First Bit MSB */ 10214 uint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */ 10215 uint32_t RDLIS:1; /* Received Data Level Inversion Selection */ 10216 uint32_t STOP:1; /* 1/2 stop bit configuration */ 10217 uint32_t SR:1; /* Soft Reset */ 10218 } B; 10219 } LINFLEX_GCR_32B_tag; 10220 10221 typedef union { /* UART Preset Time Out Register */ 10222 uint32_t R; 10223 struct { 10224 uint32_t:20; 10225 uint32_t PTO:12; /* Preset Time Out */ 10226 } B; 10227 } LINFLEX_UARTPTO_32B_tag; 10228 10229 typedef union { /* UART Current Time Out Register */ 10230 uint32_t R; 10231 struct { 10232 uint32_t:20; 10233 uint32_t CTO:12; /* Current Time Out */ 10234 } B; 10235 } LINFLEX_UARTCTO_32B_tag; 10236 10237 typedef union { /* DMA TX Enable Register */ 10238 uint32_t R; 10239 struct { 10240 uint32_t:17; 10241 uint32_t DTE:15; /* DMA Tx channel Enable */ 10242 } B; 10243 } LINFLEX_DMATXE_32B_tag; 10244 10245 typedef union { /* DMA RX Enable Register */ 10246 uint32_t R; 10247 struct { 10248 uint32_t:17; 10249 uint32_t DRE:15; /* DMA Rx channel Enable */ 10250 } B; 10251 } LINFLEX_DMARXE_32B_tag; 10252 10253 10254 10255 typedef struct LINFLEX_struct_tag { /* start of LINFLEX_tag */ 10256 /* LIN Control Register */ 10257 LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */ 10258 /* LIN Interrupt Enable Register */ 10259 LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */ 10260 /* LIN Status Register */ 10261 LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */ 10262 /* LIN Error Status Register */ 10263 LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */ 10264 /* UART Mode Control Register */ 10265 LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */ 10266 /* UART Mode Status Register */ 10267 LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */ 10268 /* LIN Time-Out Control Status Register */ 10269 LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */ 10270 /* LIN Output Compare Register */ 10271 LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */ 10272 /* LIN Time-Out Control Register */ 10273 LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */ 10274 /* LIN Fractional Baud Rate Register */ 10275 LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */ 10276 /* LIN Integer Baud Rate Register */ 10277 LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */ 10278 /* LIN Checksum Field Register */ 10279 LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */ 10280 /* LIN Control Register 2 */ 10281 LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */ 10282 /* Buffer Identifier Register */ 10283 LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */ 10284 /* Buffer Data Register Least Significant */ 10285 LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */ 10286 /* Buffer Data Register Most Significant */ 10287 LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */ 10288 /* Identifier Filter Enable Register */ 10289 LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */ 10290 /* Identifier Filter Match Index */ 10291 LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */ 10292 /* Identifier Filter Mode Register */ 10293 LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */ 10294 union { 10295 /* Identifier Filter Control Register */ 10296 LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */ 10297 10298 struct { 10299 /* Identifier Filter Control Register */ 10300 LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */ 10301 LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */ 10302 LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */ 10303 LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */ 10304 LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */ 10305 LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */ 10306 LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */ 10307 LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */ 10308 }; 10309 10310 }; 10311 int8_t LINFLEX_reserved_006C[32]; 10312 /* Global Control Register */ 10313 LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */ 10314 /* UART Preset Time Out Register */ 10315 LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */ 10316 /* UART Current Time Out Register */ 10317 LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */ 10318 /* DMA TX Enable Register */ 10319 LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */ 10320 /* DMA RX Enable Register */ 10321 LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */ 10322 } LINFLEX_tag; 10323 10324 10325 #define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL) 10326 #define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL) 10327 10328 10329 10330 /****************************************************************/ 10331 /* */ 10332 /* Module: CRC */ 10333 /* */ 10334 /****************************************************************/ 10335 10336 10337 /* Register layout for all registers CFG... */ 10338 10339 typedef union { /* CRC_CFG - CRC Configuration register */ 10340 uint32_t R; 10341 uint8_t BYTE[4]; /* individual bytes can be accessed */ 10342 uint16_t HALF[2]; /* individual halfwords can be accessed */ 10343 uint32_t WORD; /* individual words can be accessed */ 10344 struct { 10345 uint32_t:29; 10346 uint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */ 10347 uint32_t SWAP:1; /* SWAP selection */ 10348 uint32_t INV:1; /* INV selection */ 10349 } B; 10350 } CRC_CFG_32B_tag; 10351 10352 10353 /* Register layout for all registers INP... */ 10354 10355 typedef union { /* CRC_INP - CRC Input register */ 10356 uint32_t R; 10357 uint8_t BYTE[4]; /* individual bytes can be accessed */ 10358 uint16_t HALF[2]; /* individual halfwords can be accessed */ 10359 uint32_t WORD; /* individual words can be accessed */ 10360 } CRC_INP_32B_tag; 10361 10362 10363 /* Register layout for all registers CSTAT... */ 10364 10365 typedef union { /* CRC_STATUS - CRC Status register */ 10366 uint32_t R; 10367 uint8_t BYTE[4]; /* individual bytes can be accessed */ 10368 uint16_t HALF[2]; /* individual halfwords can be accessed */ 10369 uint32_t WORD; /* individual words can be accessed */ 10370 } CRC_CSTAT_32B_tag; 10371 10372 10373 /* Register layout for all registers OUTP... */ 10374 10375 typedef union { /* CRC_STATUS - CRC OUTPUT register */ 10376 uint32_t R; 10377 uint8_t BYTE[4]; /* individual bytes can be accessed */ 10378 uint16_t HALF[2]; /* individual halfwords can be accessed */ 10379 uint32_t WORD; /* individual words can be accessed */ 10380 } CRC_OUTP_32B_tag; 10381 10382 10383 typedef struct CRC_CNTX_struct_tag { 10384 10385 /* CRC_CFG - CRC Configuration register */ 10386 CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */ 10387 /* CRC_INP - CRC Input register */ 10388 CRC_INP_32B_tag INP; /* relative offset: 0x0004 */ 10389 /* CRC_STATUS - CRC Status register */ 10390 CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */ 10391 /* CRC_STATUS - CRC OUTPUT register */ 10392 CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */ 10393 10394 } CRC_CNTX_tag; 10395 10396 10397 typedef struct CRC_struct_tag { /* start of CRC_tag */ 10398 union { 10399 /* Register set CNTX */ 10400 CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */ 10401 10402 struct { 10403 /* CRC_CFG - CRC Configuration register */ 10404 CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */ 10405 /* CRC_INP - CRC Input register */ 10406 CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */ 10407 /* CRC_STATUS - CRC Status register */ 10408 CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */ 10409 /* CRC_STATUS - CRC OUTPUT register */ 10410 CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */ 10411 /* CRC_CFG - CRC Configuration register */ 10412 CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */ 10413 /* CRC_INP - CRC Input register */ 10414 CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */ 10415 /* CRC_STATUS - CRC Status register */ 10416 CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */ 10417 /* CRC_STATUS - CRC OUTPUT register */ 10418 CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */ 10419 /* CRC_CFG - CRC Configuration register */ 10420 CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */ 10421 /* CRC_INP - CRC Input register */ 10422 CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */ 10423 /* CRC_STATUS - CRC Status register */ 10424 CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */ 10425 /* CRC_STATUS - CRC OUTPUT register */ 10426 CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */ 10427 }; 10428 10429 }; 10430 } CRC_tag; 10431 10432 10433 #define CRC (*(volatile CRC_tag *) 0xFFE68000UL) 10434 10435 10436 10437 /****************************************************************/ 10438 /* */ 10439 /* Module: FCCU */ 10440 /* */ 10441 /****************************************************************/ 10442 10443 typedef union { /* FCCU Control Register */ 10444 uint32_t R; 10445 struct { 10446 uint32_t:23; 10447 uint32_t NVML:1; /* NVM configuration loaded */ 10448 uint32_t OPS:2; /* Operation status */ 10449 uint32_t:1; 10450 uint32_t OPR:5; /* Operation run */ 10451 } B; 10452 } FCCU_CTRL_32B_tag; 10453 10454 typedef union { /* FCCU CTRL Key Register */ 10455 uint32_t R; 10456 } FCCU_CTRLK_32B_tag; 10457 10458 typedef union { /* FCCU Configuration Register */ 10459 uint32_t R; 10460 struct { 10461 uint32_t:10; 10462 uint32_t RCCE1:1; /* RCC1 enable */ 10463 uint32_t RCCE0:1; /* RCC0 enable */ 10464 uint32_t SMRT:4; /* Safe Mode Request Timer */ 10465 uint32_t:4; 10466 uint32_t CM:1; /* Config mode */ 10467 uint32_t SM:1; /* Switching mode */ 10468 uint32_t PS:1; /* Polarity Selection */ 10469 uint32_t FOM:3; /* Fault Output Mode Selection */ 10470 uint32_t FOP:6; /* Fault Output Prescaler */ 10471 } B; 10472 } FCCU_CFG_32B_tag; 10473 10474 typedef union { /* FCCU CF Configuration Register 0 */ 10475 uint32_t R; 10476 struct { 10477 uint32_t CFC31:1; /* CF 31 configuration */ 10478 uint32_t CFC30:1; /* CF 30 configuration */ 10479 uint32_t CFC29:1; /* CF 29 configuration */ 10480 uint32_t CFC28:1; /* CF 28 configuration */ 10481 uint32_t CFC27:1; /* CF 27 configuration */ 10482 uint32_t CFC26:1; /* CF 26 configuration */ 10483 uint32_t CFC25:1; /* CF 25 configuration */ 10484 uint32_t CFC24:1; /* CF 24 configuration */ 10485 uint32_t CFC23:1; /* CF 23 configuration */ 10486 uint32_t CFC22:1; /* CF 22 configuration */ 10487 uint32_t CFC21:1; /* CF 21 configuration */ 10488 uint32_t CFC20:1; /* CF 20 configuration */ 10489 uint32_t CFC19:1; /* CF 19 configuration */ 10490 uint32_t CFC18:1; /* CF 18 configuration */ 10491 uint32_t CFC17:1; /* CF 17 configuration */ 10492 uint32_t CFC16:1; /* CF 16 configuration */ 10493 uint32_t CFC15:1; /* CF 15 configuration */ 10494 uint32_t CFC14:1; /* CF 14 configuration */ 10495 uint32_t CFC13:1; /* CF 13 configuration */ 10496 uint32_t CFC12:1; /* CF 12 configuration */ 10497 uint32_t CFC11:1; /* CF 11 configuration */ 10498 uint32_t CFC10:1; /* CF 10 configuration */ 10499 uint32_t CFC9:1; /* CF 9 configuration */ 10500 uint32_t CFC8:1; /* CF 8 configuration */ 10501 uint32_t CFC7:1; /* CF 7 configuration */ 10502 uint32_t CFC6:1; /* CF 6 configuration */ 10503 uint32_t CFC5:1; /* CF 5 configuration */ 10504 uint32_t CFC4:1; /* CF 4 configuration */ 10505 uint32_t CFC3:1; /* CF 3 configuration */ 10506 uint32_t CFC2:1; /* CF 2 configuration */ 10507 uint32_t CFC1:1; /* CF 1 configuration */ 10508 uint32_t CFC0:1; /* CF 0 configuration */ 10509 } B; 10510 } FCCU_CF_CFG0_32B_tag; 10511 10512 typedef union { /* FCCU CF Configuration Register 1 */ 10513 uint32_t R; 10514 struct { 10515 uint32_t CFC63:1; /* CF 63 configuration */ 10516 uint32_t CFC62:1; /* CF 62 configuration */ 10517 uint32_t CFC61:1; /* CF 61 configuration */ 10518 uint32_t CFC60:1; /* CF 60 configuration */ 10519 uint32_t CFC59:1; /* CF 59 configuration */ 10520 uint32_t CFC58:1; /* CF 58 configuration */ 10521 uint32_t CFC57:1; /* CF 57 configuration */ 10522 uint32_t CFC56:1; /* CF 56 configuration */ 10523 uint32_t CFC55:1; /* CF 55 configuration */ 10524 uint32_t CFC54:1; /* CF 54 configuration */ 10525 uint32_t CFC53:1; /* CF 53 configuration */ 10526 uint32_t CFC52:1; /* CF 52 configuration */ 10527 uint32_t CFC51:1; /* CF 51 configuration */ 10528 uint32_t CFC50:1; /* CF 50 configuration */ 10529 uint32_t CFC49:1; /* CF 49 configuration */ 10530 uint32_t CFC48:1; /* CF 48 configuration */ 10531 uint32_t CFC47:1; /* CF 47 configuration */ 10532 uint32_t CFC46:1; /* CF 46 configuration */ 10533 uint32_t CFC45:1; /* CF 45 configuration */ 10534 uint32_t CFC44:1; /* CF 44 configuration */ 10535 uint32_t CFC43:1; /* CF 43 configuration */ 10536 uint32_t CFC42:1; /* CF 42 configuration */ 10537 uint32_t CFC41:1; /* CF 41 configuration */ 10538 uint32_t CFC40:1; /* CF 40 configuration */ 10539 uint32_t CFC39:1; /* CF 39 configuration */ 10540 uint32_t CFC38:1; /* CF 38 configuration */ 10541 uint32_t CFC37:1; /* CF 37 configuration */ 10542 uint32_t CFC36:1; /* CF 36 configuration */ 10543 uint32_t CFC35:1; /* CF 35 configuration */ 10544 uint32_t CFC34:1; /* CF 34 configuration */ 10545 uint32_t CFC33:1; /* CF 33 configuration */ 10546 uint32_t CFC32:1; /* CF 32 configuration */ 10547 } B; 10548 } FCCU_CF_CFG1_32B_tag; 10549 10550 typedef union { /* FCCU CF Configuration Register 2 */ 10551 uint32_t R; 10552 struct { 10553 uint32_t CFC95:1; /* CF 95 configuration */ 10554 uint32_t CFC94:1; /* CF 94 configuration */ 10555 uint32_t CFC93:1; /* CF 93 configuration */ 10556 uint32_t CFC92:1; /* CF 92 configuration */ 10557 uint32_t CFC91:1; /* CF 91 configuration */ 10558 uint32_t CFC90:1; /* CF 90 configuration */ 10559 uint32_t CFC89:1; /* CF 89 configuration */ 10560 uint32_t CFC88:1; /* CF 88 configuration */ 10561 uint32_t CFC87:1; /* CF 87 configuration */ 10562 uint32_t CFC86:1; /* CF 86 configuration */ 10563 uint32_t CFC85:1; /* CF 85 configuration */ 10564 uint32_t CFC84:1; /* CF 84 configuration */ 10565 uint32_t CFC83:1; /* CF 83 configuration */ 10566 uint32_t CFC82:1; /* CF 82 configuration */ 10567 uint32_t CFC81:1; /* CF 81 configuration */ 10568 uint32_t CFC80:1; /* CF 80 configuration */ 10569 uint32_t CFC79:1; /* CF 79 configuration */ 10570 uint32_t CFC78:1; /* CF 78 configuration */ 10571 uint32_t CFC77:1; /* CF 77 configuration */ 10572 uint32_t CFC76:1; /* CF 76 configuration */ 10573 uint32_t CFC75:1; /* CF 75 configuration */ 10574 uint32_t CFC74:1; /* CF 74 configuration */ 10575 uint32_t CFC73:1; /* CF 73 configuration */ 10576 uint32_t CFC72:1; /* CF 72 configuration */ 10577 uint32_t CFC71:1; /* CF 71 configuration */ 10578 uint32_t CFC70:1; /* CF 70 configuration */ 10579 uint32_t CFC69:1; /* CF 69 configuration */ 10580 uint32_t CFC68:1; /* CF 68 configuration */ 10581 uint32_t CFC67:1; /* CF 67 configuration */ 10582 uint32_t CFC66:1; /* CF 66 configuration */ 10583 uint32_t CFC65:1; /* CF 65 configuration */ 10584 uint32_t CFC64:1; /* CF 64 configuration */ 10585 } B; 10586 } FCCU_CF_CFG2_32B_tag; 10587 10588 typedef union { /* FCCU CF Configuration Register 3 */ 10589 uint32_t R; 10590 struct { 10591 uint32_t CFC127:1; /* CF 127 configuration */ 10592 uint32_t CFC126:1; /* CF 126 configuration */ 10593 uint32_t CFC125:1; /* CF 125 configuration */ 10594 uint32_t CFC124:1; /* CF 124 configuration */ 10595 uint32_t CFC123:1; /* CF 123 configuration */ 10596 uint32_t CFC122:1; /* CF 122 configuration */ 10597 uint32_t CFC121:1; /* CF 121 configuration */ 10598 uint32_t CFC120:1; /* CF 120 configuration */ 10599 uint32_t CFC119:1; /* CF 119 configuration */ 10600 uint32_t CFC118:1; /* CF 118 configuration */ 10601 uint32_t CFC117:1; /* CF 117 configuration */ 10602 uint32_t CFC116:1; /* CF 116 configuration */ 10603 uint32_t CFC115:1; /* CF 115 configuration */ 10604 uint32_t CFC114:1; /* CF 114 configuration */ 10605 uint32_t CFC113:1; /* CF 113 configuration */ 10606 uint32_t CFC112:1; /* CF 112 configuration */ 10607 uint32_t CFC111:1; /* CF 111 configuration */ 10608 uint32_t CFC110:1; /* CF 110 configuration */ 10609 uint32_t CFC109:1; /* CF 109 configuration */ 10610 uint32_t CFC108:1; /* CF 108 configuration */ 10611 uint32_t CFC107:1; /* CF 107 configuration */ 10612 uint32_t CFC106:1; /* CF 106 configuration */ 10613 uint32_t CFC105:1; /* CF 105 configuration */ 10614 uint32_t CFC104:1; /* CF 104 configuration */ 10615 uint32_t CFC103:1; /* CF 103 configuration */ 10616 uint32_t CFC102:1; /* CF 102 configuration */ 10617 uint32_t CFC101:1; /* CF 101 configuration */ 10618 uint32_t CFC100:1; /* CF 100 configuration */ 10619 uint32_t CFC99:1; /* CF 99 configuration */ 10620 uint32_t CFC98:1; /* CF 98 configuration */ 10621 uint32_t CFC97:1; /* CF 97 configuration */ 10622 uint32_t CFC96:1; /* CF 96 configuration */ 10623 } B; 10624 } FCCU_CF_CFG3_32B_tag; 10625 10626 typedef union { /* FCCU NCF Configuration Register 0 */ 10627 uint32_t R; 10628 struct { 10629 uint32_t NCFC31:1; /* NCF 31 configuration */ 10630 uint32_t NCFC30:1; /* NCF 30 configuration */ 10631 uint32_t NCFC29:1; /* NCF 29 configuration */ 10632 uint32_t NCFC28:1; /* NCF 28 configuration */ 10633 uint32_t NCFC27:1; /* NCF 27 configuration */ 10634 uint32_t NCFC26:1; /* NCF 26 configuration */ 10635 uint32_t NCFC25:1; /* NCF 25 configuration */ 10636 uint32_t NCFC24:1; /* NCF 24 configuration */ 10637 uint32_t NCFC23:1; /* NCF 23 configuration */ 10638 uint32_t NCFC22:1; /* NCF 22 configuration */ 10639 uint32_t NCFC21:1; /* NCF 21 configuration */ 10640 uint32_t NCFC20:1; /* NCF 20 configuration */ 10641 uint32_t NCFC19:1; /* NCF 19 configuration */ 10642 uint32_t NCFC18:1; /* NCF 18 configuration */ 10643 uint32_t NCFC17:1; /* NCF 17 configuration */ 10644 uint32_t NCFC16:1; /* NCF 16 configuration */ 10645 uint32_t NCFC15:1; /* NCF 15 configuration */ 10646 uint32_t NCFC14:1; /* NCF 14 configuration */ 10647 uint32_t NCFC13:1; /* NCF 13 configuration */ 10648 uint32_t NCFC12:1; /* NCF 12 configuration */ 10649 uint32_t NCFC11:1; /* NCF 11 configuration */ 10650 uint32_t NCFC10:1; /* NCF 10 configuration */ 10651 uint32_t NCFC9:1; /* NCF 9 configuration */ 10652 uint32_t NCFC8:1; /* NCF 8 configuration */ 10653 uint32_t NCFC7:1; /* NCF 7 configuration */ 10654 uint32_t NCFC6:1; /* NCF 6 configuration */ 10655 uint32_t NCFC5:1; /* NCF 5 configuration */ 10656 uint32_t NCFC4:1; /* NCF 4 configuration */ 10657 uint32_t NCFC3:1; /* NCF 3 configuration */ 10658 uint32_t NCFC2:1; /* NCF 2 configuration */ 10659 uint32_t NCFC1:1; /* NCF 1 configuration */ 10660 uint32_t NCFC0:1; /* NCF 0 configuration */ 10661 } B; 10662 } FCCU_NCF_CFG0_32B_tag; 10663 10664 typedef union { /* FCCU NCF Configuration Register 1 */ 10665 uint32_t R; 10666 struct { 10667 uint32_t NCFC63:1; /* NCF 63 configuration */ 10668 uint32_t NCFC62:1; /* NCF 62 configuration */ 10669 uint32_t NCFC61:1; /* NCF 61 configuration */ 10670 uint32_t NCFC60:1; /* NCF 60 configuration */ 10671 uint32_t NCFC59:1; /* NCF 59 configuration */ 10672 uint32_t NCFC58:1; /* NCF 58 configuration */ 10673 uint32_t NCFC57:1; /* NCF 57 configuration */ 10674 uint32_t NCFC56:1; /* NCF 56 configuration */ 10675 uint32_t NCFC55:1; /* NCF 55 configuration */ 10676 uint32_t NCFC54:1; /* NCF 54 configuration */ 10677 uint32_t NCFC53:1; /* NCF 53 configuration */ 10678 uint32_t NCFC52:1; /* NCF 52 configuration */ 10679 uint32_t NCFC51:1; /* NCF 51 configuration */ 10680 uint32_t NCFC50:1; /* NCF 50 configuration */ 10681 uint32_t NCFC49:1; /* NCF 49 configuration */ 10682 uint32_t NCFC48:1; /* NCF 48 configuration */ 10683 uint32_t NCFC47:1; /* NCF 47 configuration */ 10684 uint32_t NCFC46:1; /* NCF 46 configuration */ 10685 uint32_t NCFC45:1; /* NCF 45 configuration */ 10686 uint32_t NCFC44:1; /* NCF 44 configuration */ 10687 uint32_t NCFC43:1; /* NCF 43 configuration */ 10688 uint32_t NCFC42:1; /* NCF 42 configuration */ 10689 uint32_t NCFC41:1; /* NCF 41 configuration */ 10690 uint32_t NCFC40:1; /* NCF 40 configuration */ 10691 uint32_t NCFC39:1; /* NCF 39 configuration */ 10692 uint32_t NCFC38:1; /* NCF 38 configuration */ 10693 uint32_t NCFC37:1; /* NCF 37 configuration */ 10694 uint32_t NCFC36:1; /* NCF 36 configuration */ 10695 uint32_t NCFC35:1; /* NCF 35 configuration */ 10696 uint32_t NCFC34:1; /* NCF 34 configuration */ 10697 uint32_t NCFC33:1; /* NCF 33 configuration */ 10698 uint32_t NCFC32:1; /* NCF 32 configuration */ 10699 } B; 10700 } FCCU_NCF_CFG1_32B_tag; 10701 10702 typedef union { /* FCCU NCF Configuration Register 2 */ 10703 uint32_t R; 10704 struct { 10705 uint32_t NCFC95:1; /* NCF 95 configuration */ 10706 uint32_t NCFC94:1; /* NCF 94 configuration */ 10707 uint32_t NCFC93:1; /* NCF 93 configuration */ 10708 uint32_t NCFC92:1; /* NCF 92 configuration */ 10709 uint32_t NCFC91:1; /* NCF 91 configuration */ 10710 uint32_t NCFC90:1; /* NCF 90 configuration */ 10711 uint32_t NCFC89:1; /* NCF 89 configuration */ 10712 uint32_t NCFC88:1; /* NCF 88 configuration */ 10713 uint32_t NCFC87:1; /* NCF 87 configuration */ 10714 uint32_t NCFC86:1; /* NCF 86 configuration */ 10715 uint32_t NCFC85:1; /* NCF 85 configuration */ 10716 uint32_t NCFC84:1; /* NCF 84 configuration */ 10717 uint32_t NCFC83:1; /* NCF 83 configuration */ 10718 uint32_t NCFC82:1; /* NCF 82 configuration */ 10719 uint32_t NCFC81:1; /* NCF 81 configuration */ 10720 uint32_t NCFC80:1; /* NCF 80 configuration */ 10721 uint32_t NCFC79:1; /* NCF 79 configuration */ 10722 uint32_t NCFC78:1; /* NCF 78 configuration */ 10723 uint32_t NCFC77:1; /* NCF 77 configuration */ 10724 uint32_t NCFC76:1; /* NCF 76 configuration */ 10725 uint32_t NCFC75:1; /* NCF 75 configuration */ 10726 uint32_t NCFC74:1; /* NCF 74 configuration */ 10727 uint32_t NCFC73:1; /* NCF 73 configuration */ 10728 uint32_t NCFC72:1; /* NCF 72 configuration */ 10729 uint32_t NCFC71:1; /* NCF 71 configuration */ 10730 uint32_t NCFC70:1; /* NCF 70 configuration */ 10731 uint32_t NCFC69:1; /* NCF 69 configuration */ 10732 uint32_t NCFC68:1; /* NCF 68 configuration */ 10733 uint32_t NCFC67:1; /* NCF 67 configuration */ 10734 uint32_t NCFC66:1; /* NCF 66 configuration */ 10735 uint32_t NCFC65:1; /* NCF 65 configuration */ 10736 uint32_t NCFC64:1; /* NCF 64 configuration */ 10737 } B; 10738 } FCCU_NCF_CFG2_32B_tag; 10739 10740 typedef union { /* FCCU NCF Configuration Register 3 */ 10741 uint32_t R; 10742 struct { 10743 uint32_t NCFC127:1; /* NCF 127 configuration */ 10744 uint32_t NCFC126:1; /* NCF 126 configuration */ 10745 uint32_t NCFC125:1; /* NCF 125 configuration */ 10746 uint32_t NCFC124:1; /* NCF 124 configuration */ 10747 uint32_t NCFC123:1; /* NCF 123 configuration */ 10748 uint32_t NCFC122:1; /* NCF 122 configuration */ 10749 uint32_t NCFC121:1; /* NCF 121 configuration */ 10750 uint32_t NCFC120:1; /* NCF 120 configuration */ 10751 uint32_t NCFC119:1; /* NCF 119 configuration */ 10752 uint32_t NCFC118:1; /* NCF 118 configuration */ 10753 uint32_t NCFC117:1; /* NCF 117 configuration */ 10754 uint32_t NCFC116:1; /* NCF 116 configuration */ 10755 uint32_t NCFC115:1; /* NCF 115 configuration */ 10756 uint32_t NCFC114:1; /* NCF 114 configuration */ 10757 uint32_t NCFC113:1; /* NCF 113 configuration */ 10758 uint32_t NCFC112:1; /* NCF 112 configuration */ 10759 uint32_t NCFC111:1; /* NCF 111 configuration */ 10760 uint32_t NCFC110:1; /* NCF 110 configuration */ 10761 uint32_t NCFC109:1; /* NCF 109 configuration */ 10762 uint32_t NCFC108:1; /* NCF 108 configuration */ 10763 uint32_t NCFC107:1; /* NCF 107 configuration */ 10764 uint32_t NCFC106:1; /* NCF 106 configuration */ 10765 uint32_t NCFC105:1; /* NCF 105 configuration */ 10766 uint32_t NCFC104:1; /* NCF 104 configuration */ 10767 uint32_t NCFC103:1; /* NCF 103 configuration */ 10768 uint32_t NCFC102:1; /* NCF 102 configuration */ 10769 uint32_t NCFC101:1; /* NCF 101 configuration */ 10770 uint32_t NCFC100:1; /* NCF 100 configuration */ 10771 uint32_t NCFC99:1; /* NCF 99 configuration */ 10772 uint32_t NCFC98:1; /* NCF 98 configuration */ 10773 uint32_t NCFC97:1; /* NCF 97 configuration */ 10774 uint32_t NCFC96:1; /* NCF 96 configuration */ 10775 } B; 10776 } FCCU_NCF_CFG3_32B_tag; 10777 10778 typedef union { /* FCCU CFS Configuration Register 0 */ 10779 uint32_t R; 10780 struct { 10781 uint32_t CFSC15:2; /* CF 15 state configuration */ 10782 uint32_t CFSC14:2; /* CF 14 state configuration */ 10783 uint32_t CFSC13:2; /* CF 13 state configuration */ 10784 uint32_t CFSC12:2; /* CF 12 state configuration */ 10785 uint32_t CFSC11:2; /* CF 11 state configuration */ 10786 uint32_t CFSC10:2; /* CF 10 state configuration */ 10787 uint32_t CFSC9:2; /* CF 9 state configuration */ 10788 uint32_t CFSC8:2; /* CF 8 state configuration */ 10789 uint32_t CFSC7:2; /* CF 7 state configuration */ 10790 uint32_t CFSC6:2; /* CF 6 state configuration */ 10791 uint32_t CFSC5:2; /* CF 5 state configuration */ 10792 uint32_t CFSC4:2; /* CF 4 state configuration */ 10793 uint32_t CFSC3:2; /* CF 3 state configuration */ 10794 uint32_t CFSC2:2; /* CF 2 state configuration */ 10795 uint32_t CFSC1:2; /* CF 1 state configuration */ 10796 uint32_t CFSC0:2; /* CF 0 state configuration */ 10797 } B; 10798 } FCCU_CFS_CFG0_32B_tag; 10799 10800 typedef union { /* FCCU CFS Configuration Register 1 */ 10801 uint32_t R; 10802 struct { 10803 uint32_t CFSC31:2; /* CF 31 state configuration */ 10804 uint32_t CFSC30:2; /* CF 30 state configuration */ 10805 uint32_t CFSC29:2; /* CF 29 state configuration */ 10806 uint32_t CFSC28:2; /* CF 28 state configuration */ 10807 uint32_t CFSC27:2; /* CF 27 state configuration */ 10808 uint32_t CFSC26:2; /* CF 26 state configuration */ 10809 uint32_t CFSC25:2; /* CF 25 state configuration */ 10810 uint32_t CFSC24:2; /* CF 24 state configuration */ 10811 uint32_t CFSC23:2; /* CF 23 state configuration */ 10812 uint32_t CFSC22:2; /* CF 22 state configuration */ 10813 uint32_t CFSC21:2; /* CF 21 state configuration */ 10814 uint32_t CFSC20:2; /* CF 20 state configuration */ 10815 uint32_t CFSC19:2; /* CF 19 state configuration */ 10816 uint32_t CFSC18:2; /* CF 18 state configuration */ 10817 uint32_t CFSC17:2; /* CF 17 state configuration */ 10818 uint32_t CFSC16:2; /* CF 16 state configuration */ 10819 } B; 10820 } FCCU_CFS_CFG1_32B_tag; 10821 10822 typedef union { /* FCCU CFS Configuration Register 2 */ 10823 uint32_t R; 10824 struct { 10825 uint32_t CFSC47:2; /* CF 47 state configuration */ 10826 uint32_t CFSC46:2; /* CF 46 state configuration */ 10827 uint32_t CFSC45:2; /* CF 45 state configuration */ 10828 uint32_t CFSC44:2; /* CF 44 state configuration */ 10829 uint32_t CFSC43:2; /* CF 43 state configuration */ 10830 uint32_t CFSC42:2; /* CF 42 state configuration */ 10831 uint32_t CFSC41:2; /* CF 41 state configuration */ 10832 uint32_t CFSC40:2; /* CF 40 state configuration */ 10833 uint32_t CFSC39:2; /* CF 39 state configuration */ 10834 uint32_t CFSC38:2; /* CF 38 state configuration */ 10835 uint32_t CFSC37:2; /* CF 37 state configuration */ 10836 uint32_t CFSC36:2; /* CF 36 state configuration */ 10837 uint32_t CFSC35:2; /* CF 35 state configuration */ 10838 uint32_t CFSC34:2; /* CF 34 state configuration */ 10839 uint32_t CFSC33:2; /* CF 33 state configuration */ 10840 uint32_t CFSC32:2; /* CF 32 state configuration */ 10841 } B; 10842 } FCCU_CFS_CFG2_32B_tag; 10843 10844 typedef union { /* FCCU CFS Configuration Register 3 */ 10845 uint32_t R; 10846 struct { 10847 uint32_t CFSC63:2; /* CF 63 state configuration */ 10848 uint32_t CFSC62:2; /* CF 62 state configuration */ 10849 uint32_t CFSC61:2; /* CF 61 state configuration */ 10850 uint32_t CFSC60:2; /* CF 60 state configuration */ 10851 uint32_t CFSC59:2; /* CF 59 state configuration */ 10852 uint32_t CFSC58:2; /* CF 58 state configuration */ 10853 uint32_t CFSC57:2; /* CF 57 state configuration */ 10854 uint32_t CFSC56:2; /* CF 56 state configuration */ 10855 uint32_t CFSC55:2; /* CF 55 state configuration */ 10856 uint32_t CFSC54:2; /* CF 54 state configuration */ 10857 uint32_t CFSC53:2; /* CF 53 state configuration */ 10858 uint32_t CFSC52:2; /* CF 52 state configuration */ 10859 uint32_t CFSC51:2; /* CF 51 state configuration */ 10860 uint32_t CFSC50:2; /* CF 50 state configuration */ 10861 uint32_t CFSC49:2; /* CF 49 state configuration */ 10862 uint32_t CFSC48:2; /* CF 48 state configuration */ 10863 } B; 10864 } FCCU_CFS_CFG3_32B_tag; 10865 10866 typedef union { /* FCCU CFS Configuration Register 4 */ 10867 uint32_t R; 10868 struct { 10869 uint32_t CFSC79:2; /* CF 79 state configuration */ 10870 uint32_t CFSC78:2; /* CF 78 state configuration */ 10871 uint32_t CFSC77:2; /* CF 77 state configuration */ 10872 uint32_t CFSC76:2; /* CF 76 state configuration */ 10873 uint32_t CFSC75:2; /* CF 75 state configuration */ 10874 uint32_t CFSC74:2; /* CF 74 state configuration */ 10875 uint32_t CFSC73:2; /* CF 73 state configuration */ 10876 uint32_t CFSC72:2; /* CF 72 state configuration */ 10877 uint32_t CFSC71:2; /* CF 71 state configuration */ 10878 uint32_t CFSC70:2; /* CF 70 state configuration */ 10879 uint32_t CFSC69:2; /* CF 69 state configuration */ 10880 uint32_t CFSC68:2; /* CF 68 state configuration */ 10881 uint32_t CFSC67:2; /* CF 67 state configuration */ 10882 uint32_t CFSC66:2; /* CF 66 state configuration */ 10883 uint32_t CFSC65:2; /* CF 65 state configuration */ 10884 uint32_t CFSC64:2; /* CF 64 state configuration */ 10885 } B; 10886 } FCCU_CFS_CFG4_32B_tag; 10887 10888 typedef union { /* FCCU CFS Configuration Register 5 */ 10889 uint32_t R; 10890 struct { 10891 uint32_t CFSC95:2; /* CF 95 state configuration */ 10892 uint32_t CFSC94:2; /* CF 94 state configuration */ 10893 uint32_t CFSC93:2; /* CF 93 state configuration */ 10894 uint32_t CFSC92:2; /* CF 92 state configuration */ 10895 uint32_t CFSC91:2; /* CF 91 state configuration */ 10896 uint32_t CFSC90:2; /* CF 90 state configuration */ 10897 uint32_t CFSC89:2; /* CF 89 state configuration */ 10898 uint32_t CFSC88:2; /* CF 88 state configuration */ 10899 uint32_t CFSC87:2; /* CF 87 state configuration */ 10900 uint32_t CFSC86:2; /* CF 86 state configuration */ 10901 uint32_t CFSC85:2; /* CF 85 state configuration */ 10902 uint32_t CFSC84:2; /* CF 84 state configuration */ 10903 uint32_t CFSC83:2; /* CF 83 state configuration */ 10904 uint32_t CFSC82:2; /* CF 82 state configuration */ 10905 uint32_t CFSC81:2; /* CF 81 state configuration */ 10906 uint32_t CFSC80:2; /* CF 80 state configuration */ 10907 } B; 10908 } FCCU_CFS_CFG5_32B_tag; 10909 10910 typedef union { /* FCCU CFS Configuration Register 6 */ 10911 uint32_t R; 10912 struct { 10913 uint32_t CFSC111:2; /* CF 111 state configuration */ 10914 uint32_t CFSC110:2; /* CF 110 state configuration */ 10915 uint32_t CFSC109:2; /* CF 109 state configuration */ 10916 uint32_t CFSC108:2; /* CF 108 state configuration */ 10917 uint32_t CFSC107:2; /* CF 107 state configuration */ 10918 uint32_t CFSC106:2; /* CF 106 state configuration */ 10919 uint32_t CFSC105:2; /* CF 105 state configuration */ 10920 uint32_t CFSC104:2; /* CF 104 state configuration */ 10921 uint32_t CFSC103:2; /* CF 103 state configuration */ 10922 uint32_t CFSC102:2; /* CF 102 state configuration */ 10923 uint32_t CFSC101:2; /* CF 101 state configuration */ 10924 uint32_t CFSC100:2; /* CF 100 state configuration */ 10925 uint32_t CFSC99:2; /* CF 99 state configuration */ 10926 uint32_t CFSC98:2; /* CF 98 state configuration */ 10927 uint32_t CFSC97:2; /* CF 97 state configuration */ 10928 uint32_t CFSC96:2; /* CF 96 state configuration */ 10929 } B; 10930 } FCCU_CFS_CFG6_32B_tag; 10931 10932 typedef union { /* FCCU CFS Configuration Register 7 */ 10933 uint32_t R; 10934 struct { 10935 uint32_t CFSC127:2; /* CF 127 state configuration */ 10936 uint32_t CFSC126:2; /* CF 126 state configuration */ 10937 uint32_t CFSC125:2; /* CF 125 state configuration */ 10938 uint32_t CFSC124:2; /* CF 124 state configuration */ 10939 uint32_t CFSC123:2; /* CF 123 state configuration */ 10940 uint32_t CFSC122:2; /* CF 122 state configuration */ 10941 uint32_t CFSC121:2; /* CF 121 state configuration */ 10942 uint32_t CFSC120:2; /* CF 120 state configuration */ 10943 uint32_t CFSC119:2; /* CF 119 state configuration */ 10944 uint32_t CFSC118:2; /* CF 118 state configuration */ 10945 uint32_t CFSC117:2; /* CF 117 state configuration */ 10946 uint32_t CFSC116:2; /* CF 116 state configuration */ 10947 uint32_t CFSC115:2; /* CF 115 state configuration */ 10948 uint32_t CFSC114:2; /* CF 114 state configuration */ 10949 uint32_t CFSC113:2; /* CF 113 state configuration */ 10950 uint32_t CFSC112:2; /* CF 112 state configuration */ 10951 } B; 10952 } FCCU_CFS_CFG7_32B_tag; 10953 10954 typedef union { /* FCCU NCFS Configuration Register 0 */ 10955 uint32_t R; 10956 struct { 10957 uint32_t NCFSC15:2; /* NCF 15 state configuration */ 10958 uint32_t NCFSC14:2; /* NCF 14 state configuration */ 10959 uint32_t NCFSC13:2; /* NCF 13 state configuration */ 10960 uint32_t NCFSC12:2; /* NCF 12 state configuration */ 10961 uint32_t NCFSC11:2; /* NCF 11 state configuration */ 10962 uint32_t NCFSC10:2; /* NCF 10 state configuration */ 10963 uint32_t NCFSC9:2; /* NCF 9 state configuration */ 10964 uint32_t NCFSC8:2; /* NCF 8 state configuration */ 10965 uint32_t NCFSC7:2; /* NCF 7 state configuration */ 10966 uint32_t NCFSC6:2; /* NCF 6 state configuration */ 10967 uint32_t NCFSC5:2; /* NCF 5 state configuration */ 10968 uint32_t NCFSC4:2; /* NCF 4 state configuration */ 10969 uint32_t NCFSC3:2; /* NCF 3 state configuration */ 10970 uint32_t NCFSC2:2; /* NCF 2 state configuration */ 10971 uint32_t NCFSC1:2; /* NCF 1 state configuration */ 10972 uint32_t NCFSC0:2; /* NCF 0 state configuration */ 10973 } B; 10974 } FCCU_NCFS_CFG0_32B_tag; 10975 10976 typedef union { /* FCCU NCFS Configuration Register 1 */ 10977 uint32_t R; 10978 struct { 10979 uint32_t NCFSC31:2; /* NCF 31 state configuration */ 10980 uint32_t NCFSC30:2; /* NCF 30 state configuration */ 10981 uint32_t NCFSC29:2; /* NCF 29 state configuration */ 10982 uint32_t NCFSC28:2; /* NCF 28 state configuration */ 10983 uint32_t NCFSC27:2; /* NCF 27 state configuration */ 10984 uint32_t NCFSC26:2; /* NCF 26 state configuration */ 10985 uint32_t NCFSC25:2; /* NCF 25 state configuration */ 10986 uint32_t NCFSC24:2; /* NCF 24 state configuration */ 10987 uint32_t NCFSC23:2; /* NCF 23 state configuration */ 10988 uint32_t NCFSC22:2; /* NCF 22 state configuration */ 10989 uint32_t NCFSC21:2; /* NCF 21 state configuration */ 10990 uint32_t NCFSC20:2; /* NCF 20 state configuration */ 10991 uint32_t NCFSC19:2; /* NCF 19 state configuration */ 10992 uint32_t NCFSC18:2; /* NCF 18 state configuration */ 10993 uint32_t NCFSC17:2; /* NCF 17 state configuration */ 10994 uint32_t NCFSC16:2; /* NCF 16 state configuration */ 10995 } B; 10996 } FCCU_NCFS_CFG1_32B_tag; 10997 10998 typedef union { /* FCCU NCFS Configuration Register 2 */ 10999 uint32_t R; 11000 struct { 11001 uint32_t NCFSC47:2; /* NCF 47 state configuration */ 11002 uint32_t NCFSC46:2; /* NCF 46 state configuration */ 11003 uint32_t NCFSC45:2; /* NCF 45 state configuration */ 11004 uint32_t NCFSC44:2; /* NCF 44 state configuration */ 11005 uint32_t NCFSC43:2; /* NCF 43 state configuration */ 11006 uint32_t NCFSC42:2; /* NCF 42 state configuration */ 11007 uint32_t NCFSC41:2; /* NCF 41 state configuration */ 11008 uint32_t NCFSC40:2; /* NCF 40 state configuration */ 11009 uint32_t NCFSC39:2; /* NCF 39 state configuration */ 11010 uint32_t NCFSC38:2; /* NCF 38 state configuration */ 11011 uint32_t NCFSC37:2; /* NCF 37 state configuration */ 11012 uint32_t NCFSC36:2; /* NCF 36 state configuration */ 11013 uint32_t NCFSC35:2; /* NCF 35 state configuration */ 11014 uint32_t NCFSC34:2; /* NCF 34 state configuration */ 11015 uint32_t NCFSC33:2; /* NCF 33 state configuration */ 11016 uint32_t NCFSC32:2; /* NCF 32 state configuration */ 11017 } B; 11018 } FCCU_NCFS_CFG2_32B_tag; 11019 11020 typedef union { /* FCCU NCFS Configuration Register 3 */ 11021 uint32_t R; 11022 struct { 11023 uint32_t NCFSC63:2; /* NCF 63 state configuration */ 11024 uint32_t NCFSC62:2; /* NCF 62 state configuration */ 11025 uint32_t NCFSC61:2; /* NCF 61 state configuration */ 11026 uint32_t NCFSC60:2; /* NCF 60 state configuration */ 11027 uint32_t NCFSC59:2; /* NCF 59 state configuration */ 11028 uint32_t NCFSC58:2; /* NCF 58 state configuration */ 11029 uint32_t NCFSC57:2; /* NCF 57 state configuration */ 11030 uint32_t NCFSC56:2; /* NCF 56 state configuration */ 11031 uint32_t NCFSC55:2; /* NCF 55 state configuration */ 11032 uint32_t NCFSC54:2; /* NCF 54 state configuration */ 11033 uint32_t NCFSC53:2; /* NCF 53 state configuration */ 11034 uint32_t NCFSC52:2; /* NCF 52 state configuration */ 11035 uint32_t NCFSC51:2; /* NCF 51 state configuration */ 11036 uint32_t NCFSC50:2; /* NCF 50 state configuration */ 11037 uint32_t NCFSC49:2; /* NCF 49 state configuration */ 11038 uint32_t NCFSC48:2; /* NCF 48 state configuration */ 11039 } B; 11040 } FCCU_NCFS_CFG3_32B_tag; 11041 11042 typedef union { /* FCCU NCFS Configuration Register 4 */ 11043 uint32_t R; 11044 struct { 11045 uint32_t NCFSC79:2; /* NCF 79 state configuration */ 11046 uint32_t NCFSC78:2; /* NCF 78 state configuration */ 11047 uint32_t NCFSC77:2; /* NCF 77 state configuration */ 11048 uint32_t NCFSC76:2; /* NCF 76 state configuration */ 11049 uint32_t NCFSC75:2; /* NCF 75 state configuration */ 11050 uint32_t NCFSC74:2; /* NCF 74 state configuration */ 11051 uint32_t NCFSC73:2; /* NCF 73 state configuration */ 11052 uint32_t NCFSC72:2; /* NCF 72 state configuration */ 11053 uint32_t NCFSC71:2; /* NCF 71 state configuration */ 11054 uint32_t NCFSC70:2; /* NCF 70 state configuration */ 11055 uint32_t NCFSC69:2; /* NCF 69 state configuration */ 11056 uint32_t NCFSC68:2; /* NCF 68 state configuration */ 11057 uint32_t NCFSC67:2; /* NCF 67 state configuration */ 11058 uint32_t NCFSC66:2; /* NCF 66 state configuration */ 11059 uint32_t NCFSC65:2; /* NCF 65 state configuration */ 11060 uint32_t NCFSC64:2; /* NCF 64 state configuration */ 11061 } B; 11062 } FCCU_NCFS_CFG4_32B_tag; 11063 11064 typedef union { /* FCCU NCFS Configuration Register 5 */ 11065 uint32_t R; 11066 struct { 11067 uint32_t NCFSC95:2; /* NCF 95 state configuration */ 11068 uint32_t NCFSC94:2; /* NCF 94 state configuration */ 11069 uint32_t NCFSC93:2; /* NCF 93 state configuration */ 11070 uint32_t NCFSC92:2; /* NCF 92 state configuration */ 11071 uint32_t NCFSC91:2; /* NCF 91 state configuration */ 11072 uint32_t NCFSC90:2; /* NCF 90 state configuration */ 11073 uint32_t NCFSC89:2; /* NCF 89 state configuration */ 11074 uint32_t NCFSC88:2; /* NCF 88 state configuration */ 11075 uint32_t NCFSC87:2; /* NCF 87 state configuration */ 11076 uint32_t NCFSC86:2; /* NCF 86 state configuration */ 11077 uint32_t NCFSC85:2; /* NCF 85 state configuration */ 11078 uint32_t NCFSC84:2; /* NCF 84 state configuration */ 11079 uint32_t NCFSC83:2; /* NCF 83 state configuration */ 11080 uint32_t NCFSC82:2; /* NCF 82 state configuration */ 11081 uint32_t NCFSC81:2; /* NCF 81 state configuration */ 11082 uint32_t NCFSC80:2; /* NCF 80 state configuration */ 11083 } B; 11084 } FCCU_NCFS_CFG5_32B_tag; 11085 11086 typedef union { /* FCCU NCFS Configuration Register 6 */ 11087 uint32_t R; 11088 struct { 11089 uint32_t NCFSC111:2; /* NCF 111 state configuration */ 11090 uint32_t NCFSC110:2; /* NCF 110 state configuration */ 11091 uint32_t NCFSC109:2; /* NCF 109 state configuration */ 11092 uint32_t NCFSC108:2; /* NCF 108 state configuration */ 11093 uint32_t NCFSC107:2; /* NCF 107 state configuration */ 11094 uint32_t NCFSC106:2; /* NCF 106 state configuration */ 11095 uint32_t NCFSC105:2; /* NCF 105 state configuration */ 11096 uint32_t NCFSC104:2; /* NCF 104 state configuration */ 11097 uint32_t NCFSC103:2; /* NCF 103 state configuration */ 11098 uint32_t NCFSC102:2; /* NCF 102 state configuration */ 11099 uint32_t NCFSC101:2; /* NCF 101 state configuration */ 11100 uint32_t NCFSC100:2; /* NCF 100 state configuration */ 11101 uint32_t NCFSC99:2; /* NCF 99 state configuration */ 11102 uint32_t NCFSC98:2; /* NCF 98 state configuration */ 11103 uint32_t NCFSC97:2; /* NCF 97 state configuration */ 11104 uint32_t NCFSC96:2; /* NCF 96 state configuration */ 11105 } B; 11106 } FCCU_NCFS_CFG6_32B_tag; 11107 11108 typedef union { /* FCCU NCFS Configuration Register 7 */ 11109 uint32_t R; 11110 struct { 11111 uint32_t NCFSC127:2; /* NCF 127 state configuration */ 11112 uint32_t NCFSC126:2; /* NCF 126 state configuration */ 11113 uint32_t NCFSC125:2; /* NCF 125 state configuration */ 11114 uint32_t NCFSC124:2; /* NCF 124 state configuration */ 11115 uint32_t NCFSC123:2; /* NCF 123 state configuration */ 11116 uint32_t NCFSC122:2; /* NCF 122 state configuration */ 11117 uint32_t NCFSC121:2; /* NCF 121 state configuration */ 11118 uint32_t NCFSC120:2; /* NCF 120 state configuration */ 11119 uint32_t NCFSC119:2; /* NCF 119 state configuration */ 11120 uint32_t NCFSC118:2; /* NCF 118 state configuration */ 11121 uint32_t NCFSC117:2; /* NCF 117 state configuration */ 11122 uint32_t NCFSC116:2; /* NCF 116 state configuration */ 11123 uint32_t NCFSC115:2; /* NCF 115 state configuration */ 11124 uint32_t NCFSC114:2; /* NCF 114 state configuration */ 11125 uint32_t NCFSC113:2; /* NCF 113 state configuration */ 11126 uint32_t NCFSC112:2; /* NCF 112 state configuration */ 11127 } B; 11128 } FCCU_NCFS_CFG7_32B_tag; 11129 11130 typedef union { /* FCCU CF Status Register 0 */ 11131 uint32_t R; 11132 struct { 11133 uint32_t CFS31:1; /* CF 31 status */ 11134 uint32_t CFS30:1; /* CF 30 status */ 11135 uint32_t CFS29:1; /* CF 29 status */ 11136 uint32_t CFS28:1; /* CF 28 status */ 11137 uint32_t CFS27:1; /* CF 27 status */ 11138 uint32_t CFS26:1; /* CF 26 status */ 11139 uint32_t CFS25:1; /* CF 25 status */ 11140 uint32_t CFS24:1; /* CF 24 status */ 11141 uint32_t CFS23:1; /* CF 23 status */ 11142 uint32_t CFS22:1; /* CF 22 status */ 11143 uint32_t CFS21:1; /* CF 21 status */ 11144 uint32_t CFS20:1; /* CF 20 status */ 11145 uint32_t CFS19:1; /* CF 19 status */ 11146 uint32_t CFS18:1; /* CF 18 status */ 11147 uint32_t CFS17:1; /* CF 17 status */ 11148 uint32_t CFS16:1; /* CF 16 status */ 11149 uint32_t CFS15:1; /* CF 15 status */ 11150 uint32_t CFS14:1; /* CF 14 status */ 11151 uint32_t CFS13:1; /* CF 13 status */ 11152 uint32_t CFS12:1; /* CF 12 status */ 11153 uint32_t CFS11:1; /* CF 11 status */ 11154 uint32_t CFS10:1; /* CF 10 status */ 11155 uint32_t CFS9:1; /* CF 9 status */ 11156 uint32_t CFS8:1; /* CF 8 status */ 11157 uint32_t CFS7:1; /* CF 7 status */ 11158 uint32_t CFS6:1; /* CF 6 status */ 11159 uint32_t CFS5:1; /* CF 5 status */ 11160 uint32_t CFS4:1; /* CF 4 status */ 11161 uint32_t CFS3:1; /* CF 3 status */ 11162 uint32_t CFS2:1; /* CF 2 status */ 11163 uint32_t CFS1:1; /* CF 1 status */ 11164 uint32_t CFS0:1; /* CF 0 status */ 11165 } B; 11166 } FCCU_CFS0_32B_tag; 11167 11168 typedef union { /* FCCU CF Status Register 1 */ 11169 uint32_t R; 11170 struct { 11171 uint32_t CFS63:1; /* CF 63 status */ 11172 uint32_t CFS62:1; /* CF 62 status */ 11173 uint32_t CFS61:1; /* CF 61 status */ 11174 uint32_t CFS60:1; /* CF 60 status */ 11175 uint32_t CFS59:1; /* CF 59 status */ 11176 uint32_t CFS58:1; /* CF 58 status */ 11177 uint32_t CFS57:1; /* CF 57 status */ 11178 uint32_t CFS56:1; /* CF 56 status */ 11179 uint32_t CFS55:1; /* CF 55 status */ 11180 uint32_t CFS54:1; /* CF 54 status */ 11181 uint32_t CFS53:1; /* CF 53 status */ 11182 uint32_t CFS52:1; /* CF 52 status */ 11183 uint32_t CFS51:1; /* CF 51 status */ 11184 uint32_t CFS50:1; /* CF 50 status */ 11185 uint32_t CFS49:1; /* CF 49 status */ 11186 uint32_t CFS48:1; /* CF 48 status */ 11187 uint32_t CFS47:1; /* CF 47 status */ 11188 uint32_t CFS46:1; /* CF 46 status */ 11189 uint32_t CFS45:1; /* CF 45 status */ 11190 uint32_t CFS44:1; /* CF 44 status */ 11191 uint32_t CFS43:1; /* CF 43 status */ 11192 uint32_t CFS42:1; /* CF 42 status */ 11193 uint32_t CFS41:1; /* CF 41 status */ 11194 uint32_t CFS40:1; /* CF 40 status */ 11195 uint32_t CFS39:1; /* CF 39 status */ 11196 uint32_t CFS38:1; /* CF 38 status */ 11197 uint32_t CFS37:1; /* CF 37 status */ 11198 uint32_t CFS36:1; /* CF 36 status */ 11199 uint32_t CFS35:1; /* CF 35 status */ 11200 uint32_t CFS34:1; /* CF 34 status */ 11201 uint32_t CFS33:1; /* CF 33 status */ 11202 uint32_t CFS32:1; /* CF 32 status */ 11203 } B; 11204 } FCCU_CFS1_32B_tag; 11205 11206 typedef union { /* FCCU CF Status Register 2 */ 11207 uint32_t R; 11208 struct { 11209 uint32_t CFS95:1; /* CF 95 status */ 11210 uint32_t CFS94:1; /* CF 94 status */ 11211 uint32_t CFS93:1; /* CF 93 status */ 11212 uint32_t CFS92:1; /* CF 92 status */ 11213 uint32_t CFS91:1; /* CF 91 status */ 11214 uint32_t CFS90:1; /* CF 90 status */ 11215 uint32_t CFS89:1; /* CF 89 status */ 11216 uint32_t CFS88:1; /* CF 88 status */ 11217 uint32_t CFS87:1; /* CF 87 status */ 11218 uint32_t CFS86:1; /* CF 86 status */ 11219 uint32_t CFS85:1; /* CF 85 status */ 11220 uint32_t CFS84:1; /* CF 84 status */ 11221 uint32_t CFS83:1; /* CF 83 status */ 11222 uint32_t CFS82:1; /* CF 82 status */ 11223 uint32_t CFS81:1; /* CF 81 status */ 11224 uint32_t CFS80:1; /* CF 80 status */ 11225 uint32_t CFS79:1; /* CF 79 status */ 11226 uint32_t CFS78:1; /* CF 78 status */ 11227 uint32_t CFS77:1; /* CF 77 status */ 11228 uint32_t CFS76:1; /* CF 76 status */ 11229 uint32_t CFS75:1; /* CF 75 status */ 11230 uint32_t CFS74:1; /* CF 74 status */ 11231 uint32_t CFS73:1; /* CF 73 status */ 11232 uint32_t CFS72:1; /* CF 72 status */ 11233 uint32_t CFS71:1; /* CF 71 status */ 11234 uint32_t CFS70:1; /* CF 70 status */ 11235 uint32_t CFS69:1; /* CF 69 status */ 11236 uint32_t CFS68:1; /* CF 68 status */ 11237 uint32_t CFS67:1; /* CF 67 status */ 11238 uint32_t CFS66:1; /* CF 66 status */ 11239 uint32_t CFS65:1; /* CF 65 status */ 11240 uint32_t CFS64:1; /* CF 64 status */ 11241 } B; 11242 } FCCU_CFS2_32B_tag; 11243 11244 typedef union { /* FCCU CF Status Register 3 */ 11245 uint32_t R; 11246 struct { 11247 uint32_t CFS127:1; /* CF 127 status */ 11248 uint32_t CFS126:1; /* CF 126 status */ 11249 uint32_t CFS125:1; /* CF 125 status */ 11250 uint32_t CFS124:1; /* CF 124 status */ 11251 uint32_t CFS123:1; /* CF 123 status */ 11252 uint32_t CFS122:1; /* CF 122 status */ 11253 uint32_t CFS121:1; /* CF 121 status */ 11254 uint32_t CFS120:1; /* CF 120 status */ 11255 uint32_t CFS119:1; /* CF 119 status */ 11256 uint32_t CFS118:1; /* CF 118 status */ 11257 uint32_t CFS117:1; /* CF 117 status */ 11258 uint32_t CFS116:1; /* CF 116 status */ 11259 uint32_t CFS115:1; /* CF 115 status */ 11260 uint32_t CFS114:1; /* CF 114 status */ 11261 uint32_t CFS113:1; /* CF 113 status */ 11262 uint32_t CFS112:1; /* CF 112 status */ 11263 uint32_t CFS111:1; /* CF 111 status */ 11264 uint32_t CFS110:1; /* CF 110 status */ 11265 uint32_t CFS109:1; /* CF 109 status */ 11266 uint32_t CFS108:1; /* CF 108 status */ 11267 uint32_t CFS107:1; /* CF 107 status */ 11268 uint32_t CFS106:1; /* CF 106 status */ 11269 uint32_t CFS105:1; /* CF 105 status */ 11270 uint32_t CFS104:1; /* CF 104 status */ 11271 uint32_t CFS103:1; /* CF 103 status */ 11272 uint32_t CFS102:1; /* CF 102 status */ 11273 uint32_t CFS101:1; /* CF 101 status */ 11274 uint32_t CFS100:1; /* CF 100 status */ 11275 uint32_t CFS99:1; /* CF 99 status */ 11276 uint32_t CFS98:1; /* CF 98 status */ 11277 uint32_t CFS97:1; /* CF 97 status */ 11278 uint32_t CFS96:1; /* CF 96 status */ 11279 } B; 11280 } FCCU_CFS3_32B_tag; 11281 11282 typedef union { /* FCCU_CFK - FCCU CF Key Register */ 11283 uint32_t R; 11284 } FCCU_CFK_32B_tag; 11285 11286 typedef union { /* FCCU NCF Status Register 0 */ 11287 uint32_t R; 11288 struct { 11289 uint32_t NCFS31:1; /* NCF 31 status */ 11290 uint32_t NCFS30:1; /* NCF 30 status */ 11291 uint32_t NCFS29:1; /* NCF 29 status */ 11292 uint32_t NCFS28:1; /* NCF 28 status */ 11293 uint32_t NCFS27:1; /* NCF 27 status */ 11294 uint32_t NCFS26:1; /* NCF 26 status */ 11295 uint32_t NCFS25:1; /* NCF 25 status */ 11296 uint32_t NCFS24:1; /* NCF 24 status */ 11297 uint32_t NCFS23:1; /* NCF 23 status */ 11298 uint32_t NCFS22:1; /* NCF 22 status */ 11299 uint32_t NCFS21:1; /* NCF 21 status */ 11300 uint32_t NCFS20:1; /* NCF 20 status */ 11301 uint32_t NCFS19:1; /* NCF 19 status */ 11302 uint32_t NCFS18:1; /* NCF 18 status */ 11303 uint32_t NCFS17:1; /* NCF 17 status */ 11304 uint32_t NCFS16:1; /* NCF 16 status */ 11305 uint32_t NCFS15:1; /* NCF 15 status */ 11306 uint32_t NCFS14:1; /* NCF 14 status */ 11307 uint32_t NCFS13:1; /* NCF 13 status */ 11308 uint32_t NCFS12:1; /* NCF 12 status */ 11309 uint32_t NCFS11:1; /* NCF 11 status */ 11310 uint32_t NCFS10:1; /* NCF 10 status */ 11311 uint32_t NCFS9:1; /* NCF 9 status */ 11312 uint32_t NCFS8:1; /* NCF 8 status */ 11313 uint32_t NCFS7:1; /* NCF 7 status */ 11314 uint32_t NCFS6:1; /* NCF 6 status */ 11315 uint32_t NCFS5:1; /* NCF 5 status */ 11316 uint32_t NCFS4:1; /* NCF 4 status */ 11317 uint32_t NCFS3:1; /* NCF 3 status */ 11318 uint32_t NCFS2:1; /* NCF 2 status */ 11319 uint32_t NCFS1:1; /* NCF 1 status */ 11320 uint32_t NCFS0:1; /* NCF 0 status */ 11321 } B; 11322 } FCCU_NCFS0_32B_tag; 11323 11324 typedef union { /* FCCU NCF Status Register 1 */ 11325 uint32_t R; 11326 struct { 11327 uint32_t NCFS63:1; /* NCF 63 status */ 11328 uint32_t NCFS62:1; /* NCF 62 status */ 11329 uint32_t NCFS61:1; /* NCF 61 status */ 11330 uint32_t NCFS60:1; /* NCF 60 status */ 11331 uint32_t NCFS59:1; /* NCF 59 status */ 11332 uint32_t NCFS58:1; /* NCF 58 status */ 11333 uint32_t NCFS57:1; /* NCF 57 status */ 11334 uint32_t NCFS56:1; /* NCF 56 status */ 11335 uint32_t NCFS55:1; /* NCF 55 status */ 11336 uint32_t NCFS54:1; /* NCF 54 status */ 11337 uint32_t NCFS53:1; /* NCF 53 status */ 11338 uint32_t NCFS52:1; /* NCF 52 status */ 11339 uint32_t NCFS51:1; /* NCF 51 status */ 11340 uint32_t NCFS50:1; /* NCF 50 status */ 11341 uint32_t NCFS49:1; /* NCF 49 status */ 11342 uint32_t NCFS48:1; /* NCF 48 status */ 11343 uint32_t NCFS47:1; /* NCF 47 status */ 11344 uint32_t NCFS46:1; /* NCF 46 status */ 11345 uint32_t NCFS45:1; /* NCF 45 status */ 11346 uint32_t NCFS44:1; /* NCF 44 status */ 11347 uint32_t NCFS43:1; /* NCF 43 status */ 11348 uint32_t NCFS42:1; /* NCF 42 status */ 11349 uint32_t NCFS41:1; /* NCF 41 status */ 11350 uint32_t NCFS40:1; /* NCF 40 status */ 11351 uint32_t NCFS39:1; /* NCF 39 status */ 11352 uint32_t NCFS38:1; /* NCF 38 status */ 11353 uint32_t NCFS37:1; /* NCF 37 status */ 11354 uint32_t NCFS36:1; /* NCF 36 status */ 11355 uint32_t NCFS35:1; /* NCF 35 status */ 11356 uint32_t NCFS34:1; /* NCF 34 status */ 11357 uint32_t NCFS33:1; /* NCF 33 status */ 11358 uint32_t NCFS32:1; /* NCF 32 status */ 11359 } B; 11360 } FCCU_NCFS1_32B_tag; 11361 11362 typedef union { /* FCCU NCF Status Register 2 */ 11363 uint32_t R; 11364 struct { 11365 uint32_t NCFS95:1; /* NCF 95 status */ 11366 uint32_t NCFS94:1; /* NCF 94 status */ 11367 uint32_t NCFS93:1; /* NCF 93 status */ 11368 uint32_t NCFS92:1; /* NCF 92 status */ 11369 uint32_t NCFS91:1; /* NCF 91 status */ 11370 uint32_t NCFS90:1; /* NCF 90 status */ 11371 uint32_t NCFS89:1; /* NCF 89 status */ 11372 uint32_t NCFS88:1; /* NCF 88 status */ 11373 uint32_t NCFS87:1; /* NCF 87 status */ 11374 uint32_t NCFS86:1; /* NCF 86 status */ 11375 uint32_t NCFS85:1; /* NCF 85 status */ 11376 uint32_t NCFS84:1; /* NCF 84 status */ 11377 uint32_t NCFS83:1; /* NCF 83 status */ 11378 uint32_t NCFS82:1; /* NCF 82 status */ 11379 uint32_t NCFS81:1; /* NCF 81 status */ 11380 uint32_t NCFS80:1; /* NCF 80 status */ 11381 uint32_t NCFS79:1; /* NCF 79 status */ 11382 uint32_t NCFS78:1; /* NCF 78 status */ 11383 uint32_t NCFS77:1; /* NCF 77 status */ 11384 uint32_t NCFS76:1; /* NCF 76 status */ 11385 uint32_t NCFS75:1; /* NCF 75 status */ 11386 uint32_t NCFS74:1; /* NCF 74 status */ 11387 uint32_t NCFS73:1; /* NCF 73 status */ 11388 uint32_t NCFS72:1; /* NCF 72 status */ 11389 uint32_t NCFS71:1; /* NCF 71 status */ 11390 uint32_t NCFS70:1; /* NCF 70 status */ 11391 uint32_t NCFS69:1; /* NCF 69 status */ 11392 uint32_t NCFS68:1; /* NCF 68 status */ 11393 uint32_t NCFS67:1; /* NCF 67 status */ 11394 uint32_t NCFS66:1; /* NCF 66 status */ 11395 uint32_t NCFS65:1; /* NCF 65 status */ 11396 uint32_t NCFS64:1; /* NCF 64 status */ 11397 } B; 11398 } FCCU_NCFS2_32B_tag; 11399 11400 typedef union { /* FCCU NCF Status Register 3 */ 11401 uint32_t R; 11402 struct { 11403 uint32_t NCFS127:1; /* NCF 127 status */ 11404 uint32_t NCFS126:1; /* NCF 126 status */ 11405 uint32_t NCFS125:1; /* NCF 125 status */ 11406 uint32_t NCFS124:1; /* NCF 124 status */ 11407 uint32_t NCFS123:1; /* NCF 123 status */ 11408 uint32_t NCFS122:1; /* NCF 122 status */ 11409 uint32_t NCFS121:1; /* NCF 121 status */ 11410 uint32_t NCFS120:1; /* NCF 120 status */ 11411 uint32_t NCFS119:1; /* NCF 119 status */ 11412 uint32_t NCFS118:1; /* NCF 118 status */ 11413 uint32_t NCFS117:1; /* NCF 117 status */ 11414 uint32_t NCFS116:1; /* NCF 116 status */ 11415 uint32_t NCFS115:1; /* NCF 115 status */ 11416 uint32_t NCFS114:1; /* NCF 114 status */ 11417 uint32_t NCFS113:1; /* NCF 113 status */ 11418 uint32_t NCFS112:1; /* NCF 112 status */ 11419 uint32_t NCFS111:1; /* NCF 111 status */ 11420 uint32_t NCFS110:1; /* NCF 110 status */ 11421 uint32_t NCFS109:1; /* NCF 109 status */ 11422 uint32_t NCFS108:1; /* NCF 108 status */ 11423 uint32_t NCFS107:1; /* NCF 107 status */ 11424 uint32_t NCFS106:1; /* NCF 106 status */ 11425 uint32_t NCFS105:1; /* NCF 105 status */ 11426 uint32_t NCFS104:1; /* NCF 104 status */ 11427 uint32_t NCFS103:1; /* NCF 103 status */ 11428 uint32_t NCFS102:1; /* NCF 102 status */ 11429 uint32_t NCFS101:1; /* NCF 101 status */ 11430 uint32_t NCFS100:1; /* NCF 100 status */ 11431 uint32_t NCFS99:1; /* NCF 99 status */ 11432 uint32_t NCFS98:1; /* NCF 98 status */ 11433 uint32_t NCFS97:1; /* NCF 97 status */ 11434 uint32_t NCFS96:1; /* NCF 96 status */ 11435 } B; 11436 } FCCU_NCFS3_32B_tag; 11437 11438 typedef union { /* FCCU_NCFK - FCCU NCF Key Register */ 11439 uint32_t R; 11440 } FCCU_NCFK_32B_tag; 11441 11442 typedef union { /* FCCU NCF Enable Register 0 */ 11443 uint32_t R; 11444 struct { 11445 uint32_t NCFE31:1; /* NCF 31 enable */ 11446 uint32_t NCFE30:1; /* NCF 30 enable */ 11447 uint32_t NCFE29:1; /* NCF 29 enable */ 11448 uint32_t NCFE28:1; /* NCF 28 enable */ 11449 uint32_t NCFE27:1; /* NCF 27 enable */ 11450 uint32_t NCFE26:1; /* NCF 26 enable */ 11451 uint32_t NCFE25:1; /* NCF 25 enable */ 11452 uint32_t NCFE24:1; /* NCF 24 enable */ 11453 uint32_t NCFE23:1; /* NCF 23 enable */ 11454 uint32_t NCFE22:1; /* NCF 22 enable */ 11455 uint32_t NCFE21:1; /* NCF 21 enable */ 11456 uint32_t NCFE20:1; /* NCF 20 enable */ 11457 uint32_t NCFE19:1; /* NCF 19 enable */ 11458 uint32_t NCFE18:1; /* NCF 18 enable */ 11459 uint32_t NCFE17:1; /* NCF 17 enable */ 11460 uint32_t NCFE16:1; /* NCF 16 enable */ 11461 uint32_t NCFE15:1; /* NCF 15 enable */ 11462 uint32_t NCFE14:1; /* NCF 14 enable */ 11463 uint32_t NCFE13:1; /* NCF 13 enable */ 11464 uint32_t NCFE12:1; /* NCF 12 enable */ 11465 uint32_t NCFE11:1; /* NCF 11 enable */ 11466 uint32_t NCFE10:1; /* NCF 10 enable */ 11467 uint32_t NCFE9:1; /* NCF 9 enable */ 11468 uint32_t NCFE8:1; /* NCF 8 enable */ 11469 uint32_t NCFE7:1; /* NCF 7 enable */ 11470 uint32_t NCFE6:1; /* NCF 6 enable */ 11471 uint32_t NCFE5:1; /* NCF 5 enable */ 11472 uint32_t NCFE4:1; /* NCF 4 enable */ 11473 uint32_t NCFE3:1; /* NCF 3 enable */ 11474 uint32_t NCFE2:1; /* NCF 2 enable */ 11475 uint32_t NCFE1:1; /* NCF 1 enable */ 11476 uint32_t NCFE0:1; /* NCF 0 enable */ 11477 } B; 11478 } FCCU_NCFE0_32B_tag; 11479 11480 typedef union { /* FCCU NCF Enable Register 1 */ 11481 uint32_t R; 11482 struct { 11483 uint32_t NCFE63:1; /* NCF 63 enable */ 11484 uint32_t NCFE62:1; /* NCF 62 enable */ 11485 uint32_t NCFE61:1; /* NCF 61 enable */ 11486 uint32_t NCFE60:1; /* NCF 60 enable */ 11487 uint32_t NCFE59:1; /* NCF 59 enable */ 11488 uint32_t NCFE58:1; /* NCF 58 enable */ 11489 uint32_t NCFE57:1; /* NCF 57 enable */ 11490 uint32_t NCFE56:1; /* NCF 56 enable */ 11491 uint32_t NCFE55:1; /* NCF 55 enable */ 11492 uint32_t NCFE54:1; /* NCF 54 enable */ 11493 uint32_t NCFE53:1; /* NCF 53 enable */ 11494 uint32_t NCFE52:1; /* NCF 52 enable */ 11495 uint32_t NCFE51:1; /* NCF 51 enable */ 11496 uint32_t NCFE50:1; /* NCF 50 enable */ 11497 uint32_t NCFE49:1; /* NCF 49 enable */ 11498 uint32_t NCFE48:1; /* NCF 48 enable */ 11499 uint32_t NCFE47:1; /* NCF 47 enable */ 11500 uint32_t NCFE46:1; /* NCF 46 enable */ 11501 uint32_t NCFE45:1; /* NCF 45 enable */ 11502 uint32_t NCFE44:1; /* NCF 44 enable */ 11503 uint32_t NCFE43:1; /* NCF 43 enable */ 11504 uint32_t NCFE42:1; /* NCF 42 enable */ 11505 uint32_t NCFE41:1; /* NCF 41 enable */ 11506 uint32_t NCFE40:1; /* NCF 40 enable */ 11507 uint32_t NCFE39:1; /* NCF 39 enable */ 11508 uint32_t NCFE38:1; /* NCF 38 enable */ 11509 uint32_t NCFE37:1; /* NCF 37 enable */ 11510 uint32_t NCFE36:1; /* NCF 36 enable */ 11511 uint32_t NCFE35:1; /* NCF 35 enable */ 11512 uint32_t NCFE34:1; /* NCF 34 enable */ 11513 uint32_t NCFE33:1; /* NCF 33 enable */ 11514 uint32_t NCFE32:1; /* NCF 32 enable */ 11515 } B; 11516 } FCCU_NCFE1_32B_tag; 11517 11518 typedef union { /* FCCU NCF Enable Register 2 */ 11519 uint32_t R; 11520 struct { 11521 uint32_t NCFE95:1; /* NCF 95 enable */ 11522 uint32_t NCFE94:1; /* NCF 94 enable */ 11523 uint32_t NCFE93:1; /* NCF 93 enable */ 11524 uint32_t NCFE92:1; /* NCF 92 enable */ 11525 uint32_t NCFE91:1; /* NCF 91 enable */ 11526 uint32_t NCFE90:1; /* NCF 90 enable */ 11527 uint32_t NCFE89:1; /* NCF 89 enable */ 11528 uint32_t NCFE88:1; /* NCF 88 enable */ 11529 uint32_t NCFE87:1; /* NCF 87 enable */ 11530 uint32_t NCFE86:1; /* NCF 86 enable */ 11531 uint32_t NCFE85:1; /* NCF 85 enable */ 11532 uint32_t NCFE84:1; /* NCF 84 enable */ 11533 uint32_t NCFE83:1; /* NCF 83 enable */ 11534 uint32_t NCFE82:1; /* NCF 82 enable */ 11535 uint32_t NCFE81:1; /* NCF 81 enable */ 11536 uint32_t NCFE80:1; /* NCF 80 enable */ 11537 uint32_t NCFE79:1; /* NCF 79 enable */ 11538 uint32_t NCFE78:1; /* NCF 78 enable */ 11539 uint32_t NCFE77:1; /* NCF 77 enable */ 11540 uint32_t NCFE76:1; /* NCF 76 enable */ 11541 uint32_t NCFE75:1; /* NCF 75 enable */ 11542 uint32_t NCFE74:1; /* NCF 74 enable */ 11543 uint32_t NCFE73:1; /* NCF 73 enable */ 11544 uint32_t NCFE72:1; /* NCF 72 enable */ 11545 uint32_t NCFE71:1; /* NCF 71 enable */ 11546 uint32_t NCFE70:1; /* NCF 70 enable */ 11547 uint32_t NCFE69:1; /* NCF 69 enable */ 11548 uint32_t NCFE68:1; /* NCF 68 enable */ 11549 uint32_t NCFE67:1; /* NCF 67 enable */ 11550 uint32_t NCFE66:1; /* NCF 66 enable */ 11551 uint32_t NCFE65:1; /* NCF 65 enable */ 11552 uint32_t NCFE64:1; /* NCF 64 enable */ 11553 } B; 11554 } FCCU_NCFE2_32B_tag; 11555 11556 typedef union { /* FCCU NCF Enable Register 3 */ 11557 uint32_t R; 11558 struct { 11559 uint32_t NCFE127:1; /* NCF 127 enable */ 11560 uint32_t NCFE126:1; /* NCF 126 enable */ 11561 uint32_t NCFE125:1; /* NCF 125 enable */ 11562 uint32_t NCFE124:1; /* NCF 124 enable */ 11563 uint32_t NCFE123:1; /* NCF 123 enable */ 11564 uint32_t NCFE122:1; /* NCF 122 enable */ 11565 uint32_t NCFE121:1; /* NCF 121 enable */ 11566 uint32_t NCFE120:1; /* NCF 120 enable */ 11567 uint32_t NCFE119:1; /* NCF 119 enable */ 11568 uint32_t NCFE118:1; /* NCF 118 enable */ 11569 uint32_t NCFE117:1; /* NCF 117 enable */ 11570 uint32_t NCFE116:1; /* NCF 116 enable */ 11571 uint32_t NCFE115:1; /* NCF 115 enable */ 11572 uint32_t NCFE114:1; /* NCF 114 enable */ 11573 uint32_t NCFE113:1; /* NCF 113 enable */ 11574 uint32_t NCFE112:1; /* NCF 112 enable */ 11575 uint32_t NCFE111:1; /* NCF 111 enable */ 11576 uint32_t NCFE110:1; /* NCF 110 enable */ 11577 uint32_t NCFE109:1; /* NCF 109 enable */ 11578 uint32_t NCFE108:1; /* NCF 108 enable */ 11579 uint32_t NCFE107:1; /* NCF 107 enable */ 11580 uint32_t NCFE106:1; /* NCF 106 enable */ 11581 uint32_t NCFE105:1; /* NCF 105 enable */ 11582 uint32_t NCFE104:1; /* NCF 104 enable */ 11583 uint32_t NCFE103:1; /* NCF 103 enable */ 11584 uint32_t NCFE102:1; /* NCF 102 enable */ 11585 uint32_t NCFE101:1; /* NCF 101 enable */ 11586 uint32_t NCFE100:1; /* NCF 100 enable */ 11587 uint32_t NCFE99:1; /* NCF 99 enable */ 11588 uint32_t NCFE98:1; /* NCF 98 enable */ 11589 uint32_t NCFE97:1; /* NCF 97 enable */ 11590 uint32_t NCFE96:1; /* NCF 96 enable */ 11591 } B; 11592 } FCCU_NCFE3_32B_tag; 11593 11594 typedef union { /* FCCU NCF Time-out Enable Register 0 */ 11595 uint32_t R; 11596 struct { 11597 uint32_t NCFTOE31:1; /* NCF 31 time-out enable */ 11598 uint32_t NCFTOE30:1; /* NCF 30 time-out enable */ 11599 uint32_t NCFTOE29:1; /* NCF 29 time-out enable */ 11600 uint32_t NCFTOE28:1; /* NCF 28 time-out enable */ 11601 uint32_t NCFTOE27:1; /* NCF 27 time-out enable */ 11602 uint32_t NCFTOE26:1; /* NCF 26 time-out enable */ 11603 uint32_t NCFTOE25:1; /* NCF 25 time-out enable */ 11604 uint32_t NCFTOE24:1; /* NCF 24 time-out enable */ 11605 uint32_t NCFTOE23:1; /* NCF 23 time-out enable */ 11606 uint32_t NCFTOE22:1; /* NCF 22 time-out enable */ 11607 uint32_t NCFTOE21:1; /* NCF 21 time-out enable */ 11608 uint32_t NCFTOE20:1; /* NCF 20 time-out enable */ 11609 uint32_t NCFTOE19:1; /* NCF 19 time-out enable */ 11610 uint32_t NCFTOE18:1; /* NCF 18 time-out enable */ 11611 uint32_t NCFTOE17:1; /* NCF 17 time-out enable */ 11612 uint32_t NCFTOE16:1; /* NCF 16 time-out enable */ 11613 uint32_t NCFTOE15:1; /* NCF 15 time-out enable */ 11614 uint32_t NCFTOE14:1; /* NCF 14 time-out enable */ 11615 uint32_t NCFTOE13:1; /* NCF 13 time-out enable */ 11616 uint32_t NCFTOE12:1; /* NCF 12 time-out enable */ 11617 uint32_t NCFTOE11:1; /* NCF 11 time-out enable */ 11618 uint32_t NCFTOE10:1; /* NCF 10 time-out enable */ 11619 uint32_t NCFTOE9:1; /* NCF 9 time-out enable */ 11620 uint32_t NCFTOE8:1; /* NCF 8 time-out enable */ 11621 uint32_t NCFTOE7:1; /* NCF 7 time-out enable */ 11622 uint32_t NCFTOE6:1; /* NCF 6 time-out enable */ 11623 uint32_t NCFTOE5:1; /* NCF 5 time-out enable */ 11624 uint32_t NCFTOE4:1; /* NCF 4 time-out enable */ 11625 uint32_t NCFTOE3:1; /* NCF 3 time-out enable */ 11626 uint32_t NCFTOE2:1; /* NCF 2 time-out enable */ 11627 uint32_t NCFTOE1:1; /* NCF 1 time-out enable */ 11628 uint32_t NCFTOE0:1; /* NCF 0 time-out enable */ 11629 } B; 11630 } FCCU_NCF_TOE0_32B_tag; 11631 11632 typedef union { /* FCCU NCF Time-out Enable Register 1 */ 11633 uint32_t R; 11634 struct { 11635 uint32_t NCFTOE63:1; /* NCF 63 time-out enable */ 11636 uint32_t NCFTOE62:1; /* NCF 62 time-out enable */ 11637 uint32_t NCFTOE61:1; /* NCF 61 time-out enable */ 11638 uint32_t NCFTOE60:1; /* NCF 60 time-out enable */ 11639 uint32_t NCFTOE59:1; /* NCF 59 time-out enable */ 11640 uint32_t NCFTOE58:1; /* NCF 58 time-out enable */ 11641 uint32_t NCFTOE57:1; /* NCF 57 time-out enable */ 11642 uint32_t NCFTOE56:1; /* NCF 56 time-out enable */ 11643 uint32_t NCFTOE55:1; /* NCF 55 time-out enable */ 11644 uint32_t NCFTOE54:1; /* NCF 54 time-out enable */ 11645 uint32_t NCFTOE53:1; /* NCF 53 time-out enable */ 11646 uint32_t NCFTOE52:1; /* NCF 52 time-out enable */ 11647 uint32_t NCFTOE51:1; /* NCF 51 time-out enable */ 11648 uint32_t NCFTOE50:1; /* NCF 50 time-out enable */ 11649 uint32_t NCFTOE49:1; /* NCF 49 time-out enable */ 11650 uint32_t NCFTOE48:1; /* NCF 48 time-out enable */ 11651 uint32_t NCFTOE47:1; /* NCF 47 time-out enable */ 11652 uint32_t NCFTOE46:1; /* NCF 46 time-out enable */ 11653 uint32_t NCFTOE45:1; /* NCF 45 time-out enable */ 11654 uint32_t NCFTOE44:1; /* NCF 44 time-out enable */ 11655 uint32_t NCFTOE43:1; /* NCF 43 time-out enable */ 11656 uint32_t NCFTOE42:1; /* NCF 42 time-out enable */ 11657 uint32_t NCFTOE41:1; /* NCF 41 time-out enable */ 11658 uint32_t NCFTOE40:1; /* NCF 40 time-out enable */ 11659 uint32_t NCFTOE39:1; /* NCF 39 time-out enable */ 11660 uint32_t NCFTOE38:1; /* NCF 38 time-out enable */ 11661 uint32_t NCFTOE37:1; /* NCF 37 time-out enable */ 11662 uint32_t NCFTOE36:1; /* NCF 36 time-out enable */ 11663 uint32_t NCFTOE35:1; /* NCF 35 time-out enable */ 11664 uint32_t NCFTOE34:1; /* NCF 34 time-out enable */ 11665 uint32_t NCFTOE33:1; /* NCF 33 time-out enable */ 11666 uint32_t NCFTOE32:1; /* NCF 32 time-out enable */ 11667 } B; 11668 } FCCU_NCF_TOE1_32B_tag; 11669 11670 typedef union { /* FCCU NCF Time-out Enable Register 2 */ 11671 uint32_t R; 11672 struct { 11673 uint32_t NCFTOE95:1; /* NCF 95 time-out enable */ 11674 uint32_t NCFTOE94:1; /* NCF 94 time-out enable */ 11675 uint32_t NCFTOE93:1; /* NCF 93 time-out enable */ 11676 uint32_t NCFTOE92:1; /* NCF 92 time-out enable */ 11677 uint32_t NCFTOE91:1; /* NCF 91 time-out enable */ 11678 uint32_t NCFTOE90:1; /* NCF 90 time-out enable */ 11679 uint32_t NCFTOE89:1; /* NCF 89 time-out enable */ 11680 uint32_t NCFTOE88:1; /* NCF 88 time-out enable */ 11681 uint32_t NCFTOE87:1; /* NCF 87 time-out enable */ 11682 uint32_t NCFTOE86:1; /* NCF 86 time-out enable */ 11683 uint32_t NCFTOE85:1; /* NCF 85 time-out enable */ 11684 uint32_t NCFTOE84:1; /* NCF 84 time-out enable */ 11685 uint32_t NCFTOE83:1; /* NCF 83 time-out enable */ 11686 uint32_t NCFTOE82:1; /* NCF 82 time-out enable */ 11687 uint32_t NCFTOE81:1; /* NCF 81 time-out enable */ 11688 uint32_t NCFTOE80:1; /* NCF 80 time-out enable */ 11689 uint32_t NCFTOE79:1; /* NCF 79 time-out enable */ 11690 uint32_t NCFTOE78:1; /* NCF 78 time-out enable */ 11691 uint32_t NCFTOE77:1; /* NCF 77 time-out enable */ 11692 uint32_t NCFTOE76:1; /* NCF 76 time-out enable */ 11693 uint32_t NCFTOE75:1; /* NCF 75 time-out enable */ 11694 uint32_t NCFTOE74:1; /* NCF 74 time-out enable */ 11695 uint32_t NCFTOE73:1; /* NCF 73 time-out enable */ 11696 uint32_t NCFTOE72:1; /* NCF 72 time-out enable */ 11697 uint32_t NCFTOE71:1; /* NCF 71 time-out enable */ 11698 uint32_t NCFTOE70:1; /* NCF 70 time-out enable */ 11699 uint32_t NCFTOE69:1; /* NCF 69 time-out enable */ 11700 uint32_t NCFTOE68:1; /* NCF 68 time-out enable */ 11701 uint32_t NCFTOE67:1; /* NCF 67 time-out enable */ 11702 uint32_t NCFTOE66:1; /* NCF 66 time-out enable */ 11703 uint32_t NCFTOE65:1; /* NCF 65 time-out enable */ 11704 uint32_t NCFTOE64:1; /* NCF 64 time-out enable */ 11705 } B; 11706 } FCCU_NCF_TOE2_32B_tag; 11707 11708 typedef union { /* FCCU NCF Time-out Enable Register 3 */ 11709 uint32_t R; 11710 struct { 11711 uint32_t NCFTOE127:1; /* NCF 127 time-out enable */ 11712 uint32_t NCFTOE126:1; /* NCF 126 time-out enable */ 11713 uint32_t NCFTOE125:1; /* NCF 125 time-out enable */ 11714 uint32_t NCFTOE124:1; /* NCF 124 time-out enable */ 11715 uint32_t NCFTOE123:1; /* NCF 123 time-out enable */ 11716 uint32_t NCFTOE122:1; /* NCF 122 time-out enable */ 11717 uint32_t NCFTOE121:1; /* NCF 121 time-out enable */ 11718 uint32_t NCFTOE120:1; /* NCF 120 time-out enable */ 11719 uint32_t NCFTOE119:1; /* NCF 119 time-out enable */ 11720 uint32_t NCFTOE118:1; /* NCF 118 time-out enable */ 11721 uint32_t NCFTOE117:1; /* NCF 117 time-out enable */ 11722 uint32_t NCFTOE116:1; /* NCF 116 time-out enable */ 11723 uint32_t NCFTOE115:1; /* NCF 115 time-out enable */ 11724 uint32_t NCFTOE114:1; /* NCF 114 time-out enable */ 11725 uint32_t NCFTOE113:1; /* NCF 113 time-out enable */ 11726 uint32_t NCFTOE112:1; /* NCF 112 time-out enable */ 11727 uint32_t NCFTOE111:1; /* NCF 111 time-out enable */ 11728 uint32_t NCFTOE110:1; /* NCF 110 time-out enable */ 11729 uint32_t NCFTOE109:1; /* NCF 109 time-out enable */ 11730 uint32_t NCFTOE108:1; /* NCF 108 time-out enable */ 11731 uint32_t NCFTOE107:1; /* NCF 107 time-out enable */ 11732 uint32_t NCFTOE106:1; /* NCF 106 time-out enable */ 11733 uint32_t NCFTOE105:1; /* NCF 105 time-out enable */ 11734 uint32_t NCFTOE104:1; /* NCF 104 time-out enable */ 11735 uint32_t NCFTOE103:1; /* NCF 103 time-out enable */ 11736 uint32_t NCFTOE102:1; /* NCF 102 time-out enable */ 11737 uint32_t NCFTOE101:1; /* NCF 101 time-out enable */ 11738 uint32_t NCFTOE100:1; /* NCF 100 time-out enable */ 11739 uint32_t NCFTOE99:1; /* NCF 99 time-out enable */ 11740 uint32_t NCFTOE98:1; /* NCF 98 time-out enable */ 11741 uint32_t NCFTOE97:1; /* NCF 97 time-out enable */ 11742 uint32_t NCFTOE96:1; /* NCF 96 time-out enable */ 11743 } B; 11744 } FCCU_NCF_TOE3_32B_tag; 11745 11746 typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */ 11747 uint32_t R; 11748 } FCCU_NCF_TO_32B_tag; 11749 11750 typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */ 11751 uint32_t R; 11752 struct { 11753 uint32_t:29; 11754 uint32_t TO:3; /* Configuration time-out */ 11755 } B; 11756 } FCCU_CFG_TO_32B_tag; 11757 11758 typedef union { /* FCCU_EINOUT - FCCU IO Control Register */ 11759 uint32_t R; 11760 struct { 11761 uint32_t:26; 11762 uint32_t EIN1:1; /* Error input 1 */ 11763 uint32_t EIN0:1; /* Error input 0 */ 11764 uint32_t:2; 11765 uint32_t EOUT1:1; /* Error out 1 */ 11766 uint32_t EOUT0:1; /* Error out 0 */ 11767 } B; 11768 } FCCU_EINOUT_32B_tag; 11769 11770 typedef union { /* FCCU_STAT - FCCU Status Register */ 11771 uint32_t R; 11772 struct { 11773 uint32_t:29; 11774 uint32_t STATUS:3; /* FCCU status */ 11775 } B; 11776 } FCCU_STAT_32B_tag; 11777 11778 typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */ 11779 uint32_t R; 11780 struct { 11781 uint32_t:24; 11782 uint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */ 11783 } B; 11784 } FCCU_NAFS_32B_tag; 11785 11786 typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */ 11787 uint32_t R; 11788 struct { 11789 uint32_t:22; 11790 uint32_t AFFS_SRC:2; /* Fault source */ 11791 uint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */ 11792 } B; 11793 } FCCU_AFFS_32B_tag; 11794 11795 typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */ 11796 uint32_t R; 11797 struct { 11798 uint32_t:22; 11799 uint32_t NFFS_SRC:2; /* Fault source */ 11800 uint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */ 11801 } B; 11802 } FCCU_NFFS_32B_tag; 11803 11804 typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */ 11805 uint32_t R; 11806 struct { 11807 uint32_t:24; 11808 uint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */ 11809 } B; 11810 } FCCU_FAFS_32B_tag; 11811 11812 typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */ 11813 uint32_t R; 11814 struct { 11815 uint32_t:30; 11816 uint32_t RCCS1:1; /* RCC1 Status */ 11817 uint32_t RCCS0:1; /* RCC0 Status */ 11818 } B; 11819 } FCCU_SCFS_32B_tag; 11820 11821 typedef union { /* FCCU_CFF - FCCU CF Fake Register */ 11822 uint32_t R; 11823 struct { 11824 uint32_t:25; 11825 uint32_t FCFC:7; /* Fake critical fault code */ 11826 } B; 11827 } FCCU_CFF_32B_tag; 11828 11829 typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */ 11830 uint32_t R; 11831 struct { 11832 uint32_t:25; 11833 uint32_t FNCFC:7; /* Fake non-critical fault code */ 11834 } B; 11835 } FCCU_NCFF_32B_tag; 11836 11837 typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ 11838 uint32_t R; 11839 struct { 11840 uint32_t:29; 11841 uint32_t NMI_STAT:1; /* NMI Interrupt Status */ 11842 uint32_t ALRM_STAT:1; /* Alarm Interrupt Status */ 11843 uint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */ 11844 } B; 11845 } FCCU_IRQ_STAT_32B_tag; 11846 11847 typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ 11848 uint32_t R; 11849 struct { 11850 uint32_t:31; 11851 uint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */ 11852 } B; 11853 } FCCU_IRQ_EN_32B_tag; 11854 11855 typedef union { /* FCCU_XTMR - FCCU XTMR Register */ 11856 uint32_t R; 11857 struct { 11858 uint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */ 11859 } B; 11860 } FCCU_XTMR_32B_tag; 11861 11862 typedef union { /* FCCU_MCS - FCCU MCS Register */ 11863 uint32_t R; 11864 struct { 11865 uint32_t VL3:1; /* Valid */ 11866 uint32_t FS3:1; /* Fault Status */ 11867 uint32_t:2; 11868 uint32_t MCS3:4; /* Magic Carpet oldest state */ 11869 uint32_t VL2:1; /* Valid */ 11870 uint32_t FS2:1; /* Fault Status */ 11871 uint32_t:2; 11872 uint32_t MCS2:4; /* Magic Carpet previous-previous state */ 11873 uint32_t VL1:1; /* Valid */ 11874 uint32_t FS1:1; /* Fault Status */ 11875 uint32_t:2; 11876 uint32_t MCS1:4; /* Magic Carpet previous state */ 11877 uint32_t VL0:1; /* Valid */ 11878 uint32_t FS0:1; /* Fault Status */ 11879 uint32_t:2; 11880 uint32_t MCS0:4; /* Magic Carpet latest state */ 11881 } B; 11882 } FCCU_MCS_32B_tag; 11883 11884 11885 /* Register layout for generated register(s) CF_CFG... */ 11886 11887 typedef union { /* */ 11888 uint32_t R; 11889 } FCCU_CF_CFG_32B_tag; 11890 11891 11892 /* Register layout for generated register(s) NCF_CFG... */ 11893 11894 typedef union { /* */ 11895 uint32_t R; 11896 } FCCU_NCF_CFG_32B_tag; 11897 11898 11899 /* Register layout for generated register(s) CFS_CFG... */ 11900 11901 typedef union { /* */ 11902 uint32_t R; 11903 } FCCU_CFS_CFG_32B_tag; 11904 11905 11906 /* Register layout for generated register(s) NCFS_CFG... */ 11907 11908 typedef union { /* */ 11909 uint32_t R; 11910 } FCCU_NCFS_CFG_32B_tag; 11911 11912 11913 /* Register layout for generated register(s) CFS... */ 11914 11915 typedef union { /* */ 11916 uint32_t R; 11917 } FCCU_CFS_32B_tag; 11918 11919 11920 /* Register layout for generated register(s) NCFS... */ 11921 11922 typedef union { /* */ 11923 uint32_t R; 11924 } FCCU_NCFS_32B_tag; 11925 11926 11927 /* Register layout for generated register(s) NCFE... */ 11928 11929 typedef union { /* */ 11930 uint32_t R; 11931 } FCCU_NCFE_32B_tag; 11932 11933 11934 /* Register layout for generated register(s) NCF_TOE... */ 11935 11936 typedef union { /* */ 11937 uint32_t R; 11938 } FCCU_NCF_TOE_32B_tag; 11939 11940 11941 11942 typedef struct FCCU_struct_tag { /* start of FCCU_tag */ 11943 /* FCCU Control Register */ 11944 FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ 11945 /* FCCU CTRL Key Register */ 11946 FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */ 11947 /* FCCU Configuration Register */ 11948 FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */ 11949 union { 11950 FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */ 11951 11952 struct { 11953 /* FCCU CF Configuration Register 0 */ 11954 FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */ 11955 /* FCCU CF Configuration Register 1 */ 11956 FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */ 11957 /* FCCU CF Configuration Register 2 */ 11958 FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */ 11959 /* FCCU CF Configuration Register 3 */ 11960 FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */ 11961 }; 11962 11963 }; 11964 union { 11965 FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */ 11966 11967 struct { 11968 /* FCCU NCF Configuration Register 0 */ 11969 FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */ 11970 /* FCCU NCF Configuration Register 1 */ 11971 FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */ 11972 /* FCCU NCF Configuration Register 2 */ 11973 FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */ 11974 /* FCCU NCF Configuration Register 3 */ 11975 FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */ 11976 }; 11977 11978 }; 11979 union { 11980 FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */ 11981 11982 struct { 11983 /* FCCU CFS Configuration Register 0 */ 11984 FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */ 11985 /* FCCU CFS Configuration Register 1 */ 11986 FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */ 11987 /* FCCU CFS Configuration Register 2 */ 11988 FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */ 11989 /* FCCU CFS Configuration Register 3 */ 11990 FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */ 11991 /* FCCU CFS Configuration Register 4 */ 11992 FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */ 11993 /* FCCU CFS Configuration Register 5 */ 11994 FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */ 11995 /* FCCU CFS Configuration Register 6 */ 11996 FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */ 11997 /* FCCU CFS Configuration Register 7 */ 11998 FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */ 11999 }; 12000 12001 }; 12002 union { 12003 FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */ 12004 12005 struct { 12006 /* FCCU NCFS Configuration Register 0 */ 12007 FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */ 12008 /* FCCU NCFS Configuration Register 1 */ 12009 FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */ 12010 /* FCCU NCFS Configuration Register 2 */ 12011 FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */ 12012 /* FCCU NCFS Configuration Register 3 */ 12013 FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */ 12014 /* FCCU NCFS Configuration Register 4 */ 12015 FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */ 12016 /* FCCU NCFS Configuration Register 5 */ 12017 FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */ 12018 /* FCCU NCFS Configuration Register 6 */ 12019 FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */ 12020 /* FCCU NCFS Configuration Register 7 */ 12021 FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */ 12022 }; 12023 12024 }; 12025 union { 12026 FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */ 12027 12028 struct { 12029 /* FCCU CF Status Register 0 */ 12030 FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */ 12031 /* FCCU CF Status Register 1 */ 12032 FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */ 12033 /* FCCU CF Status Register 2 */ 12034 FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */ 12035 /* FCCU CF Status Register 3 */ 12036 FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */ 12037 }; 12038 12039 }; 12040 /* FCCU_CFK - FCCU CF Key Register */ 12041 FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */ 12042 union { 12043 FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */ 12044 12045 struct { 12046 /* FCCU NCF Status Register 0 */ 12047 FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */ 12048 /* FCCU NCF Status Register 1 */ 12049 FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */ 12050 /* FCCU NCF Status Register 2 */ 12051 FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */ 12052 /* FCCU NCF Status Register 3 */ 12053 FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */ 12054 }; 12055 12056 }; 12057 /* FCCU_NCFK - FCCU NCF Key Register */ 12058 FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */ 12059 union { 12060 FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */ 12061 12062 struct { 12063 /* FCCU NCF Enable Register 0 */ 12064 FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */ 12065 /* FCCU NCF Enable Register 1 */ 12066 FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */ 12067 /* FCCU NCF Enable Register 2 */ 12068 FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */ 12069 /* FCCU NCF Enable Register 3 */ 12070 FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */ 12071 }; 12072 12073 }; 12074 union { 12075 FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */ 12076 12077 struct { 12078 /* FCCU NCF Time-out Enable Register 0 */ 12079 FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */ 12080 /* FCCU NCF Time-out Enable Register 1 */ 12081 FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */ 12082 /* FCCU NCF Time-out Enable Register 2 */ 12083 FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */ 12084 /* FCCU NCF Time-out Enable Register 3 */ 12085 FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */ 12086 }; 12087 12088 }; 12089 /* FCCU_NCF_TO - FCCU NCF Time-out Register */ 12090 FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */ 12091 /* FCCU_CFG_TO - FCCU CFG Timeout Register */ 12092 FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */ 12093 /* FCCU_EINOUT - FCCU IO Control Register */ 12094 FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */ 12095 /* FCCU_STAT - FCCU Status Register */ 12096 FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */ 12097 /* FCCU_NAFS - FCCU NA Freeze Status Register */ 12098 FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */ 12099 /* FCCU_AFFS - FCCU AF Freeze Status Register */ 12100 FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */ 12101 /* FCCU_NFFS - FCCU NF Freeze Status Register */ 12102 FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */ 12103 /* FCCU_FAFS - FCCU FA Freeze Status Register */ 12104 FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */ 12105 /* FCCU_SCFS - FCCU SC Freeze Status Register */ 12106 FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */ 12107 /* FCCU_CFF - FCCU CF Fake Register */ 12108 FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */ 12109 /* FCCU_NCFF - FCCU NCF Fake Register */ 12110 FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */ 12111 /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ 12112 FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */ 12113 /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ 12114 FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */ 12115 /* FCCU_XTMR - FCCU XTMR Register */ 12116 FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */ 12117 /* FCCU_MCS - FCCU MCS Register */ 12118 FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */ 12119 } FCCU_tag; 12120 12121 12122 #define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL) 12123 12124 12125 12126 /****************************************************************/ 12127 /* */ 12128 /* Module: SGENDIG */ 12129 /* */ 12130 /****************************************************************/ 12131 12132 typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */ 12133 uint32_t R; 12134 struct { 12135 uint32_t LDOS:1; /* Operation Status */ 12136 uint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */ 12137 uint32_t:2; 12138 uint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */ 12139 uint32_t:5; 12140 uint32_t S0H1:1; /* Operation Status */ 12141 uint32_t PDS:1; /* Operation Status */ 12142 uint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */ 12143 } B; 12144 } SGENDIG_CTRL_32B_tag; 12145 12146 typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ 12147 uint32_t R; 12148 struct { 12149 uint32_t:8; 12150 uint32_t SERR:1; /* Sine wave generator Error bit */ 12151 uint32_t:3; 12152 uint32_t FERR:1; /* Sine wave generator Force Error bit */ 12153 uint32_t:19; 12154 } B; 12155 } SGENDIG_IRQE_32B_tag; 12156 12157 12158 12159 typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */ 12160 /* SGENDIG_CTRL - SGENDIG Control Register */ 12161 SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ 12162 /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ 12163 SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */ 12164 } SGENDIG_tag; 12165 12166 12167 #define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL) 12168 12169 12170 12171 /****************************************************************/ 12172 /* */ 12173 /* Module: PBRIDGE */ 12174 /* */ 12175 /****************************************************************/ 12176 12177 typedef union { /* MPROT - Master Privilege Registers */ 12178 uint32_t R; 12179 struct { 12180 uint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */ 12181 uint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */ 12182 uint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */ 12183 uint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */ 12184 uint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */ 12185 uint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */ 12186 uint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */ 12187 uint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */ 12188 uint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */ 12189 uint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */ 12190 uint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */ 12191 uint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */ 12192 uint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */ 12193 uint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */ 12194 uint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */ 12195 uint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */ 12196 uint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */ 12197 uint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */ 12198 uint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */ 12199 uint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */ 12200 uint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */ 12201 uint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */ 12202 uint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */ 12203 uint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */ 12204 uint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */ 12205 uint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */ 12206 uint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */ 12207 uint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */ 12208 uint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */ 12209 uint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */ 12210 uint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */ 12211 uint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */ 12212 } B; 12213 } PBRIDGE_MPROT_32B_tag; 12214 12215 typedef union { /* PACR0_7 - Peripheral Access Control Registers */ 12216 uint32_t R; 12217 struct { 12218 uint32_t PACR0_BW:1; /* Buffer Writes */ 12219 uint32_t PACR0_SP:1; /* Supervisor Protect */ 12220 uint32_t PACR0_WP:1; /* Write Protect */ 12221 uint32_t PACR0_TP:1; /* Trusted Protect */ 12222 uint32_t PACR1_BW:1; /* Buffer Writes */ 12223 uint32_t PACR1_SP:1; /* Supervisor Protect */ 12224 uint32_t PACR1_WP:1; /* Write Protect */ 12225 uint32_t PACR1_TP:1; /* Trusted Protect */ 12226 uint32_t PACR2_BW:1; /* Buffer Writes */ 12227 uint32_t PACR2_SP:1; /* Supervisor Protect */ 12228 uint32_t PACR2_WP:1; /* Write Protect */ 12229 uint32_t PACR2_TP:1; /* Trusted Protect */ 12230 uint32_t PACR3_BW:1; /* Buffer Writes */ 12231 uint32_t PACR3_SP:1; /* Supervisor Protect */ 12232 uint32_t PACR3_WP:1; /* Write Protect */ 12233 uint32_t PACR3_TP:1; /* Trusted Protect */ 12234 uint32_t PACR4_BW:1; /* Buffer Writes */ 12235 uint32_t PACR4_SP:1; /* Supervisor Protect */ 12236 uint32_t PACR4_WP:1; /* Write Protect */ 12237 uint32_t PACR4_TP:1; /* Trusted Protect */ 12238 uint32_t PACR5_BW:1; /* Buffer Writes */ 12239 uint32_t PACR5_SP:1; /* Supervisor Protect */ 12240 uint32_t PACR5_WP:1; /* Write Protect */ 12241 uint32_t PACR5_TP:1; /* Trusted Protect */ 12242 uint32_t PACR6_BW:1; /* Buffer Writes */ 12243 uint32_t PACR6_SP:1; /* Supervisor Protect */ 12244 uint32_t PACR6_WP:1; /* Write Protect */ 12245 uint32_t PACR6_TP:1; /* Trusted Protect */ 12246 uint32_t PACR7_BW:1; /* Buffer Writes */ 12247 uint32_t PACR7_SP:1; /* Supervisor Protect */ 12248 uint32_t PACR7_WP:1; /* Write Protect */ 12249 uint32_t PACR7_TP:1; /* Trusted Protect */ 12250 } B; 12251 } PBRIDGE_PACR0_7_32B_tag; 12252 12253 typedef union { /* PACR8_15 - Peripheral Access Control Registers */ 12254 uint32_t R; 12255 struct { 12256 uint32_t PACR8_BW:1; /* Buffer Writes */ 12257 uint32_t PACR8_SP:1; /* Supervisor Protect */ 12258 uint32_t PACR8_WP:1; /* Write Protect */ 12259 uint32_t PACR8_TP:1; /* Trusted Protect */ 12260 uint32_t PACR9_BW:1; /* Buffer Writes */ 12261 uint32_t PACR9_SP:1; /* Supervisor Protect */ 12262 uint32_t PACR9_WP:1; /* Write Protect */ 12263 uint32_t PACR9_TP:1; /* Trusted Protect */ 12264 uint32_t PACR10_BW:1; /* Buffer Writes */ 12265 uint32_t PACR10_SP:1; /* Supervisor Protect */ 12266 uint32_t PACR10_WP:1; /* Write Protect */ 12267 uint32_t PACR10_TP:1; /* Trusted Protect */ 12268 uint32_t PACR11_BW:1; /* Buffer Writes */ 12269 uint32_t PACR11_SP:1; /* Supervisor Protect */ 12270 uint32_t PACR11_WP:1; /* Write Protect */ 12271 uint32_t PACR11_TP:1; /* Trusted Protect */ 12272 uint32_t PACR12_BW:1; /* Buffer Writes */ 12273 uint32_t PACR12_SP:1; /* Supervisor Protect */ 12274 uint32_t PACR12_WP:1; /* Write Protect */ 12275 uint32_t PACR12_TP:1; /* Trusted Protect */ 12276 uint32_t PACR13_BW:1; /* Buffer Writes */ 12277 uint32_t PACR13_SP:1; /* Supervisor Protect */ 12278 uint32_t PACR13_WP:1; /* Write Protect */ 12279 uint32_t PACR13_TP:1; /* Trusted Protect */ 12280 uint32_t PACR14_BW:1; /* Buffer Writes */ 12281 uint32_t PACR14_SP:1; /* Supervisor Protect */ 12282 uint32_t PACR14_WP:1; /* Write Protect */ 12283 uint32_t PACR14_TP:1; /* Trusted Protect */ 12284 uint32_t PACR15_BW:1; /* Buffer Writes */ 12285 uint32_t PACR15_SP:1; /* Supervisor Protect */ 12286 uint32_t PACR15_WP:1; /* Write Protect */ 12287 uint32_t PACR15_TP:1; /* Trusted Protect */ 12288 } B; 12289 } PBRIDGE_PACR8_15_32B_tag; 12290 12291 typedef union { /* PACR16_23 - Peripheral Access Control Registers */ 12292 uint32_t R; 12293 struct { 12294 uint32_t PACR16_BW:1; /* Buffer Writes */ 12295 uint32_t PACR16_SP:1; /* Supervisor Protect */ 12296 uint32_t PACR16_WP:1; /* Write Protect */ 12297 uint32_t PACR16_TP:1; /* Trusted Protect */ 12298 uint32_t PACR17_BW:1; /* Buffer Writes */ 12299 uint32_t PACR17_SP:1; /* Supervisor Protect */ 12300 uint32_t PACR17_WP:1; /* Write Protect */ 12301 uint32_t PACR17_TP:1; /* Trusted Protect */ 12302 uint32_t PACR18_BW:1; /* Buffer Writes */ 12303 uint32_t PACR18_SP:1; /* Supervisor Protect */ 12304 uint32_t PACR18_WP:1; /* Write Protect */ 12305 uint32_t PACR18_TP:1; /* Trusted Protect */ 12306 uint32_t PACR19_BW:1; /* Buffer Writes */ 12307 uint32_t PACR19_SP:1; /* Supervisor Protect */ 12308 uint32_t PACR19_WP:1; /* Write Protect */ 12309 uint32_t PACR19_TP:1; /* Trusted Protect */ 12310 uint32_t PACR20_BW:1; /* Buffer Writes */ 12311 uint32_t PACR20_SP:1; /* Supervisor Protect */ 12312 uint32_t PACR20_WP:1; /* Write Protect */ 12313 uint32_t PACR20_TP:1; /* Trusted Protect */ 12314 uint32_t PACR21_BW:1; /* Buffer Writes */ 12315 uint32_t PACR21_SP:1; /* Supervisor Protect */ 12316 uint32_t PACR21_WP:1; /* Write Protect */ 12317 uint32_t PACR21_TP:1; /* Trusted Protect */ 12318 uint32_t PACR22_BW:1; /* Buffer Writes */ 12319 uint32_t PACR22_SP:1; /* Supervisor Protect */ 12320 uint32_t PACR22_WP:1; /* Write Protect */ 12321 uint32_t PACR22_TP:1; /* Trusted Protect */ 12322 uint32_t PACR23_BW:1; /* Buffer Writes */ 12323 uint32_t PACR23_SP:1; /* Supervisor Protect */ 12324 uint32_t PACR23_WP:1; /* Write Protect */ 12325 uint32_t PACR23_TP:1; /* Trusted Protect */ 12326 } B; 12327 } PBRIDGE_PACR16_23_32B_tag; 12328 12329 typedef union { /* PACR24_31 - Peripheral Access Control Registers */ 12330 uint32_t R; 12331 struct { 12332 uint32_t PACR24_BW:1; /* Buffer Writes */ 12333 uint32_t PACR24_SP:1; /* Supervisor Protect */ 12334 uint32_t PACR24_WP:1; /* Write Protect */ 12335 uint32_t PACR24_TP:1; /* Trusted Protect */ 12336 uint32_t PACR25_BW:1; /* Buffer Writes */ 12337 uint32_t PACR25_SP:1; /* Supervisor Protect */ 12338 uint32_t PACR25_WP:1; /* Write Protect */ 12339 uint32_t PACR25_TP:1; /* Trusted Protect */ 12340 uint32_t PACR26_BW:1; /* Buffer Writes */ 12341 uint32_t PACR26_SP:1; /* Supervisor Protect */ 12342 uint32_t PACR26_WP:1; /* Write Protect */ 12343 uint32_t PACR26_TP:1; /* Trusted Protect */ 12344 uint32_t PACR27_BW:1; /* Buffer Writes */ 12345 uint32_t PACR27_SP:1; /* Supervisor Protect */ 12346 uint32_t PACR27_WP:1; /* Write Protect */ 12347 uint32_t PACR27_TP:1; /* Trusted Protect */ 12348 uint32_t PACR28_BW:1; /* Buffer Writes */ 12349 uint32_t PACR28_SP:1; /* Supervisor Protect */ 12350 uint32_t PACR28_WP:1; /* Write Protect */ 12351 uint32_t PACR28_TP:1; /* Trusted Protect */ 12352 uint32_t PACR29_BW:1; /* Buffer Writes */ 12353 uint32_t PACR29_SP:1; /* Supervisor Protect */ 12354 uint32_t PACR29_WP:1; /* Write Protect */ 12355 uint32_t PACR29_TP:1; /* Trusted Protect */ 12356 uint32_t PACR30_BW:1; /* Buffer Writes */ 12357 uint32_t PACR30_SP:1; /* Supervisor Protect */ 12358 uint32_t PACR30_WP:1; /* Write Protect */ 12359 uint32_t PACR30_TP:1; /* Trusted Protect */ 12360 uint32_t PACR31_BW:1; /* Buffer Writes */ 12361 uint32_t PACR31_SP:1; /* Supervisor Protect */ 12362 uint32_t PACR31_WP:1; /* Write Protect */ 12363 uint32_t PACR31_TP:1; /* Trusted Protect */ 12364 } B; 12365 } PBRIDGE_PACR24_31_32B_tag; 12366 12367 typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ 12368 uint32_t R; 12369 struct { 12370 uint32_t OPACR0_BW:1; /* Buffer Writes */ 12371 uint32_t OPACR0_SP:1; /* Supervisor Protect */ 12372 uint32_t OPACR0_WP:1; /* Write Protect */ 12373 uint32_t OPACR0_TP:1; /* Trusted Protect */ 12374 uint32_t OPACR1_BW:1; /* Buffer Writes */ 12375 uint32_t OPACR1_SP:1; /* Supervisor Protect */ 12376 uint32_t OPACR1_WP:1; /* Write Protect */ 12377 uint32_t OPACR1_TP:1; /* Trusted Protect */ 12378 uint32_t OPACR2_BW:1; /* Buffer Writes */ 12379 uint32_t OPACR2_SP:1; /* Supervisor Protect */ 12380 uint32_t OPACR2_WP:1; /* Write Protect */ 12381 uint32_t OPACR2_TP:1; /* Trusted Protect */ 12382 uint32_t OPACR3_BW:1; /* Buffer Writes */ 12383 uint32_t OPACR3_SP:1; /* Supervisor Protect */ 12384 uint32_t OPACR3_WP:1; /* Write Protect */ 12385 uint32_t OPACR3_TP:1; /* Trusted Protect */ 12386 uint32_t OPACR4_BW:1; /* Buffer Writes */ 12387 uint32_t OPACR4_SP:1; /* Supervisor Protect */ 12388 uint32_t OPACR4_WP:1; /* Write Protect */ 12389 uint32_t OPACR4_TP:1; /* Trusted Protect */ 12390 uint32_t OPACR5_BW:1; /* Buffer Writes */ 12391 uint32_t OPACR5_SP:1; /* Supervisor Protect */ 12392 uint32_t OPACR5_WP:1; /* Write Protect */ 12393 uint32_t OPACR5_TP:1; /* Trusted Protect */ 12394 uint32_t OPACR6_BW:1; /* Buffer Writes */ 12395 uint32_t OPACR6_SP:1; /* Supervisor Protect */ 12396 uint32_t OPACR6_WP:1; /* Write Protect */ 12397 uint32_t OPACR6_TP:1; /* Trusted Protect */ 12398 uint32_t OPACR7_BW:1; /* Buffer Writes */ 12399 uint32_t OPACR7_SP:1; /* Supervisor Protect */ 12400 uint32_t OPACR7_WP:1; /* Write Protect */ 12401 uint32_t OPACR7_TP:1; /* Trusted Protect */ 12402 } B; 12403 } PBRIDGE_OPACR0_7_32B_tag; 12404 12405 typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ 12406 uint32_t R; 12407 struct { 12408 uint32_t OPACR8_BW:1; /* Buffer Writes */ 12409 uint32_t OPACR8_SP:1; /* Supervisor Protect */ 12410 uint32_t OPACR8_WP:1; /* Write Protect */ 12411 uint32_t OPACR8_TP:1; /* Trusted Protect */ 12412 uint32_t OPACR9_BW:1; /* Buffer Writes */ 12413 uint32_t OPACR9_SP:1; /* Supervisor Protect */ 12414 uint32_t OPACR9_WP:1; /* Write Protect */ 12415 uint32_t OPACR9_TP:1; /* Trusted Protect */ 12416 uint32_t OPACR10_BW:1; /* Buffer Writes */ 12417 uint32_t OPACR10_SP:1; /* Supervisor Protect */ 12418 uint32_t OPACR10_WP:1; /* Write Protect */ 12419 uint32_t OPACR10_TP:1; /* Trusted Protect */ 12420 uint32_t OPACR11_BW:1; /* Buffer Writes */ 12421 uint32_t OPACR11_SP:1; /* Supervisor Protect */ 12422 uint32_t OPACR11_WP:1; /* Write Protect */ 12423 uint32_t OPACR11_TP:1; /* Trusted Protect */ 12424 uint32_t OPACR12_BW:1; /* Buffer Writes */ 12425 uint32_t OPACR12_SP:1; /* Supervisor Protect */ 12426 uint32_t OPACR12_WP:1; /* Write Protect */ 12427 uint32_t OPACR12_TP:1; /* Trusted Protect */ 12428 uint32_t OPACR13_BW:1; /* Buffer Writes */ 12429 uint32_t OPACR13_SP:1; /* Supervisor Protect */ 12430 uint32_t OPACR13_WP:1; /* Write Protect */ 12431 uint32_t OPACR13_TP:1; /* Trusted Protect */ 12432 uint32_t OPACR14_BW:1; /* Buffer Writes */ 12433 uint32_t OPACR14_SP:1; /* Supervisor Protect */ 12434 uint32_t OPACR14_WP:1; /* Write Protect */ 12435 uint32_t OPACR14_TP:1; /* Trusted Protect */ 12436 uint32_t OPACR15_BW:1; /* Buffer Writes */ 12437 uint32_t OPACR15_SP:1; /* Supervisor Protect */ 12438 uint32_t OPACR15_WP:1; /* Write Protect */ 12439 uint32_t OPACR15_TP:1; /* Trusted Protect */ 12440 } B; 12441 } PBRIDGE_OPACR8_15_32B_tag; 12442 12443 typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ 12444 uint32_t R; 12445 struct { 12446 uint32_t OPACR16_BW:1; /* Buffer Writes */ 12447 uint32_t OPACR16_SP:1; /* Supervisor Protect */ 12448 uint32_t OPACR16_WP:1; /* Write Protect */ 12449 uint32_t OPACR16_TP:1; /* Trusted Protect */ 12450 uint32_t OPACR17_BW:1; /* Buffer Writes */ 12451 uint32_t OPACR17_SP:1; /* Supervisor Protect */ 12452 uint32_t OPACR17_WP:1; /* Write Protect */ 12453 uint32_t OPACR17_TP:1; /* Trusted Protect */ 12454 uint32_t OPACR18_BW:1; /* Buffer Writes */ 12455 uint32_t OPACR18_SP:1; /* Supervisor Protect */ 12456 uint32_t OPACR18_WP:1; /* Write Protect */ 12457 uint32_t OPACR18_TP:1; /* Trusted Protect */ 12458 uint32_t OPACR19_BW:1; /* Buffer Writes */ 12459 uint32_t OPACR19_SP:1; /* Supervisor Protect */ 12460 uint32_t OPACR19_WP:1; /* Write Protect */ 12461 uint32_t OPACR19_TP:1; /* Trusted Protect */ 12462 uint32_t OPACR20_BW:1; /* Buffer Writes */ 12463 uint32_t OPACR20_SP:1; /* Supervisor Protect */ 12464 uint32_t OPACR20_WP:1; /* Write Protect */ 12465 uint32_t OPACR20_TP:1; /* Trusted Protect */ 12466 uint32_t OPACR21_BW:1; /* Buffer Writes */ 12467 uint32_t OPACR21_SP:1; /* Supervisor Protect */ 12468 uint32_t OPACR21_WP:1; /* Write Protect */ 12469 uint32_t OPACR21_TP:1; /* Trusted Protect */ 12470 uint32_t OPACR22_BW:1; /* Buffer Writes */ 12471 uint32_t OPACR22_SP:1; /* Supervisor Protect */ 12472 uint32_t OPACR22_WP:1; /* Write Protect */ 12473 uint32_t OPACR22_TP:1; /* Trusted Protect */ 12474 uint32_t OPACR23_BW:1; /* Buffer Writes */ 12475 uint32_t OPACR23_SP:1; /* Supervisor Protect */ 12476 uint32_t OPACR23_WP:1; /* Write Protect */ 12477 uint32_t OPACR23_TP:1; /* Trusted Protect */ 12478 } B; 12479 } PBRIDGE_OPACR16_23_32B_tag; 12480 12481 typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ 12482 uint32_t R; 12483 struct { 12484 uint32_t OPACR24_BW:1; /* Buffer Writes */ 12485 uint32_t OPACR24_SP:1; /* Supervisor Protect */ 12486 uint32_t OPACR24_WP:1; /* Write Protect */ 12487 uint32_t OPACR24_TP:1; /* Trusted Protect */ 12488 uint32_t OPACR25_BW:1; /* Buffer Writes */ 12489 uint32_t OPACR25_SP:1; /* Supervisor Protect */ 12490 uint32_t OPACR25_WP:1; /* Write Protect */ 12491 uint32_t OPACR25_TP:1; /* Trusted Protect */ 12492 uint32_t OPACR26_BW:1; /* Buffer Writes */ 12493 uint32_t OPACR26_SP:1; /* Supervisor Protect */ 12494 uint32_t OPACR26_WP:1; /* Write Protect */ 12495 uint32_t OPACR26_TP:1; /* Trusted Protect */ 12496 uint32_t OPACR27_BW:1; /* Buffer Writes */ 12497 uint32_t OPACR27_SP:1; /* Supervisor Protect */ 12498 uint32_t OPACR27_WP:1; /* Write Protect */ 12499 uint32_t OPACR27_TP:1; /* Trusted Protect */ 12500 uint32_t OPACR28_BW:1; /* Buffer Writes */ 12501 uint32_t OPACR28_SP:1; /* Supervisor Protect */ 12502 uint32_t OPACR28_WP:1; /* Write Protect */ 12503 uint32_t OPACR28_TP:1; /* Trusted Protect */ 12504 uint32_t OPACR29_BW:1; /* Buffer Writes */ 12505 uint32_t OPACR29_SP:1; /* Supervisor Protect */ 12506 uint32_t OPACR29_WP:1; /* Write Protect */ 12507 uint32_t OPACR29_TP:1; /* Trusted Protect */ 12508 uint32_t OPACR30_BW:1; /* Buffer Writes */ 12509 uint32_t OPACR30_SP:1; /* Supervisor Protect */ 12510 uint32_t OPACR30_WP:1; /* Write Protect */ 12511 uint32_t OPACR30_TP:1; /* Trusted Protect */ 12512 uint32_t OPACR31_BW:1; /* Buffer Writes */ 12513 uint32_t OPACR31_SP:1; /* Supervisor Protect */ 12514 uint32_t OPACR31_WP:1; /* Write Protect */ 12515 uint32_t OPACR31_TP:1; /* Trusted Protect */ 12516 } B; 12517 } PBRIDGE_OPACR24_31_32B_tag; 12518 12519 typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ 12520 uint32_t R; 12521 struct { 12522 uint32_t OPACR32_BW:1; /* Buffer Writes */ 12523 uint32_t OPACR32_SP:1; /* Supervisor Protect */ 12524 uint32_t OPACR32_WP:1; /* Write Protect */ 12525 uint32_t OPACR32_TP:1; /* Trusted Protect */ 12526 uint32_t OPACR33_BW:1; /* Buffer Writes */ 12527 uint32_t OPACR33_SP:1; /* Supervisor Protect */ 12528 uint32_t OPACR33_WP:1; /* Write Protect */ 12529 uint32_t OPACR33_TP:1; /* Trusted Protect */ 12530 uint32_t OPACR34_BW:1; /* Buffer Writes */ 12531 uint32_t OPACR34_SP:1; /* Supervisor Protect */ 12532 uint32_t OPACR34_WP:1; /* Write Protect */ 12533 uint32_t OPACR34_TP:1; /* Trusted Protect */ 12534 uint32_t OPACR35_BW:1; /* Buffer Writes */ 12535 uint32_t OPACR35_SP:1; /* Supervisor Protect */ 12536 uint32_t OPACR35_WP:1; /* Write Protect */ 12537 uint32_t OPACR35_TP:1; /* Trusted Protect */ 12538 uint32_t OPACR36_BW:1; /* Buffer Writes */ 12539 uint32_t OPACR36_SP:1; /* Supervisor Protect */ 12540 uint32_t OPACR36_WP:1; /* Write Protect */ 12541 uint32_t OPACR36_TP:1; /* Trusted Protect */ 12542 uint32_t OPACR37_BW:1; /* Buffer Writes */ 12543 uint32_t OPACR37_SP:1; /* Supervisor Protect */ 12544 uint32_t OPACR37_WP:1; /* Write Protect */ 12545 uint32_t OPACR37_TP:1; /* Trusted Protect */ 12546 uint32_t OPACR38_BW:1; /* Buffer Writes */ 12547 uint32_t OPACR38_SP:1; /* Supervisor Protect */ 12548 uint32_t OPACR38_WP:1; /* Write Protect */ 12549 uint32_t OPACR38_TP:1; /* Trusted Protect */ 12550 uint32_t OPACR39_BW:1; /* Buffer Writes */ 12551 uint32_t OPACR39_SP:1; /* Supervisor Protect */ 12552 uint32_t OPACR39_WP:1; /* Write Protect */ 12553 uint32_t OPACR39_TP:1; /* Trusted Protect */ 12554 } B; 12555 } PBRIDGE_OPACR32_39_32B_tag; 12556 12557 typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ 12558 uint32_t R; 12559 struct { 12560 uint32_t OPACR40_BW:1; /* Buffer Writes */ 12561 uint32_t OPACR40_SP:1; /* Supervisor Protect */ 12562 uint32_t OPACR40_WP:1; /* Write Protect */ 12563 uint32_t OPACR40_TP:1; /* Trusted Protect */ 12564 uint32_t OPACR41_BW:1; /* Buffer Writes */ 12565 uint32_t OPACR41_SP:1; /* Supervisor Protect */ 12566 uint32_t OPACR41_WP:1; /* Write Protect */ 12567 uint32_t OPACR41_TP:1; /* Trusted Protect */ 12568 uint32_t OPACR42_BW:1; /* Buffer Writes */ 12569 uint32_t OPACR42_SP:1; /* Supervisor Protect */ 12570 uint32_t OPACR42_WP:1; /* Write Protect */ 12571 uint32_t OPACR42_TP:1; /* Trusted Protect */ 12572 uint32_t OPACR43_BW:1; /* Buffer Writes */ 12573 uint32_t OPACR43_SP:1; /* Supervisor Protect */ 12574 uint32_t OPACR43_WP:1; /* Write Protect */ 12575 uint32_t OPACR43_TP:1; /* Trusted Protect */ 12576 uint32_t OPACR44_BW:1; /* Buffer Writes */ 12577 uint32_t OPACR44_SP:1; /* Supervisor Protect */ 12578 uint32_t OPACR44_WP:1; /* Write Protect */ 12579 uint32_t OPACR44_TP:1; /* Trusted Protect */ 12580 uint32_t OPACR45_BW:1; /* Buffer Writes */ 12581 uint32_t OPACR45_SP:1; /* Supervisor Protect */ 12582 uint32_t OPACR45_WP:1; /* Write Protect */ 12583 uint32_t OPACR45_TP:1; /* Trusted Protect */ 12584 uint32_t OPACR46_BW:1; /* Buffer Writes */ 12585 uint32_t OPACR46_SP:1; /* Supervisor Protect */ 12586 uint32_t OPACR46_WP:1; /* Write Protect */ 12587 uint32_t OPACR46_TP:1; /* Trusted Protect */ 12588 uint32_t OPACR47_BW:1; /* Buffer Writes */ 12589 uint32_t OPACR47_SP:1; /* Supervisor Protect */ 12590 uint32_t OPACR47_WP:1; /* Write Protect */ 12591 uint32_t OPACR47_TP:1; /* Trusted Protect */ 12592 } B; 12593 } PBRIDGE_OPACR40_47_32B_tag; 12594 12595 typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ 12596 uint32_t R; 12597 struct { 12598 uint32_t OPACR48_BW:1; /* Buffer Writes */ 12599 uint32_t OPACR48_SP:1; /* Supervisor Protect */ 12600 uint32_t OPACR48_WP:1; /* Write Protect */ 12601 uint32_t OPACR48_TP:1; /* Trusted Protect */ 12602 uint32_t OPACR49_BW:1; /* Buffer Writes */ 12603 uint32_t OPACR49_SP:1; /* Supervisor Protect */ 12604 uint32_t OPACR49_WP:1; /* Write Protect */ 12605 uint32_t OPACR49_TP:1; /* Trusted Protect */ 12606 uint32_t OPACR50_BW:1; /* Buffer Writes */ 12607 uint32_t OPACR50_SP:1; /* Supervisor Protect */ 12608 uint32_t OPACR50_WP:1; /* Write Protect */ 12609 uint32_t OPACR50_TP:1; /* Trusted Protect */ 12610 uint32_t OPACR51_BW:1; /* Buffer Writes */ 12611 uint32_t OPACR51_SP:1; /* Supervisor Protect */ 12612 uint32_t OPACR51_WP:1; /* Write Protect */ 12613 uint32_t OPACR51_TP:1; /* Trusted Protect */ 12614 uint32_t OPACR52_BW:1; /* Buffer Writes */ 12615 uint32_t OPACR52_SP:1; /* Supervisor Protect */ 12616 uint32_t OPACR52_WP:1; /* Write Protect */ 12617 uint32_t OPACR52_TP:1; /* Trusted Protect */ 12618 uint32_t OPACR53_BW:1; /* Buffer Writes */ 12619 uint32_t OPACR53_SP:1; /* Supervisor Protect */ 12620 uint32_t OPACR53_WP:1; /* Write Protect */ 12621 uint32_t OPACR53_TP:1; /* Trusted Protect */ 12622 uint32_t OPACR54_BW:1; /* Buffer Writes */ 12623 uint32_t OPACR54_SP:1; /* Supervisor Protect */ 12624 uint32_t OPACR54_WP:1; /* Write Protect */ 12625 uint32_t OPACR54_TP:1; /* Trusted Protect */ 12626 uint32_t OPACR55_BW:1; /* Buffer Writes */ 12627 uint32_t OPACR55_SP:1; /* Supervisor Protect */ 12628 uint32_t OPACR55_WP:1; /* Write Protect */ 12629 uint32_t OPACR55_TP:1; /* Trusted Protect */ 12630 } B; 12631 } PBRIDGE_OPACR48_55_32B_tag; 12632 12633 typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ 12634 uint32_t R; 12635 struct { 12636 uint32_t OPACR56_BW:1; /* Buffer Writes */ 12637 uint32_t OPACR56_SP:1; /* Supervisor Protect */ 12638 uint32_t OPACR56_WP:1; /* Write Protect */ 12639 uint32_t OPACR56_TP:1; /* Trusted Protect */ 12640 uint32_t OPACR57_BW:1; /* Buffer Writes */ 12641 uint32_t OPACR57_SP:1; /* Supervisor Protect */ 12642 uint32_t OPACR57_WP:1; /* Write Protect */ 12643 uint32_t OPACR57_TP:1; /* Trusted Protect */ 12644 uint32_t OPACR58_BW:1; /* Buffer Writes */ 12645 uint32_t OPACR58_SP:1; /* Supervisor Protect */ 12646 uint32_t OPACR58_WP:1; /* Write Protect */ 12647 uint32_t OPACR58_TP:1; /* Trusted Protect */ 12648 uint32_t OPACR59_BW:1; /* Buffer Writes */ 12649 uint32_t OPACR59_SP:1; /* Supervisor Protect */ 12650 uint32_t OPACR59_WP:1; /* Write Protect */ 12651 uint32_t OPACR59_TP:1; /* Trusted Protect */ 12652 uint32_t OPACR60_BW:1; /* Buffer Writes */ 12653 uint32_t OPACR60_SP:1; /* Supervisor Protect */ 12654 uint32_t OPACR60_WP:1; /* Write Protect */ 12655 uint32_t OPACR60_TP:1; /* Trusted Protect */ 12656 uint32_t OPACR61_BW:1; /* Buffer Writes */ 12657 uint32_t OPACR61_SP:1; /* Supervisor Protect */ 12658 uint32_t OPACR61_WP:1; /* Write Protect */ 12659 uint32_t OPACR61_TP:1; /* Trusted Protect */ 12660 uint32_t OPACR62_BW:1; /* Buffer Writes */ 12661 uint32_t OPACR62_SP:1; /* Supervisor Protect */ 12662 uint32_t OPACR62_WP:1; /* Write Protect */ 12663 uint32_t OPACR62_TP:1; /* Trusted Protect */ 12664 uint32_t OPACR63_BW:1; /* Buffer Writes */ 12665 uint32_t OPACR63_SP:1; /* Supervisor Protect */ 12666 uint32_t OPACR63_WP:1; /* Write Protect */ 12667 uint32_t OPACR63_TP:1; /* Trusted Protect */ 12668 } B; 12669 } PBRIDGE_OPACR56_63_32B_tag; 12670 12671 typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ 12672 uint32_t R; 12673 struct { 12674 uint32_t OPACR64_BW:1; /* Buffer Writes */ 12675 uint32_t OPACR64_SP:1; /* Supervisor Protect */ 12676 uint32_t OPACR64_WP:1; /* Write Protect */ 12677 uint32_t OPACR64_TP:1; /* Trusted Protect */ 12678 uint32_t OPACR65_BW:1; /* Buffer Writes */ 12679 uint32_t OPACR65_SP:1; /* Supervisor Protect */ 12680 uint32_t OPACR65_WP:1; /* Write Protect */ 12681 uint32_t OPACR65_TP:1; /* Trusted Protect */ 12682 uint32_t OPACR66_BW:1; /* Buffer Writes */ 12683 uint32_t OPACR66_SP:1; /* Supervisor Protect */ 12684 uint32_t OPACR66_WP:1; /* Write Protect */ 12685 uint32_t OPACR66_TP:1; /* Trusted Protect */ 12686 uint32_t OPACR67_BW:1; /* Buffer Writes */ 12687 uint32_t OPACR67_SP:1; /* Supervisor Protect */ 12688 uint32_t OPACR67_WP:1; /* Write Protect */ 12689 uint32_t OPACR67_TP:1; /* Trusted Protect */ 12690 uint32_t OPACR68_BW:1; /* Buffer Writes */ 12691 uint32_t OPACR68_SP:1; /* Supervisor Protect */ 12692 uint32_t OPACR68_WP:1; /* Write Protect */ 12693 uint32_t OPACR68_TP:1; /* Trusted Protect */ 12694 uint32_t OPACR69_BW:1; /* Buffer Writes */ 12695 uint32_t OPACR69_SP:1; /* Supervisor Protect */ 12696 uint32_t OPACR69_WP:1; /* Write Protect */ 12697 uint32_t OPACR69_TP:1; /* Trusted Protect */ 12698 uint32_t OPACR70_BW:1; /* Buffer Writes */ 12699 uint32_t OPACR70_SP:1; /* Supervisor Protect */ 12700 uint32_t OPACR70_WP:1; /* Write Protect */ 12701 uint32_t OPACR70_TP:1; /* Trusted Protect */ 12702 uint32_t OPACR71_BW:1; /* Buffer Writes */ 12703 uint32_t OPACR71_SP:1; /* Supervisor Protect */ 12704 uint32_t OPACR71_WP:1; /* Write Protect */ 12705 uint32_t OPACR71_TP:1; /* Trusted Protect */ 12706 } B; 12707 } PBRIDGE_OPACR64_71_32B_tag; 12708 12709 typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ 12710 uint32_t R; 12711 struct { 12712 uint32_t OPACR72_BW:1; /* Buffer Writes */ 12713 uint32_t OPACR72_SP:1; /* Supervisor Protect */ 12714 uint32_t OPACR72_WP:1; /* Write Protect */ 12715 uint32_t OPACR72_TP:1; /* Trusted Protect */ 12716 uint32_t OPACR73_BW:1; /* Buffer Writes */ 12717 uint32_t OPACR73_SP:1; /* Supervisor Protect */ 12718 uint32_t OPACR73_WP:1; /* Write Protect */ 12719 uint32_t OPACR73_TP:1; /* Trusted Protect */ 12720 uint32_t OPACR74_BW:1; /* Buffer Writes */ 12721 uint32_t OPACR74_SP:1; /* Supervisor Protect */ 12722 uint32_t OPACR74_WP:1; /* Write Protect */ 12723 uint32_t OPACR74_TP:1; /* Trusted Protect */ 12724 uint32_t OPACR75_BW:1; /* Buffer Writes */ 12725 uint32_t OPACR75_SP:1; /* Supervisor Protect */ 12726 uint32_t OPACR75_WP:1; /* Write Protect */ 12727 uint32_t OPACR75_TP:1; /* Trusted Protect */ 12728 uint32_t OPACR76_BW:1; /* Buffer Writes */ 12729 uint32_t OPACR76_SP:1; /* Supervisor Protect */ 12730 uint32_t OPACR76_WP:1; /* Write Protect */ 12731 uint32_t OPACR76_TP:1; /* Trusted Protect */ 12732 uint32_t OPACR77_BW:1; /* Buffer Writes */ 12733 uint32_t OPACR77_SP:1; /* Supervisor Protect */ 12734 uint32_t OPACR77_WP:1; /* Write Protect */ 12735 uint32_t OPACR77_TP:1; /* Trusted Protect */ 12736 uint32_t OPACR78_BW:1; /* Buffer Writes */ 12737 uint32_t OPACR78_SP:1; /* Supervisor Protect */ 12738 uint32_t OPACR78_WP:1; /* Write Protect */ 12739 uint32_t OPACR78_TP:1; /* Trusted Protect */ 12740 uint32_t OPACR79_BW:1; /* Buffer Writes */ 12741 uint32_t OPACR79_SP:1; /* Supervisor Protect */ 12742 uint32_t OPACR79_WP:1; /* Write Protect */ 12743 uint32_t OPACR79_TP:1; /* Trusted Protect */ 12744 } B; 12745 } PBRIDGE_OPACR72_79_32B_tag; 12746 12747 typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ 12748 uint32_t R; 12749 struct { 12750 uint32_t OPACR80_BW:1; /* Buffer Writes */ 12751 uint32_t OPACR80_SP:1; /* Supervisor Protect */ 12752 uint32_t OPACR80_WP:1; /* Write Protect */ 12753 uint32_t OPACR80_TP:1; /* Trusted Protect */ 12754 uint32_t OPACR81_BW:1; /* Buffer Writes */ 12755 uint32_t OPACR81_SP:1; /* Supervisor Protect */ 12756 uint32_t OPACR81_WP:1; /* Write Protect */ 12757 uint32_t OPACR81_TP:1; /* Trusted Protect */ 12758 uint32_t OPACR82_BW:1; /* Buffer Writes */ 12759 uint32_t OPACR82_SP:1; /* Supervisor Protect */ 12760 uint32_t OPACR82_WP:1; /* Write Protect */ 12761 uint32_t OPACR82_TP:1; /* Trusted Protect */ 12762 uint32_t OPACR83_BW:1; /* Buffer Writes */ 12763 uint32_t OPACR83_SP:1; /* Supervisor Protect */ 12764 uint32_t OPACR83_WP:1; /* Write Protect */ 12765 uint32_t OPACR83_TP:1; /* Trusted Protect */ 12766 uint32_t OPACR84_BW:1; /* Buffer Writes */ 12767 uint32_t OPACR84_SP:1; /* Supervisor Protect */ 12768 uint32_t OPACR84_WP:1; /* Write Protect */ 12769 uint32_t OPACR84_TP:1; /* Trusted Protect */ 12770 uint32_t OPACR85_BW:1; /* Buffer Writes */ 12771 uint32_t OPACR85_SP:1; /* Supervisor Protect */ 12772 uint32_t OPACR85_WP:1; /* Write Protect */ 12773 uint32_t OPACR85_TP:1; /* Trusted Protect */ 12774 uint32_t OPACR86_BW:1; /* Buffer Writes */ 12775 uint32_t OPACR86_SP:1; /* Supervisor Protect */ 12776 uint32_t OPACR86_WP:1; /* Write Protect */ 12777 uint32_t OPACR86_TP:1; /* Trusted Protect */ 12778 uint32_t OPACR87_BW:1; /* Buffer Writes */ 12779 uint32_t OPACR87_SP:1; /* Supervisor Protect */ 12780 uint32_t OPACR87_WP:1; /* Write Protect */ 12781 uint32_t OPACR87_TP:1; /* Trusted Protect */ 12782 } B; 12783 } PBRIDGE_OPACR80_87_32B_tag; 12784 12785 typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ 12786 uint32_t R; 12787 struct { 12788 uint32_t OPACR88_BW:1; /* Buffer Writes */ 12789 uint32_t OPACR88_SP:1; /* Supervisor Protect */ 12790 uint32_t OPACR88_WP:1; /* Write Protect */ 12791 uint32_t OPACR88_TP:1; /* Trusted Protect */ 12792 uint32_t OPACR89_BW:1; /* Buffer Writes */ 12793 uint32_t OPACR89_SP:1; /* Supervisor Protect */ 12794 uint32_t OPACR89_WP:1; /* Write Protect */ 12795 uint32_t OPACR89_TP:1; /* Trusted Protect */ 12796 uint32_t OPACR90_BW:1; /* Buffer Writes */ 12797 uint32_t OPACR90_SP:1; /* Supervisor Protect */ 12798 uint32_t OPACR90_WP:1; /* Write Protect */ 12799 uint32_t OPACR90_TP:1; /* Trusted Protect */ 12800 uint32_t OPACR91_BW:1; /* Buffer Writes */ 12801 uint32_t OPACR91_SP:1; /* Supervisor Protect */ 12802 uint32_t OPACR91_WP:1; /* Write Protect */ 12803 uint32_t OPACR91_TP:1; /* Trusted Protect */ 12804 uint32_t OPACR92_BW:1; /* Buffer Writes */ 12805 uint32_t OPACR92_SP:1; /* Supervisor Protect */ 12806 uint32_t OPACR92_WP:1; /* Write Protect */ 12807 uint32_t OPACR92_TP:1; /* Trusted Protect */ 12808 uint32_t OPACR93_BW:1; /* Buffer Writes */ 12809 uint32_t OPACR93_SP:1; /* Supervisor Protect */ 12810 uint32_t OPACR93_WP:1; /* Write Protect */ 12811 uint32_t OPACR93_TP:1; /* Trusted Protect */ 12812 uint32_t OPACR94_BW:1; /* Buffer Writes */ 12813 uint32_t OPACR94_SP:1; /* Supervisor Protect */ 12814 uint32_t OPACR94_WP:1; /* Write Protect */ 12815 uint32_t OPACR94_TP:1; /* Trusted Protect */ 12816 uint32_t OPACR95_BW:1; /* Buffer Writes */ 12817 uint32_t OPACR95_SP:1; /* Supervisor Protect */ 12818 uint32_t OPACR95_WP:1; /* Write Protect */ 12819 uint32_t OPACR95_TP:1; /* Trusted Protect */ 12820 } B; 12821 } PBRIDGE_OPACR88_95_32B_tag; 12822 12823 12824 12825 typedef struct PBRIDGE_struct_tag { /* start of PBRIDGE_tag */ 12826 /* MPROT - Master Privilege Registers */ 12827 PBRIDGE_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */ 12828 int8_t PBRIDGE_reserved_0004[28]; 12829 /* PACR0_7 - Peripheral Access Control Registers */ 12830 PBRIDGE_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */ 12831 /* PACR8_15 - Peripheral Access Control Registers */ 12832 PBRIDGE_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */ 12833 /* PACR16_23 - Peripheral Access Control Registers */ 12834 PBRIDGE_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */ 12835 /* PACR24_31 - Peripheral Access Control Registers */ 12836 PBRIDGE_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */ 12837 int8_t PBRIDGE_reserved_0030[16]; 12838 /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ 12839 PBRIDGE_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */ 12840 /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ 12841 PBRIDGE_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */ 12842 /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ 12843 PBRIDGE_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */ 12844 /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ 12845 PBRIDGE_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */ 12846 /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ 12847 PBRIDGE_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */ 12848 /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ 12849 PBRIDGE_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */ 12850 /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ 12851 PBRIDGE_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */ 12852 /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ 12853 PBRIDGE_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */ 12854 /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ 12855 PBRIDGE_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */ 12856 /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ 12857 PBRIDGE_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */ 12858 /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ 12859 PBRIDGE_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */ 12860 /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ 12861 PBRIDGE_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */ 12862 } PBRIDGE_tag; 12863 12864 12865 #define PBRIDGE (*(volatile PBRIDGE_tag *) 0xFFF00000UL) 12866 12867 12868 12869 /****************************************************************/ 12870 /* */ 12871 /* Module: MAX */ 12872 /* */ 12873 /****************************************************************/ 12874 12875 12876 /* Register layout for all registers MPR... */ 12877 12878 typedef union { /* Master Priority Register for slave port n */ 12879 uint32_t R; 12880 struct { 12881 uint32_t:1; 12882 uint32_t MSTR_7:3; /* Master 7 Priority */ 12883 uint32_t:1; 12884 uint32_t MSTR_6:3; /* Master 6 Priority */ 12885 uint32_t:1; 12886 uint32_t MSTR_5:3; /* Master 5 Priority */ 12887 uint32_t:1; 12888 uint32_t MSTR_4:3; /* Master 4 Priority */ 12889 uint32_t:1; 12890 uint32_t MSTR_3:3; /* Master 3 Priority */ 12891 uint32_t:1; 12892 uint32_t MSTR_2:3; /* Master 2 Priority */ 12893 uint32_t:1; 12894 uint32_t MSTR_1:3; /* Master 1 Priority */ 12895 uint32_t:1; 12896 uint32_t MSTR_0:3; /* Master 0 Priority */ 12897 } B; 12898 } MAX_MPR_32B_tag; 12899 12900 12901 /* Register layout for all registers AMPR matches xxx */ 12902 12903 12904 /* Register layout for all registers SGPCR... */ 12905 12906 typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 12907 uint32_t R; 12908 struct { 12909 uint32_t RO:1; /* Read Only */ 12910 uint32_t HLP:1; /* Halt Low Priority */ 12911 uint32_t:6; 12912 uint32_t HPE7:1; /* High Priority Enable */ 12913 uint32_t HPE6:1; /* High Priority Enable */ 12914 uint32_t HPE5:1; /* High Priority Enable */ 12915 uint32_t HPE4:1; /* High Priority Enable */ 12916 uint32_t HPE3:1; /* High Priority Enable */ 12917 uint32_t HPE2:1; /* High Priority Enable */ 12918 uint32_t HPE1:1; /* High Priority Enable */ 12919 uint32_t HPE0:1; /* High Priority Enable */ 12920 uint32_t:6; 12921 uint32_t ARB:2; /* Arbitration Mode */ 12922 uint32_t:2; 12923 uint32_t PCTL:2; /* Parking Control */ 12924 uint32_t:1; 12925 uint32_t PARK:3; /* Park */ 12926 } B; 12927 } MAX_SGPCR_32B_tag; 12928 12929 12930 /* Register layout for all registers ASGPCR... */ 12931 12932 typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 12933 uint32_t R; 12934 struct { 12935 uint32_t:1; 12936 uint32_t HLP:1; /* Halt Low Priority */ 12937 uint32_t:6; 12938 uint32_t HPE7:1; /* High Priority Enable */ 12939 uint32_t HPE6:1; /* High Priority Enable */ 12940 uint32_t HPE5:1; /* High Priority Enable */ 12941 uint32_t HPE4:1; /* High Priority Enable */ 12942 uint32_t HPE3:1; /* High Priority Enable */ 12943 uint32_t HPE2:1; /* High Priority Enable */ 12944 uint32_t HPE1:1; /* High Priority Enable */ 12945 uint32_t HPE0:1; /* High Priority Enable */ 12946 uint32_t:6; 12947 uint32_t ARB:2; /* Arbitration Mode */ 12948 uint32_t:2; 12949 uint32_t PCTL:2; /* Parking Control */ 12950 uint32_t:1; 12951 uint32_t PARK:3; /* Park */ 12952 } B; 12953 } MAX_ASGPCR_32B_tag; 12954 12955 12956 /* Register layout for all registers MGPCR... */ 12957 12958 typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */ 12959 uint32_t R; 12960 struct { 12961 uint32_t:29; 12962 uint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ 12963 } B; 12964 } MAX_MGPCR_32B_tag; 12965 12966 12967 typedef struct MAX_SLAVE_PORT_struct_tag { 12968 12969 /* Master Priority Register for slave port n */ 12970 MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */ 12971 /* Alternate Master Priority Register for slave port n */ 12972 MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */ 12973 int8_t MAX_SLAVE_PORT_reserved_0008[8]; 12974 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 12975 MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */ 12976 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 12977 MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */ 12978 int8_t MAX_SLAVE_PORT_reserved_0018[232]; 12979 12980 } MAX_SLAVE_PORT_tag; 12981 12982 typedef struct MAX_MASTER_PORT_struct_tag { 12983 12984 /* MAX_MGPCRn - Master General Purpose Control Register n */ 12985 MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */ 12986 int8_t MAX_MASTER_PORT_reserved_0004[252]; 12987 12988 } MAX_MASTER_PORT_tag; 12989 12990 12991 typedef struct MAX_struct_tag { /* start of MAX_tag */ 12992 union { 12993 /* Register set SLAVE_PORT */ 12994 MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */ 12995 12996 struct { 12997 /* Master Priority Register for slave port n */ 12998 MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */ 12999 /* Alternate Master Priority Register for slave port n */ 13000 MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */ 13001 int8_t MAX_reserved_0008_I1[8]; 13002 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13003 MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */ 13004 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13005 MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */ 13006 int8_t MAX_reserved_0018_I1[232]; 13007 /* Master Priority Register for slave port n */ 13008 MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */ 13009 /* Alternate Master Priority Register for slave port n */ 13010 MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */ 13011 int8_t MAX_reserved_0108_I1[8]; 13012 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13013 MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */ 13014 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13015 MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */ 13016 int8_t MAX_reserved_0118_I1[232]; 13017 /* Master Priority Register for slave port n */ 13018 MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */ 13019 /* Alternate Master Priority Register for slave port n */ 13020 MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */ 13021 int8_t MAX_reserved_0208_I1[8]; 13022 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13023 MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */ 13024 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13025 MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */ 13026 int8_t MAX_reserved_0218_I1[232]; 13027 /* Master Priority Register for slave port n */ 13028 MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */ 13029 /* Alternate Master Priority Register for slave port n */ 13030 MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */ 13031 int8_t MAX_reserved_0308_I1[8]; 13032 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13033 MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */ 13034 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13035 MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */ 13036 int8_t MAX_reserved_0318_I1[232]; 13037 /* Master Priority Register for slave port n */ 13038 MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */ 13039 /* Alternate Master Priority Register for slave port n */ 13040 MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */ 13041 int8_t MAX_reserved_0408_I1[8]; 13042 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13043 MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */ 13044 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13045 MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */ 13046 int8_t MAX_reserved_0418_I1[232]; 13047 /* Master Priority Register for slave port n */ 13048 MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */ 13049 /* Alternate Master Priority Register for slave port n */ 13050 MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */ 13051 int8_t MAX_reserved_0508_I1[8]; 13052 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13053 MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */ 13054 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13055 MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */ 13056 int8_t MAX_reserved_0518_I1[232]; 13057 /* Master Priority Register for slave port n */ 13058 MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */ 13059 /* Alternate Master Priority Register for slave port n */ 13060 MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */ 13061 int8_t MAX_reserved_0608_I1[8]; 13062 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13063 MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */ 13064 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13065 MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */ 13066 int8_t MAX_reserved_0618_I1[232]; 13067 /* Master Priority Register for slave port n */ 13068 MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */ 13069 /* Alternate Master Priority Register for slave port n */ 13070 MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */ 13071 int8_t MAX_reserved_0708_I1[8]; 13072 /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ 13073 MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */ 13074 /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ 13075 MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */ 13076 int8_t MAX_reserved_0718_E1[232]; 13077 }; 13078 13079 }; 13080 union { 13081 /* Register set MASTER_PORT */ 13082 MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */ 13083 13084 struct { 13085 /* MAX_MGPCRn - Master General Purpose Control Register n */ 13086 MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */ 13087 int8_t MAX_reserved_0804_I1[252]; 13088 MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */ 13089 int8_t MAX_reserved_0904_I1[252]; 13090 MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */ 13091 int8_t MAX_reserved_0A04_I1[252]; 13092 MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */ 13093 int8_t MAX_reserved_0B04_I1[252]; 13094 MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */ 13095 int8_t MAX_reserved_0C04_I1[252]; 13096 MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */ 13097 int8_t MAX_reserved_0D04_I1[252]; 13098 MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */ 13099 int8_t MAX_reserved_0E04_I1[252]; 13100 MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */ 13101 int8_t MAX_reserved_0F04_E1[252]; 13102 }; 13103 13104 }; 13105 } MAX_tag; 13106 13107 13108 #define MAX (*(volatile MAX_tag *) 0xFFF04000UL) 13109 13110 13111 13112 /****************************************************************/ 13113 /* */ 13114 /* Module: MPU */ 13115 /* */ 13116 /****************************************************************/ 13117 13118 typedef union { /* MPU_CESR - MPU Control/Error Status Register */ 13119 uint32_t R; 13120 struct { 13121 uint32_t SPERR:8; /* Slave Port n Error */ 13122 uint32_t:4; 13123 uint32_t HRL:4; /* Hardware Revision Level */ 13124 uint32_t NSP:4; /* Number of Slave Ports */ 13125 uint32_t NRGD:4; /* Number of Region Descriptors */ 13126 uint32_t:7; 13127 uint32_t VLD:1; /* Valid bit */ 13128 } B; 13129 } MPU_CESR_32B_tag; 13130 13131 13132 /* Register layout for all registers EAR... */ 13133 13134 typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */ 13135 uint32_t R; 13136 struct { 13137 uint32_t EADDR:32; /* Error Address */ 13138 } B; 13139 } MPU_EAR_32B_tag; 13140 13141 13142 /* Register layout for all registers EDR... */ 13143 13144 typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ 13145 uint32_t R; 13146 struct { 13147 uint32_t EACD:16; /* Error Access Control Detail */ 13148 uint32_t EPID:8; /* Error Process Identification */ 13149 uint32_t EMN:4; /* Error Master Number */ 13150 uint32_t EATTR:3; /* Error Attributes */ 13151 uint32_t ERW:1; /* Error Read/Write */ 13152 } B; 13153 } MPU_EDR_32B_tag; 13154 13155 13156 /* Register layout for all registers RGD_WORD0... */ 13157 13158 typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13159 uint32_t R; 13160 struct { 13161 uint32_t SRTADDR:27; /* Start Address */ 13162 uint32_t:5; 13163 } B; 13164 } MPU_RGD_WORD0_32B_tag; 13165 13166 13167 /* Register layout for all registers RGD_WORD1... */ 13168 13169 typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13170 uint32_t R; 13171 struct { 13172 uint32_t ENDADDR:27; /* End Address */ 13173 uint32_t:5; 13174 } B; 13175 } MPU_RGD_WORD1_32B_tag; 13176 13177 13178 /* Register layout for all registers RGD_WORD2... */ 13179 13180 typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13181 uint32_t R; 13182 struct { 13183 uint32_t M7RE:1; /* Bus Master 7 Read Enable */ 13184 uint32_t M7WE:1; /* Bus Master 7 Write Enable */ 13185 uint32_t M6RE:1; /* Bus Master 6 Read Enable */ 13186 uint32_t M6WE:1; /* Bus Master 7 Write Enable */ 13187 uint32_t M5RE:1; /* Bus Master 5 Read Enable */ 13188 uint32_t M5WE:1; /* Bus Master 5 Write Enable */ 13189 uint32_t M4RE:1; /* Bus Master 4 Read Enable */ 13190 uint32_t M4WE:1; /* Bus Master 4 Write Enable */ 13191 uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ 13192 uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ 13193 uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ 13194 uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ 13195 uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ 13196 uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ 13197 uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ 13198 uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ 13199 uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ 13200 uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ 13201 uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ 13202 uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ 13203 } B; 13204 } MPU_RGD_WORD2_32B_tag; 13205 13206 13207 /* Register layout for all registers RGD_WORD3... */ 13208 13209 typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13210 uint32_t R; 13211 struct { 13212 uint32_t PID:8; /* Process Identifier */ 13213 uint32_t PIDMASK:8; /* Process Identifier Mask */ 13214 uint32_t:15; 13215 uint32_t VLD:1; /* Valid */ 13216 } B; 13217 } MPU_RGD_WORD3_32B_tag; 13218 13219 13220 /* Register layout for all registers RGDAAC... */ 13221 13222 typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ 13223 uint32_t R; 13224 struct { 13225 uint32_t M7RE:1; /* Bus Master 7 Read Enable */ 13226 uint32_t M7WE:1; /* Bus Master 7 Write Enable */ 13227 uint32_t M6RE:1; /* Bus Master 6 Read Enable */ 13228 uint32_t M6WE:1; /* Bus Master 7 Write Enable */ 13229 uint32_t M5RE:1; /* Bus Master 5 Read Enable */ 13230 uint32_t M5WE:1; /* Bus Master 5 Write Enable */ 13231 uint32_t M4RE:1; /* Bus Master 4 Read Enable */ 13232 uint32_t M4WE:1; /* Bus Master 4 Write Enable */ 13233 uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ 13234 uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ 13235 uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ 13236 uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ 13237 uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ 13238 uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ 13239 uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ 13240 uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ 13241 uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ 13242 uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ 13243 uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ 13244 uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ 13245 } B; 13246 } MPU_RGDAAC_32B_tag; 13247 13248 13249 typedef struct MPU_SLAVE_PORT_struct_tag { 13250 13251 /* MPU_EARn - MPU Error Address Register, Slave Port n */ 13252 MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */ 13253 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ 13254 MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */ 13255 13256 } MPU_SLAVE_PORT_tag; 13257 13258 typedef struct MPU_REGION_struct_tag { 13259 13260 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13261 MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */ 13262 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13263 MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */ 13264 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13265 MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */ 13266 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13267 MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */ 13268 13269 } MPU_REGION_tag; 13270 13271 13272 typedef struct MPU_struct_tag { /* start of MPU_tag */ 13273 /* MPU_CESR - MPU Control/Error Status Register */ 13274 MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */ 13275 int8_t MPU_reserved_0004_C[12]; 13276 union { 13277 /* Register set SLAVE_PORT */ 13278 MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */ 13279 13280 struct { 13281 /* MPU_EARn - MPU Error Address Register, Slave Port n */ 13282 MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */ 13283 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ 13284 MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */ 13285 /* MPU_EARn - MPU Error Address Register, Slave Port n */ 13286 MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */ 13287 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ 13288 MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */ 13289 /* MPU_EARn - MPU Error Address Register, Slave Port n */ 13290 MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */ 13291 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ 13292 MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */ 13293 /* MPU_EARn - MPU Error Address Register, Slave Port n */ 13294 MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */ 13295 /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ 13296 MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */ 13297 }; 13298 13299 }; 13300 int8_t MPU_reserved_0030_C[976]; 13301 union { 13302 /* Register set REGION */ 13303 MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */ 13304 13305 struct { 13306 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13307 MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */ 13308 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13309 MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */ 13310 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13311 MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */ 13312 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13313 MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */ 13314 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13315 MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */ 13316 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13317 MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */ 13318 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13319 MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */ 13320 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13321 MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */ 13322 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13323 MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */ 13324 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13325 MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */ 13326 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13327 MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */ 13328 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13329 MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */ 13330 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13331 MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */ 13332 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13333 MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */ 13334 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13335 MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */ 13336 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13337 MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */ 13338 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13339 MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */ 13340 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13341 MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */ 13342 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13343 MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */ 13344 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13345 MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */ 13346 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13347 MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */ 13348 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13349 MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */ 13350 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13351 MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */ 13352 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13353 MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */ 13354 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13355 MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */ 13356 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13357 MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */ 13358 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13359 MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */ 13360 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13361 MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */ 13362 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13363 MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */ 13364 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13365 MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */ 13366 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13367 MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */ 13368 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13369 MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */ 13370 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13371 MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */ 13372 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13373 MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */ 13374 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13375 MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */ 13376 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13377 MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */ 13378 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13379 MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */ 13380 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13381 MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */ 13382 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13383 MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */ 13384 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13385 MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */ 13386 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13387 MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */ 13388 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13389 MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */ 13390 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13391 MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */ 13392 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13393 MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */ 13394 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13395 MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */ 13396 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13397 MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */ 13398 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13399 MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */ 13400 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13401 MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */ 13402 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13403 MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */ 13404 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13405 MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */ 13406 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13407 MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */ 13408 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13409 MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */ 13410 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13411 MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */ 13412 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13413 MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */ 13414 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13415 MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */ 13416 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13417 MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */ 13418 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13419 MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */ 13420 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13421 MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */ 13422 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13423 MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */ 13424 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13425 MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */ 13426 /* MPU_RGDn_Word0 - MPU Region Descriptor */ 13427 MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */ 13428 /* MPU_RGDn_Word1 - MPU Region Descriptor */ 13429 MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */ 13430 /* MPU_RGDn_Word2 - MPU Region Descriptor */ 13431 MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */ 13432 /* MPU_RGDn_Word3 - MPU Region Descriptor */ 13433 MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */ 13434 }; 13435 13436 }; 13437 int8_t MPU_reserved_0500_C[768]; 13438 union { 13439 /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ 13440 MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */ 13441 13442 struct { 13443 /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ 13444 MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */ 13445 MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */ 13446 MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */ 13447 MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */ 13448 MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */ 13449 MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */ 13450 MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */ 13451 MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */ 13452 MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */ 13453 MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */ 13454 MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */ 13455 MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */ 13456 MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */ 13457 MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */ 13458 MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */ 13459 MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */ 13460 }; 13461 13462 }; 13463 } MPU_tag; 13464 13465 13466 #define MPU (*(volatile MPU_tag *) 0xFFF10000UL) 13467 13468 13469 13470 /****************************************************************/ 13471 /* */ 13472 /* Module: SEMA4 */ 13473 /* */ 13474 /****************************************************************/ 13475 13476 13477 /* Register layout for all registers GATE... */ 13478 13479 typedef union { /* SEMA4_GATEn - Semephores Gate Register */ 13480 uint8_t R; 13481 struct { 13482 uint8_t:6; 13483 uint8_t GTFSM:2; /* Gate Finite State machine */ 13484 } B; 13485 } SEMA4_GATE_8B_tag; 13486 13487 typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ 13488 uint16_t R; 13489 struct { 13490 uint16_t INE:16; /* Interrupt Request Notification Enable */ 13491 } B; 13492 } SEMA4_CP0INE_16B_tag; 13493 13494 typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ 13495 uint16_t R; 13496 struct { 13497 uint16_t INE:16; /* Interrupt Request Notification Enable */ 13498 } B; 13499 } SEMA4_CP1INE_16B_tag; 13500 13501 typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ 13502 uint16_t R; 13503 struct { 13504 uint16_t GN:16; /* Gate 0 Notification */ 13505 } B; 13506 } SEMA4_CP0NTF_16B_tag; 13507 13508 typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ 13509 uint16_t R; 13510 struct { 13511 uint16_t GN:16; /* Gate 1 Notification */ 13512 } B; 13513 } SEMA4_CP1NTF_16B_tag; 13514 13515 typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */ 13516 uint16_t R; 13517 struct { 13518 uint16_t:2; 13519 uint16_t RSTGSM:2; /* Reset Gate Finite State Machine */ 13520 uint16_t RSTGDP:7; /* Reset Gate Data Pattern */ 13521 uint16_t RSTGMS:3; /* Reset Gate Bus Master */ 13522 uint16_t RSTGTN:8; /* Reset Gate Number */ 13523 } B; 13524 } SEMA4_RSTGT_16B_tag; 13525 13526 typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ 13527 uint16_t R; 13528 struct { 13529 uint16_t:2; 13530 uint16_t RSTNSM:2; /* Reset Gate Finite State Machine */ 13531 uint16_t RSTNDP:7; /* Reset Gate Data Pattern */ 13532 uint16_t RSTNMS:3; /* Reset Gate Bus Master */ 13533 uint16_t RSTNTN:8; /* Reset Gate Number */ 13534 } B; 13535 } SEMA4_RSTNTF_16B_tag; 13536 13537 13538 13539 typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */ 13540 union { 13541 /* SEMA4_GATEn - Semephores Gate Register */ 13542 SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */ 13543 13544 struct { 13545 /* SEMA4_GATEn - Semephores Gate Register */ 13546 SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */ 13547 SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */ 13548 SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */ 13549 SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */ 13550 SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */ 13551 SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */ 13552 SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */ 13553 SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */ 13554 SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */ 13555 SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */ 13556 SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */ 13557 SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */ 13558 SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */ 13559 SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */ 13560 SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */ 13561 SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */ 13562 }; 13563 13564 }; 13565 int8_t SEMA4_reserved_0010[48]; 13566 /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ 13567 SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */ 13568 int8_t SEMA4_reserved_0042[6]; 13569 /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ 13570 SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */ 13571 int8_t SEMA4_reserved_004A[54]; 13572 /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ 13573 SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */ 13574 int8_t SEMA4_reserved_0082[6]; 13575 /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ 13576 SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */ 13577 int8_t SEMA4_reserved_008A[118]; 13578 /* SEMA4_RSTGT - Semaphores Reset Gate */ 13579 SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */ 13580 int8_t SEMA4_reserved_0102[2]; 13581 /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ 13582 SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */ 13583 } SEMA4_tag; 13584 13585 13586 #define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL) 13587 13588 13589 13590 /****************************************************************/ 13591 /* */ 13592 /* Module: SWT */ 13593 /* */ 13594 /****************************************************************/ 13595 13596 typedef union { /* SWT_CR - Control Register */ 13597 uint32_t R; 13598 struct { 13599 uint32_t MAP0:1; /* Master Acces Protection for Master 0 */ 13600 uint32_t MAP1:1; /* Master Acces Protection for Master 1 */ 13601 uint32_t MAP2:1; /* Master Acces Protection for Master 2 */ 13602 uint32_t MAP3:1; /* Master Acces Protection for Master 3 */ 13603 uint32_t MAP4:1; /* Master Acces Protection for Master 4 */ 13604 uint32_t MAP5:1; /* Master Acces Protection for Master 5 */ 13605 uint32_t MAP6:1; /* Master Acces Protection for Master 6 */ 13606 uint32_t MAP7:1; /* Master Acces Protection for Master 7 */ 13607 uint32_t:14; 13608 uint32_t KEY:1; /* Keyed Service Mode */ 13609 uint32_t RIA:1; /* Reset on Invalid Access */ 13610 uint32_t WND:1; /* Window Mode */ 13611 uint32_t ITR:1; /* Interrupt Then Reset */ 13612 uint32_t HLK:1; /* Hard Lock */ 13613 uint32_t SLK:1; /* Soft Lock */ 13614 uint32_t:1; 13615 uint32_t STP:1; /* Stop Mode Control */ 13616 uint32_t FRZ:1; /* Debug Mode Control */ 13617 uint32_t WEN:1; /* Watchdog Enabled */ 13618 } B; 13619 } SWT_CR_32B_tag; 13620 13621 typedef union { /* SWT_IR - SWT Interrupt Register */ 13622 uint32_t R; 13623 struct { 13624 uint32_t:31; 13625 uint32_t TIF:1; /* Time Out Interrupt Flag */ 13626 } B; 13627 } SWT_IR_32B_tag; 13628 13629 typedef union { /* SWT_TO - SWT Time-Out Register */ 13630 uint32_t R; 13631 struct { 13632 uint32_t WTO:32; /* Watchdog Time Out Period */ 13633 } B; 13634 } SWT_TO_32B_tag; 13635 13636 typedef union { /* SWT_WN - SWT Window Register */ 13637 uint32_t R; 13638 struct { 13639 uint32_t WST:32; /* Watchdog Time Out Period */ 13640 } B; 13641 } SWT_WN_32B_tag; 13642 13643 typedef union { /* SWT_SR - SWT Service Register */ 13644 uint32_t R; 13645 struct { 13646 uint32_t:16; 13647 uint32_t WSC:16; /* Watchdog Service Code */ 13648 } B; 13649 } SWT_SR_32B_tag; 13650 13651 typedef union { /* SWT_CO - SWT Counter Output Register */ 13652 uint32_t R; 13653 struct { 13654 uint32_t CNT:32; /* Watchdog Count */ 13655 } B; 13656 } SWT_CO_32B_tag; 13657 13658 typedef union { /* SWT_SK - SWT Service Key Register */ 13659 uint32_t R; 13660 struct { 13661 uint32_t:16; 13662 uint32_t SERVICEKEY:16; /* Service Key */ 13663 } B; 13664 } SWT_SK_32B_tag; 13665 13666 13667 13668 typedef struct SWT_struct_tag { /* start of SWT_tag */ 13669 /* SWT_CR - Control Register */ 13670 SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ 13671 /* SWT_IR - SWT Interrupt Register */ 13672 SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */ 13673 /* SWT_TO - SWT Time-Out Register */ 13674 SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */ 13675 /* SWT_WN - SWT Window Register */ 13676 SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */ 13677 /* SWT_SR - SWT Service Register */ 13678 SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */ 13679 /* SWT_CO - SWT Counter Output Register */ 13680 SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */ 13681 /* SWT_SK - SWT Service Key Register */ 13682 SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */ 13683 } SWT_tag; 13684 13685 13686 #define SWT (*(volatile SWT_tag *) 0xFFF38000UL) 13687 13688 13689 13690 /****************************************************************/ 13691 /* */ 13692 /* Module: STM */ 13693 /* */ 13694 /****************************************************************/ 13695 13696 typedef union { /* STM_CR - Control Register */ 13697 uint32_t R; 13698 struct { 13699 uint32_t:16; 13700 uint32_t CPS:8; /* Counter Prescaler */ 13701 uint32_t:6; 13702 uint32_t FRZ:1; /* Freeze Control */ 13703 uint32_t TEN:1; /* Timer Counter Enabled */ 13704 } B; 13705 } STM_CR_32B_tag; 13706 13707 typedef union { /* STM_CNT - STM Count Register */ 13708 uint32_t R; 13709 } STM_CNT_32B_tag; 13710 13711 13712 /* Register layout for all registers CCR... */ 13713 13714 typedef union { /* STM_CCRn - STM Channel Control Register */ 13715 uint32_t R; 13716 struct { 13717 uint32_t:31; 13718 uint32_t CEN:1; /* Channel Enable */ 13719 } B; 13720 } STM_CCR_32B_tag; 13721 13722 13723 /* Register layout for all registers CIR... */ 13724 13725 typedef union { /* STM_CIRn - STM Channel Interrupt Register */ 13726 uint32_t R; 13727 struct { 13728 uint32_t:31; 13729 uint32_t CIF:1; /* Channel Interrupt Flag */ 13730 } B; 13731 } STM_CIR_32B_tag; 13732 13733 13734 /* Register layout for all registers CMP... */ 13735 13736 typedef union { /* STM_CMPn - STM Channel Compare Register */ 13737 uint32_t R; 13738 } STM_CMP_32B_tag; 13739 13740 13741 typedef struct STM_CHANNEL_struct_tag { 13742 13743 /* STM_CCRn - STM Channel Control Register */ 13744 STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */ 13745 /* STM_CIRn - STM Channel Interrupt Register */ 13746 STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */ 13747 /* STM_CMPn - STM Channel Compare Register */ 13748 STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */ 13749 int8_t STM_CHANNEL_reserved_000C[4]; 13750 13751 } STM_CHANNEL_tag; 13752 13753 13754 typedef struct STM_struct_tag { /* start of STM_tag */ 13755 union { 13756 STM_CR_32B_tag CR0; /* deprecated - please avoid */ 13757 13758 /* STM_CR - Control Register */ 13759 STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ 13760 13761 }; 13762 union { 13763 STM_CNT_32B_tag CNT0; /* deprecated - please avoid */ 13764 13765 /* STM_CNT - STM Count Register */ 13766 STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */ 13767 13768 }; 13769 int8_t STM_reserved_0008_C[8]; 13770 union { 13771 /* Register set CHANNEL */ 13772 STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */ 13773 13774 struct { 13775 /* STM_CCRn - STM Channel Control Register */ 13776 STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */ 13777 /* STM_CIRn - STM Channel Interrupt Register */ 13778 STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */ 13779 /* STM_CMPn - STM Channel Compare Register */ 13780 STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */ 13781 int8_t STM_reserved_001C_I1[4]; 13782 /* STM_CCRn - STM Channel Control Register */ 13783 STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */ 13784 /* STM_CIRn - STM Channel Interrupt Register */ 13785 STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */ 13786 /* STM_CMPn - STM Channel Compare Register */ 13787 STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */ 13788 int8_t STM_reserved_002C_I1[4]; 13789 /* STM_CCRn - STM Channel Control Register */ 13790 STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */ 13791 /* STM_CIRn - STM Channel Interrupt Register */ 13792 STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */ 13793 /* STM_CMPn - STM Channel Compare Register */ 13794 STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */ 13795 int8_t STM_reserved_003C_I1[4]; 13796 /* STM_CCRn - STM Channel Control Register */ 13797 STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */ 13798 /* STM_CIRn - STM Channel Interrupt Register */ 13799 STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */ 13800 /* STM_CMPn - STM Channel Compare Register */ 13801 STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */ 13802 int8_t STM_reserved_004C_E1[4]; 13803 }; 13804 13805 }; 13806 } STM_tag; 13807 13808 13809 #define STM (*(volatile STM_tag *) 0xFFF3C000UL) 13810 13811 13812 13813 /****************************************************************/ 13814 /* */ 13815 /* Module: SPP_MCM */ 13816 /* */ 13817 /****************************************************************/ 13818 13819 typedef union { /* SPP_MCM_PCT - Processor Core Type */ 13820 uint16_t R; 13821 struct { 13822 uint16_t PCTYPE:16; /* Processor Core Type */ 13823 } B; 13824 } SPP_MCM_PCT_16B_tag; 13825 13826 typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ 13827 uint16_t R; 13828 struct { 13829 uint16_t PLREVISION:16; /* Platform Revision */ 13830 } B; 13831 } SPP_MCM_PLREV_16B_tag; 13832 13833 typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ 13834 uint32_t R; 13835 struct { 13836 uint32_t PMC:32; /* IPS Module Configuration */ 13837 } B; 13838 } SPP_MCM_IOPMC_32B_tag; 13839 13840 typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ 13841 uint8_t R; 13842 struct { 13843 uint8_t POR:1; /* Power on Reset */ 13844 #ifndef USE_FIELD_ALIASES_SPP_MCM 13845 uint8_t OFPLR:1; /* Off-Platform Reset */ 13846 #else 13847 uint8_t DIR:1; /* deprecated name - please avoid */ 13848 #endif 13849 uint8_t:6; 13850 } B; 13851 } SPP_MCM_MRSR_8B_tag; 13852 13853 typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ 13854 uint8_t R; 13855 struct { 13856 uint8_t ENBWCR:1; /* Enable WCR */ 13857 uint8_t:3; 13858 uint8_t PRILVL:4; /* Interrupt Priority Level */ 13859 } B; 13860 } SPP_MCM_MWCR_8B_tag; 13861 13862 typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ 13863 uint8_t R; 13864 struct { 13865 uint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */ 13866 uint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */ 13867 uint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */ 13868 uint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */ 13869 uint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */ 13870 uint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */ 13871 uint8_t:2; 13872 } B; 13873 } SPP_MCM_MIR_8B_tag; 13874 13875 typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ 13876 uint32_t R; 13877 struct { 13878 uint32_t MUSERDCR:32; /* User Defined Control Register */ 13879 } B; 13880 } SPP_MCM_MUDCR_32B_tag; 13881 13882 typedef union { /* SPP_MCM_ECR - ECC Configuration Register */ 13883 uint8_t R; 13884 struct { 13885 uint8_t:2; 13886 #ifndef USE_FIELD_ALIASES_SPP_MCM 13887 uint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */ 13888 #else 13889 uint8_t ER1BR:1; /* deprecated name - please avoid */ 13890 #endif 13891 #ifndef USE_FIELD_ALIASES_SPP_MCM 13892 uint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */ 13893 #else 13894 uint8_t EF1BR:1; /* deprecated name - please avoid */ 13895 #endif 13896 uint8_t:2; 13897 #ifndef USE_FIELD_ALIASES_SPP_MCM 13898 uint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */ 13899 #else 13900 uint8_t ERNCR:1; /* deprecated name - please avoid */ 13901 #endif 13902 #ifndef USE_FIELD_ALIASES_SPP_MCM 13903 uint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */ 13904 #else 13905 uint8_t EFNCR:1; /* deprecated name - please avoid */ 13906 #endif 13907 } B; 13908 } SPP_MCM_ECR_8B_tag; 13909 13910 typedef union { /* SPP_MCM_ESR - ECC Status Register */ 13911 uint8_t R; 13912 struct { 13913 uint8_t:2; 13914 #ifndef USE_FIELD_ALIASES_SPP_MCM 13915 uint8_t PR1BC:1; /* Platform RAM 1-bit Correction */ 13916 #else 13917 uint8_t R1BC:1; /* deprecated name - please avoid */ 13918 #endif 13919 #ifndef USE_FIELD_ALIASES_SPP_MCM 13920 uint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */ 13921 #else 13922 uint8_t F1BC:1; /* deprecated name - please avoid */ 13923 #endif 13924 uint8_t:2; 13925 #ifndef USE_FIELD_ALIASES_SPP_MCM 13926 uint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */ 13927 #else 13928 uint8_t RNCE:1; /* deprecated name - please avoid */ 13929 #endif 13930 #ifndef USE_FIELD_ALIASES_SPP_MCM 13931 uint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */ 13932 #else 13933 uint8_t FNCE:1; /* deprecated name - please avoid */ 13934 #endif 13935 } B; 13936 } SPP_MCM_ESR_8B_tag; 13937 13938 typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */ 13939 uint16_t R; 13940 struct { 13941 uint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */ 13942 uint16_t:1; 13943 uint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */ 13944 uint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */ 13945 uint16_t:2; 13946 uint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */ 13947 uint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */ 13948 uint16_t:1; 13949 uint16_t ERRBIT:7; /* Error Bit Position */ 13950 } B; 13951 } SPP_MCM_EEGR_16B_tag; 13952 13953 typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ 13954 uint32_t R; 13955 } SPP_MCM_PFEAR_32B_tag; 13956 13957 typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ 13958 uint8_t R; 13959 } SPP_MCM_PFEMR_8B_tag; 13960 13961 typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ 13962 uint8_t R; 13963 struct { 13964 #ifndef USE_FIELD_ALIASES_SPP_MCM 13965 uint8_t F_WRITE:1; /* AMBA-AHBH Write */ 13966 #else 13967 uint8_t WRITE:1; /* deprecated name - please avoid */ 13968 #endif 13969 #ifndef USE_FIELD_ALIASES_SPP_MCM 13970 uint8_t F_SIZE:3; /* AMBA-AHBH Size */ 13971 #else 13972 uint8_t SIZE:3; /* deprecated name - please avoid */ 13973 #endif 13974 #ifndef USE_FIELD_ALIASES_SPP_MCM 13975 uint8_t F_PROTECT:4; /* AMBA-AHBH PROT */ 13976 #else 13977 uint8_t PROTECTION:4; /* deprecated name - please avoid */ 13978 #endif 13979 } B; 13980 } SPP_MCM_PFEAT_8B_tag; 13981 13982 typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ 13983 uint32_t R; 13984 } SPP_MCM_PFEDRH_32B_tag; 13985 13986 typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ 13987 uint32_t R; 13988 } SPP_MCM_PFEDR_32B_tag; 13989 13990 typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ 13991 uint32_t R; 13992 } SPP_MCM_PREAR_32B_tag; 13993 13994 typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ 13995 uint8_t R; 13996 } SPP_MCM_PRESR_8B_tag; 13997 13998 typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ 13999 uint8_t R; 14000 struct { 14001 uint8_t:4; 14002 #ifndef USE_FIELD_ALIASES_SPP_MCM 14003 uint8_t PR_EMR:4; /* Platform RAM ECC Master Number */ 14004 #else 14005 uint8_t REMR:4; /* deprecated name - please avoid */ 14006 #endif 14007 } B; 14008 } SPP_MCM_PREMR_8B_tag; 14009 14010 typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ 14011 uint8_t R; 14012 struct { 14013 #ifndef USE_FIELD_ALIASES_SPP_MCM 14014 uint8_t R_WRITE:1; /* AMBA-AHBH Write */ 14015 #else 14016 uint8_t WRITE:1; /* deprecated name - please avoid */ 14017 #endif 14018 #ifndef USE_FIELD_ALIASES_SPP_MCM 14019 uint8_t R_SIZE:3; /* AMBA-AHBH Size */ 14020 #else 14021 uint8_t SIZE:3; /* deprecated name - please avoid */ 14022 #endif 14023 #ifndef USE_FIELD_ALIASES_SPP_MCM 14024 uint8_t R_PROTECT:4; /* AMBA-AHBH PROT */ 14025 #else 14026 uint8_t PROTECTION:4; /* deprecated name - please avoid */ 14027 #endif 14028 } B; 14029 } SPP_MCM_PREAT_8B_tag; 14030 14031 typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ 14032 uint32_t R; 14033 } SPP_MCM_PREDRH_32B_tag; 14034 14035 typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ 14036 uint32_t R; 14037 } SPP_MCM_PREDR_32B_tag; 14038 14039 14040 14041 typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */ 14042 /* SPP_MCM_PCT - Processor Core Type */ 14043 SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */ 14044 union { 14045 SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */ 14046 14047 /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ 14048 SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */ 14049 14050 }; 14051 int8_t SPP_MCM_reserved_0004_C[4]; 14052 union { 14053 SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */ 14054 14055 /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ 14056 SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */ 14057 14058 }; 14059 int8_t SPP_MCM_reserved_000C[3]; 14060 /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ 14061 SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */ 14062 int8_t SPP_MCM_reserved_0010[3]; 14063 /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ 14064 SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */ 14065 int8_t SPP_MCM_reserved_0014[11]; 14066 /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ 14067 SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */ 14068 int8_t SPP_MCM_reserved_0020[4]; 14069 /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ 14070 SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */ 14071 int8_t SPP_MCM_reserved_0028[27]; 14072 /* SPP_MCM_ECR - ECC Configuration Register */ 14073 SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */ 14074 int8_t SPP_MCM_reserved_0044[3]; 14075 /* SPP_MCM_ESR - ECC Status Register */ 14076 SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */ 14077 int8_t SPP_MCM_reserved_0048[2]; 14078 /* SPP_MCM_EEGR - ECC Error Generation Register */ 14079 SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */ 14080 int8_t SPP_MCM_reserved_004C_C[4]; 14081 union { 14082 /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ 14083 SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */ 14084 14085 SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */ 14086 14087 }; 14088 int8_t SPP_MCM_reserved_0054_C[2]; 14089 union { 14090 /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ 14091 SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */ 14092 14093 SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */ 14094 14095 }; 14096 union { 14097 /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ 14098 SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */ 14099 14100 SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */ 14101 14102 }; 14103 /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ 14104 SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */ 14105 union { 14106 /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ 14107 SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */ 14108 14109 SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */ 14110 14111 }; 14112 union { 14113 SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */ 14114 14115 /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ 14116 SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */ 14117 14118 }; 14119 int8_t SPP_MCM_reserved_0064_C; 14120 union { 14121 SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */ 14122 14123 /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ 14124 SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */ 14125 14126 }; 14127 union { 14128 SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */ 14129 14130 /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ 14131 SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */ 14132 14133 }; 14134 union { 14135 SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */ 14136 14137 /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ 14138 SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */ 14139 14140 }; 14141 /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ 14142 SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */ 14143 union { 14144 SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */ 14145 14146 /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ 14147 SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */ 14148 14149 }; 14150 } SPP_MCM_tag; 14151 14152 14153 #define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL) 14154 14155 14156 14157 /****************************************************************/ 14158 /* */ 14159 /* Module: SPP_DMA2 */ 14160 /* */ 14161 /****************************************************************/ 14162 14163 typedef union { /* SPP_DMA2_DMACR - DMA Control Register */ 14164 uint32_t R; 14165 struct { 14166 uint32_t:14; 14167 uint32_t CX:1; /* Cancel Transfer */ 14168 uint32_t ECX:1; /* Error Cancel Transfer */ 14169 uint32_t GRP3PRI:2; /* Channel Group 3 Priority */ 14170 uint32_t GRP2PRI:2; /* Channel Group 2 Priority */ 14171 uint32_t GRP1PRI:2; /* Channel Group 1 Priority */ 14172 uint32_t GRP0PRI:2; /* Channel Group 0 Priority */ 14173 uint32_t EMLM:1; /* Enable Minor Loop Mapping */ 14174 uint32_t CLM:1; /* Continuous Link Mode */ 14175 uint32_t HALT:1; /* Halt DMA Operations */ 14176 uint32_t HOE:1; /* Halt on Error */ 14177 uint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ 14178 uint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ 14179 uint32_t EDBG:1; /* Enable Debug */ 14180 uint32_t EBW:1; /* Enable Buffered Writes */ 14181 } B; 14182 } SPP_DMA2_DMACR_32B_tag; 14183 14184 typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */ 14185 uint32_t R; 14186 struct { 14187 uint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */ 14188 uint32_t:14; 14189 uint32_t ECX:1; /* Transfer Cancelled */ 14190 uint32_t GPE:1; /* Group Priority Error */ 14191 uint32_t CPE:1; /* Channel Priority Error */ 14192 uint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */ 14193 uint32_t SAE:1; /* Source Address Error */ 14194 uint32_t SOE:1; /* Source Offset Error */ 14195 uint32_t DAE:1; /* Destination Address Error */ 14196 uint32_t DOE:1; /* Destination Offset Error */ 14197 uint32_t NCE:1; /* Nbytes/Citer Configuration Error */ 14198 uint32_t SGE:1; /* Scatter/Gather Configuration Error */ 14199 uint32_t SBE:1; /* Source Bus Error */ 14200 uint32_t DBE:1; /* Destination Bus Error */ 14201 } B; 14202 } SPP_DMA2_DMAES_32B_tag; 14203 14204 typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ 14205 uint32_t R; 14206 struct { 14207 uint32_t ERQ:32; /* DMA Enable Request */ 14208 } B; 14209 } SPP_DMA2_DMAERQH_32B_tag; 14210 14211 typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ 14212 uint32_t R; 14213 struct { 14214 uint32_t ERQ:32; /* DMA Enable Request */ 14215 } B; 14216 } SPP_DMA2_DMAERQL_32B_tag; 14217 14218 typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ 14219 uint32_t R; 14220 struct { 14221 uint32_t EEI:32; /* DMA Enable Error Interrupt */ 14222 } B; 14223 } SPP_DMA2_DMAEEIH_32B_tag; 14224 14225 typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ 14226 uint32_t R; 14227 struct { 14228 uint32_t EEI:32; /* DMA Enable Error Interrupt */ 14229 } B; 14230 } SPP_DMA2_DMAEEIL_32B_tag; 14231 14232 typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ 14233 uint8_t R; 14234 struct { 14235 uint8_t:1; 14236 uint8_t SERQ:7; /* Set Enable Request */ 14237 } B; 14238 } SPP_DMA2_DMASERQ_8B_tag; 14239 14240 typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ 14241 uint8_t R; 14242 struct { 14243 uint8_t:1; 14244 uint8_t CERQ:7; /* Clear Enable Request */ 14245 } B; 14246 } SPP_DMA2_DMACERQ_8B_tag; 14247 14248 typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ 14249 uint8_t R; 14250 struct { 14251 uint8_t:1; 14252 uint8_t SEEI:7; /* Set Enable Error Interrupt */ 14253 } B; 14254 } SPP_DMA2_DMASEEI_8B_tag; 14255 14256 typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ 14257 uint8_t R; 14258 struct { 14259 uint8_t:1; 14260 uint8_t CEEI:7; /* Clear Enable Error Interrupt */ 14261 } B; 14262 } SPP_DMA2_DMACEEI_8B_tag; 14263 14264 typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ 14265 uint8_t R; 14266 struct { 14267 uint8_t:1; 14268 uint8_t CINT:7; /* Clear Interrupt Request */ 14269 } B; 14270 } SPP_DMA2_DMACINT_8B_tag; 14271 14272 typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */ 14273 uint8_t R; 14274 struct { 14275 uint8_t:1; 14276 uint8_t CERR:7; /* Clear Error Indicator */ 14277 } B; 14278 } SPP_DMA2_DMACERR_8B_tag; 14279 14280 typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */ 14281 uint8_t R; 14282 struct { 14283 uint8_t:1; 14284 uint8_t SSRT:7; /* Set START Bit */ 14285 } B; 14286 } SPP_DMA2_DMASSRT_8B_tag; 14287 14288 typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ 14289 uint8_t R; 14290 struct { 14291 uint8_t:1; 14292 uint8_t CDNE:7; /* Clear DONE Status Bit */ 14293 } B; 14294 } SPP_DMA2_DMACDNE_8B_tag; 14295 14296 typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ 14297 uint32_t R; 14298 struct { 14299 uint32_t INT:32; /* DMA Interrupt Request */ 14300 } B; 14301 } SPP_DMA2_DMAINTH_32B_tag; 14302 14303 typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ 14304 uint32_t R; 14305 struct { 14306 uint32_t INT:32; /* DMA Interrupt Request */ 14307 } B; 14308 } SPP_DMA2_DMAINTL_32B_tag; 14309 14310 typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */ 14311 uint32_t R; 14312 struct { 14313 uint32_t ERR:32; /* DMA Error n */ 14314 } B; 14315 } SPP_DMA2_DMAERRH_32B_tag; 14316 14317 typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */ 14318 uint32_t R; 14319 struct { 14320 uint32_t ERR:32; /* DMA Error n */ 14321 } B; 14322 } SPP_DMA2_DMAERRL_32B_tag; 14323 14324 typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ 14325 uint32_t R; 14326 struct { 14327 uint32_t HRS:32; /* DMA Hardware Request Status */ 14328 } B; 14329 } SPP_DMA2_DMAHRSH_32B_tag; 14330 14331 typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ 14332 uint32_t R; 14333 struct { 14334 uint32_t HRS:32; /* DMA Hardware Request Status */ 14335 } B; 14336 } SPP_DMA2_DMAHRSL_32B_tag; 14337 14338 typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ 14339 uint32_t R; 14340 struct { 14341 uint32_t GPOR:32; /* DMA General Purpose Output */ 14342 } B; 14343 } SPP_DMA2_DMAGPOR_32B_tag; 14344 14345 14346 /* Register layout for all registers DCHPRI... */ 14347 14348 typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ 14349 uint8_t R; 14350 struct { 14351 uint8_t ECP:1; /* Enable Channel Preemption */ 14352 uint8_t DPA:1; /* Disable Preempt Ability */ 14353 uint8_t GRPPRI:2; /* Channel n Current Group Priority */ 14354 uint8_t CHPRI:4; /* Channel n Arbitration Priority */ 14355 } B; 14356 } SPP_DMA2_DCHPRI_8B_tag; 14357 14358 14359 /* Register layout for all registers TCDWORD0_... */ 14360 14361 typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */ 14362 uint32_t R; 14363 struct { 14364 uint32_t SADDR:32; /* Source Address */ 14365 } B; 14366 } SPP_DMA2_TCDWORD0__32B_tag; 14367 14368 14369 /* Register layout for all registers TCDWORD4_... */ 14370 14371 typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14372 uint32_t R; 14373 struct { 14374 uint32_t SMOD:5; /* Source Address Modulo */ 14375 uint32_t SSIZE:3; /* Source Data Transfer Size */ 14376 uint32_t DMOD:5; /* Destination Address Module */ 14377 uint32_t DSIZE:3; /* Destination Data Transfer Size */ 14378 uint32_t SOFF:16; /* Source Address Signed Offset */ 14379 } B; 14380 } SPP_DMA2_TCDWORD4__32B_tag; 14381 14382 14383 /* Register layout for all registers TCDWORD8_... */ 14384 14385 typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */ 14386 uint32_t R; 14387 struct { 14388 uint32_t SMLOE:1; /* Source Minor Loop Offset Enable */ 14389 uint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */ 14390 uint32_t MLOFF:20; /* Minor Loop Offset */ 14391 uint32_t NBYTES:10; /* Inner Minor byte transfer Count */ 14392 } B; 14393 } SPP_DMA2_TCDWORD8__32B_tag; 14394 14395 14396 /* Register layout for all registers TCDWORD12_... */ 14397 14398 typedef union { /* SPP_DMA2_TCDn Word3 - slast */ 14399 uint32_t R; 14400 struct { 14401 uint32_t SLAST:32; /* Last Source Address Adjustment */ 14402 } B; 14403 } SPP_DMA2_TCDWORD12__32B_tag; 14404 14405 14406 /* Register layout for all registers TCDWORD16_... */ 14407 14408 typedef union { /* SPP_DMA2_TCDn Word4 - daddr */ 14409 uint32_t R; 14410 struct { 14411 uint32_t DADDR:32; /* Destination Address */ 14412 } B; 14413 } SPP_DMA2_TCDWORD16__32B_tag; 14414 14415 14416 /* Register layout for all registers TCDWORD20_... */ 14417 14418 typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14419 uint32_t R; 14420 struct { 14421 uint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */ 14422 uint32_t CITER_LINKCH:6; /* Link Channel Number */ 14423 uint32_t CITER:9; /* Current Major Iteration Count */ 14424 uint32_t DOFF:16; /* Destination Address Signed Offset */ 14425 } B; 14426 } SPP_DMA2_TCDWORD20__32B_tag; 14427 14428 14429 /* Register layout for all registers TCDWORD24_... */ 14430 14431 typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14432 uint32_t R; 14433 struct { 14434 uint32_t DLAST_SGA:32; /* Last destination address adjustment */ 14435 } B; 14436 } SPP_DMA2_TCDWORD24__32B_tag; 14437 14438 14439 /* Register layout for all registers TCDWORD28_... */ 14440 14441 typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14442 uint32_t R; 14443 struct { 14444 14445 #ifndef USE_FIELD_ALIASES_SPP_DMA2 14446 uint32_t BITER_E_LINK:1; /* beginning ("major") iteration count */ 14447 #else 14448 uint32_t BITERE_LINK:1; /* deprecated name - please avoid */ 14449 #endif 14450 uint32_t BITER:15; /* Enable Channel to Channel linking on minor loop complete */ 14451 uint32_t BWC:2; /* Bandwidth Control */ 14452 uint32_t MAJOR_LINKCH:6; /* Link Channel Number */ 14453 uint32_t DONE:1; /* channel done */ 14454 uint32_t ACTIVE:1; /* Channel Active */ 14455 uint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */ 14456 uint32_t E_SG:1; /* Enable Scatter/Gather Processing */ 14457 uint32_t D_REQ:1; /* Disable Request */ 14458 uint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */ 14459 uint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */ 14460 uint32_t START:1; /* Channel Start */ 14461 } B; 14462 } SPP_DMA2_TCDWORD28__32B_tag; 14463 14464 14465 typedef struct SPP_DMA2_CHANNEL_struct_tag { 14466 14467 /* SPP_DMA2_TCDn Word0 - Source Address */ 14468 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */ 14469 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14470 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */ 14471 /* SPP_DMA2_TCDn Word2 - nbytes */ 14472 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */ 14473 /* SPP_DMA2_TCDn Word3 - slast */ 14474 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */ 14475 /* SPP_DMA2_TCDn Word4 - daddr */ 14476 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */ 14477 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14478 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */ 14479 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14480 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */ 14481 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14482 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */ 14483 14484 } SPP_DMA2_CHANNEL_tag; 14485 14486 14487 typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */ 14488 /* SPP_DMA2_DMACR - DMA Control Register */ 14489 SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */ 14490 /* SPP_DMA2_DMAES - DMA Error Status Register */ 14491 SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */ 14492 /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ 14493 SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */ 14494 /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ 14495 SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */ 14496 /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ 14497 SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */ 14498 /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ 14499 SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */ 14500 /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ 14501 SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */ 14502 /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ 14503 SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */ 14504 /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ 14505 SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */ 14506 /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ 14507 SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */ 14508 /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ 14509 SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */ 14510 /* SPP_DMA2_DMACERR - DMA Clear Error */ 14511 SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */ 14512 /* SPP_DMA2_DMASSRT - DMA Set START Bit */ 14513 SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */ 14514 /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ 14515 SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */ 14516 /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ 14517 SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */ 14518 /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ 14519 SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */ 14520 /* SPP_DMA2_DMAERRH - DMA Error Register */ 14521 SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */ 14522 /* SPP_DMA2_DMAERRL - DMA Error Register */ 14523 SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */ 14524 /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ 14525 SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */ 14526 /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ 14527 SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */ 14528 /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ 14529 SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */ 14530 int8_t SPP_DMA2_reserved_003C_C[196]; 14531 union { 14532 /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ 14533 SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */ 14534 14535 struct { 14536 /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ 14537 SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */ 14538 SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */ 14539 SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */ 14540 SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */ 14541 SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */ 14542 SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */ 14543 SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */ 14544 SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */ 14545 SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */ 14546 SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */ 14547 SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */ 14548 SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */ 14549 SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */ 14550 SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */ 14551 SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */ 14552 SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */ 14553 SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */ 14554 SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */ 14555 SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */ 14556 SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */ 14557 SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */ 14558 SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */ 14559 SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */ 14560 SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */ 14561 SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */ 14562 SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */ 14563 SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */ 14564 SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */ 14565 SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */ 14566 SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */ 14567 SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */ 14568 SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */ 14569 SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */ 14570 SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */ 14571 SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */ 14572 SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */ 14573 SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */ 14574 SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */ 14575 SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */ 14576 SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */ 14577 SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */ 14578 SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */ 14579 SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */ 14580 SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */ 14581 SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */ 14582 SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */ 14583 SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */ 14584 SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */ 14585 SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */ 14586 SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */ 14587 SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */ 14588 SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */ 14589 SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */ 14590 SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */ 14591 SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */ 14592 SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */ 14593 SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */ 14594 SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */ 14595 SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */ 14596 SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */ 14597 SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */ 14598 SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */ 14599 SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */ 14600 SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */ 14601 }; 14602 14603 }; 14604 int8_t SPP_DMA2_reserved_0140_C[3776]; 14605 union { 14606 /* Register set CHANNEL */ 14607 SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */ 14608 14609 struct { 14610 /* SPP_DMA2_TCDn Word0 - Source Address */ 14611 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */ 14612 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14613 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */ 14614 /* SPP_DMA2_TCDn Word2 - nbytes */ 14615 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */ 14616 /* SPP_DMA2_TCDn Word3 - slast */ 14617 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */ 14618 /* SPP_DMA2_TCDn Word4 - daddr */ 14619 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */ 14620 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14621 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */ 14622 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14623 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */ 14624 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14625 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */ 14626 /* SPP_DMA2_TCDn Word0 - Source Address */ 14627 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */ 14628 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14629 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */ 14630 /* SPP_DMA2_TCDn Word2 - nbytes */ 14631 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */ 14632 /* SPP_DMA2_TCDn Word3 - slast */ 14633 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */ 14634 /* SPP_DMA2_TCDn Word4 - daddr */ 14635 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */ 14636 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14637 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */ 14638 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14639 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */ 14640 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14641 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */ 14642 /* SPP_DMA2_TCDn Word0 - Source Address */ 14643 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */ 14644 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14645 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */ 14646 /* SPP_DMA2_TCDn Word2 - nbytes */ 14647 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */ 14648 /* SPP_DMA2_TCDn Word3 - slast */ 14649 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */ 14650 /* SPP_DMA2_TCDn Word4 - daddr */ 14651 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */ 14652 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14653 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */ 14654 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14655 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */ 14656 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14657 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */ 14658 /* SPP_DMA2_TCDn Word0 - Source Address */ 14659 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */ 14660 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14661 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */ 14662 /* SPP_DMA2_TCDn Word2 - nbytes */ 14663 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */ 14664 /* SPP_DMA2_TCDn Word3 - slast */ 14665 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */ 14666 /* SPP_DMA2_TCDn Word4 - daddr */ 14667 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */ 14668 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14669 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */ 14670 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14671 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */ 14672 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14673 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */ 14674 /* SPP_DMA2_TCDn Word0 - Source Address */ 14675 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */ 14676 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14677 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */ 14678 /* SPP_DMA2_TCDn Word2 - nbytes */ 14679 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */ 14680 /* SPP_DMA2_TCDn Word3 - slast */ 14681 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */ 14682 /* SPP_DMA2_TCDn Word4 - daddr */ 14683 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */ 14684 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14685 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */ 14686 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14687 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */ 14688 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14689 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */ 14690 /* SPP_DMA2_TCDn Word0 - Source Address */ 14691 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */ 14692 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14693 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */ 14694 /* SPP_DMA2_TCDn Word2 - nbytes */ 14695 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */ 14696 /* SPP_DMA2_TCDn Word3 - slast */ 14697 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */ 14698 /* SPP_DMA2_TCDn Word4 - daddr */ 14699 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */ 14700 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14701 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */ 14702 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14703 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */ 14704 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14705 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */ 14706 /* SPP_DMA2_TCDn Word0 - Source Address */ 14707 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */ 14708 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14709 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */ 14710 /* SPP_DMA2_TCDn Word2 - nbytes */ 14711 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */ 14712 /* SPP_DMA2_TCDn Word3 - slast */ 14713 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */ 14714 /* SPP_DMA2_TCDn Word4 - daddr */ 14715 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */ 14716 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14717 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */ 14718 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14719 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */ 14720 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14721 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */ 14722 /* SPP_DMA2_TCDn Word0 - Source Address */ 14723 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */ 14724 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14725 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */ 14726 /* SPP_DMA2_TCDn Word2 - nbytes */ 14727 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */ 14728 /* SPP_DMA2_TCDn Word3 - slast */ 14729 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */ 14730 /* SPP_DMA2_TCDn Word4 - daddr */ 14731 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */ 14732 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14733 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */ 14734 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14735 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */ 14736 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14737 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */ 14738 /* SPP_DMA2_TCDn Word0 - Source Address */ 14739 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */ 14740 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14741 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */ 14742 /* SPP_DMA2_TCDn Word2 - nbytes */ 14743 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */ 14744 /* SPP_DMA2_TCDn Word3 - slast */ 14745 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */ 14746 /* SPP_DMA2_TCDn Word4 - daddr */ 14747 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */ 14748 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14749 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */ 14750 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14751 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */ 14752 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14753 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */ 14754 /* SPP_DMA2_TCDn Word0 - Source Address */ 14755 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */ 14756 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14757 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */ 14758 /* SPP_DMA2_TCDn Word2 - nbytes */ 14759 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */ 14760 /* SPP_DMA2_TCDn Word3 - slast */ 14761 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */ 14762 /* SPP_DMA2_TCDn Word4 - daddr */ 14763 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */ 14764 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14765 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */ 14766 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14767 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */ 14768 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14769 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */ 14770 /* SPP_DMA2_TCDn Word0 - Source Address */ 14771 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */ 14772 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14773 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */ 14774 /* SPP_DMA2_TCDn Word2 - nbytes */ 14775 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */ 14776 /* SPP_DMA2_TCDn Word3 - slast */ 14777 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */ 14778 /* SPP_DMA2_TCDn Word4 - daddr */ 14779 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */ 14780 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14781 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */ 14782 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14783 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */ 14784 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14785 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */ 14786 /* SPP_DMA2_TCDn Word0 - Source Address */ 14787 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */ 14788 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14789 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */ 14790 /* SPP_DMA2_TCDn Word2 - nbytes */ 14791 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */ 14792 /* SPP_DMA2_TCDn Word3 - slast */ 14793 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */ 14794 /* SPP_DMA2_TCDn Word4 - daddr */ 14795 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */ 14796 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14797 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */ 14798 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14799 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */ 14800 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14801 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */ 14802 /* SPP_DMA2_TCDn Word0 - Source Address */ 14803 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */ 14804 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14805 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */ 14806 /* SPP_DMA2_TCDn Word2 - nbytes */ 14807 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */ 14808 /* SPP_DMA2_TCDn Word3 - slast */ 14809 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */ 14810 /* SPP_DMA2_TCDn Word4 - daddr */ 14811 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */ 14812 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14813 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */ 14814 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14815 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */ 14816 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14817 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */ 14818 /* SPP_DMA2_TCDn Word0 - Source Address */ 14819 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */ 14820 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14821 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */ 14822 /* SPP_DMA2_TCDn Word2 - nbytes */ 14823 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */ 14824 /* SPP_DMA2_TCDn Word3 - slast */ 14825 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */ 14826 /* SPP_DMA2_TCDn Word4 - daddr */ 14827 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */ 14828 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14829 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */ 14830 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14831 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */ 14832 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14833 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */ 14834 /* SPP_DMA2_TCDn Word0 - Source Address */ 14835 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */ 14836 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14837 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */ 14838 /* SPP_DMA2_TCDn Word2 - nbytes */ 14839 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */ 14840 /* SPP_DMA2_TCDn Word3 - slast */ 14841 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */ 14842 /* SPP_DMA2_TCDn Word4 - daddr */ 14843 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */ 14844 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14845 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */ 14846 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14847 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */ 14848 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14849 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */ 14850 /* SPP_DMA2_TCDn Word0 - Source Address */ 14851 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */ 14852 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14853 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */ 14854 /* SPP_DMA2_TCDn Word2 - nbytes */ 14855 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */ 14856 /* SPP_DMA2_TCDn Word3 - slast */ 14857 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */ 14858 /* SPP_DMA2_TCDn Word4 - daddr */ 14859 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */ 14860 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14861 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */ 14862 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14863 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */ 14864 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14865 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */ 14866 /* SPP_DMA2_TCDn Word0 - Source Address */ 14867 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */ 14868 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14869 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */ 14870 /* SPP_DMA2_TCDn Word2 - nbytes */ 14871 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */ 14872 /* SPP_DMA2_TCDn Word3 - slast */ 14873 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */ 14874 /* SPP_DMA2_TCDn Word4 - daddr */ 14875 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */ 14876 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14877 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */ 14878 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14879 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */ 14880 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14881 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */ 14882 /* SPP_DMA2_TCDn Word0 - Source Address */ 14883 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */ 14884 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14885 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */ 14886 /* SPP_DMA2_TCDn Word2 - nbytes */ 14887 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */ 14888 /* SPP_DMA2_TCDn Word3 - slast */ 14889 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */ 14890 /* SPP_DMA2_TCDn Word4 - daddr */ 14891 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */ 14892 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14893 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */ 14894 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14895 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */ 14896 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14897 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */ 14898 /* SPP_DMA2_TCDn Word0 - Source Address */ 14899 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */ 14900 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14901 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */ 14902 /* SPP_DMA2_TCDn Word2 - nbytes */ 14903 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */ 14904 /* SPP_DMA2_TCDn Word3 - slast */ 14905 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */ 14906 /* SPP_DMA2_TCDn Word4 - daddr */ 14907 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */ 14908 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14909 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */ 14910 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14911 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */ 14912 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14913 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */ 14914 /* SPP_DMA2_TCDn Word0 - Source Address */ 14915 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */ 14916 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14917 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */ 14918 /* SPP_DMA2_TCDn Word2 - nbytes */ 14919 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */ 14920 /* SPP_DMA2_TCDn Word3 - slast */ 14921 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */ 14922 /* SPP_DMA2_TCDn Word4 - daddr */ 14923 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */ 14924 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14925 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */ 14926 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14927 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */ 14928 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14929 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */ 14930 /* SPP_DMA2_TCDn Word0 - Source Address */ 14931 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */ 14932 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14933 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */ 14934 /* SPP_DMA2_TCDn Word2 - nbytes */ 14935 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */ 14936 /* SPP_DMA2_TCDn Word3 - slast */ 14937 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */ 14938 /* SPP_DMA2_TCDn Word4 - daddr */ 14939 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */ 14940 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14941 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */ 14942 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14943 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */ 14944 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14945 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */ 14946 /* SPP_DMA2_TCDn Word0 - Source Address */ 14947 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */ 14948 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14949 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */ 14950 /* SPP_DMA2_TCDn Word2 - nbytes */ 14951 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */ 14952 /* SPP_DMA2_TCDn Word3 - slast */ 14953 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */ 14954 /* SPP_DMA2_TCDn Word4 - daddr */ 14955 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */ 14956 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14957 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */ 14958 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14959 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */ 14960 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14961 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */ 14962 /* SPP_DMA2_TCDn Word0 - Source Address */ 14963 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */ 14964 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14965 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */ 14966 /* SPP_DMA2_TCDn Word2 - nbytes */ 14967 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */ 14968 /* SPP_DMA2_TCDn Word3 - slast */ 14969 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */ 14970 /* SPP_DMA2_TCDn Word4 - daddr */ 14971 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */ 14972 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14973 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */ 14974 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14975 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */ 14976 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14977 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */ 14978 /* SPP_DMA2_TCDn Word0 - Source Address */ 14979 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */ 14980 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14981 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */ 14982 /* SPP_DMA2_TCDn Word2 - nbytes */ 14983 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */ 14984 /* SPP_DMA2_TCDn Word3 - slast */ 14985 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */ 14986 /* SPP_DMA2_TCDn Word4 - daddr */ 14987 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */ 14988 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 14989 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */ 14990 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 14991 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */ 14992 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 14993 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */ 14994 /* SPP_DMA2_TCDn Word0 - Source Address */ 14995 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */ 14996 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 14997 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */ 14998 /* SPP_DMA2_TCDn Word2 - nbytes */ 14999 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */ 15000 /* SPP_DMA2_TCDn Word3 - slast */ 15001 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */ 15002 /* SPP_DMA2_TCDn Word4 - daddr */ 15003 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */ 15004 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15005 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */ 15006 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15007 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */ 15008 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15009 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */ 15010 /* SPP_DMA2_TCDn Word0 - Source Address */ 15011 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */ 15012 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15013 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */ 15014 /* SPP_DMA2_TCDn Word2 - nbytes */ 15015 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */ 15016 /* SPP_DMA2_TCDn Word3 - slast */ 15017 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */ 15018 /* SPP_DMA2_TCDn Word4 - daddr */ 15019 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */ 15020 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15021 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */ 15022 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15023 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */ 15024 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15025 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */ 15026 /* SPP_DMA2_TCDn Word0 - Source Address */ 15027 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */ 15028 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15029 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */ 15030 /* SPP_DMA2_TCDn Word2 - nbytes */ 15031 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */ 15032 /* SPP_DMA2_TCDn Word3 - slast */ 15033 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */ 15034 /* SPP_DMA2_TCDn Word4 - daddr */ 15035 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */ 15036 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15037 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */ 15038 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15039 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */ 15040 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15041 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */ 15042 /* SPP_DMA2_TCDn Word0 - Source Address */ 15043 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */ 15044 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15045 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */ 15046 /* SPP_DMA2_TCDn Word2 - nbytes */ 15047 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */ 15048 /* SPP_DMA2_TCDn Word3 - slast */ 15049 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */ 15050 /* SPP_DMA2_TCDn Word4 - daddr */ 15051 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */ 15052 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15053 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */ 15054 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15055 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */ 15056 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15057 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */ 15058 /* SPP_DMA2_TCDn Word0 - Source Address */ 15059 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */ 15060 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15061 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */ 15062 /* SPP_DMA2_TCDn Word2 - nbytes */ 15063 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */ 15064 /* SPP_DMA2_TCDn Word3 - slast */ 15065 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */ 15066 /* SPP_DMA2_TCDn Word4 - daddr */ 15067 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */ 15068 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15069 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */ 15070 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15071 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */ 15072 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15073 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */ 15074 /* SPP_DMA2_TCDn Word0 - Source Address */ 15075 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */ 15076 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15077 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */ 15078 /* SPP_DMA2_TCDn Word2 - nbytes */ 15079 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */ 15080 /* SPP_DMA2_TCDn Word3 - slast */ 15081 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */ 15082 /* SPP_DMA2_TCDn Word4 - daddr */ 15083 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */ 15084 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15085 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */ 15086 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15087 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */ 15088 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15089 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */ 15090 /* SPP_DMA2_TCDn Word0 - Source Address */ 15091 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */ 15092 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15093 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */ 15094 /* SPP_DMA2_TCDn Word2 - nbytes */ 15095 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */ 15096 /* SPP_DMA2_TCDn Word3 - slast */ 15097 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */ 15098 /* SPP_DMA2_TCDn Word4 - daddr */ 15099 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */ 15100 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15101 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */ 15102 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15103 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */ 15104 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15105 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */ 15106 /* SPP_DMA2_TCDn Word0 - Source Address */ 15107 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */ 15108 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15109 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */ 15110 /* SPP_DMA2_TCDn Word2 - nbytes */ 15111 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */ 15112 /* SPP_DMA2_TCDn Word3 - slast */ 15113 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */ 15114 /* SPP_DMA2_TCDn Word4 - daddr */ 15115 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */ 15116 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15117 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */ 15118 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15119 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */ 15120 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15121 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */ 15122 /* SPP_DMA2_TCDn Word0 - Source Address */ 15123 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */ 15124 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15125 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */ 15126 /* SPP_DMA2_TCDn Word2 - nbytes */ 15127 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */ 15128 /* SPP_DMA2_TCDn Word3 - slast */ 15129 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */ 15130 /* SPP_DMA2_TCDn Word4 - daddr */ 15131 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */ 15132 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15133 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */ 15134 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15135 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */ 15136 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15137 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */ 15138 /* SPP_DMA2_TCDn Word0 - Source Address */ 15139 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */ 15140 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15141 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */ 15142 /* SPP_DMA2_TCDn Word2 - nbytes */ 15143 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */ 15144 /* SPP_DMA2_TCDn Word3 - slast */ 15145 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */ 15146 /* SPP_DMA2_TCDn Word4 - daddr */ 15147 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */ 15148 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15149 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */ 15150 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15151 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */ 15152 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15153 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */ 15154 /* SPP_DMA2_TCDn Word0 - Source Address */ 15155 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */ 15156 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15157 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */ 15158 /* SPP_DMA2_TCDn Word2 - nbytes */ 15159 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */ 15160 /* SPP_DMA2_TCDn Word3 - slast */ 15161 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */ 15162 /* SPP_DMA2_TCDn Word4 - daddr */ 15163 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */ 15164 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15165 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */ 15166 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15167 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */ 15168 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15169 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */ 15170 /* SPP_DMA2_TCDn Word0 - Source Address */ 15171 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */ 15172 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15173 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */ 15174 /* SPP_DMA2_TCDn Word2 - nbytes */ 15175 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */ 15176 /* SPP_DMA2_TCDn Word3 - slast */ 15177 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */ 15178 /* SPP_DMA2_TCDn Word4 - daddr */ 15179 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */ 15180 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15181 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */ 15182 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15183 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */ 15184 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15185 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */ 15186 /* SPP_DMA2_TCDn Word0 - Source Address */ 15187 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */ 15188 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15189 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */ 15190 /* SPP_DMA2_TCDn Word2 - nbytes */ 15191 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */ 15192 /* SPP_DMA2_TCDn Word3 - slast */ 15193 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */ 15194 /* SPP_DMA2_TCDn Word4 - daddr */ 15195 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */ 15196 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15197 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */ 15198 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15199 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */ 15200 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15201 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */ 15202 /* SPP_DMA2_TCDn Word0 - Source Address */ 15203 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */ 15204 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15205 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */ 15206 /* SPP_DMA2_TCDn Word2 - nbytes */ 15207 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */ 15208 /* SPP_DMA2_TCDn Word3 - slast */ 15209 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */ 15210 /* SPP_DMA2_TCDn Word4 - daddr */ 15211 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */ 15212 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15213 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */ 15214 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15215 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */ 15216 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15217 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */ 15218 /* SPP_DMA2_TCDn Word0 - Source Address */ 15219 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */ 15220 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15221 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */ 15222 /* SPP_DMA2_TCDn Word2 - nbytes */ 15223 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */ 15224 /* SPP_DMA2_TCDn Word3 - slast */ 15225 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */ 15226 /* SPP_DMA2_TCDn Word4 - daddr */ 15227 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */ 15228 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15229 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */ 15230 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15231 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */ 15232 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15233 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */ 15234 /* SPP_DMA2_TCDn Word0 - Source Address */ 15235 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */ 15236 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15237 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */ 15238 /* SPP_DMA2_TCDn Word2 - nbytes */ 15239 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */ 15240 /* SPP_DMA2_TCDn Word3 - slast */ 15241 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */ 15242 /* SPP_DMA2_TCDn Word4 - daddr */ 15243 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */ 15244 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15245 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */ 15246 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15247 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */ 15248 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15249 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */ 15250 /* SPP_DMA2_TCDn Word0 - Source Address */ 15251 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */ 15252 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15253 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */ 15254 /* SPP_DMA2_TCDn Word2 - nbytes */ 15255 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */ 15256 /* SPP_DMA2_TCDn Word3 - slast */ 15257 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */ 15258 /* SPP_DMA2_TCDn Word4 - daddr */ 15259 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */ 15260 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15261 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */ 15262 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15263 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */ 15264 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15265 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */ 15266 /* SPP_DMA2_TCDn Word0 - Source Address */ 15267 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */ 15268 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15269 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */ 15270 /* SPP_DMA2_TCDn Word2 - nbytes */ 15271 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */ 15272 /* SPP_DMA2_TCDn Word3 - slast */ 15273 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */ 15274 /* SPP_DMA2_TCDn Word4 - daddr */ 15275 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */ 15276 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15277 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */ 15278 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15279 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */ 15280 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15281 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */ 15282 /* SPP_DMA2_TCDn Word0 - Source Address */ 15283 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */ 15284 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15285 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */ 15286 /* SPP_DMA2_TCDn Word2 - nbytes */ 15287 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */ 15288 /* SPP_DMA2_TCDn Word3 - slast */ 15289 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */ 15290 /* SPP_DMA2_TCDn Word4 - daddr */ 15291 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */ 15292 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15293 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */ 15294 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15295 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */ 15296 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15297 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */ 15298 /* SPP_DMA2_TCDn Word0 - Source Address */ 15299 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */ 15300 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15301 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */ 15302 /* SPP_DMA2_TCDn Word2 - nbytes */ 15303 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */ 15304 /* SPP_DMA2_TCDn Word3 - slast */ 15305 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */ 15306 /* SPP_DMA2_TCDn Word4 - daddr */ 15307 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */ 15308 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15309 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */ 15310 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15311 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */ 15312 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15313 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */ 15314 /* SPP_DMA2_TCDn Word0 - Source Address */ 15315 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */ 15316 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15317 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */ 15318 /* SPP_DMA2_TCDn Word2 - nbytes */ 15319 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */ 15320 /* SPP_DMA2_TCDn Word3 - slast */ 15321 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */ 15322 /* SPP_DMA2_TCDn Word4 - daddr */ 15323 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */ 15324 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15325 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */ 15326 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15327 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */ 15328 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15329 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */ 15330 /* SPP_DMA2_TCDn Word0 - Source Address */ 15331 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */ 15332 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15333 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */ 15334 /* SPP_DMA2_TCDn Word2 - nbytes */ 15335 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */ 15336 /* SPP_DMA2_TCDn Word3 - slast */ 15337 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */ 15338 /* SPP_DMA2_TCDn Word4 - daddr */ 15339 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */ 15340 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15341 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */ 15342 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15343 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */ 15344 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15345 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */ 15346 /* SPP_DMA2_TCDn Word0 - Source Address */ 15347 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */ 15348 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15349 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */ 15350 /* SPP_DMA2_TCDn Word2 - nbytes */ 15351 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */ 15352 /* SPP_DMA2_TCDn Word3 - slast */ 15353 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */ 15354 /* SPP_DMA2_TCDn Word4 - daddr */ 15355 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */ 15356 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15357 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */ 15358 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15359 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */ 15360 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15361 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */ 15362 /* SPP_DMA2_TCDn Word0 - Source Address */ 15363 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */ 15364 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15365 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */ 15366 /* SPP_DMA2_TCDn Word2 - nbytes */ 15367 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */ 15368 /* SPP_DMA2_TCDn Word3 - slast */ 15369 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */ 15370 /* SPP_DMA2_TCDn Word4 - daddr */ 15371 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */ 15372 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15373 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */ 15374 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15375 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */ 15376 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15377 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */ 15378 /* SPP_DMA2_TCDn Word0 - Source Address */ 15379 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */ 15380 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15381 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */ 15382 /* SPP_DMA2_TCDn Word2 - nbytes */ 15383 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */ 15384 /* SPP_DMA2_TCDn Word3 - slast */ 15385 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */ 15386 /* SPP_DMA2_TCDn Word4 - daddr */ 15387 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */ 15388 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15389 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */ 15390 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15391 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */ 15392 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15393 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */ 15394 /* SPP_DMA2_TCDn Word0 - Source Address */ 15395 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */ 15396 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15397 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */ 15398 /* SPP_DMA2_TCDn Word2 - nbytes */ 15399 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */ 15400 /* SPP_DMA2_TCDn Word3 - slast */ 15401 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */ 15402 /* SPP_DMA2_TCDn Word4 - daddr */ 15403 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */ 15404 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15405 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */ 15406 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15407 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */ 15408 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15409 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */ 15410 /* SPP_DMA2_TCDn Word0 - Source Address */ 15411 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */ 15412 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15413 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */ 15414 /* SPP_DMA2_TCDn Word2 - nbytes */ 15415 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */ 15416 /* SPP_DMA2_TCDn Word3 - slast */ 15417 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */ 15418 /* SPP_DMA2_TCDn Word4 - daddr */ 15419 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */ 15420 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15421 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */ 15422 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15423 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */ 15424 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15425 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */ 15426 /* SPP_DMA2_TCDn Word0 - Source Address */ 15427 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */ 15428 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15429 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */ 15430 /* SPP_DMA2_TCDn Word2 - nbytes */ 15431 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */ 15432 /* SPP_DMA2_TCDn Word3 - slast */ 15433 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */ 15434 /* SPP_DMA2_TCDn Word4 - daddr */ 15435 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */ 15436 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15437 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */ 15438 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15439 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */ 15440 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15441 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */ 15442 /* SPP_DMA2_TCDn Word0 - Source Address */ 15443 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */ 15444 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15445 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */ 15446 /* SPP_DMA2_TCDn Word2 - nbytes */ 15447 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */ 15448 /* SPP_DMA2_TCDn Word3 - slast */ 15449 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */ 15450 /* SPP_DMA2_TCDn Word4 - daddr */ 15451 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */ 15452 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15453 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */ 15454 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15455 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */ 15456 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15457 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */ 15458 /* SPP_DMA2_TCDn Word0 - Source Address */ 15459 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */ 15460 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15461 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */ 15462 /* SPP_DMA2_TCDn Word2 - nbytes */ 15463 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */ 15464 /* SPP_DMA2_TCDn Word3 - slast */ 15465 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */ 15466 /* SPP_DMA2_TCDn Word4 - daddr */ 15467 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */ 15468 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15469 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */ 15470 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15471 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */ 15472 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15473 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */ 15474 /* SPP_DMA2_TCDn Word0 - Source Address */ 15475 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */ 15476 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15477 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */ 15478 /* SPP_DMA2_TCDn Word2 - nbytes */ 15479 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */ 15480 /* SPP_DMA2_TCDn Word3 - slast */ 15481 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */ 15482 /* SPP_DMA2_TCDn Word4 - daddr */ 15483 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */ 15484 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15485 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */ 15486 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15487 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */ 15488 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15489 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */ 15490 /* SPP_DMA2_TCDn Word0 - Source Address */ 15491 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */ 15492 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15493 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */ 15494 /* SPP_DMA2_TCDn Word2 - nbytes */ 15495 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */ 15496 /* SPP_DMA2_TCDn Word3 - slast */ 15497 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */ 15498 /* SPP_DMA2_TCDn Word4 - daddr */ 15499 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */ 15500 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15501 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */ 15502 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15503 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */ 15504 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15505 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */ 15506 /* SPP_DMA2_TCDn Word0 - Source Address */ 15507 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */ 15508 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15509 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */ 15510 /* SPP_DMA2_TCDn Word2 - nbytes */ 15511 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */ 15512 /* SPP_DMA2_TCDn Word3 - slast */ 15513 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */ 15514 /* SPP_DMA2_TCDn Word4 - daddr */ 15515 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */ 15516 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15517 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */ 15518 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15519 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */ 15520 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15521 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */ 15522 /* SPP_DMA2_TCDn Word0 - Source Address */ 15523 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */ 15524 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15525 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */ 15526 /* SPP_DMA2_TCDn Word2 - nbytes */ 15527 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */ 15528 /* SPP_DMA2_TCDn Word3 - slast */ 15529 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */ 15530 /* SPP_DMA2_TCDn Word4 - daddr */ 15531 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */ 15532 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15533 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */ 15534 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15535 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */ 15536 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15537 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */ 15538 /* SPP_DMA2_TCDn Word0 - Source Address */ 15539 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */ 15540 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15541 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */ 15542 /* SPP_DMA2_TCDn Word2 - nbytes */ 15543 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */ 15544 /* SPP_DMA2_TCDn Word3 - slast */ 15545 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */ 15546 /* SPP_DMA2_TCDn Word4 - daddr */ 15547 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */ 15548 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15549 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */ 15550 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15551 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */ 15552 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15553 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */ 15554 /* SPP_DMA2_TCDn Word0 - Source Address */ 15555 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */ 15556 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15557 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */ 15558 /* SPP_DMA2_TCDn Word2 - nbytes */ 15559 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */ 15560 /* SPP_DMA2_TCDn Word3 - slast */ 15561 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */ 15562 /* SPP_DMA2_TCDn Word4 - daddr */ 15563 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */ 15564 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15565 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */ 15566 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15567 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */ 15568 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15569 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */ 15570 /* SPP_DMA2_TCDn Word0 - Source Address */ 15571 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */ 15572 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15573 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */ 15574 /* SPP_DMA2_TCDn Word2 - nbytes */ 15575 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */ 15576 /* SPP_DMA2_TCDn Word3 - slast */ 15577 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */ 15578 /* SPP_DMA2_TCDn Word4 - daddr */ 15579 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */ 15580 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15581 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */ 15582 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15583 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */ 15584 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15585 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */ 15586 /* SPP_DMA2_TCDn Word0 - Source Address */ 15587 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */ 15588 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15589 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */ 15590 /* SPP_DMA2_TCDn Word2 - nbytes */ 15591 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */ 15592 /* SPP_DMA2_TCDn Word3 - slast */ 15593 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */ 15594 /* SPP_DMA2_TCDn Word4 - daddr */ 15595 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */ 15596 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15597 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */ 15598 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15599 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */ 15600 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15601 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */ 15602 /* SPP_DMA2_TCDn Word0 - Source Address */ 15603 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */ 15604 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15605 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */ 15606 /* SPP_DMA2_TCDn Word2 - nbytes */ 15607 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */ 15608 /* SPP_DMA2_TCDn Word3 - slast */ 15609 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */ 15610 /* SPP_DMA2_TCDn Word4 - daddr */ 15611 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */ 15612 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15613 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */ 15614 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15615 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */ 15616 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15617 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */ 15618 /* SPP_DMA2_TCDn Word0 - Source Address */ 15619 SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */ 15620 /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ 15621 SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */ 15622 /* SPP_DMA2_TCDn Word2 - nbytes */ 15623 SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */ 15624 /* SPP_DMA2_TCDn Word3 - slast */ 15625 SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */ 15626 /* SPP_DMA2_TCDn Word4 - daddr */ 15627 SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */ 15628 /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ 15629 SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */ 15630 /* SPP_DMA2_TCDn Word6 - dlast_sga */ 15631 SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */ 15632 /* SPP_DMA2_TCDn Word7 - biter, etc. */ 15633 SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */ 15634 }; 15635 15636 }; 15637 } SPP_DMA2_tag; 15638 15639 15640 #define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL) 15641 15642 15643 15644 /****************************************************************/ 15645 /* */ 15646 /* Module: INTC */ 15647 /* */ 15648 /****************************************************************/ 15649 15650 typedef union { /* BCR - Block Configuration Register */ 15651 uint32_t R; 15652 struct { 15653 uint32_t:18; 15654 uint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */ 15655 uint32_t:4; 15656 uint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */ 15657 uint32_t:2; 15658 #ifndef USE_FIELD_ALIASES_INTC 15659 uint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */ 15660 #else 15661 uint32_t VTES:1; /* deprecated name - please avoid */ 15662 #endif 15663 uint32_t:4; 15664 #ifndef USE_FIELD_ALIASES_INTC 15665 uint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */ 15666 #else 15667 uint32_t HVEN:1; /* deprecated name - please avoid */ 15668 #endif 15669 } B; 15670 } INTC_BCR_32B_tag; 15671 15672 typedef union { /* CPR - Current Priority Register - Processor 0 */ 15673 uint32_t R; 15674 struct { 15675 uint32_t:28; 15676 uint32_t PRI:4; /* Priority Bits */ 15677 } B; 15678 } INTC_CPR_PRC0_32B_tag; 15679 15680 typedef union { /* CPR - Current Priority Register - Processor 1 */ 15681 uint32_t R; 15682 struct { 15683 uint32_t:28; 15684 uint32_t PRI:4; /* Priority Bits */ 15685 } B; 15686 } INTC_CPR_PRC1_32B_tag; 15687 15688 typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */ 15689 uint32_t R; 15690 struct { 15691 #ifndef USE_FIELD_ALIASES_INTC 15692 uint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */ 15693 #else 15694 uint32_t VTBA:21; /* deprecated name - please avoid */ 15695 #endif 15696 #ifndef USE_FIELD_ALIASES_INTC 15697 uint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */ 15698 #else 15699 uint32_t INTVEC:9; /* deprecated name - please avoid */ 15700 #endif 15701 uint32_t:2; 15702 } B; 15703 } INTC_IACKR_PRC0_32B_tag; 15704 15705 typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */ 15706 uint32_t R; 15707 struct { 15708 uint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */ 15709 uint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */ 15710 uint32_t:2; 15711 } B; 15712 } INTC_IACKR_PRC1_32B_tag; 15713 15714 typedef union { /* EOIR- End of Interrupt Register - Processor 0 */ 15715 uint32_t R; 15716 } INTC_EOIR_PRC0_32B_tag; 15717 15718 typedef union { /* EOIR- End of Interrupt Register - Processor 1 */ 15719 uint32_t R; 15720 } INTC_EOIR_PRC1_32B_tag; 15721 15722 15723 /* Register layout for all registers SSCIR... */ 15724 15725 typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ 15726 uint8_t R; 15727 struct { 15728 uint8_t:6; 15729 uint8_t SET:1; /* Set Flag bit */ 15730 uint8_t CLR:1; /* Clear Flag bit */ 15731 } B; 15732 } INTC_SSCIR_8B_tag; 15733 15734 typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ 15735 uint32_t R; 15736 struct { 15737 uint32_t:6; 15738 uint32_t SET0:1; /* Set Flag 0 bit */ 15739 uint32_t CLR0:1; /* Clear Flag 0 bit */ 15740 uint32_t:6; 15741 uint32_t SET1:1; /* Set Flag 1 bit */ 15742 uint32_t CLR1:1; /* Clear Flag 1 bit */ 15743 uint32_t:6; 15744 uint32_t SET2:1; /* Set Flag 2 bit */ 15745 uint32_t CLR2:1; /* Clear Flag 2 bit */ 15746 uint32_t:6; 15747 uint32_t SET3:1; /* Set Flag 3 bit */ 15748 uint32_t CLR3:1; /* Clear Flag 3 bit */ 15749 } B; 15750 } INTC_SSCIR0_3_32B_tag; 15751 15752 typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ 15753 uint32_t R; 15754 struct { 15755 uint32_t:6; 15756 uint32_t SET4:1; /* Set Flag 4 bit */ 15757 uint32_t CLR4:1; /* Clear Flag 4 bit */ 15758 uint32_t:6; 15759 uint32_t SET5:1; /* Set Flag 5 bit */ 15760 uint32_t CLR5:1; /* Clear Flag 5 bit */ 15761 uint32_t:6; 15762 uint32_t SET6:1; /* Set Flag 6 bit */ 15763 uint32_t CLR6:1; /* Clear Flag 6 bit */ 15764 uint32_t:6; 15765 uint32_t SET7:1; /* Set Flag 7 bit */ 15766 uint32_t CLR7:1; /* Clear Flag 7 bit */ 15767 } B; 15768 } INTC_SSCIR4_7_32B_tag; 15769 15770 15771 /* Register layout for all registers PSR... */ 15772 15773 typedef union { /* PSR0-511 - Priority Select Registers */ 15774 uint8_t R; 15775 struct { 15776 uint8_t PRC_SEL:2; /* Processor Select */ 15777 uint8_t:2; 15778 uint8_t PRI:4; /* Priority Select */ 15779 } B; 15780 } INTC_PSR_8B_tag; 15781 15782 15783 /* Register layout for all registers PSR... */ 15784 15785 typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */ 15786 uint32_t R; 15787 struct { 15788 uint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */ 15789 uint32_t:2; 15790 uint32_t PRI0:4; /* Priority Select - Entry 0 */ 15791 uint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */ 15792 uint32_t:2; 15793 uint32_t PRI1:4; /* Priority Select - Entry 1 */ 15794 uint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */ 15795 uint32_t:2; 15796 uint32_t PRI2:4; /* Priority Select - Entry 2 */ 15797 uint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */ 15798 uint32_t:2; 15799 uint32_t PRI3:4; /* Priority Select - Entry 3 */ 15800 } B; 15801 } INTC_PSR_32B_tag; 15802 15803 15804 15805 typedef struct INTC_struct_tag { /* start of INTC_tag */ 15806 union { 15807 INTC_BCR_32B_tag MCR; /* deprecated - please avoid */ 15808 15809 /* BCR - Block Configuration Register */ 15810 INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */ 15811 15812 }; 15813 int8_t INTC_reserved_0004_C[4]; 15814 union { 15815 /* CPR - Current Priority Register - Processor 0 */ 15816 INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */ 15817 15818 INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */ 15819 15820 }; 15821 /* CPR - Current Priority Register - Processor 1 */ 15822 INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */ 15823 union { 15824 /* IACKR- Interrupt Acknowledge Register - Processor 0 */ 15825 INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */ 15826 15827 INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */ 15828 15829 }; 15830 /* IACKR- Interrupt Acknowledge Register - Processor 1 */ 15831 INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */ 15832 union { 15833 /* EOIR- End of Interrupt Register - Processor 0 */ 15834 INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */ 15835 15836 INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */ 15837 15838 }; 15839 /* EOIR- End of Interrupt Register - Processor 1 */ 15840 INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */ 15841 union { 15842 /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ 15843 INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */ 15844 15845 struct { 15846 /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ 15847 INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */ 15848 INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */ 15849 INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */ 15850 INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */ 15851 INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */ 15852 INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */ 15853 INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */ 15854 INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */ 15855 }; 15856 15857 struct { 15858 /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ 15859 INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */ 15860 /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ 15861 INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */ 15862 }; 15863 15864 }; 15865 int8_t INTC_reserved_0028_C[24]; 15866 union { 15867 /* PSR0_3 - 508_511 - Priority Select Registers */ 15868 INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */ 15869 15870 /* PSR0-511 - Priority Select Registers */ 15871 INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */ 15872 15873 struct { 15874 /* PSR0_3 - 508_511 - Priority Select Registers */ 15875 INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */ 15876 INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */ 15877 INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */ 15878 INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */ 15879 INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */ 15880 INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */ 15881 INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */ 15882 INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */ 15883 INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */ 15884 INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */ 15885 INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */ 15886 INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */ 15887 INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */ 15888 INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */ 15889 INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */ 15890 INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */ 15891 INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */ 15892 INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */ 15893 INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */ 15894 INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */ 15895 INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */ 15896 INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */ 15897 INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */ 15898 INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */ 15899 INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */ 15900 INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */ 15901 INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */ 15902 INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */ 15903 INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */ 15904 INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */ 15905 INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */ 15906 INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */ 15907 INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */ 15908 INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */ 15909 INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */ 15910 INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */ 15911 INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */ 15912 INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */ 15913 INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */ 15914 INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */ 15915 INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */ 15916 INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */ 15917 INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */ 15918 INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */ 15919 INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */ 15920 INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */ 15921 INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */ 15922 INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */ 15923 INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */ 15924 INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */ 15925 INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */ 15926 INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */ 15927 INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */ 15928 INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */ 15929 INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */ 15930 INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */ 15931 INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */ 15932 INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */ 15933 INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */ 15934 INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */ 15935 INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */ 15936 INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */ 15937 INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */ 15938 INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */ 15939 INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */ 15940 INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */ 15941 INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */ 15942 INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */ 15943 INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */ 15944 INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */ 15945 INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */ 15946 INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */ 15947 INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */ 15948 INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */ 15949 INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */ 15950 INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */ 15951 INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */ 15952 INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */ 15953 INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */ 15954 INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */ 15955 INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */ 15956 INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */ 15957 INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */ 15958 INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */ 15959 INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */ 15960 INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */ 15961 INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */ 15962 INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */ 15963 INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */ 15964 INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */ 15965 INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */ 15966 INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */ 15967 INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */ 15968 INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */ 15969 INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */ 15970 INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */ 15971 INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */ 15972 INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */ 15973 INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */ 15974 INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */ 15975 INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */ 15976 INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */ 15977 INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */ 15978 INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */ 15979 INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */ 15980 INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */ 15981 INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */ 15982 INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */ 15983 INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */ 15984 INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */ 15985 INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */ 15986 INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */ 15987 INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */ 15988 INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */ 15989 INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */ 15990 INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */ 15991 INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */ 15992 INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */ 15993 INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */ 15994 INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */ 15995 INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */ 15996 INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */ 15997 INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */ 15998 INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */ 15999 INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */ 16000 INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */ 16001 INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */ 16002 INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */ 16003 }; 16004 16005 struct { 16006 /* PSR0-511 - Priority Select Registers */ 16007 INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */ 16008 INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */ 16009 INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */ 16010 INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */ 16011 INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */ 16012 INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */ 16013 INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */ 16014 INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */ 16015 INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */ 16016 INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */ 16017 INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */ 16018 INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */ 16019 INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */ 16020 INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */ 16021 INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */ 16022 INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */ 16023 INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */ 16024 INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */ 16025 INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */ 16026 INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */ 16027 INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */ 16028 INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */ 16029 INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */ 16030 INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */ 16031 INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */ 16032 INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */ 16033 INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */ 16034 INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */ 16035 INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */ 16036 INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */ 16037 INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */ 16038 INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */ 16039 INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */ 16040 INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */ 16041 INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */ 16042 INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */ 16043 INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */ 16044 INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */ 16045 INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */ 16046 INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */ 16047 INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */ 16048 INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */ 16049 INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */ 16050 INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */ 16051 INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */ 16052 INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */ 16053 INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */ 16054 INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */ 16055 INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */ 16056 INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */ 16057 INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */ 16058 INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */ 16059 INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */ 16060 INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */ 16061 INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */ 16062 INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */ 16063 INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */ 16064 INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */ 16065 INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */ 16066 INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */ 16067 INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */ 16068 INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */ 16069 INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */ 16070 INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */ 16071 INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */ 16072 INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */ 16073 INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */ 16074 INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */ 16075 INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */ 16076 INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */ 16077 INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */ 16078 INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */ 16079 INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */ 16080 INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */ 16081 INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */ 16082 INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */ 16083 INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */ 16084 INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */ 16085 INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */ 16086 INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */ 16087 INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */ 16088 INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */ 16089 INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */ 16090 INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */ 16091 INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */ 16092 INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */ 16093 INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */ 16094 INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */ 16095 INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */ 16096 INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */ 16097 INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */ 16098 INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */ 16099 INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */ 16100 INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */ 16101 INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */ 16102 INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */ 16103 INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */ 16104 INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */ 16105 INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */ 16106 INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */ 16107 INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */ 16108 INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */ 16109 INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */ 16110 INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */ 16111 INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */ 16112 INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */ 16113 INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */ 16114 INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */ 16115 INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */ 16116 INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */ 16117 INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */ 16118 INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */ 16119 INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */ 16120 INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */ 16121 INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */ 16122 INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */ 16123 INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */ 16124 INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */ 16125 INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */ 16126 INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */ 16127 INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */ 16128 INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */ 16129 INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */ 16130 INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */ 16131 INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */ 16132 INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */ 16133 INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */ 16134 INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */ 16135 INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */ 16136 INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */ 16137 INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */ 16138 INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */ 16139 INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */ 16140 INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */ 16141 INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */ 16142 INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */ 16143 INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */ 16144 INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */ 16145 INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */ 16146 INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */ 16147 INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */ 16148 INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */ 16149 INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */ 16150 INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */ 16151 INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */ 16152 INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */ 16153 INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */ 16154 INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */ 16155 INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */ 16156 INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */ 16157 INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */ 16158 INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */ 16159 INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */ 16160 INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */ 16161 INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */ 16162 INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */ 16163 INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */ 16164 INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */ 16165 INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */ 16166 INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */ 16167 INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */ 16168 INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */ 16169 INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */ 16170 INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */ 16171 INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */ 16172 INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */ 16173 INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */ 16174 INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */ 16175 INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */ 16176 INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */ 16177 INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */ 16178 INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */ 16179 INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */ 16180 INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */ 16181 INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */ 16182 INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */ 16183 INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */ 16184 INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */ 16185 INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */ 16186 INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */ 16187 INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */ 16188 INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */ 16189 INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */ 16190 INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */ 16191 INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */ 16192 INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */ 16193 INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */ 16194 INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */ 16195 INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */ 16196 INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */ 16197 INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */ 16198 INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */ 16199 INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */ 16200 INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */ 16201 INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */ 16202 INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */ 16203 INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */ 16204 INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */ 16205 INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */ 16206 INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */ 16207 INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */ 16208 INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */ 16209 INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */ 16210 INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */ 16211 INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */ 16212 INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */ 16213 INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */ 16214 INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */ 16215 INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */ 16216 INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */ 16217 INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */ 16218 INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */ 16219 INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */ 16220 INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */ 16221 INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */ 16222 INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */ 16223 INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */ 16224 INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */ 16225 INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */ 16226 INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */ 16227 INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */ 16228 INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */ 16229 INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */ 16230 INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */ 16231 INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */ 16232 INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */ 16233 INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */ 16234 INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */ 16235 INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */ 16236 INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */ 16237 INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */ 16238 INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */ 16239 INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */ 16240 INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */ 16241 INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */ 16242 INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */ 16243 INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */ 16244 INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */ 16245 INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */ 16246 INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */ 16247 INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */ 16248 INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */ 16249 INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */ 16250 INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */ 16251 INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */ 16252 INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */ 16253 INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */ 16254 INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */ 16255 INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */ 16256 INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */ 16257 INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */ 16258 INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */ 16259 INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */ 16260 INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */ 16261 INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */ 16262 INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */ 16263 INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */ 16264 INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */ 16265 INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */ 16266 INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */ 16267 INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */ 16268 INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */ 16269 INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */ 16270 INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */ 16271 INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */ 16272 INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */ 16273 INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */ 16274 INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */ 16275 INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */ 16276 INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */ 16277 INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */ 16278 INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */ 16279 INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */ 16280 INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */ 16281 INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */ 16282 INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */ 16283 INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */ 16284 INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */ 16285 INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */ 16286 INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */ 16287 INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */ 16288 INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */ 16289 INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */ 16290 INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */ 16291 INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */ 16292 INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */ 16293 INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */ 16294 INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */ 16295 INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */ 16296 INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */ 16297 INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */ 16298 INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */ 16299 INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */ 16300 INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */ 16301 INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */ 16302 INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */ 16303 INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */ 16304 INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */ 16305 INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */ 16306 INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */ 16307 INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */ 16308 INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */ 16309 INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */ 16310 INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */ 16311 INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */ 16312 INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */ 16313 INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */ 16314 INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */ 16315 INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */ 16316 INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */ 16317 INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */ 16318 INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */ 16319 INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */ 16320 INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */ 16321 INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */ 16322 INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */ 16323 INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */ 16324 INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */ 16325 INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */ 16326 INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */ 16327 INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */ 16328 INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */ 16329 INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */ 16330 INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */ 16331 INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */ 16332 INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */ 16333 INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */ 16334 INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */ 16335 INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */ 16336 INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */ 16337 INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */ 16338 INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */ 16339 INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */ 16340 INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */ 16341 INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */ 16342 INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */ 16343 INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */ 16344 INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */ 16345 INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */ 16346 INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */ 16347 INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */ 16348 INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */ 16349 INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */ 16350 INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */ 16351 INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */ 16352 INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */ 16353 INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */ 16354 INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */ 16355 INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */ 16356 INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */ 16357 INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */ 16358 INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */ 16359 INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */ 16360 INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */ 16361 INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */ 16362 INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */ 16363 INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */ 16364 INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */ 16365 INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */ 16366 INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */ 16367 INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */ 16368 INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */ 16369 INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */ 16370 INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */ 16371 INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */ 16372 INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */ 16373 INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */ 16374 INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */ 16375 INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */ 16376 INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */ 16377 INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */ 16378 INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */ 16379 INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */ 16380 INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */ 16381 INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */ 16382 INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */ 16383 INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */ 16384 INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */ 16385 INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */ 16386 INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */ 16387 INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */ 16388 INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */ 16389 INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */ 16390 INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */ 16391 INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */ 16392 INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */ 16393 INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */ 16394 INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */ 16395 INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */ 16396 INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */ 16397 INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */ 16398 INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */ 16399 INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */ 16400 INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */ 16401 INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */ 16402 INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */ 16403 INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */ 16404 INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */ 16405 INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */ 16406 INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */ 16407 INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */ 16408 INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */ 16409 INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */ 16410 INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */ 16411 INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */ 16412 INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */ 16413 INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */ 16414 INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */ 16415 INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */ 16416 INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */ 16417 INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */ 16418 INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */ 16419 INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */ 16420 INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */ 16421 INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */ 16422 INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */ 16423 INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */ 16424 INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */ 16425 INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */ 16426 INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */ 16427 INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */ 16428 INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */ 16429 INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */ 16430 INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */ 16431 INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */ 16432 INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */ 16433 INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */ 16434 INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */ 16435 INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */ 16436 INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */ 16437 INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */ 16438 INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */ 16439 INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */ 16440 INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */ 16441 INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */ 16442 INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */ 16443 INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */ 16444 INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */ 16445 INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */ 16446 INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */ 16447 INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */ 16448 INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */ 16449 INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */ 16450 INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */ 16451 INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */ 16452 INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */ 16453 INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */ 16454 INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */ 16455 INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */ 16456 INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */ 16457 INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */ 16458 INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */ 16459 INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */ 16460 INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */ 16461 INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */ 16462 INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */ 16463 INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */ 16464 INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */ 16465 INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */ 16466 INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */ 16467 INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */ 16468 INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */ 16469 INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */ 16470 INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */ 16471 INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */ 16472 INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */ 16473 INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */ 16474 INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */ 16475 INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */ 16476 INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */ 16477 INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */ 16478 INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */ 16479 INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */ 16480 INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */ 16481 INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */ 16482 INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */ 16483 INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */ 16484 INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */ 16485 INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */ 16486 INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */ 16487 INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */ 16488 INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */ 16489 INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */ 16490 INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */ 16491 INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */ 16492 INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */ 16493 INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */ 16494 INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */ 16495 INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */ 16496 INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */ 16497 INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */ 16498 INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */ 16499 INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */ 16500 INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */ 16501 INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */ 16502 INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */ 16503 INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */ 16504 INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */ 16505 INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */ 16506 INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */ 16507 INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */ 16508 INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */ 16509 INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */ 16510 INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */ 16511 INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */ 16512 INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */ 16513 INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */ 16514 INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */ 16515 INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */ 16516 INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */ 16517 INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */ 16518 INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */ 16519 }; 16520 16521 }; 16522 } INTC_tag; 16523 16524 16525 #define INTC (*(volatile INTC_tag *) 0xFFF48000UL) 16526 16527 16528 16529 /****************************************************************/ 16530 /* */ 16531 /* Module: DSPI */ 16532 /* */ 16533 /****************************************************************/ 16534 16535 typedef union DSPI_MCR_tag { /* MCR - Module Configuration Register */ 16536 uint32_t R; 16537 struct { 16538 uint32_t MSTR:1; /* Master/Slave mode select */ 16539 uint32_t CONT_SCKE:1; /* Continuous SCK Enable */ 16540 uint32_t DCONF:2; /* DSPI Configuration */ 16541 uint32_t FRZ:1; /* Freeze */ 16542 uint32_t MTFE:1; /* Modified Timing Format Enable */ 16543 uint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */ 16544 uint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */ 16545 uint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */ 16546 uint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */ 16547 uint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */ 16548 uint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */ 16549 uint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */ 16550 uint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */ 16551 uint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */ 16552 uint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */ 16553 uint32_t DOZE:1; /* Doze Enable */ 16554 uint32_t MDIS:1; /* Module Disable */ 16555 uint32_t DIS_TXF:1; /* Disable Transmit FIFO */ 16556 uint32_t DIS_RXF:1; /* Disable Receive FIFO */ 16557 uint32_t CLR_TXF:1; /* Clear TX FIFO */ 16558 uint32_t CLR_RXF:1; /* Clear RX FIFO */ 16559 uint32_t SMPL_PT:2; /* Sample Point */ 16560 uint32_t:7; 16561 uint32_t HALT:1; /* Halt */ 16562 } B; 16563 } DSPI_MCR_32B_tag; 16564 16565 typedef union { /* TCR - Transfer Count Register */ 16566 uint32_t R; 16567 struct { 16568 #ifndef USE_FIELD_ALIASES_DSPI 16569 uint32_t SPI_TCNT:16; /* SPI Transfer Counter */ 16570 #else 16571 uint32_t TCNT:16; /* deprecated name - please avoid */ 16572 #endif 16573 uint32_t:16; 16574 } B; 16575 } DSPI_TCR_32B_tag; 16576 16577 16578 /* Register layout for all registers CTAR... */ 16579 16580 typedef union DSPI_CTAR_tag { /* CTAR0-7 - Clock and Transfer Attribute Registers */ 16581 uint32_t R; 16582 struct { 16583 uint32_t DBR:1; /* Double Baud Rate */ 16584 uint32_t FMSZ:4; /* Frame Size */ 16585 uint32_t CPOL:1; /* Clock Polarity */ 16586 uint32_t CPHA:1; /* Clock Phase */ 16587 uint32_t LSBFE:1; /* LSB First Enable */ 16588 uint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */ 16589 uint32_t PASC:2; /* After SCK Delay Prescaler */ 16590 uint32_t PDT:2; /* Delay after Transfer Prescaler */ 16591 uint32_t PBR:2; /* Baud Rate Prescaler */ 16592 uint32_t CSSCK:4; /* PCS to SCK Delay Scaler */ 16593 uint32_t ASC:4; /* After SCK Delay Scaler */ 16594 uint32_t DT:4; /* Delay after Transfer Scaler */ 16595 uint32_t BR:4; /* Baud Rate Scaler */ 16596 } B; 16597 } DSPI_CTAR_32B_tag; 16598 16599 typedef union DSPI_SR_tag { /* SR - Status Register */ 16600 uint32_t R; 16601 struct { 16602 uint32_t TCF:1; /* Transfer Complete Flag */ 16603 uint32_t TXRXS:1; /* TX & RX Status */ 16604 uint32_t:1; 16605 uint32_t EOQF:1; /* End of queue Flag */ 16606 uint32_t TFUF:1; /* Transmit FIFO Underflow Flag */ 16607 uint32_t:1; 16608 uint32_t TFFF:1; /* Transmit FIFO FIll Flag */ 16609 uint32_t:5; 16610 uint32_t RFOF:1; /* Receive FIFO Overflow Flag */ 16611 uint32_t:1; 16612 uint32_t RFDF:1; /* Receive FIFO Drain Flag */ 16613 uint32_t:1; 16614 uint32_t TXCTR:4; /* TX FIFO Counter */ 16615 uint32_t TXNXTPTR:4; /* Transmit Next Pointer */ 16616 uint32_t RXCTR:4; /* RX FIFO Counter */ 16617 uint32_t POPNXTPTR:4; /* Pop Next Pointer */ 16618 } B; 16619 } DSPI_SR_32B_tag; 16620 16621 typedef union DSPI_RSER_tag { /* RSER - DMA/Interrupt Request Register */ 16622 uint32_t R; 16623 struct { 16624 #ifndef USE_FIELD_ALIASES_DSPI 16625 uint32_t TCF_RE:1; /* Transmission Complete Request Enable */ 16626 #else 16627 uint32_t TCFRE:1; /* deprecated name - please avoid */ 16628 #endif 16629 uint32_t:2; 16630 #ifndef USE_FIELD_ALIASES_DSPI 16631 uint32_t EOQF_RE:1; /* DSPI Finished Request Enable */ 16632 #else 16633 uint32_t EOQFRE:1; /* deprecated name - please avoid */ 16634 #endif 16635 #ifndef USE_FIELD_ALIASES_DSPI 16636 uint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */ 16637 #else 16638 uint32_t TFUFRE:1; /* deprecated name - please avoid */ 16639 #endif 16640 uint32_t:1; 16641 #ifndef USE_FIELD_ALIASES_DSPI 16642 uint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */ 16643 #else 16644 uint32_t TFFFRE:1; /* deprecated name - please avoid */ 16645 #endif 16646 #ifndef USE_FIELD_ALIASES_DSPI 16647 uint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */ 16648 #else 16649 uint32_t TFFFDIRS:1; /* deprecated name - please avoid */ 16650 #endif 16651 uint32_t:4; 16652 #ifndef USE_FIELD_ALIASES_DSPI 16653 uint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */ 16654 #else 16655 uint32_t RFOFRE:1; /* deprecated name - please avoid */ 16656 #endif 16657 uint32_t:1; 16658 #ifndef USE_FIELD_ALIASES_DSPI 16659 uint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */ 16660 #else 16661 uint32_t RFDFRE:1; /* deprecated name - please avoid */ 16662 #endif 16663 #ifndef USE_FIELD_ALIASES_DSPI 16664 uint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */ 16665 #else 16666 uint32_t RFDFDIRS:1; /* deprecated name - please avoid */ 16667 #endif 16668 uint32_t:16; 16669 } B; 16670 } DSPI_RSER_32B_tag; 16671 16672 typedef union DSPI_PUSHR_tag { /* PUSHR - PUSH TX FIFO Register */ 16673 uint32_t R; 16674 struct { 16675 uint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */ 16676 uint32_t CTAS:3; /* Clock and Transfer Attributes Select */ 16677 uint32_t EOQ:1; /* End of Queue */ 16678 uint32_t CTCNT:1; /* Clear SPI_TCNT */ 16679 uint32_t:2; 16680 uint32_t PCS7:1; /* Peripheral Chip Select 7 */ 16681 uint32_t PCS6:1; /* Peripheral Chip Select 6 */ 16682 uint32_t PCS5:1; /* Peripheral Chip Select 5 */ 16683 uint32_t PCS4:1; /* Peripheral Chip Select 4 */ 16684 uint32_t PCS3:1; /* Peripheral Chip Select 3 */ 16685 uint32_t PCS2:1; /* Peripheral Chip Select 2 */ 16686 uint32_t PCS1:1; /* Peripheral Chip Select 1 */ 16687 uint32_t PCS0:1; /* Peripheral Chip Select 0 */ 16688 uint32_t TXDATA:16; /* Transmit Data */ 16689 } B; 16690 } DSPI_PUSHR_32B_tag; 16691 16692 typedef union DSPI_POPR_tag { /* POPR - POP RX FIFO Register */ 16693 uint32_t R; 16694 struct { 16695 uint32_t:16; 16696 uint32_t RXDATA:16; /* Receive Data */ 16697 } B; 16698 } DSPI_POPR_32B_tag; 16699 16700 16701 /* Register layout for all registers TXFR... */ 16702 16703 typedef union { /* Transmit FIFO Registers */ 16704 uint32_t R; 16705 struct { 16706 #ifndef USE_FIELD_ALIASES_DSPI 16707 uint32_t FIFO_TXCMD:16; /* Transmit Command */ 16708 #else 16709 uint32_t TXCMD:16; /* deprecated name - please avoid */ 16710 #endif 16711 #ifndef USE_FIELD_ALIASES_DSPI 16712 uint32_t FIFO_TXDATA:16; /* Transmit Data */ 16713 #else 16714 uint32_t TXDATA:16; /* deprecated name - please avoid */ 16715 #endif 16716 } B; 16717 } DSPI_TXFR_32B_tag; 16718 16719 16720 /* Register layout for all registers RXFR... */ 16721 16722 typedef union { /* Receive FIFO Registers */ 16723 uint32_t R; 16724 struct { 16725 uint32_t:16; 16726 #ifndef USE_FIELD_ALIASES_DSPI 16727 uint32_t FIFO_RXDATA:16; /* Transmit Data */ 16728 #else 16729 uint32_t RXDATA:16; /* deprecated name - please avoid */ 16730 #endif 16731 } B; 16732 } DSPI_RXFR_32B_tag; 16733 16734 typedef union { /* DSICR - DSI Configuration Register */ 16735 uint32_t R; 16736 struct { 16737 uint32_t MTOE:1; /* Multiple Transfer Operation Enable */ 16738 uint32_t:1; 16739 uint32_t MTOCNT:6; /* Multiple Transfer Operation Count */ 16740 uint32_t:4; 16741 uint32_t TXSS:1; /* Transmit Data Source Select */ 16742 uint32_t TPOL:1; /* Trigger Polarity */ 16743 uint32_t TRRE:1; /* Trigger Reception Enable */ 16744 uint32_t CID:1; /* Change in Data Transfer Enable */ 16745 uint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */ 16746 uint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */ 16747 uint32_t:4; 16748 uint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */ 16749 uint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */ 16750 uint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */ 16751 uint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */ 16752 uint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */ 16753 uint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */ 16754 uint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */ 16755 uint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */ 16756 } B; 16757 } DSPI_DSICR_32B_tag; 16758 16759 typedef union { /* SDR - DSI Serialization Data Register */ 16760 uint32_t R; 16761 struct { 16762 uint32_t:16; 16763 uint32_t SER_DATA:16; /* Serialized Data */ 16764 } B; 16765 } DSPI_SDR_32B_tag; 16766 16767 typedef union { /* ASDR - DSI Alternate Serialization Data Register */ 16768 uint32_t R; 16769 struct { 16770 uint32_t:16; 16771 uint32_t ASER_DATA:16; /* Alternate Serialized Data */ 16772 } B; 16773 } DSPI_ASDR_32B_tag; 16774 16775 typedef union { /* COMPR - DSI Transmit Comparison Register */ 16776 uint32_t R; 16777 struct { 16778 uint32_t:16; 16779 uint32_t COMP_DATA:16; /* Compare Data */ 16780 } B; 16781 } DSPI_COMPR_32B_tag; 16782 16783 typedef union { /* DDR - DSI Deserialization Data Register */ 16784 uint32_t R; 16785 struct { 16786 uint32_t:16; 16787 uint32_t DESER_DATA:16; /* Deserialized Data */ 16788 } B; 16789 } DSPI_DDR_32B_tag; 16790 16791 typedef union { /* DSICR1 - DSI Configuration Register 1 */ 16792 uint32_t R; 16793 } DSPI_DSICR1_32B_tag; 16794 16795 16796 16797 typedef struct DSPI_tag { /* start of DSPI_tag */ 16798 /* MCR - Module Configuration Register */ 16799 DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ 16800 int8_t DSPI_reserved_0004[4]; 16801 /* TCR - Transfer Count Register */ 16802 DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */ 16803 union { 16804 /* CTAR0-7 - Clock and Transfer Attribute Registers */ 16805 DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */ 16806 16807 struct { 16808 /* CTAR0-7 - Clock and Transfer Attribute Registers */ 16809 DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */ 16810 DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */ 16811 DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */ 16812 DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */ 16813 DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */ 16814 DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */ 16815 DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */ 16816 DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */ 16817 }; 16818 16819 }; 16820 /* SR - Status Register */ 16821 DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */ 16822 /* RSER - DMA/Interrupt Request Register */ 16823 DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */ 16824 /* PUSHR - PUSH TX FIFO Register */ 16825 DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */ 16826 /* POPR - POP RX FIFO Register */ 16827 DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */ 16828 union { 16829 /* Transmit FIFO Registers */ 16830 DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */ 16831 16832 struct { 16833 /* Transmit FIFO Registers */ 16834 DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */ 16835 DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */ 16836 DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */ 16837 DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */ 16838 DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */ 16839 }; 16840 16841 }; 16842 int8_t DSPI_reserved_0050_C[44]; 16843 union { 16844 /* Receive FIFO Registers */ 16845 DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */ 16846 16847 struct { 16848 /* Receive FIFO Registers */ 16849 DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */ 16850 DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */ 16851 DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */ 16852 DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */ 16853 DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */ 16854 }; 16855 16856 }; 16857 int8_t DSPI_reserved_0090[44]; 16858 /* DSICR - DSI Configuration Register */ 16859 DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */ 16860 /* SDR - DSI Serialization Data Register */ 16861 DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */ 16862 /* ASDR - DSI Alternate Serialization Data Register */ 16863 DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */ 16864 /* COMPR - DSI Transmit Comparison Register */ 16865 DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */ 16866 /* DDR - DSI Deserialization Data Register */ 16867 DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */ 16868 /* DSICR1 - DSI Configuration Register 1 */ 16869 DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */ 16870 } DSPI_tag; 16871 16872 16873 #define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL) 16874 #define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL) 16875 #define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL) 16876 16877 16878 16879 /****************************************************************/ 16880 /* */ 16881 /* Module: FLEXCAN */ 16882 /* */ 16883 /****************************************************************/ 16884 16885 typedef union { /* MCR - Module Configuration Register */ 16886 uint32_t R; 16887 struct { 16888 uint32_t MDIS:1; /* Module Disable */ 16889 uint32_t FRZ:1; /* Freeze Enable */ 16890 uint32_t FEN:1; /* FIFO Enable */ 16891 uint32_t HALT:1; /* Halt Flexcan */ 16892 #ifndef USE_FIELD_ALIASES_FLEXCAN 16893 uint32_t NOT_RDY:1; /* Flexcan Not Ready */ 16894 #else 16895 uint32_t NOTRDY:1; /* deprecated name - please avoid */ 16896 #endif 16897 #ifndef USE_FIELD_ALIASES_FLEXCAN 16898 uint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */ 16899 #else 16900 uint32_t WAKMSK:1; /* deprecated name - please avoid */ 16901 #endif 16902 #ifndef USE_FIELD_ALIASES_FLEXCAN 16903 uint32_t SOFT_RST:1; /* Soft Reset */ 16904 #else 16905 uint32_t SOFTRST:1; /* deprecated name - please avoid */ 16906 #endif 16907 #ifndef USE_FIELD_ALIASES_FLEXCAN 16908 uint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */ 16909 #else 16910 uint32_t FRZACK:1; /* deprecated name - please avoid */ 16911 #endif 16912 uint32_t SUPV:1; /* Supervisor Mode */ 16913 #ifndef USE_FIELD_ALIASES_FLEXCAN 16914 uint32_t SLF_WAK:1; /* Self Wake Up */ 16915 #else 16916 uint32_t SLFWAK:1; /* deprecated name - please avoid */ 16917 #endif 16918 #ifndef USE_FIELD_ALIASES_FLEXCAN 16919 uint32_t WRN_EN:1; /* Warning Interrupt Enable */ 16920 #else 16921 uint32_t WRNEN:1; /* deprecated name - please avoid */ 16922 #endif 16923 #ifndef USE_FIELD_ALIASES_FLEXCAN 16924 uint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */ 16925 #else 16926 uint32_t LPMACK:1; /* deprecated name - please avoid */ 16927 #endif 16928 #ifndef USE_FIELD_ALIASES_FLEXCAN 16929 uint32_t WAK_SRC:1; /* Wake Up Source */ 16930 #else 16931 uint32_t WAKSRC:1; /* deprecated name - please avoid */ 16932 #endif 16933 uint32_t DOZE:1; /* Doze Mode Enable */ 16934 #ifndef USE_FIELD_ALIASES_FLEXCAN 16935 uint32_t SRX_DIS:1; /* Self Reception Disable */ 16936 #else 16937 uint32_t SRXDIS:1; /* deprecated name - please avoid */ 16938 #endif 16939 uint32_t BCC:1; /* Backwards Compatibility Configuration */ 16940 uint32_t:2; 16941 uint32_t LPRIO_EN:1; /* Local Priority Enable */ 16942 uint32_t AEN:1; /* Abort Enable */ 16943 uint32_t:2; 16944 uint32_t IDAM:2; /* ID Acceptance Mode */ 16945 uint32_t:2; 16946 uint32_t MAXMB:6; /* Maximum Number of Message Buffers */ 16947 } B; 16948 } FLEXCAN_MCR_32B_tag; 16949 16950 typedef union { /* CTRL - Control Register */ 16951 uint32_t R; 16952 struct { 16953 uint32_t PRESDIV:8; /* Prescaler Divsion Factor */ 16954 uint32_t RJW:2; /* Resync Jump Width */ 16955 uint32_t PSEG1:3; /* Phase Segment 1 */ 16956 uint32_t PSEG2:3; /* Phase Segment 2 */ 16957 #ifndef USE_FIELD_ALIASES_FLEXCAN 16958 uint32_t BOFF_MSK:1; /* Bus Off Mask */ 16959 #else 16960 uint32_t BOFFMSK:1; /* deprecated name - please avoid */ 16961 #endif 16962 #ifndef USE_FIELD_ALIASES_FLEXCAN 16963 uint32_t ERR_MSK:1; /* Error Mask */ 16964 #else 16965 uint32_t ERRMSK:1; /* deprecated name - please avoid */ 16966 #endif 16967 #ifndef USE_FIELD_ALIASES_FLEXCAN 16968 uint32_t CLK_SRC:1; /* CAN Engine Clock Source */ 16969 #else 16970 uint32_t CLKSRC:1; /* deprecated name - please avoid */ 16971 #endif 16972 uint32_t LPB:1; /* Loop Back */ 16973 #ifndef USE_FIELD_ALIASES_FLEXCAN 16974 uint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */ 16975 #else 16976 uint32_t TWRNMSK:1; /* deprecated name - please avoid */ 16977 #endif 16978 #ifndef USE_FIELD_ALIASES_FLEXCAN 16979 uint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */ 16980 #else 16981 uint32_t RWRNMSK:1; /* deprecated name - please avoid */ 16982 #endif 16983 uint32_t:2; 16984 uint32_t SMP:1; /* Sampling Mode */ 16985 #ifndef USE_FIELD_ALIASES_FLEXCAN 16986 uint32_t BOFF_REC:1; /* Bus Off Recovery Mode */ 16987 #else 16988 uint32_t BOFFREC:1; /* deprecated name - please avoid */ 16989 #endif 16990 uint32_t TSYN:1; /* Timer Sync Mode */ 16991 uint32_t LBUF:1; /* Lowest Buffer Transmitted First */ 16992 uint32_t LOM:1; /* Listen-Only Mode */ 16993 uint32_t PROPSEG:3; /* Propagation Segment */ 16994 } B; 16995 } FLEXCAN_CTRL_32B_tag; 16996 16997 typedef union { /* TIMER - Free Running Timer */ 16998 uint32_t R; 16999 } FLEXCAN_TIMER_32B_tag; 17000 17001 typedef union { /* RXGMASK - Rx Global Mask Register */ 17002 uint32_t R; 17003 #ifndef USE_FIELD_ALIASES_FLEXCAN 17004 struct { 17005 uint32_t MI:32; /* deprecated field -- do not use */ 17006 } B; 17007 #endif 17008 } FLEXCAN_RXGMASK_32B_tag; 17009 17010 typedef union { /* RX14MASK - Rx 14 Mask Register */ 17011 uint32_t R; 17012 #ifndef USE_FIELD_ALIASES_FLEXCAN 17013 struct { 17014 uint32_t MI:32; /* deprecated field -- do not use */ 17015 } B; 17016 #endif 17017 } FLEXCAN_RX14MASK_32B_tag; 17018 17019 typedef union { /* RX15MASK - Rx 15 Mask Register */ 17020 uint32_t R; 17021 #ifndef USE_FIELD_ALIASES_FLEXCAN 17022 struct { 17023 uint32_t MI:32; /* deprecated field -- do not use */ 17024 } B; 17025 #endif 17026 } FLEXCAN_RX15MASK_32B_tag; 17027 17028 typedef union { /* ECR - Error Counter Register */ 17029 uint32_t R; 17030 struct { 17031 uint32_t:16; 17032 #ifndef USE_FIELD_ALIASES_FLEXCAN 17033 uint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */ 17034 #else 17035 uint32_t RXECNT:8; /* deprecated name - please avoid */ 17036 #endif 17037 #ifndef USE_FIELD_ALIASES_FLEXCAN 17038 uint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */ 17039 #else 17040 uint32_t TXECNT:8; /* deprecated name - please avoid */ 17041 #endif 17042 } B; 17043 } FLEXCAN_ECR_32B_tag; 17044 17045 typedef union { /* ESR - Error and Status Register */ 17046 uint32_t R; 17047 struct { 17048 uint32_t:14; 17049 #ifndef USE_FIELD_ALIASES_FLEXCAN 17050 uint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */ 17051 #else 17052 uint32_t TWRNINT:1; /* deprecated name - please avoid */ 17053 #endif 17054 #ifndef USE_FIELD_ALIASES_FLEXCAN 17055 uint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */ 17056 #else 17057 uint32_t RWRNINT:1; /* deprecated name - please avoid */ 17058 #endif 17059 #ifndef USE_FIELD_ALIASES_FLEXCAN 17060 uint32_t BIT1_ERR:1; /* Bit 1 Error */ 17061 #else 17062 uint32_t BIT1ERR:1; /* deprecated name - please avoid */ 17063 #endif 17064 #ifndef USE_FIELD_ALIASES_FLEXCAN 17065 uint32_t BIT0_ERR:1; /* Bit 0 Error */ 17066 #else 17067 uint32_t BIT0ERR:1; /* deprecated name - please avoid */ 17068 #endif 17069 #ifndef USE_FIELD_ALIASES_FLEXCAN 17070 uint32_t ACK_ERR:1; /* Acknowledge Error */ 17071 #else 17072 uint32_t ACKERR:1; /* deprecated name - please avoid */ 17073 #endif 17074 #ifndef USE_FIELD_ALIASES_FLEXCAN 17075 uint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */ 17076 #else 17077 uint32_t CRCERR:1; /* deprecated name - please avoid */ 17078 #endif 17079 #ifndef USE_FIELD_ALIASES_FLEXCAN 17080 uint32_t FRM_ERR:1; /* Form Error */ 17081 #else 17082 uint32_t FRMERR:1; /* deprecated name - please avoid */ 17083 #endif 17084 #ifndef USE_FIELD_ALIASES_FLEXCAN 17085 uint32_t STF_ERR:1; /* Stuffing Error */ 17086 #else 17087 uint32_t STFERR:1; /* deprecated name - please avoid */ 17088 #endif 17089 #ifndef USE_FIELD_ALIASES_FLEXCAN 17090 uint32_t TX_WRN:1; /* Tx Error Counter */ 17091 #else 17092 uint32_t TXWRN:1; /* deprecated name - please avoid */ 17093 #endif 17094 #ifndef USE_FIELD_ALIASES_FLEXCAN 17095 uint32_t RX_WRN:1; /* Rx Error Counter */ 17096 #else 17097 uint32_t RXWRN:1; /* deprecated name - please avoid */ 17098 #endif 17099 uint32_t IDLE:1; /* CAN bus Idle State */ 17100 uint32_t TXRX:1; /* Current Flexcan Status */ 17101 #ifndef USE_FIELD_ALIASES_FLEXCAN 17102 uint32_t FLT_CONF:2; /* Fault Confinement State */ 17103 #else 17104 uint32_t FLTCONF:2; /* deprecated name - please avoid */ 17105 #endif 17106 uint32_t:1; 17107 #ifndef USE_FIELD_ALIASES_FLEXCAN 17108 uint32_t BOFF_INT:1; /* Bus Off Interrupt */ 17109 #else 17110 uint32_t BOFFINT:1; /* deprecated name - please avoid */ 17111 #endif 17112 #ifndef USE_FIELD_ALIASES_FLEXCAN 17113 uint32_t ERR_INT:1; /* Error Interrupt */ 17114 #else 17115 uint32_t ERRINT:1; /* deprecated name - please avoid */ 17116 #endif 17117 #ifndef USE_FIELD_ALIASES_FLEXCAN 17118 uint32_t WAK_INT:1; /* Wake-Up Interrupt */ 17119 #else 17120 uint32_t WAKINT:1; /* deprecated name - please avoid */ 17121 #endif 17122 } B; 17123 } FLEXCAN_ESR_32B_tag; 17124 17125 typedef union { /* IMASK2 - Interrupt Masks 2 Register */ 17126 uint32_t R; 17127 struct { 17128 uint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */ 17129 uint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */ 17130 uint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */ 17131 uint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */ 17132 uint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */ 17133 uint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */ 17134 uint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */ 17135 uint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */ 17136 uint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */ 17137 uint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */ 17138 uint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */ 17139 uint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */ 17140 uint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */ 17141 uint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */ 17142 uint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */ 17143 uint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */ 17144 uint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */ 17145 uint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */ 17146 uint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */ 17147 uint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */ 17148 uint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */ 17149 uint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */ 17150 uint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */ 17151 uint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */ 17152 uint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */ 17153 uint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */ 17154 uint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */ 17155 uint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */ 17156 uint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */ 17157 uint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */ 17158 uint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */ 17159 uint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */ 17160 } B; 17161 } FLEXCAN_IMASK2_32B_tag; 17162 17163 typedef union { /* IMASK1 - Interrupt Masks 1 Register */ 17164 uint32_t R; 17165 struct { 17166 uint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */ 17167 uint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */ 17168 uint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */ 17169 uint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */ 17170 uint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */ 17171 uint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */ 17172 uint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */ 17173 uint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */ 17174 uint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */ 17175 uint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */ 17176 uint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */ 17177 uint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */ 17178 uint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */ 17179 uint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */ 17180 uint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */ 17181 uint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */ 17182 uint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */ 17183 uint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */ 17184 uint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */ 17185 uint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */ 17186 uint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */ 17187 uint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */ 17188 #ifndef USE_FIELD_ALIASES_FLEXCAN 17189 uint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */ 17190 #else 17191 uint32_t BUF09M:1; /* deprecated name - please avoid */ 17192 #endif 17193 #ifndef USE_FIELD_ALIASES_FLEXCAN 17194 uint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */ 17195 #else 17196 uint32_t BUF08M:1; /* deprecated name - please avoid */ 17197 #endif 17198 #ifndef USE_FIELD_ALIASES_FLEXCAN 17199 uint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */ 17200 #else 17201 uint32_t BUF07M:1; /* deprecated name - please avoid */ 17202 #endif 17203 #ifndef USE_FIELD_ALIASES_FLEXCAN 17204 uint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */ 17205 #else 17206 uint32_t BUF06M:1; /* deprecated name - please avoid */ 17207 #endif 17208 #ifndef USE_FIELD_ALIASES_FLEXCAN 17209 uint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */ 17210 #else 17211 uint32_t BUF05M:1; /* deprecated name - please avoid */ 17212 #endif 17213 #ifndef USE_FIELD_ALIASES_FLEXCAN 17214 uint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */ 17215 #else 17216 uint32_t BUF04M:1; /* deprecated name - please avoid */ 17217 #endif 17218 #ifndef USE_FIELD_ALIASES_FLEXCAN 17219 uint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */ 17220 #else 17221 uint32_t BUF03M:1; /* deprecated name - please avoid */ 17222 #endif 17223 #ifndef USE_FIELD_ALIASES_FLEXCAN 17224 uint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */ 17225 #else 17226 uint32_t BUF02M:1; /* deprecated name - please avoid */ 17227 #endif 17228 #ifndef USE_FIELD_ALIASES_FLEXCAN 17229 uint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */ 17230 #else 17231 uint32_t BUF01M:1; /* deprecated name - please avoid */ 17232 #endif 17233 #ifndef USE_FIELD_ALIASES_FLEXCAN 17234 uint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */ 17235 #else 17236 uint32_t BUF00M:1; /* deprecated name - please avoid */ 17237 #endif 17238 } B; 17239 } FLEXCAN_IMASK1_32B_tag; 17240 17241 typedef union { /* IFLAG2 - Interrupt Flags 2 Register */ 17242 uint32_t R; 17243 struct { 17244 uint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */ 17245 uint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */ 17246 uint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */ 17247 uint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */ 17248 uint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */ 17249 uint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */ 17250 uint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */ 17251 uint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */ 17252 uint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */ 17253 uint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */ 17254 uint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */ 17255 uint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */ 17256 uint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */ 17257 uint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */ 17258 uint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */ 17259 uint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */ 17260 uint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */ 17261 uint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */ 17262 uint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */ 17263 uint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */ 17264 uint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */ 17265 uint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */ 17266 uint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */ 17267 uint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */ 17268 uint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */ 17269 uint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */ 17270 uint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */ 17271 uint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */ 17272 uint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */ 17273 uint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */ 17274 uint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */ 17275 uint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */ 17276 } B; 17277 } FLEXCAN_IFLAG2_32B_tag; 17278 17279 typedef union { /* IFLAG1 - Interrupt Flags 1 Register */ 17280 uint32_t R; 17281 struct { 17282 uint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */ 17283 uint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */ 17284 uint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */ 17285 uint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */ 17286 uint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */ 17287 uint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */ 17288 uint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */ 17289 uint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */ 17290 uint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */ 17291 uint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */ 17292 uint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */ 17293 uint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */ 17294 uint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */ 17295 uint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */ 17296 uint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */ 17297 uint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */ 17298 uint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */ 17299 uint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */ 17300 uint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */ 17301 uint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */ 17302 uint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */ 17303 uint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */ 17304 #ifndef USE_FIELD_ALIASES_FLEXCAN 17305 uint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */ 17306 #else 17307 uint32_t BUF09I:1; /* deprecated name - please avoid */ 17308 #endif 17309 #ifndef USE_FIELD_ALIASES_FLEXCAN 17310 uint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */ 17311 #else 17312 uint32_t BUF08I:1; /* deprecated name - please avoid */ 17313 #endif 17314 #ifndef USE_FIELD_ALIASES_FLEXCAN 17315 uint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */ 17316 #else 17317 uint32_t BUF07I:1; /* deprecated name - please avoid */ 17318 #endif 17319 #ifndef USE_FIELD_ALIASES_FLEXCAN 17320 uint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */ 17321 #else 17322 uint32_t BUF06I:1; /* deprecated name - please avoid */ 17323 #endif 17324 #ifndef USE_FIELD_ALIASES_FLEXCAN 17325 uint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */ 17326 #else 17327 uint32_t BUF05I:1; /* deprecated name - please avoid */ 17328 #endif 17329 #ifndef USE_FIELD_ALIASES_FLEXCAN 17330 uint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */ 17331 #else 17332 uint32_t BUF04I:1; /* deprecated name - please avoid */ 17333 #endif 17334 #ifndef USE_FIELD_ALIASES_FLEXCAN 17335 uint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */ 17336 #else 17337 uint32_t BUF03I:1; /* deprecated name - please avoid */ 17338 #endif 17339 #ifndef USE_FIELD_ALIASES_FLEXCAN 17340 uint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */ 17341 #else 17342 uint32_t BUF02I:1; /* deprecated name - please avoid */ 17343 #endif 17344 #ifndef USE_FIELD_ALIASES_FLEXCAN 17345 uint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */ 17346 #else 17347 uint32_t BUF01I:1; /* deprecated name - please avoid */ 17348 #endif 17349 #ifndef USE_FIELD_ALIASES_FLEXCAN 17350 uint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */ 17351 #else 17352 uint32_t BUF00I:1; /* deprecated name - please avoid */ 17353 #endif 17354 } B; 17355 } FLEXCAN_IFLAG1_32B_tag; 17356 17357 17358 /* Register layout for all registers MSG_CS... */ 17359 17360 typedef union { /* Message Buffer Control and Status */ 17361 uint32_t R; 17362 struct { 17363 uint32_t:4; 17364 uint32_t CODE:4; /* Message Buffer Code */ 17365 uint32_t:1; 17366 uint32_t SRR:1; /* Substitute Remote Request */ 17367 uint32_t IDE:1; /* ID Extended Bit */ 17368 uint32_t RTR:1; /* Remote Transmission Request */ 17369 uint32_t LENGTH:4; /* Length of Data in Bytes */ 17370 uint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */ 17371 } B; 17372 } FLEXCAN_MSG_CS_32B_tag; 17373 17374 17375 /* Register layout for all registers MSG_ID... */ 17376 17377 typedef union { /* Message Buffer Identifier Field */ 17378 uint32_t R; 17379 struct { 17380 uint32_t PRIO:3; /* Local Priority */ 17381 uint32_t STD_ID:11; 17382 uint32_t EXT_ID:18; 17383 } B; 17384 } FLEXCAN_MSG_ID_32B_tag; 17385 17386 17387 /* Register layout for all registers MSG_BYTE0_3... */ 17388 17389 typedef union { /* Message Buffer Data Register */ 17390 uint32_t R; 17391 uint8_t BYTE[4]; /* individual bytes can be accessed */ 17392 uint32_t WORD; /* individual words can be accessed */ 17393 } FLEXCAN_MSG_DATA_32B_tag; 17394 17395 typedef union { 17396 uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ 17397 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ 17398 uint32_t W[2]; /* Data buffer in words (32 bits) */ 17399 uint32_t R[2]; /* Data buffer in words (32 bits) */ 17400 } FLEXCAN_MSG_DATA2_32B_tag; 17401 17402 /* Register layout for all registers MSG_BYTE4_7 matches xxx */ 17403 17404 17405 /* Register layout for all registers RXIMR... */ 17406 17407 typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ 17408 uint32_t R; 17409 } FLEXCAN_RXIMR_32B_tag; 17410 17411 17412 typedef struct FLEXCAN_MB_struct_tag { 17413 17414 union { 17415 /* Message Buffer Control and Status */ 17416 FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */ 17417 FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */ 17418 }; 17419 union { 17420 /* Message Buffer Identifier Field */ 17421 FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */ 17422 FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */ 17423 }; 17424 union { /* Message Buffer Data Register */ 17425 17426 struct { 17427 FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */ 17428 /* Message Buffer Data Register */ 17429 FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */ 17430 }; 17431 17432 FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */ 17433 17434 }; 17435 17436 } FLEXCAN_MB_tag; 17437 17438 17439 typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */ 17440 /* MCR - Module Configuration Register */ 17441 FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ 17442 union { 17443 /* CTRL - Control Register */ 17444 FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */ 17445 17446 FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */ 17447 17448 }; 17449 /* TIMER - Free Running Timer */ 17450 FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */ 17451 int8_t FLEXCAN_reserved_000C[4]; 17452 /* RXGMASK - Rx Global Mask Register */ 17453 FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */ 17454 /* RX14MASK - Rx 14 Mask Register */ 17455 FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */ 17456 /* RX15MASK - Rx 15 Mask Register */ 17457 FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */ 17458 /* ECR - Error Counter Register */ 17459 FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */ 17460 /* ESR - Error and Status Register */ 17461 FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */ 17462 union { 17463 FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */ 17464 17465 /* IMASK2 - Interrupt Masks 2 Register */ 17466 FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */ 17467 17468 }; 17469 union { 17470 FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */ 17471 17472 /* IMASK1 - Interrupt Masks 1 Register */ 17473 FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */ 17474 17475 }; 17476 union { 17477 FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */ 17478 17479 /* IFLAG2 - Interrupt Flags 2 Register */ 17480 FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */ 17481 17482 }; 17483 union { 17484 FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */ 17485 17486 /* IFLAG1 - Interrupt Flags 1 Register */ 17487 FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */ 17488 17489 }; 17490 int8_t FLEXCAN_reserved_0034_C[76]; 17491 union { 17492 /* Register set MB */ 17493 FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */ 17494 17495 /* Alias name for MB */ 17496 FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */ 17497 17498 struct { 17499 /* Message Buffer Control and Status */ 17500 FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */ 17501 /* Message Buffer Identifier Field */ 17502 FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */ 17503 /* Message Buffer Data Register */ 17504 FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */ 17505 /* Message Buffer Data Register */ 17506 FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */ 17507 /* Message Buffer Control and Status */ 17508 FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */ 17509 /* Message Buffer Identifier Field */ 17510 FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */ 17511 /* Message Buffer Data Register */ 17512 FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */ 17513 /* Message Buffer Data Register */ 17514 FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */ 17515 /* Message Buffer Control and Status */ 17516 FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */ 17517 /* Message Buffer Identifier Field */ 17518 FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */ 17519 /* Message Buffer Data Register */ 17520 FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */ 17521 /* Message Buffer Data Register */ 17522 FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */ 17523 /* Message Buffer Control and Status */ 17524 FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */ 17525 /* Message Buffer Identifier Field */ 17526 FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */ 17527 /* Message Buffer Data Register */ 17528 FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */ 17529 /* Message Buffer Data Register */ 17530 FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */ 17531 /* Message Buffer Control and Status */ 17532 FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */ 17533 /* Message Buffer Identifier Field */ 17534 FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */ 17535 /* Message Buffer Data Register */ 17536 FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */ 17537 /* Message Buffer Data Register */ 17538 FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */ 17539 /* Message Buffer Control and Status */ 17540 FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */ 17541 /* Message Buffer Identifier Field */ 17542 FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */ 17543 /* Message Buffer Data Register */ 17544 FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */ 17545 /* Message Buffer Data Register */ 17546 FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */ 17547 /* Message Buffer Control and Status */ 17548 FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */ 17549 /* Message Buffer Identifier Field */ 17550 FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */ 17551 /* Message Buffer Data Register */ 17552 FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */ 17553 /* Message Buffer Data Register */ 17554 FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */ 17555 /* Message Buffer Control and Status */ 17556 FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */ 17557 /* Message Buffer Identifier Field */ 17558 FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */ 17559 /* Message Buffer Data Register */ 17560 FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */ 17561 /* Message Buffer Data Register */ 17562 FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */ 17563 /* Message Buffer Control and Status */ 17564 FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */ 17565 /* Message Buffer Identifier Field */ 17566 FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */ 17567 /* Message Buffer Data Register */ 17568 FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */ 17569 /* Message Buffer Data Register */ 17570 FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */ 17571 /* Message Buffer Control and Status */ 17572 FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */ 17573 /* Message Buffer Identifier Field */ 17574 FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */ 17575 /* Message Buffer Data Register */ 17576 FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */ 17577 /* Message Buffer Data Register */ 17578 FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */ 17579 /* Message Buffer Control and Status */ 17580 FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */ 17581 /* Message Buffer Identifier Field */ 17582 FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */ 17583 /* Message Buffer Data Register */ 17584 FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */ 17585 /* Message Buffer Data Register */ 17586 FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */ 17587 /* Message Buffer Control and Status */ 17588 FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */ 17589 /* Message Buffer Identifier Field */ 17590 FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */ 17591 /* Message Buffer Data Register */ 17592 FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */ 17593 /* Message Buffer Data Register */ 17594 FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */ 17595 /* Message Buffer Control and Status */ 17596 FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */ 17597 /* Message Buffer Identifier Field */ 17598 FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */ 17599 /* Message Buffer Data Register */ 17600 FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */ 17601 /* Message Buffer Data Register */ 17602 FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */ 17603 /* Message Buffer Control and Status */ 17604 FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */ 17605 /* Message Buffer Identifier Field */ 17606 FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */ 17607 /* Message Buffer Data Register */ 17608 FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */ 17609 /* Message Buffer Data Register */ 17610 FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */ 17611 /* Message Buffer Control and Status */ 17612 FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */ 17613 /* Message Buffer Identifier Field */ 17614 FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */ 17615 /* Message Buffer Data Register */ 17616 FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */ 17617 /* Message Buffer Data Register */ 17618 FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */ 17619 /* Message Buffer Control and Status */ 17620 FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */ 17621 /* Message Buffer Identifier Field */ 17622 FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */ 17623 /* Message Buffer Data Register */ 17624 FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */ 17625 /* Message Buffer Data Register */ 17626 FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */ 17627 /* Message Buffer Control and Status */ 17628 FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */ 17629 /* Message Buffer Identifier Field */ 17630 FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */ 17631 /* Message Buffer Data Register */ 17632 FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */ 17633 /* Message Buffer Data Register */ 17634 FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */ 17635 /* Message Buffer Control and Status */ 17636 FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */ 17637 /* Message Buffer Identifier Field */ 17638 FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */ 17639 /* Message Buffer Data Register */ 17640 FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */ 17641 /* Message Buffer Data Register */ 17642 FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */ 17643 /* Message Buffer Control and Status */ 17644 FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */ 17645 /* Message Buffer Identifier Field */ 17646 FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */ 17647 /* Message Buffer Data Register */ 17648 FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */ 17649 /* Message Buffer Data Register */ 17650 FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */ 17651 /* Message Buffer Control and Status */ 17652 FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */ 17653 /* Message Buffer Identifier Field */ 17654 FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */ 17655 /* Message Buffer Data Register */ 17656 FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */ 17657 /* Message Buffer Data Register */ 17658 FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */ 17659 /* Message Buffer Control and Status */ 17660 FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */ 17661 /* Message Buffer Identifier Field */ 17662 FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */ 17663 /* Message Buffer Data Register */ 17664 FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */ 17665 /* Message Buffer Data Register */ 17666 FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */ 17667 /* Message Buffer Control and Status */ 17668 FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */ 17669 /* Message Buffer Identifier Field */ 17670 FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */ 17671 /* Message Buffer Data Register */ 17672 FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */ 17673 /* Message Buffer Data Register */ 17674 FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */ 17675 /* Message Buffer Control and Status */ 17676 FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */ 17677 /* Message Buffer Identifier Field */ 17678 FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */ 17679 /* Message Buffer Data Register */ 17680 FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */ 17681 /* Message Buffer Data Register */ 17682 FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */ 17683 /* Message Buffer Control and Status */ 17684 FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */ 17685 /* Message Buffer Identifier Field */ 17686 FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */ 17687 /* Message Buffer Data Register */ 17688 FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */ 17689 /* Message Buffer Data Register */ 17690 FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */ 17691 /* Message Buffer Control and Status */ 17692 FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */ 17693 /* Message Buffer Identifier Field */ 17694 FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */ 17695 /* Message Buffer Data Register */ 17696 FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */ 17697 /* Message Buffer Data Register */ 17698 FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */ 17699 /* Message Buffer Control and Status */ 17700 FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */ 17701 /* Message Buffer Identifier Field */ 17702 FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */ 17703 /* Message Buffer Data Register */ 17704 FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */ 17705 /* Message Buffer Data Register */ 17706 FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */ 17707 /* Message Buffer Control and Status */ 17708 FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */ 17709 /* Message Buffer Identifier Field */ 17710 FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */ 17711 /* Message Buffer Data Register */ 17712 FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */ 17713 /* Message Buffer Data Register */ 17714 FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */ 17715 /* Message Buffer Control and Status */ 17716 FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */ 17717 /* Message Buffer Identifier Field */ 17718 FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */ 17719 /* Message Buffer Data Register */ 17720 FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */ 17721 /* Message Buffer Data Register */ 17722 FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */ 17723 /* Message Buffer Control and Status */ 17724 FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */ 17725 /* Message Buffer Identifier Field */ 17726 FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */ 17727 /* Message Buffer Data Register */ 17728 FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */ 17729 /* Message Buffer Data Register */ 17730 FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */ 17731 /* Message Buffer Control and Status */ 17732 FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */ 17733 /* Message Buffer Identifier Field */ 17734 FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */ 17735 /* Message Buffer Data Register */ 17736 FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */ 17737 /* Message Buffer Data Register */ 17738 FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */ 17739 /* Message Buffer Control and Status */ 17740 FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */ 17741 /* Message Buffer Identifier Field */ 17742 FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */ 17743 /* Message Buffer Data Register */ 17744 FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */ 17745 /* Message Buffer Data Register */ 17746 FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */ 17747 /* Message Buffer Control and Status */ 17748 FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */ 17749 /* Message Buffer Identifier Field */ 17750 FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */ 17751 /* Message Buffer Data Register */ 17752 FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */ 17753 /* Message Buffer Data Register */ 17754 FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */ 17755 /* Message Buffer Control and Status */ 17756 FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */ 17757 /* Message Buffer Identifier Field */ 17758 FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */ 17759 /* Message Buffer Data Register */ 17760 FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */ 17761 /* Message Buffer Data Register */ 17762 FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */ 17763 /* Message Buffer Control and Status */ 17764 FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */ 17765 /* Message Buffer Identifier Field */ 17766 FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */ 17767 /* Message Buffer Data Register */ 17768 FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */ 17769 /* Message Buffer Data Register */ 17770 FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */ 17771 /* Message Buffer Control and Status */ 17772 FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */ 17773 /* Message Buffer Identifier Field */ 17774 FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */ 17775 /* Message Buffer Data Register */ 17776 FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */ 17777 /* Message Buffer Data Register */ 17778 FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */ 17779 /* Message Buffer Control and Status */ 17780 FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */ 17781 /* Message Buffer Identifier Field */ 17782 FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */ 17783 /* Message Buffer Data Register */ 17784 FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */ 17785 /* Message Buffer Data Register */ 17786 FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */ 17787 /* Message Buffer Control and Status */ 17788 FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */ 17789 /* Message Buffer Identifier Field */ 17790 FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */ 17791 /* Message Buffer Data Register */ 17792 FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */ 17793 /* Message Buffer Data Register */ 17794 FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */ 17795 /* Message Buffer Control and Status */ 17796 FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */ 17797 /* Message Buffer Identifier Field */ 17798 FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */ 17799 /* Message Buffer Data Register */ 17800 FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */ 17801 /* Message Buffer Data Register */ 17802 FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */ 17803 /* Message Buffer Control and Status */ 17804 FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */ 17805 /* Message Buffer Identifier Field */ 17806 FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */ 17807 /* Message Buffer Data Register */ 17808 FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */ 17809 /* Message Buffer Data Register */ 17810 FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */ 17811 /* Message Buffer Control and Status */ 17812 FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */ 17813 /* Message Buffer Identifier Field */ 17814 FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */ 17815 /* Message Buffer Data Register */ 17816 FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */ 17817 /* Message Buffer Data Register */ 17818 FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */ 17819 /* Message Buffer Control and Status */ 17820 FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */ 17821 /* Message Buffer Identifier Field */ 17822 FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */ 17823 /* Message Buffer Data Register */ 17824 FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */ 17825 /* Message Buffer Data Register */ 17826 FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */ 17827 /* Message Buffer Control and Status */ 17828 FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */ 17829 /* Message Buffer Identifier Field */ 17830 FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */ 17831 /* Message Buffer Data Register */ 17832 FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */ 17833 /* Message Buffer Data Register */ 17834 FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */ 17835 /* Message Buffer Control and Status */ 17836 FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */ 17837 /* Message Buffer Identifier Field */ 17838 FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */ 17839 /* Message Buffer Data Register */ 17840 FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */ 17841 /* Message Buffer Data Register */ 17842 FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */ 17843 /* Message Buffer Control and Status */ 17844 FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */ 17845 /* Message Buffer Identifier Field */ 17846 FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */ 17847 /* Message Buffer Data Register */ 17848 FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */ 17849 /* Message Buffer Data Register */ 17850 FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */ 17851 /* Message Buffer Control and Status */ 17852 FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */ 17853 /* Message Buffer Identifier Field */ 17854 FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */ 17855 /* Message Buffer Data Register */ 17856 FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */ 17857 /* Message Buffer Data Register */ 17858 FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */ 17859 /* Message Buffer Control and Status */ 17860 FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */ 17861 /* Message Buffer Identifier Field */ 17862 FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */ 17863 /* Message Buffer Data Register */ 17864 FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */ 17865 /* Message Buffer Data Register */ 17866 FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */ 17867 /* Message Buffer Control and Status */ 17868 FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */ 17869 /* Message Buffer Identifier Field */ 17870 FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */ 17871 /* Message Buffer Data Register */ 17872 FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */ 17873 /* Message Buffer Data Register */ 17874 FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */ 17875 /* Message Buffer Control and Status */ 17876 FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */ 17877 /* Message Buffer Identifier Field */ 17878 FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */ 17879 /* Message Buffer Data Register */ 17880 FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */ 17881 /* Message Buffer Data Register */ 17882 FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */ 17883 /* Message Buffer Control and Status */ 17884 FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */ 17885 /* Message Buffer Identifier Field */ 17886 FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */ 17887 /* Message Buffer Data Register */ 17888 FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */ 17889 /* Message Buffer Data Register */ 17890 FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */ 17891 /* Message Buffer Control and Status */ 17892 FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */ 17893 /* Message Buffer Identifier Field */ 17894 FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */ 17895 /* Message Buffer Data Register */ 17896 FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */ 17897 /* Message Buffer Data Register */ 17898 FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */ 17899 /* Message Buffer Control and Status */ 17900 FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */ 17901 /* Message Buffer Identifier Field */ 17902 FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */ 17903 /* Message Buffer Data Register */ 17904 FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */ 17905 /* Message Buffer Data Register */ 17906 FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */ 17907 /* Message Buffer Control and Status */ 17908 FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */ 17909 /* Message Buffer Identifier Field */ 17910 FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */ 17911 /* Message Buffer Data Register */ 17912 FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */ 17913 /* Message Buffer Data Register */ 17914 FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */ 17915 /* Message Buffer Control and Status */ 17916 FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */ 17917 /* Message Buffer Identifier Field */ 17918 FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */ 17919 /* Message Buffer Data Register */ 17920 FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */ 17921 /* Message Buffer Data Register */ 17922 FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */ 17923 /* Message Buffer Control and Status */ 17924 FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */ 17925 /* Message Buffer Identifier Field */ 17926 FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */ 17927 /* Message Buffer Data Register */ 17928 FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */ 17929 /* Message Buffer Data Register */ 17930 FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */ 17931 /* Message Buffer Control and Status */ 17932 FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */ 17933 /* Message Buffer Identifier Field */ 17934 FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */ 17935 /* Message Buffer Data Register */ 17936 FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */ 17937 /* Message Buffer Data Register */ 17938 FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */ 17939 /* Message Buffer Control and Status */ 17940 FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */ 17941 /* Message Buffer Identifier Field */ 17942 FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */ 17943 /* Message Buffer Data Register */ 17944 FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */ 17945 /* Message Buffer Data Register */ 17946 FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */ 17947 /* Message Buffer Control and Status */ 17948 FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */ 17949 /* Message Buffer Identifier Field */ 17950 FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */ 17951 /* Message Buffer Data Register */ 17952 FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */ 17953 /* Message Buffer Data Register */ 17954 FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */ 17955 /* Message Buffer Control and Status */ 17956 FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */ 17957 /* Message Buffer Identifier Field */ 17958 FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */ 17959 /* Message Buffer Data Register */ 17960 FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */ 17961 /* Message Buffer Data Register */ 17962 FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */ 17963 /* Message Buffer Control and Status */ 17964 FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */ 17965 /* Message Buffer Identifier Field */ 17966 FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */ 17967 /* Message Buffer Data Register */ 17968 FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */ 17969 /* Message Buffer Data Register */ 17970 FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */ 17971 /* Message Buffer Control and Status */ 17972 FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */ 17973 /* Message Buffer Identifier Field */ 17974 FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */ 17975 /* Message Buffer Data Register */ 17976 FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */ 17977 /* Message Buffer Data Register */ 17978 FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */ 17979 /* Message Buffer Control and Status */ 17980 FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */ 17981 /* Message Buffer Identifier Field */ 17982 FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */ 17983 /* Message Buffer Data Register */ 17984 FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */ 17985 /* Message Buffer Data Register */ 17986 FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */ 17987 /* Message Buffer Control and Status */ 17988 FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */ 17989 /* Message Buffer Identifier Field */ 17990 FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */ 17991 /* Message Buffer Data Register */ 17992 FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */ 17993 /* Message Buffer Data Register */ 17994 FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */ 17995 /* Message Buffer Control and Status */ 17996 FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */ 17997 /* Message Buffer Identifier Field */ 17998 FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */ 17999 /* Message Buffer Data Register */ 18000 FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */ 18001 /* Message Buffer Data Register */ 18002 FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */ 18003 /* Message Buffer Control and Status */ 18004 FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */ 18005 /* Message Buffer Identifier Field */ 18006 FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */ 18007 /* Message Buffer Data Register */ 18008 FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */ 18009 /* Message Buffer Data Register */ 18010 FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */ 18011 }; 18012 18013 }; 18014 int8_t FLEXCAN_reserved_0480_C[1024]; 18015 union { 18016 /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ 18017 FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */ 18018 18019 struct { 18020 /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ 18021 FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */ 18022 FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */ 18023 FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */ 18024 FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */ 18025 FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */ 18026 FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */ 18027 FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */ 18028 FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */ 18029 FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */ 18030 FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */ 18031 FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */ 18032 FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */ 18033 FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */ 18034 FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */ 18035 FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */ 18036 FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */ 18037 FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */ 18038 FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */ 18039 FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */ 18040 FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */ 18041 FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */ 18042 FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */ 18043 FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */ 18044 FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */ 18045 FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */ 18046 FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */ 18047 FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */ 18048 FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */ 18049 FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */ 18050 FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */ 18051 FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */ 18052 FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */ 18053 FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */ 18054 FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */ 18055 FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */ 18056 FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */ 18057 FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */ 18058 FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */ 18059 FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */ 18060 FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */ 18061 FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */ 18062 FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */ 18063 FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */ 18064 FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */ 18065 FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */ 18066 FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */ 18067 FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */ 18068 FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */ 18069 FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */ 18070 FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */ 18071 FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */ 18072 FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */ 18073 FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */ 18074 FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */ 18075 FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */ 18076 FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */ 18077 FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */ 18078 FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */ 18079 FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */ 18080 FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */ 18081 FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */ 18082 FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */ 18083 FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */ 18084 FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */ 18085 }; 18086 18087 }; 18088 } FLEXCAN_tag; 18089 18090 18091 #define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL) 18092 #define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL) 18093 18094 18095 18096 /****************************************************************/ 18097 /* */ 18098 /* Module: DMA_CH_MUX */ 18099 /* */ 18100 /****************************************************************/ 18101 18102 18103 /* Register layout for all registers CHCONFIG... */ 18104 18105 typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */ 18106 uint8_t R; 18107 struct { 18108 uint8_t ENBL:1; /* DMA Channel Enable */ 18109 uint8_t TRIG:1; /* DMA Channel Trigger Enable */ 18110 uint8_t SOURCE:6; /* DMA Channel Source */ 18111 } B; 18112 } DMA_CH_MUX_CHCONFIG_8B_tag; 18113 18114 18115 18116 typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */ 18117 union { 18118 /* CHCONFIG[0-15] - Channel Configuration Registers */ 18119 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */ 18120 18121 struct { 18122 /* CHCONFIG[0-15] - Channel Configuration Registers */ 18123 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */ 18124 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */ 18125 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */ 18126 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */ 18127 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */ 18128 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */ 18129 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */ 18130 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */ 18131 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */ 18132 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */ 18133 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */ 18134 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */ 18135 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */ 18136 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */ 18137 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */ 18138 DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */ 18139 }; 18140 18141 }; 18142 } DMA_CH_MUX_tag; 18143 18144 18145 #define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL) 18146 18147 18148 18149 /****************************************************************/ 18150 /* */ 18151 /* Module: FR */ 18152 /* */ 18153 /****************************************************************/ 18154 18155 typedef union { /* Module Version Number */ 18156 uint16_t R; 18157 struct { 18158 uint16_t CHIVER:8; /* VERSION NUMBER OF CHI */ 18159 uint16_t PEVER:8; /* VERSION NUMBER OF PE */ 18160 } B; 18161 } FR_MVR_16B_tag; 18162 18163 typedef union { /* Module Configuration Register */ 18164 uint16_t R; 18165 struct { 18166 uint16_t MEN:1; /* Module Enable */ 18167 uint16_t SBFF:1; /* System Bus Failure Freeze */ 18168 #ifndef USE_FIELD_ALIASES_FR 18169 uint16_t SCM:1; /* single channel device mode */ 18170 #else 18171 uint16_t SCMD:1; /* deprecated name - please avoid */ 18172 #endif 18173 uint16_t CHB:1; /* Channel B enable */ 18174 uint16_t CHA:1; /* channel A enable */ 18175 uint16_t SFFE:1; /* Sync. frame filter Enable */ 18176 uint16_t ECCE:1; /* ECC Functionlity Enable */ 18177 uint16_t TMODER:1; /* Functional Test mode */ 18178 uint16_t FUM:1; /* FIFO Update Mode */ 18179 uint16_t FAM:1; /* FIFO Address Mode */ 18180 uint16_t:1; 18181 uint16_t CLKSEL:1; /* Protocol Engine clock source select */ 18182 uint16_t BITRATE:3; /* Bus bit rate */ 18183 uint16_t:1; 18184 } B; 18185 } FR_MCR_16B_tag; 18186 18187 typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */ 18188 uint16_t R; 18189 struct { 18190 uint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */ 18191 } B; 18192 } FR_SYMBADHR_16B_tag; 18193 18194 typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */ 18195 uint16_t R; 18196 struct { 18197 uint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */ 18198 uint16_t:4; 18199 } B; 18200 } FR_SYMBADLR_16B_tag; 18201 18202 typedef union { /* STROBE SIGNAL CONTROL REGISTER */ 18203 uint16_t R; 18204 struct { 18205 uint16_t WMD:1; /* DEFINES WRITE MODE OF REG */ 18206 uint16_t:3; 18207 uint16_t SEL:4; /* STROBE SIGNSL SELECT */ 18208 uint16_t:3; 18209 uint16_t ENB:1; /* STROBE SIGNAL ENABLE */ 18210 uint16_t:2; 18211 uint16_t STBPSEL:2; /* STROBE PORT SELECT */ 18212 } B; 18213 } FR_STBSCR_16B_tag; 18214 18215 typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */ 18216 uint16_t R; 18217 struct { 18218 uint16_t:1; 18219 uint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */ 18220 uint16_t:1; 18221 uint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */ 18222 } B; 18223 } FR_MBDSR_16B_tag; 18224 18225 typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ 18226 uint16_t R; 18227 struct { 18228 uint16_t:2; 18229 uint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */ 18230 uint16_t:2; 18231 uint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */ 18232 } B; 18233 } FR_MBSSUTR_16B_tag; 18234 18235 typedef union { /* PE DRAM ACCESS REGISTER */ 18236 uint16_t R; 18237 struct { 18238 uint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */ 18239 uint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */ 18240 uint16_t DAD:1; /* PE DRAM ACCESS DONE */ 18241 } B; 18242 } FR_PEDRAR_16B_tag; 18243 18244 typedef union { /* PE DRAM DATA REGISTER */ 18245 uint16_t R; 18246 struct { 18247 uint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */ 18248 } B; 18249 } FR_PEDRDR_16B_tag; 18250 18251 typedef union { /* PROTOCOL OPERATION CONTROL REG */ 18252 uint16_t R; 18253 struct { 18254 uint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */ 18255 uint16_t:3; 18256 uint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */ 18257 uint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */ 18258 uint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */ 18259 uint16_t:3; 18260 uint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */ 18261 } B; 18262 } FR_POCR_16B_tag; 18263 18264 typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */ 18265 uint16_t R; 18266 struct { 18267 uint16_t MIF:1; /* MODULE INTERRUPT FLAG */ 18268 uint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */ 18269 uint16_t CHIF:1; /* CHI INTERRUPT FLAG */ 18270 #ifndef USE_FIELD_ALIASES_FR 18271 uint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */ 18272 #else 18273 uint16_t WKUPIF:1; /* deprecated name - please avoid */ 18274 #endif 18275 #ifndef USE_FIELD_ALIASES_FR 18276 uint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */ 18277 #else 18278 uint16_t FNEBIF:1; /* deprecated name - please avoid */ 18279 #endif 18280 #ifndef USE_FIELD_ALIASES_FR 18281 uint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */ 18282 #else 18283 uint16_t FNEAIF:1; /* deprecated name - please avoid */ 18284 #endif 18285 uint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */ 18286 uint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */ 18287 uint16_t MIE:1; /* MODULE INTERRUPT ENABLE */ 18288 uint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */ 18289 uint16_t CHIE:1; /* CHI INTERRUPT ENABLE */ 18290 #ifndef USE_FIELD_ALIASES_FR 18291 uint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */ 18292 #else 18293 uint16_t WKUPIE:1; /* deprecated name - please avoid */ 18294 #endif 18295 uint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */ 18296 uint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */ 18297 uint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */ 18298 uint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */ 18299 } B; 18300 } FR_GIFER_16B_tag; 18301 18302 typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ 18303 uint16_t R; 18304 struct { 18305 #ifndef USE_FIELD_ALIASES_FR 18306 uint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */ 18307 #else 18308 uint16_t FATLIF:1; /* deprecated name - please avoid */ 18309 #endif 18310 #ifndef USE_FIELD_ALIASES_FR 18311 uint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */ 18312 #else 18313 uint16_t INTLIF:1; /* deprecated name - please avoid */ 18314 #endif 18315 #ifndef USE_FIELD_ALIASES_FR 18316 uint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */ 18317 #else 18318 uint16_t ILCFIF:1; /* deprecated name - please avoid */ 18319 #endif 18320 #ifndef USE_FIELD_ALIASES_FR 18321 uint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */ 18322 #else 18323 uint16_t CSAIF:1; /* deprecated name - please avoid */ 18324 #endif 18325 #ifndef USE_FIELD_ALIASES_FR 18326 uint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */ 18327 #else 18328 uint16_t MRCIF:1; /* deprecated name - please avoid */ 18329 #endif 18330 #ifndef USE_FIELD_ALIASES_FR 18331 uint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */ 18332 #else 18333 uint16_t MOCIF:1; /* deprecated name - please avoid */ 18334 #endif 18335 #ifndef USE_FIELD_ALIASES_FR 18336 uint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */ 18337 #else 18338 uint16_t CCLIF:1; /* deprecated name - please avoid */ 18339 #endif 18340 #ifndef USE_FIELD_ALIASES_FR 18341 uint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */ 18342 #else 18343 uint16_t MXSIF:1; /* deprecated name - please avoid */ 18344 #endif 18345 #ifndef USE_FIELD_ALIASES_FR 18346 uint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */ 18347 #else 18348 uint16_t MTXIF:1; /* deprecated name - please avoid */ 18349 #endif 18350 #ifndef USE_FIELD_ALIASES_FR 18351 uint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */ 18352 #else 18353 uint16_t LTXBIF:1; /* deprecated name - please avoid */ 18354 #endif 18355 #ifndef USE_FIELD_ALIASES_FR 18356 uint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */ 18357 #else 18358 uint16_t LTXAIF:1; /* deprecated name - please avoid */ 18359 #endif 18360 #ifndef USE_FIELD_ALIASES_FR 18361 uint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */ 18362 #else 18363 uint16_t TBVBIF:1; /* deprecated name - please avoid */ 18364 #endif 18365 #ifndef USE_FIELD_ALIASES_FR 18366 uint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */ 18367 #else 18368 uint16_t TBVAIF:1; /* deprecated name - please avoid */ 18369 #endif 18370 #ifndef USE_FIELD_ALIASES_FR 18371 uint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */ 18372 #else 18373 uint16_t TI2IF:1; /* deprecated name - please avoid */ 18374 #endif 18375 #ifndef USE_FIELD_ALIASES_FR 18376 uint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */ 18377 #else 18378 uint16_t TI1IF:1; /* deprecated name - please avoid */ 18379 #endif 18380 #ifndef USE_FIELD_ALIASES_FR 18381 uint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */ 18382 #else 18383 uint16_t CYSIF:1; /* deprecated name - please avoid */ 18384 #endif 18385 } B; 18386 } FR_PIFR0_16B_tag; 18387 18388 typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ 18389 uint16_t R; 18390 struct { 18391 #ifndef USE_FIELD_ALIASES_FR 18392 uint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */ 18393 #else 18394 uint16_t EMCIF:1; /* deprecated name - please avoid */ 18395 #endif 18396 #ifndef USE_FIELD_ALIASES_FR 18397 uint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */ 18398 #else 18399 uint16_t IPCIF:1; /* deprecated name - please avoid */ 18400 #endif 18401 #ifndef USE_FIELD_ALIASES_FR 18402 uint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */ 18403 #else 18404 uint16_t PECFIF:1; /* deprecated name - please avoid */ 18405 #endif 18406 #ifndef USE_FIELD_ALIASES_FR 18407 uint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */ 18408 #else 18409 uint16_t PSCIF:1; /* deprecated name - please avoid */ 18410 #endif 18411 #ifndef USE_FIELD_ALIASES_FR 18412 uint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */ 18413 #else 18414 uint16_t SSI3IF:1; /* deprecated name - please avoid */ 18415 #endif 18416 #ifndef USE_FIELD_ALIASES_FR 18417 uint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */ 18418 #else 18419 uint16_t SSI2IF:1; /* deprecated name - please avoid */ 18420 #endif 18421 #ifndef USE_FIELD_ALIASES_FR 18422 uint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */ 18423 #else 18424 uint16_t SSI1IF:1; /* deprecated name - please avoid */ 18425 #endif 18426 #ifndef USE_FIELD_ALIASES_FR 18427 uint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */ 18428 #else 18429 uint16_t SSI0IF:1; /* deprecated name - please avoid */ 18430 #endif 18431 uint16_t:2; 18432 #ifndef USE_FIELD_ALIASES_FR 18433 uint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */ 18434 #else 18435 uint16_t EVTIF:1; /* deprecated name - please avoid */ 18436 #endif 18437 #ifndef USE_FIELD_ALIASES_FR 18438 uint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */ 18439 #else 18440 uint16_t ODTIF:1; /* deprecated name - please avoid */ 18441 #endif 18442 uint16_t:4; 18443 } B; 18444 } FR_PIFR1_16B_tag; 18445 18446 typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ 18447 uint16_t R; 18448 struct { 18449 #ifndef USE_FIELD_ALIASES_FR 18450 uint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */ 18451 #else 18452 uint16_t FATLIE:1; /* deprecated name - please avoid */ 18453 #endif 18454 #ifndef USE_FIELD_ALIASES_FR 18455 uint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */ 18456 #else 18457 uint16_t INTLIE:1; /* deprecated name - please avoid */ 18458 #endif 18459 #ifndef USE_FIELD_ALIASES_FR 18460 uint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */ 18461 #else 18462 uint16_t ILCFIE:1; /* deprecated name - please avoid */ 18463 #endif 18464 #ifndef USE_FIELD_ALIASES_FR 18465 uint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */ 18466 #else 18467 uint16_t CSAIE:1; /* deprecated name - please avoid */ 18468 #endif 18469 #ifndef USE_FIELD_ALIASES_FR 18470 uint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */ 18471 #else 18472 uint16_t MRCIE:1; /* deprecated name - please avoid */ 18473 #endif 18474 #ifndef USE_FIELD_ALIASES_FR 18475 uint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */ 18476 #else 18477 uint16_t MOCIE:1; /* deprecated name - please avoid */ 18478 #endif 18479 #ifndef USE_FIELD_ALIASES_FR 18480 uint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */ 18481 #else 18482 uint16_t CCLIE:1; /* deprecated name - please avoid */ 18483 #endif 18484 #ifndef USE_FIELD_ALIASES_FR 18485 uint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */ 18486 #else 18487 uint16_t MXSIE:1; /* deprecated name - please avoid */ 18488 #endif 18489 #ifndef USE_FIELD_ALIASES_FR 18490 uint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */ 18491 #else 18492 uint16_t MTXIE:1; /* deprecated name - please avoid */ 18493 #endif 18494 #ifndef USE_FIELD_ALIASES_FR 18495 uint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */ 18496 #else 18497 uint16_t LTXBIE:1; /* deprecated name - please avoid */ 18498 #endif 18499 #ifndef USE_FIELD_ALIASES_FR 18500 uint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */ 18501 #else 18502 uint16_t LTXAIE:1; /* deprecated name - please avoid */ 18503 #endif 18504 #ifndef USE_FIELD_ALIASES_FR 18505 uint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */ 18506 #else 18507 uint16_t TBVBIE:1; /* deprecated name - please avoid */ 18508 #endif 18509 #ifndef USE_FIELD_ALIASES_FR 18510 uint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */ 18511 #else 18512 uint16_t TBVAIE:1; /* deprecated name - please avoid */ 18513 #endif 18514 #ifndef USE_FIELD_ALIASES_FR 18515 uint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */ 18516 #else 18517 uint16_t TI2IE:1; /* deprecated name - please avoid */ 18518 #endif 18519 #ifndef USE_FIELD_ALIASES_FR 18520 uint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */ 18521 #else 18522 uint16_t TI1IE:1; /* deprecated name - please avoid */ 18523 #endif 18524 #ifndef USE_FIELD_ALIASES_FR 18525 uint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */ 18526 #else 18527 uint16_t CYSIE:1; /* deprecated name - please avoid */ 18528 #endif 18529 } B; 18530 } FR_PIER0_16B_tag; 18531 18532 typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ 18533 uint16_t R; 18534 struct { 18535 #ifndef USE_FIELD_ALIASES_FR 18536 uint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */ 18537 #else 18538 uint16_t EMCIE:1; /* deprecated name - please avoid */ 18539 #endif 18540 #ifndef USE_FIELD_ALIASES_FR 18541 uint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */ 18542 #else 18543 uint16_t IPCIE:1; /* deprecated name - please avoid */ 18544 #endif 18545 #ifndef USE_FIELD_ALIASES_FR 18546 uint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */ 18547 #else 18548 uint16_t PECFIE:1; /* deprecated name - please avoid */ 18549 #endif 18550 #ifndef USE_FIELD_ALIASES_FR 18551 uint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */ 18552 #else 18553 uint16_t PSCIE:1; /* deprecated name - please avoid */ 18554 #endif 18555 #ifndef USE_FIELD_ALIASES_FR 18556 uint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */ 18557 #else 18558 uint16_t SSI3IE:1; 18559 uint16_t SSI2IE:1; 18560 uint16_t SSI1IE:1; 18561 uint16_t SSI0IE:1; 18562 #endif 18563 18564 uint16_t:2; 18565 #ifndef USE_FIELD_ALIASES_FR 18566 uint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */ 18567 #else 18568 uint16_t EVTIE:1; /* deprecated name - please avoid */ 18569 #endif 18570 #ifndef USE_FIELD_ALIASES_FR 18571 uint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */ 18572 #else 18573 uint16_t ODTIE:1; /* deprecated name - please avoid */ 18574 #endif 18575 uint16_t:4; 18576 } B; 18577 } FR_PIER1_16B_tag; 18578 18579 typedef union { /* CHI ERROR FLAG REGISTER */ 18580 uint16_t R; 18581 struct { 18582 #ifndef USE_FIELD_ALIASES_FR 18583 uint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */ 18584 #else 18585 uint16_t FRLBEF:1; /* deprecated name - please avoid */ 18586 #endif 18587 #ifndef USE_FIELD_ALIASES_FR 18588 uint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */ 18589 #else 18590 uint16_t FRLAEF:1; /* deprecated name - please avoid */ 18591 #endif 18592 #ifndef USE_FIELD_ALIASES_FR 18593 uint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */ 18594 #else 18595 uint16_t PCMIEF:1; /* deprecated name - please avoid */ 18596 #endif 18597 #ifndef USE_FIELD_ALIASES_FR 18598 uint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */ 18599 #else 18600 uint16_t FOVBEF:1; /* deprecated name - please avoid */ 18601 #endif 18602 #ifndef USE_FIELD_ALIASES_FR 18603 uint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */ 18604 #else 18605 uint16_t FOVAEF:1; /* deprecated name - please avoid */ 18606 #endif 18607 #ifndef USE_FIELD_ALIASES_FR 18608 uint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */ 18609 #else 18610 uint16_t MSBEF:1; /* deprecated name - please avoid */ 18611 #endif 18612 #ifndef USE_FIELD_ALIASES_FR 18613 uint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */ 18614 #else 18615 uint16_t MBUEF:1; /* deprecated name - please avoid */ 18616 #endif 18617 #ifndef USE_FIELD_ALIASES_FR 18618 uint16_t LCK_EF:1; /* LOCK ERROR FLAG */ 18619 #else 18620 uint16_t LCKEF:1; /* deprecated name - please avoid */ 18621 #endif 18622 #ifndef USE_FIELD_ALIASES_FR 18623 uint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */ 18624 #else 18625 uint16_t DBLEF:1; /* deprecated name - please avoid */ 18626 #endif 18627 #ifndef USE_FIELD_ALIASES_FR 18628 uint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */ 18629 #else 18630 uint16_t SBCFEF:1; /* deprecated name - please avoid */ 18631 #endif 18632 #ifndef USE_FIELD_ALIASES_FR 18633 uint16_t FID_EF:1; /* FRAME ID ERROR FLAG */ 18634 #else 18635 uint16_t FIDEF:1; /* deprecated name - please avoid */ 18636 #endif 18637 #ifndef USE_FIELD_ALIASES_FR 18638 uint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */ 18639 #else 18640 uint16_t DPLEF:1; /* deprecated name - please avoid */ 18641 #endif 18642 #ifndef USE_FIELD_ALIASES_FR 18643 uint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */ 18644 #else 18645 uint16_t SPLEF:1; /* deprecated name - please avoid */ 18646 #endif 18647 #ifndef USE_FIELD_ALIASES_FR 18648 uint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */ 18649 #else 18650 uint16_t NMLEF:1; /* deprecated name - please avoid */ 18651 #endif 18652 #ifndef USE_FIELD_ALIASES_FR 18653 uint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */ 18654 #else 18655 uint16_t NMFEF:1; /* deprecated name - please avoid */ 18656 #endif 18657 #ifndef USE_FIELD_ALIASES_FR 18658 uint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */ 18659 #else 18660 uint16_t ILSAEF:1; /* deprecated name - please avoid */ 18661 #endif 18662 } B; 18663 } FR_CHIERFR_16B_tag; 18664 18665 typedef union { /* Message Buffer Interrupt Vector Register */ 18666 uint16_t R; 18667 struct { 18668 uint16_t:2; 18669 uint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */ 18670 uint16_t:2; 18671 uint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */ 18672 } B; 18673 } FR_MBIVEC_16B_tag; 18674 18675 typedef union { /* Channel A Status Error Counter Register */ 18676 uint16_t R; 18677 struct { 18678 uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ 18679 } B; 18680 } FR_CASERCR_16B_tag; 18681 18682 typedef union { /* Channel B Status Error Counter Register */ 18683 uint16_t R; 18684 struct { 18685 uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ 18686 } B; 18687 } FR_CBSERCR_16B_tag; 18688 18689 typedef union { /* Protocol Status Register 0 */ 18690 uint16_t R; 18691 struct { 18692 uint16_t ERRMODE:2; /* Error Mode */ 18693 uint16_t SLOTMODE:2; /* Slot Mode */ 18694 uint16_t:1; 18695 uint16_t PROTSTATE:3; /* Protocol State */ 18696 #ifndef USE_FIELD_ALIASES_FR 18697 uint16_t STARTUPSTATE:4; /* Startup State */ 18698 #else 18699 uint16_t SUBSTATE:4; /* deprecated name - please avoid */ 18700 #endif 18701 uint16_t WAKEUPSTATE:4; /* Wakeup Status */ 18702 } B; 18703 } FR_PSR0_16B_tag; 18704 18705 typedef union { /* Protocol Status Register 1 */ 18706 uint16_t R; 18707 struct { 18708 uint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */ 18709 uint16_t CSP:1; /* Leading Coldstart Path */ 18710 uint16_t:1; 18711 uint16_t REMCSAT:5; /* Remaining Coldstart Attempts */ 18712 uint16_t CPN:1; /* Leading Coldstart Path Noise */ 18713 uint16_t HHR:1; /* Host Halt Request Pending */ 18714 uint16_t FRZ:1; /* Freeze Occurred */ 18715 uint16_t APTAC:5; /* Allow Passive to Active Counter */ 18716 } B; 18717 } FR_PSR1_16B_tag; 18718 18719 typedef union { /* Protocol Status Register 2 */ 18720 uint16_t R; 18721 struct { 18722 uint16_t NBVB:1; /* NIT Boundary Violation on Channel B */ 18723 uint16_t NSEB:1; /* NIT Syntax Error on Channel B */ 18724 uint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */ 18725 #ifndef USE_FIELD_ALIASES_FR 18726 uint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */ 18727 #else 18728 uint16_t SBVB:1; /* deprecated name - please avoid */ 18729 #endif 18730 uint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */ 18731 uint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */ 18732 uint16_t NBVA:1; /* NIT Boundary Violation on Channel A */ 18733 uint16_t NSEA:1; /* NIT Syntax Error on Channel A */ 18734 uint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */ 18735 uint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */ 18736 uint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */ 18737 uint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */ 18738 uint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */ 18739 } B; 18740 } FR_PSR2_16B_tag; 18741 18742 typedef union { /* Protocol Status Register 3 */ 18743 uint16_t R; 18744 struct { 18745 uint16_t:2; 18746 uint16_t WUB:1; /* Wakeup Symbol Received on Channel B */ 18747 uint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */ 18748 uint16_t AACB:1; /* Aggregated Additional Communication on Channel B */ 18749 uint16_t ACEB:1; /* Aggregated Content Error on Channel B */ 18750 uint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */ 18751 uint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */ 18752 uint16_t:2; 18753 uint16_t WUA:1; /* Wakeup Symbol Received on Channel A */ 18754 uint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */ 18755 uint16_t AACA:1; /* Aggregated Additional Communication on Channel A */ 18756 uint16_t ACEA:1; /* Aggregated Content Error on Channel A */ 18757 uint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */ 18758 uint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */ 18759 } B; 18760 } FR_PSR3_16B_tag; 18761 18762 typedef union { /* Macrotick Counter Register */ 18763 uint16_t R; 18764 struct { 18765 uint16_t:2; 18766 uint16_t MTCT:14; /* Macrotick Counter */ 18767 } B; 18768 } FR_MTCTR_16B_tag; 18769 18770 typedef union { /* Cycle Counter Register */ 18771 uint16_t R; 18772 struct { 18773 uint16_t:10; 18774 uint16_t CYCCNT:6; /* Cycle Counter */ 18775 } B; 18776 } FR_CYCTR_16B_tag; 18777 18778 typedef union { /* Slot Counter Channel A Register */ 18779 uint16_t R; 18780 struct { 18781 uint16_t:5; 18782 uint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */ 18783 } B; 18784 } FR_SLTCTAR_16B_tag; 18785 18786 typedef union { /* Slot Counter Channel B Register */ 18787 uint16_t R; 18788 struct { 18789 uint16_t:5; 18790 uint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */ 18791 } B; 18792 } FR_SLTCTBR_16B_tag; 18793 18794 typedef union { /* Rate Correction Value Register */ 18795 uint16_t R; 18796 struct { 18797 uint16_t RATECORR:16; /* Rate Correction Value */ 18798 } B; 18799 } FR_RTCORVR_16B_tag; 18800 18801 typedef union { /* Offset Correction Value Register */ 18802 uint16_t R; 18803 struct { 18804 uint16_t:6; 18805 uint16_t OFFSETCORR:10; /* Offset Correction Value */ 18806 } B; 18807 } FR_OFCORVR_16B_tag; 18808 18809 typedef union { /* Combined Interrupt Flag Register */ 18810 uint16_t R; 18811 struct { 18812 uint16_t:8; 18813 #ifndef USE_FIELD_ALIASES_FR 18814 uint16_t MIF:1; /* Module Interrupt Flag */ 18815 #else 18816 uint16_t MIFR:1; /* deprecated name - please avoid */ 18817 #endif 18818 #ifndef USE_FIELD_ALIASES_FR 18819 uint16_t PRIF:1; /* Protocol Interrupt Flag */ 18820 #else 18821 uint16_t PRIFR:1; /* deprecated name - please avoid */ 18822 #endif 18823 #ifndef USE_FIELD_ALIASES_FR 18824 uint16_t CHIF:1; /* CHI Interrupt Flag */ 18825 #else 18826 uint16_t CHIFR:1; /* deprecated name - please avoid */ 18827 #endif 18828 #ifndef USE_FIELD_ALIASES_FR 18829 uint16_t WUPIF:1; /* Wakeup Interrupt Flag */ 18830 #else 18831 uint16_t WUPIFR:1; /* deprecated name - please avoid */ 18832 #endif 18833 #ifndef USE_FIELD_ALIASES_FR 18834 uint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */ 18835 #else 18836 uint16_t FNEBIFR:1; /* deprecated name - please avoid */ 18837 #endif 18838 #ifndef USE_FIELD_ALIASES_FR 18839 uint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */ 18840 #else 18841 uint16_t FNEAIFR:1; /* deprecated name - please avoid */ 18842 #endif 18843 #ifndef USE_FIELD_ALIASES_FR 18844 uint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */ 18845 #else 18846 uint16_t RBIFR:1; /* deprecated name - please avoid */ 18847 #endif 18848 #ifndef USE_FIELD_ALIASES_FR 18849 uint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */ 18850 #else 18851 uint16_t TBIFR:1; /* deprecated name - please avoid */ 18852 #endif 18853 } B; 18854 } FR_CIFR_16B_tag; 18855 18856 typedef union { /* System Memory Access Time-Out Register */ 18857 uint16_t R; 18858 struct { 18859 uint16_t:8; 18860 uint16_t TIMEOUT:8; /* Time-Out */ 18861 } B; 18862 } FR_SYMATOR_16B_tag; 18863 18864 typedef union { /* Sync Frame Counter Register */ 18865 uint16_t R; 18866 struct { 18867 uint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */ 18868 uint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */ 18869 uint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */ 18870 uint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */ 18871 } B; 18872 } FR_SFCNTR_16B_tag; 18873 18874 typedef union { /* Sync Frame Table Offset Register */ 18875 uint16_t R; 18876 struct { 18877 uint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */ 18878 uint16_t:1; 18879 } B; 18880 } FR_SFTOR_16B_tag; 18881 18882 typedef union { /* Sync Frame Table Configuration, Control, Status Register */ 18883 uint16_t R; 18884 struct { 18885 uint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */ 18886 uint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */ 18887 uint16_t CYCNUM:6; /* Cycle Number */ 18888 uint16_t ELKS:1; /* Even Cycle Tables Lock Status */ 18889 uint16_t OLKS:1; /* Odd Cycle Tables Lock Status */ 18890 uint16_t EVAL:1; /* Even Cycle Tables Valid */ 18891 uint16_t OVAL:1; /* Odd Cycle Tables Valid */ 18892 uint16_t:1; 18893 uint16_t OPT:1; /* One Pair Trigger */ 18894 uint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */ 18895 #ifndef USE_FIELD_ALIASES_FR 18896 uint16_t SIVEN:1; /* Sync Frame ID Table Enable */ 18897 #else 18898 uint16_t SIDEN:1; /* deprecated name - please avoid */ 18899 #endif 18900 } B; 18901 } FR_SFTCCSR_16B_tag; 18902 18903 typedef union { /* Sync Frame ID Rejection Filter */ 18904 uint16_t R; 18905 struct { 18906 uint16_t:6; 18907 uint16_t SYNFRID:10; /* Sync Frame Rejection ID */ 18908 } B; 18909 } FR_SFIDRFR_16B_tag; 18910 18911 typedef union { /* Sync Frame ID Acceptance Filter Value Register */ 18912 uint16_t R; 18913 struct { 18914 uint16_t:6; 18915 uint16_t FVAL:10; /* Filter Value */ 18916 } B; 18917 } FR_SFIDAFVR_16B_tag; 18918 18919 typedef union { /* Sync Frame ID Acceptance Filter Mask Register */ 18920 uint16_t R; 18921 struct { 18922 uint16_t:6; 18923 uint16_t FMSK:10; /* Filter Mask */ 18924 } B; 18925 } FR_SFIDAFMR_16B_tag; 18926 18927 typedef union { /* Network Management Vector Register0 */ 18928 uint16_t R; 18929 struct { 18930 uint16_t NMVP_15_8:8; /* Network Management Vector Part */ 18931 uint16_t NMVP_7_0:8; /* Network Management Vector Part */ 18932 } B; 18933 } FR_NMVR0_16B_tag; 18934 18935 typedef union { /* Network Management Vector Register1 */ 18936 uint16_t R; 18937 struct { 18938 uint16_t NMVP_15_8:8; /* Network Management Vector Part */ 18939 uint16_t NMVP_7_0:8; /* Network Management Vector Part */ 18940 } B; 18941 } FR_NMVR1_16B_tag; 18942 18943 typedef union { /* Network Management Vector Register2 */ 18944 uint16_t R; 18945 struct { 18946 uint16_t NMVP_15_8:8; /* Network Management Vector Part */ 18947 uint16_t NMVP_7_0:8; /* Network Management Vector Part */ 18948 } B; 18949 } FR_NMVR2_16B_tag; 18950 18951 typedef union { /* Network Management Vector Register3 */ 18952 uint16_t R; 18953 struct { 18954 uint16_t NMVP_15_8:8; /* Network Management Vector Part */ 18955 uint16_t NMVP_7_0:8; /* Network Management Vector Part */ 18956 } B; 18957 } FR_NMVR3_16B_tag; 18958 18959 typedef union { /* Network Management Vector Register4 */ 18960 uint16_t R; 18961 struct { 18962 uint16_t NMVP_15_8:8; /* Network Management Vector Part */ 18963 uint16_t NMVP_7_0:8; /* Network Management Vector Part */ 18964 } B; 18965 } FR_NMVR4_16B_tag; 18966 18967 typedef union { /* Network Management Vector Register5 */ 18968 uint16_t R; 18969 struct { 18970 uint16_t NMVP_15_8:8; /* Network Management Vector Part */ 18971 uint16_t NMVP_7_0:8; /* Network Management Vector Part */ 18972 } B; 18973 } FR_NMVR5_16B_tag; 18974 18975 typedef union { /* Network Management Vector Length Register */ 18976 uint16_t R; 18977 struct { 18978 uint16_t:12; 18979 uint16_t NMVL:4; /* Network Management Vector Length */ 18980 } B; 18981 } FR_NMVLR_16B_tag; 18982 18983 typedef union { /* Timer Configuration and Control Register */ 18984 uint16_t R; 18985 struct { 18986 uint16_t:2; 18987 #ifndef USE_FIELD_ALIASES_FR 18988 uint16_t T2_CFG:1; /* Timer T2 Configuration */ 18989 #else 18990 uint16_t T2CFG:1; /* Timer T2 Configuration */ 18991 #endif 18992 #ifndef USE_FIELD_ALIASES_FR 18993 uint16_t T2_REP:1; /* Timer T2 Repetitive Mode */ 18994 #else 18995 uint16_t T2REP:1; /* Timer T2 Configuration */ 18996 #endif 18997 uint16_t:1; 18998 uint16_t T2SP:1; /* Timer T2 Stop */ 18999 uint16_t T2TR:1; /* Timer T2 Trigger */ 19000 uint16_t T2ST:1; /* Timer T2 State */ 19001 uint16_t:3; 19002 #ifndef USE_FIELD_ALIASES_FR 19003 uint16_t T1_REP:1; /* Timer T1 Repetitive Mode */ 19004 #else 19005 uint16_t T1REP:1; 19006 #endif 19007 uint16_t:1; 19008 uint16_t T1SP:1; /* Timer T1 Stop */ 19009 uint16_t T1TR:1; /* Timer T1 Trigger */ 19010 uint16_t T1ST:1; /* Timer T1 State */ 19011 } B; 19012 } FR_TICCR_16B_tag; 19013 19014 typedef union { /* Timer 1 Cycle Set Register */ 19015 uint16_t R; 19016 struct { 19017 uint16_t:2; 19018 #ifndef USE_FIELD_ALIASES_FR 19019 uint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */ 19020 #else 19021 uint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */ 19022 #endif 19023 uint16_t:2; 19024 #ifndef USE_FIELD_ALIASES_FR 19025 uint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */ 19026 #else 19027 uint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */ 19028 #endif 19029 } B; 19030 } FR_TI1CYSR_16B_tag; 19031 19032 typedef union { /* Timer 1 Macrotick Offset Register */ 19033 uint16_t R; 19034 struct { 19035 uint16_t:2; 19036 uint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */ 19037 } B; 19038 } FR_TI1MTOR_16B_tag; 19039 19040 typedef union { /* Timer 2 Configuration Register 0 */ 19041 uint16_t R; 19042 struct { 19043 uint16_t:2; 19044 uint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */ 19045 uint16_t:2; 19046 uint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */ 19047 } B; 19048 } FR_TI2CR0_16B_tag; 19049 19050 typedef union { /* Timer 2 Configuration Register 1 */ 19051 uint16_t R; 19052 struct { 19053 uint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */ 19054 } B; 19055 } FR_TI2CR1_16B_tag; 19056 19057 typedef union { /* Slot Status Selection Register */ 19058 uint16_t R; 19059 struct { 19060 uint16_t WMD:1; /* Write Mode */ 19061 uint16_t:1; 19062 uint16_t SEL:2; /* Selector */ 19063 uint16_t:1; 19064 uint16_t SLOTNUMBER:11; /* Slot Number */ 19065 } B; 19066 } FR_SSSR_16B_tag; 19067 19068 typedef union { /* Slot Status Counter Condition Register */ 19069 uint16_t R; 19070 struct { 19071 uint16_t WMD:1; /* Write Mode */ 19072 uint16_t:1; 19073 uint16_t SEL:2; /* Selector */ 19074 uint16_t:1; 19075 uint16_t CNTCFG:2; /* Counter Configuration */ 19076 uint16_t MCY:1; /* Multi Cycle Selection */ 19077 uint16_t VFR:1; /* Valid Frame Restriction */ 19078 uint16_t SYF:1; /* Sync Frame Restriction */ 19079 uint16_t NUF:1; /* Null Frame Restriction */ 19080 uint16_t SUF:1; /* Startup Frame Restriction */ 19081 uint16_t STATUSMASK:4; /* Slot Status Mask */ 19082 } B; 19083 } FR_SSCCR_16B_tag; 19084 19085 typedef union { /* Slot Status Register0 */ 19086 uint16_t R; 19087 struct { 19088 uint16_t VFB:1; /* Valid Frame on Channel B */ 19089 uint16_t SYB:1; /* Sync Frame Indicator Channel B */ 19090 uint16_t NFB:1; /* Null Frame Indicator Channel B */ 19091 uint16_t SUB:1; /* Startup Frame Indicator Channel B */ 19092 uint16_t SEB:1; /* Syntax Error on Channel B */ 19093 uint16_t CEB:1; /* Content Error on Channel B */ 19094 uint16_t BVB:1; /* Boundary Violation on Channel B */ 19095 uint16_t TCB:1; /* Transmission Conflict on Channel B */ 19096 uint16_t VFA:1; /* Valid Frame on Channel A */ 19097 uint16_t SYA:1; /* Sync Frame Indicator Channel A */ 19098 uint16_t NFA:1; /* Null Frame Indicator Channel A */ 19099 uint16_t SUA:1; /* Startup Frame Indicator Channel A */ 19100 uint16_t SEA:1; /* Syntax Error on Channel A */ 19101 uint16_t CEA:1; /* Content Error on Channel A */ 19102 uint16_t BVA:1; /* Boundary Violation on Channel A */ 19103 uint16_t TCA:1; /* Transmission Conflict on Channel A */ 19104 } B; 19105 } FR_SSR_16B_tag; 19106 19107 19108 19109 typedef union { /* Slot Status Counter Register0 */ 19110 uint16_t R; 19111 struct { 19112 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ 19113 } B; 19114 } FR_SSCR0_16B_tag; 19115 19116 typedef union { /* Slot Status Counter Register1 */ 19117 uint16_t R; 19118 struct { 19119 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ 19120 } B; 19121 } FR_SSCR1_16B_tag; 19122 19123 typedef union { /* Slot Status Counter Register2 */ 19124 uint16_t R; 19125 struct { 19126 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ 19127 } B; 19128 } FR_SSCR2_16B_tag; 19129 19130 typedef union { /* Slot Status Counter Register3 */ 19131 uint16_t R; 19132 struct { 19133 uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ 19134 } B; 19135 } FR_SSCR3_16B_tag; 19136 19137 typedef union { /* MTS A Configuration Register */ 19138 uint16_t R; 19139 struct { 19140 uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ 19141 uint16_t:1; 19142 uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ 19143 uint16_t:2; 19144 uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ 19145 } B; 19146 } FR_MTSACFR_16B_tag; 19147 19148 typedef union { /* MTS B Configuration Register */ 19149 uint16_t R; 19150 struct { 19151 uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ 19152 uint16_t:1; 19153 uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ 19154 uint16_t:2; 19155 uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ 19156 } B; 19157 } FR_MTSBCFR_16B_tag; 19158 19159 typedef union { /* Receive Shadow Buffer Index Register */ 19160 uint16_t R; 19161 struct { 19162 uint16_t WMD:1; /* Write Mode */ 19163 uint16_t:1; 19164 uint16_t SEL:2; /* Selector */ 19165 uint16_t:5; 19166 uint16_t RSBIDX:7; /* Receive Shadow Buffer Index */ 19167 } B; 19168 } FR_RSBIR_16B_tag; 19169 19170 typedef union { /* Receive FIFO Watermark and Selection Register */ 19171 uint16_t R; 19172 struct { 19173 uint16_t WM:8; /* Watermark Value */ 19174 uint16_t:7; 19175 uint16_t SEL:1; /* Select */ 19176 } B; 19177 } FR_RFWMSR_16B_tag; 19178 19179 typedef union { /* Receive FIFO Start Index Register */ 19180 uint16_t R; 19181 struct { 19182 uint16_t:6; 19183 uint16_t SIDX:10; /* Start Index */ 19184 } B; 19185 } FR_RF_RFSIR_16B_tag; 19186 19187 typedef union { /* Receive FIFO Depth and Size Register */ 19188 uint16_t R; 19189 struct { 19190 #ifndef USE_FIELD_ALIASES_FR 19191 uint16_t FIFO_DEPTH:8; /* FIFO Depth */ 19192 #else 19193 uint16_t FIFODEPTH:8; /* deprecated name - please avoid */ 19194 #endif 19195 uint16_t:1; 19196 #ifndef USE_FIELD_ALIASES_FR 19197 uint16_t ENTRY_SIZE:7; /* Entry Size */ 19198 #else 19199 uint16_t ENTRYSIZE:7; /* deprecated name - please avoid */ 19200 #endif 19201 } B; 19202 } FR_RFDSR_16B_tag; 19203 19204 typedef union { /* Receive FIFO A Read Index Register */ 19205 uint16_t R; 19206 struct { 19207 uint16_t:6; 19208 uint16_t RDIDX:10; /* Read Index */ 19209 } B; 19210 } FR_RFARIR_16B_tag; 19211 19212 typedef union { /* Receive FIFO B Read Index Register */ 19213 uint16_t R; 19214 struct { 19215 uint16_t:6; 19216 uint16_t RDIDX:10; /* Read Index */ 19217 } B; 19218 } FR_RFBRIR_16B_tag; 19219 19220 typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */ 19221 uint16_t R; 19222 struct { 19223 uint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */ 19224 } B; 19225 } FR_RFMIDAFVR_16B_tag; 19226 19227 typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */ 19228 uint16_t R; 19229 struct { 19230 uint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */ 19231 } B; 19232 } FR_RFMIDAFMR_16B_tag; 19233 19234 typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */ 19235 uint16_t R; 19236 struct { 19237 uint16_t:5; 19238 uint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */ 19239 } B; 19240 } FR_RFFIDRFVR_16B_tag; 19241 19242 typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */ 19243 uint16_t R; 19244 struct { 19245 uint16_t:5; 19246 uint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */ 19247 } B; 19248 } FR_RFFIDRFMR_16B_tag; 19249 19250 typedef union { /* Receive FIFO Range Filter Configuration Register */ 19251 uint16_t R; 19252 struct { 19253 uint16_t WMD:1; /* Write Mode */ 19254 uint16_t IBD:1; /* Interval Boundary */ 19255 uint16_t SEL:2; /* Filter Selector */ 19256 uint16_t:1; 19257 uint16_t SID:11; /* Slot ID */ 19258 } B; 19259 } FR_RFRFCFR_16B_tag; 19260 19261 typedef union { /* Receive FIFO Range Filter Control Register */ 19262 uint16_t R; 19263 struct { 19264 uint16_t:4; 19265 uint16_t F3MD:1; /* Range Filter 3 Mode */ 19266 uint16_t F2MD:1; /* Range Filter 2 Mode */ 19267 uint16_t F1MD:1; /* Range Filter 1 Mode */ 19268 uint16_t F0MD:1; /* Range Filter 0 Mode */ 19269 uint16_t:4; 19270 uint16_t F3EN:1; /* Range Filter 3 Enable */ 19271 uint16_t F2EN:1; /* Range Filter 2 Enable */ 19272 uint16_t F1EN:1; /* Range Filter 1 Enable */ 19273 uint16_t F0EN:1; /* Range Filter 0 Enable */ 19274 } B; 19275 } FR_RFRFCTR_16B_tag; 19276 19277 typedef union { /* Last Dynamic Transmit Slot Channel A Register */ 19278 uint16_t R; 19279 struct { 19280 uint16_t:5; 19281 uint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */ 19282 } B; 19283 } FR_LDTXSLAR_16B_tag; 19284 19285 typedef union { /* Last Dynamic Transmit Slot Channel B Register */ 19286 uint16_t R; 19287 struct { 19288 uint16_t:5; 19289 uint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */ 19290 } B; 19291 } FR_LDTXSLBR_16B_tag; 19292 19293 typedef union { /* Protocol Configuration Register 0 */ 19294 uint16_t R; 19295 struct { 19296 uint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */ 19297 uint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */ 19298 } B; 19299 } FR_PCR0_16B_tag; 19300 19301 typedef union { /* Protocol Configuration Register 1 */ 19302 uint16_t R; 19303 struct { 19304 uint16_t:2; 19305 uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */ 19306 } B; 19307 } FR_PCR1_16B_tag; 19308 19309 typedef union { /* Protocol Configuration Register 2 */ 19310 uint16_t R; 19311 struct { 19312 uint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */ 19313 uint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */ 19314 } B; 19315 } FR_PCR2_16B_tag; 19316 19317 typedef union { /* Protocol Configuration Register 3 */ 19318 uint16_t R; 19319 struct { 19320 uint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */ 19321 #ifndef USE_FIELD_ALIASES_FR 19322 uint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */ 19323 #else 19324 uint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */ 19325 #endif 19326 uint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */ 19327 } B; 19328 } FR_PCR3_16B_tag; 19329 19330 typedef union { /* Protocol Configuration Register 4 */ 19331 uint16_t R; 19332 struct { 19333 uint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */ 19334 uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */ 19335 } B; 19336 } FR_PCR4_16B_tag; 19337 19338 typedef union { /* Protocol Configuration Register 5 */ 19339 uint16_t R; 19340 struct { 19341 uint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */ 19342 uint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */ 19343 uint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */ 19344 } B; 19345 } FR_PCR5_16B_tag; 19346 19347 typedef union { /* Protocol Configuration Register 6 */ 19348 uint16_t R; 19349 struct { 19350 uint16_t:1; 19351 uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */ 19352 uint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */ 19353 } B; 19354 } FR_PCR6_16B_tag; 19355 19356 typedef union { /* Protocol Configuration Register 7 */ 19357 uint16_t R; 19358 struct { 19359 uint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */ 19360 uint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */ 19361 } B; 19362 } FR_PCR7_16B_tag; 19363 19364 typedef union { /* Protocol Configuration Register 8 */ 19365 uint16_t R; 19366 struct { 19367 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */ 19368 uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */ 19369 uint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */ 19370 } B; 19371 } FR_PCR8_16B_tag; 19372 19373 typedef union { /* Protocol Configuration Register 9 */ 19374 uint16_t R; 19375 struct { 19376 uint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */ 19377 uint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */ 19378 uint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */ 19379 } B; 19380 } FR_PCR9_16B_tag; 19381 19382 typedef union { /* Protocol Configuration Register 10 */ 19383 uint16_t R; 19384 struct { 19385 uint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */ 19386 uint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */ 19387 uint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */ 19388 } B; 19389 } FR_PCR10_16B_tag; 19390 19391 typedef union { /* Protocol Configuration Register 11 */ 19392 uint16_t R; 19393 struct { 19394 uint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */ 19395 uint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */ 19396 uint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */ 19397 } B; 19398 } FR_PCR11_16B_tag; 19399 19400 typedef union { /* Protocol Configuration Register 12 */ 19401 uint16_t R; 19402 struct { 19403 uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */ 19404 uint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */ 19405 } B; 19406 } FR_PCR12_16B_tag; 19407 19408 typedef union { /* Protocol Configuration Register 13 */ 19409 uint16_t R; 19410 struct { 19411 uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */ 19412 uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */ 19413 } B; 19414 } FR_PCR13_16B_tag; 19415 19416 typedef union { /* Protocol Configuration Register 14 */ 19417 uint16_t R; 19418 struct { 19419 uint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */ 19420 #ifndef USE_FIELD_ALIASES_FR 19421 uint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */ 19422 #else 19423 uint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */ 19424 #endif 19425 } B; 19426 } FR_PCR14_16B_tag; 19427 19428 typedef union { /* Protocol Configuration Register 15 */ 19429 uint16_t R; 19430 struct { 19431 #ifndef USE_FIELD_ALIASES_FR 19432 uint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */ 19433 #else 19434 uint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ 19435 #endif 19436 } B; 19437 } FR_PCR15_16B_tag; 19438 19439 typedef union { /* Protocol Configuration Register 16 */ 19440 uint16_t R; 19441 struct { 19442 uint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */ 19443 #ifndef USE_FIELD_ALIASES_FR 19444 uint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */ 19445 #else 19446 uint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */ 19447 #endif 19448 } B; 19449 } FR_PCR16_16B_tag; 19450 19451 typedef union { /* Protocol Configuration Register 17 */ 19452 uint16_t R; 19453 struct { 19454 #ifndef USE_FIELD_ALIASES_FR 19455 uint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */ 19456 #else 19457 uint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ 19458 #endif 19459 } B; 19460 } FR_PCR17_16B_tag; 19461 19462 typedef union { /* Protocol Configuration Register 18 */ 19463 uint16_t R; 19464 struct { 19465 uint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */ 19466 uint16_t KEY_SLOT_ID:10; /* pKeySlotId */ 19467 } B; 19468 } FR_PCR18_16B_tag; 19469 19470 typedef union { /* Protocol Configuration Register 19 */ 19471 uint16_t R; 19472 struct { 19473 uint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */ 19474 uint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */ 19475 } B; 19476 } FR_PCR19_16B_tag; 19477 19478 typedef union { /* Protocol Configuration Register 20 */ 19479 uint16_t R; 19480 struct { 19481 uint16_t MICRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */ 19482 uint16_t MICRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */ 19483 } B; 19484 } FR_PCR20_16B_tag; 19485 19486 typedef union { /* Protocol Configuration Register 21 */ 19487 uint16_t R; 19488 struct { 19489 uint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */ 19490 uint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */ 19491 } B; 19492 } FR_PCR21_16B_tag; 19493 19494 typedef union { /* Protocol Configuration Register 22 */ 19495 uint16_t R; 19496 struct { 19497 uint16_t R:1; /* Reserved bit */ 19498 #ifndef USE_FIELD_ALIASES_FR 19499 uint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */ 19500 #else 19501 uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */ 19502 #endif 19503 #ifndef USE_FIELD_ALIASES_FR 19504 uint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */ 19505 #else 19506 uint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */ 19507 #endif 19508 } B; 19509 } FR_PCR22_16B_tag; 19510 19511 typedef union { /* Protocol Configuration Register 23 */ 19512 uint16_t R; 19513 struct { 19514 #ifndef USE_FIELD_ALIASES_FR 19515 uint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */ 19516 #else 19517 uint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */ 19518 #endif 19519 } B; 19520 } FR_PCR23_16B_tag; 19521 19522 typedef union { /* Protocol Configuration Register 24 */ 19523 uint16_t R; 19524 struct { 19525 uint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */ 19526 uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */ 19527 #ifndef USE_FIELD_ALIASES_FR 19528 uint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */ 19529 #else 19530 uint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */ 19531 #endif 19532 } B; 19533 } FR_PCR24_16B_tag; 19534 19535 typedef union { /* Protocol Configuration Register 25 */ 19536 uint16_t R; 19537 struct { 19538 #ifndef USE_FIELD_ALIASES_FR 19539 uint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */ 19540 #else 19541 uint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */ 19542 #endif 19543 } B; 19544 } FR_PCR25_16B_tag; 19545 19546 typedef union { /* Protocol Configuration Register 26 */ 19547 uint16_t R; 19548 struct { 19549 uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */ 19550 uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */ 19551 #ifndef USE_FIELD_ALIASES_FR 19552 uint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */ 19553 #else 19554 uint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */ 19555 #endif 19556 } B; 19557 } FR_PCR26_16B_tag; 19558 19559 typedef union { /* Protocol Configuration Register 27 */ 19560 uint16_t R; 19561 struct { 19562 #ifndef USE_FIELD_ALIASES_FR 19563 uint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */ 19564 #else 19565 uint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */ 19566 #endif 19567 } B; 19568 } FR_PCR27_16B_tag; 19569 19570 typedef union { /* Protocol Configuration Register 28 */ 19571 uint16_t R; 19572 struct { 19573 uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */ 19574 uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */ 19575 } B; 19576 } FR_PCR28_16B_tag; 19577 19578 typedef union { /* Protocol Configuration Register 29 */ 19579 uint16_t R; 19580 struct { 19581 uint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */ 19582 uint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */ 19583 } B; 19584 } FR_PCR29_16B_tag; 19585 19586 typedef union { /* Protocol Configuration Register 30 */ 19587 uint16_t R; 19588 struct { 19589 uint16_t:12; 19590 uint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */ 19591 } B; 19592 } FR_PCR30_16B_tag; 19593 19594 typedef union { /* Receive FIFO System Memory Base Address High Register */ 19595 uint16_t R; 19596 struct { 19597 uint16_t SMBA_31_16:16; /* System Memory Base Address */ 19598 } B; 19599 } FR_RFSYMBHADR_16B_tag; 19600 19601 typedef union { /* Receive FIFO System Memory Base Address Low Register */ 19602 uint16_t R; 19603 struct { 19604 uint16_t:4; 19605 uint16_t SMBA_15_4:12; /* System Memory Base Address */ 19606 } B; 19607 } FR_RFSYMBLADR_16B_tag; 19608 19609 typedef union { /* Receive FIFO Periodic Timer Register */ 19610 uint16_t R; 19611 struct { 19612 uint16_t:2; 19613 uint16_t PTD:14; /* Periodic Timer Duration */ 19614 } B; 19615 } FR_RFPTR_16B_tag; 19616 19617 typedef union { /* Receive FIFO Fill Level and Pop Count Register */ 19618 uint16_t R; 19619 struct { 19620 uint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */ 19621 uint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */ 19622 } B; 19623 } FR_RFFLPCR_16B_tag; 19624 19625 typedef union { /* ECC Error Interrupt Flag and Enable Register */ 19626 uint16_t R; 19627 struct { 19628 uint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */ 19629 uint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */ 19630 uint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */ 19631 uint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */ 19632 uint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */ 19633 uint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */ 19634 uint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */ 19635 uint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */ 19636 uint16_t:4; 19637 uint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */ 19638 uint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */ 19639 uint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */ 19640 uint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */ 19641 } B; 19642 } FR_EEIFER_16B_tag; 19643 19644 typedef union { /* ECC Error Report and Injection Control Register */ 19645 uint16_t R; 19646 struct { 19647 uint16_t BSY:1; /* Register Update Busy */ 19648 uint16_t:5; 19649 uint16_t ERS:2; /* Error Report Select */ 19650 uint16_t:3; 19651 uint16_t ERM:1; /* Error Report Mode */ 19652 uint16_t:2; 19653 uint16_t EIM:1; /* Error Injection Mode */ 19654 uint16_t EIE:1; /* Error Injection Enable */ 19655 } B; 19656 } FR_EERICR_16B_tag; 19657 19658 typedef union { /* ECC Error Report Adress Register */ 19659 uint16_t R; 19660 struct { 19661 uint16_t MID:1; /* Memory Identifier */ 19662 uint16_t BANK:3; /* Memory Bank */ 19663 uint16_t ADDR:12; /* Memory Address */ 19664 } B; 19665 } FR_EERAR_16B_tag; 19666 19667 typedef union { /* ECC Error Report Data Register */ 19668 uint16_t R; 19669 struct { 19670 uint16_t DATA:16; /* Data */ 19671 } B; 19672 } FR_EERDR_16B_tag; 19673 19674 typedef union { /* ECC Error Report Code Register */ 19675 uint16_t R; 19676 struct { 19677 uint16_t:11; 19678 uint16_t CODE:5; /* Code */ 19679 } B; 19680 } FR_EERCR_16B_tag; 19681 19682 typedef union { /* ECC Error Injection Address Register */ 19683 uint16_t R; 19684 struct { 19685 uint16_t MID:1; /* Memory Identifier */ 19686 uint16_t BANK:3; /* Memory Bank */ 19687 uint16_t ADDR:12; /* Memory Address */ 19688 } B; 19689 } FR_EEIAR_16B_tag; 19690 19691 typedef union { /* ECC Error Injection Data Register */ 19692 uint16_t R; 19693 struct { 19694 uint16_t DATA:16; /* Data */ 19695 } B; 19696 } FR_EEIDR_16B_tag; 19697 19698 typedef union { /* ECC Error Injection Code Register */ 19699 uint16_t R; 19700 struct { 19701 uint16_t:11; 19702 uint16_t CODE:5; /* Code */ 19703 } B; 19704 } FR_EEICR_16B_tag; 19705 19706 19707 /* Register layout for all registers MBCCSR... */ 19708 19709 typedef union { /* Message Buffer Configuration Control Status Register */ 19710 uint16_t R; 19711 struct { 19712 uint16_t:1; 19713 uint16_t MCM:1; /* Message Buffer Commit Mode */ 19714 uint16_t MBT:1; /* Message Buffer Type */ 19715 uint16_t MTD:1; /* Message Buffer Transfer Direction */ 19716 uint16_t CMT:1; /* Commit for Transmission */ 19717 uint16_t EDT:1; /* Enable/Disable Trigger */ 19718 uint16_t LCKT:1; /* Lock/Unlock Trigger */ 19719 uint16_t MBIE:1; /* Message Buffer Interrupt Enable */ 19720 uint16_t:3; 19721 uint16_t DUP:1; /* Data Updated */ 19722 uint16_t DVAL:1; /* DataValid */ 19723 uint16_t EDS:1; /* Enable/Disable Status */ 19724 uint16_t LCKS:1; /* LockStatus */ 19725 uint16_t MBIF:1; /* Message Buffer Interrupt Flag */ 19726 } B; 19727 } FR_MBCCSR_16B_tag; 19728 19729 19730 /* Register layout for all registers MBCCFR... */ 19731 19732 typedef union { /* Message Buffer Cycle Counter Filter Register */ 19733 uint16_t R; 19734 struct { 19735 uint16_t MTM:1; /* Message Buffer Transmission Mode */ 19736 #ifndef USE_FIELD_ALIASES_FR 19737 uint16_t CHA:1; /* Channel Assignment */ 19738 #else 19739 uint16_t CHNLA:1; /* deprecated name - please avoid */ 19740 #endif 19741 #ifndef USE_FIELD_ALIASES_FR 19742 uint16_t CHB:1; /* Channel Assignment */ 19743 #else 19744 uint16_t CHNLB:1; /* deprecated name - please avoid */ 19745 #endif 19746 uint16_t CCFE:1; /* Cycle Counter Filtering Enable */ 19747 uint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */ 19748 uint16_t CCFVAL:6; /* Cycle Counter Filtering Value */ 19749 } B; 19750 } FR_MBCCFR_16B_tag; 19751 19752 19753 /* Register layout for all registers MBFIDR... */ 19754 19755 typedef union { /* Message Buffer Frame ID Register */ 19756 uint16_t R; 19757 struct { 19758 uint16_t:5; 19759 uint16_t FID:11; /* Frame ID */ 19760 } B; 19761 } FR_MBFIDR_16B_tag; 19762 19763 19764 /* Register layout for all registers MBIDXR... */ 19765 19766 typedef union { /* Message Buffer Index Register */ 19767 uint16_t R; 19768 struct { 19769 uint16_t:9; 19770 uint16_t MBIDX:7; /* Message Buffer Index */ 19771 } B; 19772 } FR_MBIDXR_16B_tag; 19773 19774 19775 /* Register layout for generated register(s) NMVR... */ 19776 19777 typedef union { /* */ 19778 uint16_t R; 19779 } FR_NMVR_16B_tag; 19780 19781 19782 19783 19784 /* Register layout for generated register(s) SSCR... */ 19785 19786 typedef union { /* */ 19787 uint16_t R; 19788 } FR_SSCR_16B_tag; 19789 19790 19791 typedef struct FR_MB_struct_tag { 19792 19793 /* Message Buffer Configuration Control Status Register */ 19794 FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */ 19795 /* Message Buffer Cycle Counter Filter Register */ 19796 FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */ 19797 /* Message Buffer Frame ID Register */ 19798 FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */ 19799 /* Message Buffer Index Register */ 19800 FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */ 19801 19802 } FR_MB_tag; 19803 19804 19805 typedef struct FR_struct_tag { /* start of FR_tag */ 19806 /* Module Version Number */ 19807 FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */ 19808 /* Module Configuration Register */ 19809 FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */ 19810 union { 19811 FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */ 19812 19813 /* SYSTEM MEMORY BASE ADD HIGH REG */ 19814 FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */ 19815 19816 }; 19817 union { 19818 FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */ 19819 19820 /* SYSTEM MEMORY BASE ADD LOW REG */ 19821 FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */ 19822 19823 }; 19824 /* STROBE SIGNAL CONTROL REGISTER */ 19825 FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */ 19826 int8_t FR_reserved_000A[2]; 19827 /* MESSAGE BUFFER DATA SIZE REGISTER */ 19828 FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */ 19829 /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ 19830 FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */ 19831 union { 19832 /* PE DRAM ACCESS REGISTER */ 19833 FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */ 19834 19835 FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */ 19836 19837 }; 19838 union { 19839 /* PE DRAM DATA REGISTER */ 19840 FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */ 19841 19842 FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */ 19843 19844 }; 19845 /* PROTOCOL OPERATION CONTROL REG */ 19846 FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */ 19847 /* GLOBAL INTERRUPT FLAG & ENABLE REG */ 19848 FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */ 19849 /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ 19850 FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */ 19851 /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ 19852 FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */ 19853 /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ 19854 FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */ 19855 /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ 19856 FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */ 19857 /* CHI ERROR FLAG REGISTER */ 19858 FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */ 19859 /* Message Buffer Interrupt Vector Register */ 19860 FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */ 19861 /* Channel A Status Error Counter Register */ 19862 FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */ 19863 /* Channel B Status Error Counter Register */ 19864 FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */ 19865 /* Protocol Status Register 0 */ 19866 FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */ 19867 /* Protocol Status Register 1 */ 19868 FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */ 19869 /* Protocol Status Register 2 */ 19870 FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */ 19871 /* Protocol Status Register 3 */ 19872 FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */ 19873 /* Macrotick Counter Register */ 19874 FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */ 19875 /* Cycle Counter Register */ 19876 FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */ 19877 /* Slot Counter Channel A Register */ 19878 FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */ 19879 /* Slot Counter Channel B Register */ 19880 FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */ 19881 /* Rate Correction Value Register */ 19882 FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */ 19883 /* Offset Correction Value Register */ 19884 FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */ 19885 union { 19886 FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */ 19887 19888 /* Combined Interrupt Flag Register */ 19889 FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */ 19890 19891 }; 19892 /* System Memory Access Time-Out Register */ 19893 FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */ 19894 /* Sync Frame Counter Register */ 19895 FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */ 19896 /* Sync Frame Table Offset Register */ 19897 FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */ 19898 /* Sync Frame Table Configuration, Control, Status Register */ 19899 FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */ 19900 /* Sync Frame ID Rejection Filter */ 19901 FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */ 19902 /* Sync Frame ID Acceptance Filter Value Register */ 19903 FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */ 19904 /* Sync Frame ID Acceptance Filter Mask Register */ 19905 FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */ 19906 union { 19907 FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */ 19908 19909 struct { 19910 /* Network Management Vector Register0 */ 19911 FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */ 19912 /* Network Management Vector Register1 */ 19913 FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */ 19914 /* Network Management Vector Register2 */ 19915 FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */ 19916 /* Network Management Vector Register3 */ 19917 FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */ 19918 /* Network Management Vector Register4 */ 19919 FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */ 19920 /* Network Management Vector Register5 */ 19921 FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */ 19922 }; 19923 19924 }; 19925 /* Network Management Vector Length Register */ 19926 FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */ 19927 /* Timer Configuration and Control Register */ 19928 FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */ 19929 /* Timer 1 Cycle Set Register */ 19930 FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */ 19931 union { 19932 /* Timer 1 Macrotick Offset Register */ 19933 FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */ 19934 19935 FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */ 19936 19937 }; 19938 /* Timer 2 Configuration Register 0 */ 19939 FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */ 19940 /* Timer 2 Configuration Register 1 */ 19941 FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */ 19942 /* Slot Status Selection Register */ 19943 FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */ 19944 /* Slot Status Counter Condition Register */ 19945 FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */ 19946 union { 19947 FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */ 19948 19949 struct { 19950 /* Slot Status Register0 */ 19951 FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */ 19952 /* Slot Status Register1 */ 19953 FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */ 19954 /* Slot Status Register2 */ 19955 FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */ 19956 /* Slot Status Register3 */ 19957 FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */ 19958 /* Slot Status Register4 */ 19959 FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */ 19960 /* Slot Status Register5 */ 19961 FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */ 19962 /* Slot Status Register6 */ 19963 FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */ 19964 /* Slot Status Register7 */ 19965 FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */ 19966 }; 19967 19968 }; 19969 union { 19970 FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */ 19971 19972 struct { 19973 /* Slot Status Counter Register0 */ 19974 FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */ 19975 /* Slot Status Counter Register1 */ 19976 FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */ 19977 /* Slot Status Counter Register2 */ 19978 FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */ 19979 /* Slot Status Counter Register3 */ 19980 FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */ 19981 }; 19982 19983 }; 19984 /* MTS A Configuration Register */ 19985 FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */ 19986 /* MTS B Configuration Register */ 19987 FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */ 19988 /* Receive Shadow Buffer Index Register */ 19989 FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */ 19990 union { 19991 /* Receive FIFO Watermark and Selection Register */ 19992 FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */ 19993 19994 FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */ 19995 19996 }; 19997 union { 19998 FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */ 19999 20000 /* Receive FIFO Start Index Register */ 20001 FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */ 20002 20003 }; 20004 /* Receive FIFO Depth and Size Register */ 20005 FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */ 20006 /* Receive FIFO A Read Index Register */ 20007 FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */ 20008 /* Receive FIFO B Read Index Register */ 20009 FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */ 20010 /* Receive FIFO Message ID Acceptance Filter Value Register */ 20011 FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */ 20012 union { 20013 /* Receive FIFO Message ID Acceptance Filter Mask Register */ 20014 FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */ 20015 20016 FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */ 20017 20018 }; 20019 /* Receive FIFO Frame ID Rejection Filter Value Register */ 20020 FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */ 20021 /* Receive FIFO Frame ID Rejection Filter Mask Register */ 20022 FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */ 20023 /* Receive FIFO Range Filter Configuration Register */ 20024 FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */ 20025 /* Receive FIFO Range Filter Control Register */ 20026 FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */ 20027 /* Last Dynamic Transmit Slot Channel A Register */ 20028 FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */ 20029 /* Last Dynamic Transmit Slot Channel B Register */ 20030 FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */ 20031 /* Protocol Configuration Register 0 */ 20032 FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */ 20033 /* Protocol Configuration Register 1 */ 20034 FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */ 20035 /* Protocol Configuration Register 2 */ 20036 FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */ 20037 /* Protocol Configuration Register 3 */ 20038 FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */ 20039 /* Protocol Configuration Register 4 */ 20040 FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */ 20041 /* Protocol Configuration Register 5 */ 20042 FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */ 20043 /* Protocol Configuration Register 6 */ 20044 FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */ 20045 /* Protocol Configuration Register 7 */ 20046 FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */ 20047 /* Protocol Configuration Register 8 */ 20048 FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */ 20049 /* Protocol Configuration Register 9 */ 20050 FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */ 20051 /* Protocol Configuration Register 10 */ 20052 FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */ 20053 /* Protocol Configuration Register 11 */ 20054 FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */ 20055 /* Protocol Configuration Register 12 */ 20056 FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */ 20057 /* Protocol Configuration Register 13 */ 20058 FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */ 20059 /* Protocol Configuration Register 14 */ 20060 FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */ 20061 /* Protocol Configuration Register 15 */ 20062 FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */ 20063 /* Protocol Configuration Register 16 */ 20064 FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */ 20065 /* Protocol Configuration Register 17 */ 20066 FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */ 20067 /* Protocol Configuration Register 18 */ 20068 FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */ 20069 /* Protocol Configuration Register 19 */ 20070 FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */ 20071 /* Protocol Configuration Register 20 */ 20072 FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */ 20073 /* Protocol Configuration Register 21 */ 20074 FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */ 20075 /* Protocol Configuration Register 22 */ 20076 FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */ 20077 /* Protocol Configuration Register 23 */ 20078 FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */ 20079 /* Protocol Configuration Register 24 */ 20080 FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */ 20081 /* Protocol Configuration Register 25 */ 20082 FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */ 20083 /* Protocol Configuration Register 26 */ 20084 FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */ 20085 /* Protocol Configuration Register 27 */ 20086 FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */ 20087 /* Protocol Configuration Register 28 */ 20088 FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */ 20089 /* Protocol Configuration Register 29 */ 20090 FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */ 20091 /* Protocol Configuration Register 30 */ 20092 FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */ 20093 int8_t FR_reserved_00DE[10]; 20094 /* Receive FIFO System Memory Base Address High Register */ 20095 FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */ 20096 /* Receive FIFO System Memory Base Address Low Register */ 20097 FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */ 20098 /* Receive FIFO Periodic Timer Register */ 20099 FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */ 20100 /* Receive FIFO Fill Level and Pop Count Register */ 20101 FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */ 20102 /* ECC Error Interrupt Flag and Enable Register */ 20103 FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */ 20104 /* ECC Error Report and Injection Control Register */ 20105 FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */ 20106 /* ECC Error Report Adress Register */ 20107 FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */ 20108 /* ECC Error Report Data Register */ 20109 FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */ 20110 /* ECC Error Report Code Register */ 20111 FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */ 20112 /* ECC Error Injection Address Register */ 20113 FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */ 20114 /* ECC Error Injection Data Register */ 20115 FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */ 20116 /* ECC Error Injection Code Register */ 20117 FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */ 20118 union { 20119 /* Register set MB */ 20120 FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */ 20121 20122 FR_MB_tag MBCCS[64]; /* offset: 0x0100 (0x0008 x 64) */ 20123 20124 struct { 20125 /* Message Buffer Configuration Control Status Register */ 20126 FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */ 20127 /* Message Buffer Cycle Counter Filter Register */ 20128 FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */ 20129 /* Message Buffer Frame ID Register */ 20130 FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */ 20131 /* Message Buffer Index Register */ 20132 FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */ 20133 /* Message Buffer Configuration Control Status Register */ 20134 FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */ 20135 /* Message Buffer Cycle Counter Filter Register */ 20136 FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */ 20137 /* Message Buffer Frame ID Register */ 20138 FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */ 20139 /* Message Buffer Index Register */ 20140 FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */ 20141 /* Message Buffer Configuration Control Status Register */ 20142 FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */ 20143 /* Message Buffer Cycle Counter Filter Register */ 20144 FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */ 20145 /* Message Buffer Frame ID Register */ 20146 FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */ 20147 /* Message Buffer Index Register */ 20148 FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */ 20149 /* Message Buffer Configuration Control Status Register */ 20150 FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */ 20151 /* Message Buffer Cycle Counter Filter Register */ 20152 FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */ 20153 /* Message Buffer Frame ID Register */ 20154 FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */ 20155 /* Message Buffer Index Register */ 20156 FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */ 20157 /* Message Buffer Configuration Control Status Register */ 20158 FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */ 20159 /* Message Buffer Cycle Counter Filter Register */ 20160 FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */ 20161 /* Message Buffer Frame ID Register */ 20162 FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */ 20163 /* Message Buffer Index Register */ 20164 FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */ 20165 /* Message Buffer Configuration Control Status Register */ 20166 FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */ 20167 /* Message Buffer Cycle Counter Filter Register */ 20168 FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */ 20169 /* Message Buffer Frame ID Register */ 20170 FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */ 20171 /* Message Buffer Index Register */ 20172 FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */ 20173 /* Message Buffer Configuration Control Status Register */ 20174 FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */ 20175 /* Message Buffer Cycle Counter Filter Register */ 20176 FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */ 20177 /* Message Buffer Frame ID Register */ 20178 FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */ 20179 /* Message Buffer Index Register */ 20180 FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */ 20181 /* Message Buffer Configuration Control Status Register */ 20182 FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */ 20183 /* Message Buffer Cycle Counter Filter Register */ 20184 FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */ 20185 /* Message Buffer Frame ID Register */ 20186 FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */ 20187 /* Message Buffer Index Register */ 20188 FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */ 20189 /* Message Buffer Configuration Control Status Register */ 20190 FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */ 20191 /* Message Buffer Cycle Counter Filter Register */ 20192 FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */ 20193 /* Message Buffer Frame ID Register */ 20194 FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */ 20195 /* Message Buffer Index Register */ 20196 FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */ 20197 /* Message Buffer Configuration Control Status Register */ 20198 FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */ 20199 /* Message Buffer Cycle Counter Filter Register */ 20200 FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */ 20201 /* Message Buffer Frame ID Register */ 20202 FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */ 20203 /* Message Buffer Index Register */ 20204 FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */ 20205 /* Message Buffer Configuration Control Status Register */ 20206 FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */ 20207 /* Message Buffer Cycle Counter Filter Register */ 20208 FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */ 20209 /* Message Buffer Frame ID Register */ 20210 FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */ 20211 /* Message Buffer Index Register */ 20212 FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */ 20213 /* Message Buffer Configuration Control Status Register */ 20214 FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */ 20215 /* Message Buffer Cycle Counter Filter Register */ 20216 FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */ 20217 /* Message Buffer Frame ID Register */ 20218 FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */ 20219 /* Message Buffer Index Register */ 20220 FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */ 20221 /* Message Buffer Configuration Control Status Register */ 20222 FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */ 20223 /* Message Buffer Cycle Counter Filter Register */ 20224 FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */ 20225 /* Message Buffer Frame ID Register */ 20226 FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */ 20227 /* Message Buffer Index Register */ 20228 FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */ 20229 /* Message Buffer Configuration Control Status Register */ 20230 FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */ 20231 /* Message Buffer Cycle Counter Filter Register */ 20232 FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */ 20233 /* Message Buffer Frame ID Register */ 20234 FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */ 20235 /* Message Buffer Index Register */ 20236 FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */ 20237 /* Message Buffer Configuration Control Status Register */ 20238 FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */ 20239 /* Message Buffer Cycle Counter Filter Register */ 20240 FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */ 20241 /* Message Buffer Frame ID Register */ 20242 FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */ 20243 /* Message Buffer Index Register */ 20244 FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */ 20245 /* Message Buffer Configuration Control Status Register */ 20246 FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */ 20247 /* Message Buffer Cycle Counter Filter Register */ 20248 FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */ 20249 /* Message Buffer Frame ID Register */ 20250 FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */ 20251 /* Message Buffer Index Register */ 20252 FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */ 20253 /* Message Buffer Configuration Control Status Register */ 20254 FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */ 20255 /* Message Buffer Cycle Counter Filter Register */ 20256 FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */ 20257 /* Message Buffer Frame ID Register */ 20258 FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */ 20259 /* Message Buffer Index Register */ 20260 FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */ 20261 /* Message Buffer Configuration Control Status Register */ 20262 FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */ 20263 /* Message Buffer Cycle Counter Filter Register */ 20264 FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */ 20265 /* Message Buffer Frame ID Register */ 20266 FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */ 20267 /* Message Buffer Index Register */ 20268 FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */ 20269 /* Message Buffer Configuration Control Status Register */ 20270 FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */ 20271 /* Message Buffer Cycle Counter Filter Register */ 20272 FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */ 20273 /* Message Buffer Frame ID Register */ 20274 FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */ 20275 /* Message Buffer Index Register */ 20276 FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */ 20277 /* Message Buffer Configuration Control Status Register */ 20278 FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */ 20279 /* Message Buffer Cycle Counter Filter Register */ 20280 FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */ 20281 /* Message Buffer Frame ID Register */ 20282 FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */ 20283 /* Message Buffer Index Register */ 20284 FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */ 20285 /* Message Buffer Configuration Control Status Register */ 20286 FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */ 20287 /* Message Buffer Cycle Counter Filter Register */ 20288 FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */ 20289 /* Message Buffer Frame ID Register */ 20290 FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */ 20291 /* Message Buffer Index Register */ 20292 FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */ 20293 /* Message Buffer Configuration Control Status Register */ 20294 FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */ 20295 /* Message Buffer Cycle Counter Filter Register */ 20296 FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */ 20297 /* Message Buffer Frame ID Register */ 20298 FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */ 20299 /* Message Buffer Index Register */ 20300 FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */ 20301 /* Message Buffer Configuration Control Status Register */ 20302 FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */ 20303 /* Message Buffer Cycle Counter Filter Register */ 20304 FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */ 20305 /* Message Buffer Frame ID Register */ 20306 FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */ 20307 /* Message Buffer Index Register */ 20308 FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */ 20309 /* Message Buffer Configuration Control Status Register */ 20310 FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */ 20311 /* Message Buffer Cycle Counter Filter Register */ 20312 FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */ 20313 /* Message Buffer Frame ID Register */ 20314 FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */ 20315 /* Message Buffer Index Register */ 20316 FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */ 20317 /* Message Buffer Configuration Control Status Register */ 20318 FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */ 20319 /* Message Buffer Cycle Counter Filter Register */ 20320 FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */ 20321 /* Message Buffer Frame ID Register */ 20322 FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */ 20323 /* Message Buffer Index Register */ 20324 FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */ 20325 /* Message Buffer Configuration Control Status Register */ 20326 FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */ 20327 /* Message Buffer Cycle Counter Filter Register */ 20328 FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */ 20329 /* Message Buffer Frame ID Register */ 20330 FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */ 20331 /* Message Buffer Index Register */ 20332 FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */ 20333 /* Message Buffer Configuration Control Status Register */ 20334 FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */ 20335 /* Message Buffer Cycle Counter Filter Register */ 20336 FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */ 20337 /* Message Buffer Frame ID Register */ 20338 FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */ 20339 /* Message Buffer Index Register */ 20340 FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */ 20341 /* Message Buffer Configuration Control Status Register */ 20342 FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */ 20343 /* Message Buffer Cycle Counter Filter Register */ 20344 FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */ 20345 /* Message Buffer Frame ID Register */ 20346 FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */ 20347 /* Message Buffer Index Register */ 20348 FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */ 20349 /* Message Buffer Configuration Control Status Register */ 20350 FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */ 20351 /* Message Buffer Cycle Counter Filter Register */ 20352 FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */ 20353 /* Message Buffer Frame ID Register */ 20354 FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */ 20355 /* Message Buffer Index Register */ 20356 FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */ 20357 /* Message Buffer Configuration Control Status Register */ 20358 FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */ 20359 /* Message Buffer Cycle Counter Filter Register */ 20360 FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */ 20361 /* Message Buffer Frame ID Register */ 20362 FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */ 20363 /* Message Buffer Index Register */ 20364 FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */ 20365 /* Message Buffer Configuration Control Status Register */ 20366 FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */ 20367 /* Message Buffer Cycle Counter Filter Register */ 20368 FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */ 20369 /* Message Buffer Frame ID Register */ 20370 FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */ 20371 /* Message Buffer Index Register */ 20372 FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */ 20373 /* Message Buffer Configuration Control Status Register */ 20374 FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */ 20375 /* Message Buffer Cycle Counter Filter Register */ 20376 FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */ 20377 /* Message Buffer Frame ID Register */ 20378 FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */ 20379 /* Message Buffer Index Register */ 20380 FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */ 20381 /* Message Buffer Configuration Control Status Register */ 20382 FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */ 20383 /* Message Buffer Cycle Counter Filter Register */ 20384 FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */ 20385 /* Message Buffer Frame ID Register */ 20386 FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */ 20387 /* Message Buffer Index Register */ 20388 FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */ 20389 /* Message Buffer Configuration Control Status Register */ 20390 FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */ 20391 /* Message Buffer Cycle Counter Filter Register */ 20392 FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */ 20393 /* Message Buffer Frame ID Register */ 20394 FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */ 20395 /* Message Buffer Index Register */ 20396 FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */ 20397 /* Message Buffer Configuration Control Status Register */ 20398 FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */ 20399 /* Message Buffer Cycle Counter Filter Register */ 20400 FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */ 20401 /* Message Buffer Frame ID Register */ 20402 FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */ 20403 /* Message Buffer Index Register */ 20404 FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */ 20405 /* Message Buffer Configuration Control Status Register */ 20406 FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */ 20407 /* Message Buffer Cycle Counter Filter Register */ 20408 FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */ 20409 /* Message Buffer Frame ID Register */ 20410 FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */ 20411 /* Message Buffer Index Register */ 20412 FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */ 20413 /* Message Buffer Configuration Control Status Register */ 20414 FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */ 20415 /* Message Buffer Cycle Counter Filter Register */ 20416 FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */ 20417 /* Message Buffer Frame ID Register */ 20418 FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */ 20419 /* Message Buffer Index Register */ 20420 FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */ 20421 /* Message Buffer Configuration Control Status Register */ 20422 FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */ 20423 /* Message Buffer Cycle Counter Filter Register */ 20424 FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */ 20425 /* Message Buffer Frame ID Register */ 20426 FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */ 20427 /* Message Buffer Index Register */ 20428 FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */ 20429 /* Message Buffer Configuration Control Status Register */ 20430 FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */ 20431 /* Message Buffer Cycle Counter Filter Register */ 20432 FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */ 20433 /* Message Buffer Frame ID Register */ 20434 FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */ 20435 /* Message Buffer Index Register */ 20436 FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */ 20437 /* Message Buffer Configuration Control Status Register */ 20438 FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */ 20439 /* Message Buffer Cycle Counter Filter Register */ 20440 FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */ 20441 /* Message Buffer Frame ID Register */ 20442 FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */ 20443 /* Message Buffer Index Register */ 20444 FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */ 20445 /* Message Buffer Configuration Control Status Register */ 20446 FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */ 20447 /* Message Buffer Cycle Counter Filter Register */ 20448 FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */ 20449 /* Message Buffer Frame ID Register */ 20450 FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */ 20451 /* Message Buffer Index Register */ 20452 FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */ 20453 /* Message Buffer Configuration Control Status Register */ 20454 FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */ 20455 /* Message Buffer Cycle Counter Filter Register */ 20456 FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */ 20457 /* Message Buffer Frame ID Register */ 20458 FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */ 20459 /* Message Buffer Index Register */ 20460 FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */ 20461 /* Message Buffer Configuration Control Status Register */ 20462 FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */ 20463 /* Message Buffer Cycle Counter Filter Register */ 20464 FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */ 20465 /* Message Buffer Frame ID Register */ 20466 FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */ 20467 /* Message Buffer Index Register */ 20468 FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */ 20469 /* Message Buffer Configuration Control Status Register */ 20470 FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */ 20471 /* Message Buffer Cycle Counter Filter Register */ 20472 FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */ 20473 /* Message Buffer Frame ID Register */ 20474 FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */ 20475 /* Message Buffer Index Register */ 20476 FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */ 20477 /* Message Buffer Configuration Control Status Register */ 20478 FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */ 20479 /* Message Buffer Cycle Counter Filter Register */ 20480 FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */ 20481 /* Message Buffer Frame ID Register */ 20482 FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */ 20483 /* Message Buffer Index Register */ 20484 FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */ 20485 /* Message Buffer Configuration Control Status Register */ 20486 FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */ 20487 /* Message Buffer Cycle Counter Filter Register */ 20488 FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */ 20489 /* Message Buffer Frame ID Register */ 20490 FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */ 20491 /* Message Buffer Index Register */ 20492 FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */ 20493 /* Message Buffer Configuration Control Status Register */ 20494 FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */ 20495 /* Message Buffer Cycle Counter Filter Register */ 20496 FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */ 20497 /* Message Buffer Frame ID Register */ 20498 FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */ 20499 /* Message Buffer Index Register */ 20500 FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */ 20501 /* Message Buffer Configuration Control Status Register */ 20502 FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */ 20503 /* Message Buffer Cycle Counter Filter Register */ 20504 FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */ 20505 /* Message Buffer Frame ID Register */ 20506 FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */ 20507 /* Message Buffer Index Register */ 20508 FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */ 20509 /* Message Buffer Configuration Control Status Register */ 20510 FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */ 20511 /* Message Buffer Cycle Counter Filter Register */ 20512 FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */ 20513 /* Message Buffer Frame ID Register */ 20514 FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */ 20515 /* Message Buffer Index Register */ 20516 FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */ 20517 /* Message Buffer Configuration Control Status Register */ 20518 FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */ 20519 /* Message Buffer Cycle Counter Filter Register */ 20520 FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */ 20521 /* Message Buffer Frame ID Register */ 20522 FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */ 20523 /* Message Buffer Index Register */ 20524 FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */ 20525 /* Message Buffer Configuration Control Status Register */ 20526 FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */ 20527 /* Message Buffer Cycle Counter Filter Register */ 20528 FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */ 20529 /* Message Buffer Frame ID Register */ 20530 FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */ 20531 /* Message Buffer Index Register */ 20532 FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */ 20533 /* Message Buffer Configuration Control Status Register */ 20534 FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */ 20535 /* Message Buffer Cycle Counter Filter Register */ 20536 FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */ 20537 /* Message Buffer Frame ID Register */ 20538 FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */ 20539 /* Message Buffer Index Register */ 20540 FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */ 20541 /* Message Buffer Configuration Control Status Register */ 20542 FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */ 20543 /* Message Buffer Cycle Counter Filter Register */ 20544 FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */ 20545 /* Message Buffer Frame ID Register */ 20546 FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */ 20547 /* Message Buffer Index Register */ 20548 FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */ 20549 /* Message Buffer Configuration Control Status Register */ 20550 FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */ 20551 /* Message Buffer Cycle Counter Filter Register */ 20552 FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */ 20553 /* Message Buffer Frame ID Register */ 20554 FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */ 20555 /* Message Buffer Index Register */ 20556 FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */ 20557 /* Message Buffer Configuration Control Status Register */ 20558 FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */ 20559 /* Message Buffer Cycle Counter Filter Register */ 20560 FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */ 20561 /* Message Buffer Frame ID Register */ 20562 FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */ 20563 /* Message Buffer Index Register */ 20564 FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */ 20565 /* Message Buffer Configuration Control Status Register */ 20566 FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */ 20567 /* Message Buffer Cycle Counter Filter Register */ 20568 FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */ 20569 /* Message Buffer Frame ID Register */ 20570 FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */ 20571 /* Message Buffer Index Register */ 20572 FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */ 20573 /* Message Buffer Configuration Control Status Register */ 20574 FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */ 20575 /* Message Buffer Cycle Counter Filter Register */ 20576 FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */ 20577 /* Message Buffer Frame ID Register */ 20578 FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */ 20579 /* Message Buffer Index Register */ 20580 FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */ 20581 /* Message Buffer Configuration Control Status Register */ 20582 FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */ 20583 /* Message Buffer Cycle Counter Filter Register */ 20584 FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */ 20585 /* Message Buffer Frame ID Register */ 20586 FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */ 20587 /* Message Buffer Index Register */ 20588 FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */ 20589 /* Message Buffer Configuration Control Status Register */ 20590 FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */ 20591 /* Message Buffer Cycle Counter Filter Register */ 20592 FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */ 20593 /* Message Buffer Frame ID Register */ 20594 FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */ 20595 /* Message Buffer Index Register */ 20596 FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */ 20597 /* Message Buffer Configuration Control Status Register */ 20598 FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */ 20599 /* Message Buffer Cycle Counter Filter Register */ 20600 FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */ 20601 /* Message Buffer Frame ID Register */ 20602 FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */ 20603 /* Message Buffer Index Register */ 20604 FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */ 20605 /* Message Buffer Configuration Control Status Register */ 20606 FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */ 20607 /* Message Buffer Cycle Counter Filter Register */ 20608 FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */ 20609 /* Message Buffer Frame ID Register */ 20610 FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */ 20611 /* Message Buffer Index Register */ 20612 FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */ 20613 /* Message Buffer Configuration Control Status Register */ 20614 FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */ 20615 /* Message Buffer Cycle Counter Filter Register */ 20616 FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */ 20617 /* Message Buffer Frame ID Register */ 20618 FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */ 20619 /* Message Buffer Index Register */ 20620 FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */ 20621 /* Message Buffer Configuration Control Status Register */ 20622 FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */ 20623 /* Message Buffer Cycle Counter Filter Register */ 20624 FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */ 20625 /* Message Buffer Frame ID Register */ 20626 FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */ 20627 /* Message Buffer Index Register */ 20628 FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */ 20629 /* Message Buffer Configuration Control Status Register */ 20630 FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */ 20631 /* Message Buffer Cycle Counter Filter Register */ 20632 FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */ 20633 /* Message Buffer Frame ID Register */ 20634 FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */ 20635 /* Message Buffer Index Register */ 20636 FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */ 20637 }; 20638 20639 }; 20640 } FR_tag; 20641 20642 20643 #define FR (*(volatile FR_tag *) 0xFFFE0000UL) 20644 20645 20646 20647 20648 20649 #ifdef __MWERKS__ 20650 #pragma pop 20651 #endif 20652 20653 #ifdef __cplusplus 20654 } 20655 #endif 20656 #endif /* ASM */ 20657 #endif /* _leopard_H_*/ 20658 20659 /* End of file */ 20660
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