include/mpc55xx/fsl-mpc555x.h

0001 /*
0002  * Modifications of the original file provided by Freescale are:
0003  *
0004  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0016  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0017  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0018  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0019  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0020  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0021  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0022  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0023  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0024  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0025  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 /**************************************************************************/
0029 /* FILE NAME: mpc5554.h                      COPYRIGHT (c) Freescale 2007 */
0030 /* VERSION:  1.7                                  All Rights Reserved     */
0031 /*                                                                        */
0032 /* DESCRIPTION:                                                           */
0033 /* This file contain all of the register and bit field definitions for    */
0034 /* MPC5554.                                                               */
0035 /*========================================================================*/
0036 /* UPDATE HISTORY                                                         */
0037 /* REV      AUTHOR      DATE       DESCRIPTION OF CHANGE                  */
0038 /* ---   -----------  ---------    ---------------------                  */
0039 /* 0.01  J. Loeliger  03/Mar/03    Initial version of file for MPC5554.   */
0040 /*                                  Based on SoC version 0.7.             */
0041 /* 0.02  J. Loeliger  05/Mar/03    All registers and bit fields now       */
0042 /*                                  defined.                              */
0043 /* 0.03  J. Loeliger  05/May/03    Updated to current spec., fixed several*/
0044 /*                                   bugs and naming/formating issues.    */
0045 /* 0.04  J. Loeliger  16/May/03    More fixes and naming/formating issues.*/
0046 /* 0.05  J. Loeliger  19/Aug/03    Updated for latest documentation.      */
0047 /* 0.06  J. Loeliger  03/Sep/03    Changed to include motint.h            */
0048 /*                                  Updated many register names.          */
0049 /* 0.07  J. Loeliger  04/Nov/03    Changed to include typedefs.h and more */
0050 /*                                  register name updates.                */
0051 /* 0.08  J. Loeliger  25/Feb/04    Added MetroWerks #pragmas.             */
0052 /*                                  Updated for user manual 1.0           */
0053 /* 0.09  J. Loeliger  27/Feb/04    Updated eDMA tcd section and some more */
0054 /*                                  bit field names to match user's man.  */
0055 /* 0.10  J. Loeliger  01/Apr/04    Fixed register spacing in ADC and eTPU */
0056 /* 0.11  J. Loeliger  16/Jun/04    Many fixes and updated to user's       */
0057 /*                                  manual, also some testing done.       */
0058 /* 0.12  J. Loeliger  25/Jun/04    Fixed problems in edma and eTPU.       */
0059 /* 0.13  J. Loeliger  16/Jul/04    Fixed mistake in FlexCAN TIMER size and*/
0060 /*                                  changed eTPU memory defs to start with*/
0061 /*                                  ETPU_                                 */
0062 /* 0.14  J. Loeliger  17/Nov/04    Added ETPU_CODE_RAM definition.        */
0063 /*                                  All code moved to CVS repository.     */
0064 /*                                  Updated copyright to Freescale.       */
0065 /*                                  Added new SCMOFFDATAR register to eTPU*/
0066 /*                                  Fixed REDCR_A&B bit fields in eTPU.   */
0067 /*                                  Added new DBR bit in CTAR for DSPI.   */
0068 /* 0.15  J. Loeliger  29/Nov/04    Added support for new eTPU util funcs. */
0069 /*                                  Added bit fields for FlexCAN buffer ID*/
0070 /* 0.16  J. Loeliger  01/Dec/04    Corrected comments in  release 0.16.   */
0071 /* 0.17  J. Loeliger  02/Dec/04    Moved eTPU variable definitions to a   */
0072 /*                                   seperate new file.                   */
0073 /*                                   Removed SIU variable the GPIO        */
0074 /*                                   routines do not need it.             */
0075 /* 1.0  G.Emerson     22/Feb/05    No real changes to this file.          */
0076 /*                                 Joint generation with mpc5553.h        */
0077 /* 1.1   G. Emerson   6/Jun/05     Changes to SIU to allow for upward     */
0078 /*                                 expansion of PCR/GPDI/GPDO             */
0079 /*                                 Added #defines for memory sizes etc    */
0080 /* 1.2   G. Emerson   21/Sep/05    PBRIDGES fixes                         */
0081 /* 1.3   G. Emerson   03/Jan/06    Pbridge MPCR/PACR/OPACR now generic    */
0082 /*                                 XBAR MPR now generic                   */
0083 /*                                 ECSM has FSBMCR on all integrations    */
0084 /* 1.4   G. Emerson   24/Jan/06    Make Pbridges, XBAR, Flash BIU         */
0085 /*                                 integration specific                   */
0086 /* 1.5   S. Mathieson 28/Jul/06    Split out unused bit to support build  */
0087 /*                                 process. No real change.               */
0088 /* 1.6   S. Mathieson 30/Aug/06    SPR: L1SCR0, updated bit name from DPP */
0089 /*                                 to DPB to align with documentation.    */
0090 /* 1.7   S. Mathieson 26/Feb/07    eDMA TCD format updated to include     */
0091 /*                                 alternate configuration. INTC,         */
0092 /*                                 correction to the number of PSR        */
0093 /*                                 registers.                             */
0094 /**************************************************************************/
0095 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
0096
0097 #ifndef _MPC5554_H_
0098 #define _MPC5554_H_
0099
0100 #ifndef ASM
0101
0102 #include <stdint.h>
0103
0104 #include <mpc55xx/regs-edma.h>
0105
0106 #ifdef  __cplusplus
0107 extern "C" {
0108 #endif
0109
0110 #ifdef __MWERKS__
0111 #pragma push
0112 #pragma ANSI_strict off
0113 #endif
0114
0115 /****************************************************************************/
0116 /*                          MODULE : PBRIDGE_A Peripheral Bridge            */
0117 /****************************************************************************/
0118     struct PBRIDGE_A_tag {
0119         union {
0120             uint32_t R;
0121             struct {
0122                 uint32_t MBW0:1;
0123                 uint32_t MTR0:1;
0124                 uint32_t MTW0:1;
0125                 uint32_t MPL0:1;
0126                 uint32_t MBW1:1;
0127                 uint32_t MTR1:1;
0128                 uint32_t MTW1:1;
0129                 uint32_t MPL1:1;
0130                 uint32_t MBW2:1;
0131                 uint32_t MTR2:1;
0132                 uint32_t MTW2:1;
0133                 uint32_t MPL2:1;
0134                 uint32_t MBW3:1;
0135                 uint32_t MTR3:1;
0136                 uint32_t MTW3:1;
0137                 uint32_t MPL3:1;
0138
0139                   uint32_t:4;
0140
0141                   uint32_t:4;
0142
0143                   uint32_t:4;
0144
0145                   uint32_t:4;
0146             } B;
0147         } MPCR;                 /* Master Privilege Control Register */
0148
0149         uint32_t pbridge_a_reserved2[7];
0150
0151         union {
0152             uint32_t R;
0153             struct {
0154                 uint32_t BW0:1;
0155                 uint32_t SP0:1;
0156                 uint32_t WP0:1;
0157                 uint32_t TP0:1;
0158                   uint32_t:28;
0159             } B;
0160         } PACR0;
0161
0162         uint32_t pbridge_a_reserved3[7];
0163
0164         union {
0165             uint32_t R;
0166             struct {
0167                 uint32_t BW0:1;
0168                 uint32_t SP0:1;
0169                 uint32_t WP0:1;
0170                 uint32_t TP0:1;
0171                 uint32_t BW1:1;
0172                 uint32_t SP1:1;
0173                 uint32_t WP1:1;
0174                 uint32_t TP1:1;
0175                 uint32_t BW2:1;
0176                 uint32_t SP2:1;
0177                 uint32_t WP2:1;
0178                 uint32_t TP2:1;
0179                   uint32_t:4;
0180                 uint32_t BW4:1;
0181                 uint32_t SP4:1;
0182                 uint32_t WP4:1;
0183                 uint32_t TP4:1;
0184                   uint32_t:12;
0185             } B;
0186         } OPACR0;
0187
0188         union {
0189             uint32_t R;
0190             struct {
0191
0192                 uint32_t BW0:1;        /* EMIOS */
0193                 uint32_t SP0:1;
0194                 uint32_t WP0:1;
0195                 uint32_t TP0:1;
0196
0197                   uint32_t:28;
0198             } B;
0199         } OPACR1;
0200
0201         union {
0202             uint32_t R;
0203             struct {
0204                 uint32_t BW0:1;
0205                 uint32_t SP0:1;
0206                 uint32_t WP0:1;
0207                 uint32_t TP0:1;
0208                   uint32_t:4;
0209                 uint32_t BW2:1;
0210                 uint32_t SP2:1;
0211                 uint32_t WP2:1;
0212                 uint32_t TP2:1;
0213                 uint32_t BW3:1;
0214                 uint32_t SP3:1;
0215                 uint32_t WP3:1;
0216                 uint32_t TP3:1;
0217                 uint32_t BW4:1;
0218                 uint32_t SP4:1;
0219                 uint32_t WP4:1;
0220                 uint32_t TP4:1;
0221                   uint32_t:12;
0222             } B;
0223         } OPACR2;
0224
0225     };
0226
0227 /****************************************************************************/
0228 /*                          MODULE : PBRIDGE_B Peripheral Bridge            */
0229 /****************************************************************************/
0230     struct PBRIDGE_B_tag {
0231         union {
0232             uint32_t R;
0233             struct {
0234                 uint32_t MBW0:1;
0235                 uint32_t MTR0:1;
0236                 uint32_t MTW0:1;
0237                 uint32_t MPL0:1;
0238                 uint32_t MBW1:1;
0239                 uint32_t MTR1:1;
0240                 uint32_t MTW1:1;
0241                 uint32_t MPL1:1;
0242                 uint32_t MBW2:1;
0243                 uint32_t MTR2:1;
0244                 uint32_t MTW2:1;
0245                 uint32_t MPL2:1;
0246                 uint32_t MBW3:1;
0247                 uint32_t MTR3:1;
0248                 uint32_t MTW3:1;
0249                 uint32_t MPL3:1;
0250
0251                   uint32_t:4;
0252
0253                   uint32_t:4;
0254
0255                   uint32_t:4;
0256
0257                   uint32_t:4;
0258             } B;
0259         } MPCR;                 /* Master Privilege Control Register */
0260
0261         uint32_t pbridge_b_reserved2[7];
0262
0263         union {
0264             uint32_t R;
0265             struct {
0266                 uint32_t BW0:1;
0267                 uint32_t SP0:1;
0268                 uint32_t WP0:1;
0269                 uint32_t TP0:1;
0270                 uint32_t BW1:1;
0271                 uint32_t SP1:1;
0272                 uint32_t WP1:1;
0273                 uint32_t TP1:1;
0274                   uint32_t:24;
0275             } B;
0276         } PACR0;
0277
0278         uint32_t pbridge_b_reserved3;
0279
0280         union {
0281             uint32_t R;
0282             struct {
0283                 uint32_t BW0:1;
0284                 uint32_t SP0:1;
0285                 uint32_t WP0:1;
0286                 uint32_t TP0:1;
0287                 uint32_t BW1:1;
0288                 uint32_t SP1:1;
0289                 uint32_t WP1:1;
0290                 uint32_t TP1:1;
0291                 uint32_t BW2:1;
0292                 uint32_t SP2:1;
0293                 uint32_t WP2:1;
0294                 uint32_t TP2:1;
0295
0296                   uint32_t:4;
0297
0298                   uint32_t:16;
0299
0300             } B;
0301         } PACR2;
0302
0303         uint32_t pbridge_b_reserved4[5];
0304
0305         union {
0306             uint32_t R;
0307             struct {
0308                 uint32_t BW0:1;
0309                 uint32_t SP0:1;
0310                 uint32_t WP0:1;
0311                 uint32_t TP0:1;
0312                   uint32_t:12;
0313
0314                 uint32_t BW4:1;        /* DSPI_A */
0315                 uint32_t SP4:1;
0316                 uint32_t WP4:1;
0317                 uint32_t TP4:1;
0318
0319                 uint32_t BW5:1;        /* DSPI_B */
0320                 uint32_t SP5:1;
0321                 uint32_t WP5:1;
0322                 uint32_t TP5:1;
0323
0324                 uint32_t BW6:1;
0325                 uint32_t SP6:1;
0326                 uint32_t WP6:1;
0327                 uint32_t TP6:1;
0328                 uint32_t BW7:1;
0329                 uint32_t SP7:1;
0330                 uint32_t WP7:1;
0331                 uint32_t TP7:1;
0332             } B;
0333         } OPACR0;
0334
0335         union {
0336             uint32_t R;
0337             struct {
0338                 uint32_t:16;
0339                 uint32_t BW4:1;
0340                 uint32_t SP4:1;
0341                 uint32_t WP4:1;
0342                 uint32_t TP4:1;
0343
0344                 uint32_t BW5:1;        /* ESCI_B */
0345                 uint32_t SP5:1;
0346                 uint32_t WP5:1;
0347                 uint32_t TP5:1;
0348
0349                   uint32_t:8;
0350             } B;
0351         } OPACR1;
0352
0353         union {
0354             uint32_t R;
0355             struct {
0356                 uint32_t BW0:1;
0357                 uint32_t SP0:1;
0358                 uint32_t WP0:1;
0359                 uint32_t TP0:1;
0360
0361                 uint32_t BW1:1;        /* CAN_B */
0362                 uint32_t SP1:1;
0363                 uint32_t WP1:1;
0364                 uint32_t TP1:1;
0365
0366                 uint32_t BW2:1;
0367                 uint32_t SP2:1;
0368                 uint32_t WP2:1;
0369                 uint32_t TP2:1;
0370
0371                   uint32_t:4;
0372
0373                   uint32_t:4;
0374
0375                   uint32_t:12;
0376             } B;
0377         } OPACR2;
0378
0379         union {
0380             uint32_t R;
0381             struct {
0382
0383                 uint32_t:4;
0384
0385                 uint32_t:24;
0386                 uint32_t BW7:1;
0387                 uint32_t SP7:1;
0388                 uint32_t WP7:1;
0389                 uint32_t TP7:1;
0390             } B;
0391         } OPACR3;
0392
0393     };
0394 /****************************************************************************/
0395 /*                     MODULE : FMPLL                                       */
0396 /****************************************************************************/
0397     struct FMPLL_tag {
0398         union FMPLL_SYNCR_tag {
0399             uint32_t R;
0400             struct {
0401                 uint32_t:1;
0402                 uint32_t PREDIV:3;
0403                 uint32_t MFD:5;
0404                   uint32_t:1;
0405                 uint32_t RFD:3;
0406                 uint32_t LOCEN:1;
0407                 uint32_t LOLRE:1;
0408                 uint32_t LOCRE:1;
0409                 uint32_t DISCLK:1;
0410                 uint32_t LOLIRQ:1;
0411                 uint32_t LOCIRQ:1;
0412                 uint32_t RATE:1;
0413                 uint32_t DEPTH:2;
0414                 uint32_t EXP:10;
0415             } B;
0416         } SYNCR;
0417
0418         union FMPLL_SYNSR_tag {
0419             uint32_t R;
0420             struct {
0421                 uint32_t:22;
0422                 uint32_t LOLF:1;
0423                 uint32_t LOC:1;
0424                 uint32_t MODE:1;
0425                 uint32_t PLLSEL:1;
0426                 uint32_t PLLREF:1;
0427                 uint32_t LOCKS:1;
0428                 uint32_t LOCK:1;
0429                 uint32_t LOCF:1;
0430                 uint32_t CALDONE:1;
0431                 uint32_t CALPASS:1;
0432             } B;
0433         } SYNSR;
0434
0435     };
0436 /****************************************************************************/
0437 /*                     MODULE : External Bus Interface (EBI)                */
0438 /****************************************************************************/
0439     struct EBI_CS_tag {
0440         union {                 /* Base Register Bank */
0441             uint32_t R;
0442             struct {
0443                 uint32_t BA:17;
0444                   uint32_t:3;
0445                 uint32_t PS:1;
0446                   uint32_t:4;
0447                 uint32_t BL:1;
0448                 uint32_t WEBS:1;
0449                 uint32_t TBDIP:1;
0450                   uint32_t:2;
0451                 uint32_t BI:1;
0452                 uint32_t V:1;
0453             } B;
0454         } BR;
0455
0456         union {                 /* Option Register Bank */
0457             uint32_t R;
0458             struct {
0459                 uint32_t AM:17;
0460                   uint32_t:7;
0461                 uint32_t SCY:4;
0462                   uint32_t:1;
0463                 uint32_t BSCY:2;
0464                   uint32_t:1;
0465             } B;
0466         } OR;
0467     };
0468
0469     struct EBI_CAL_CS_tag {
0470         uint32_t ebi_cal_cs_reserved [2];
0471     };
0472
0473     struct EBI_tag {
0474         union EBI_MCR_tag {     /* Module Configuration Register */
0475             uint32_t R;
0476             struct {
0477                 uint32_t:5;
0478                 uint32_t SIZEEN:1;
0479                 uint32_t SIZE:2;
0480                   uint32_t:8;
0481                 uint32_t ACGE:1;
0482                 uint32_t EXTM:1;
0483                 uint32_t EARB:1;
0484                 uint32_t EARP:2;
0485                   uint32_t:4;
0486                 uint32_t MDIS:1;
0487                   uint32_t:5;
0488                 uint32_t DBM:1;
0489             } B;
0490         } MCR;
0491
0492         uint32_t EBI_reserved1;
0493
0494         union {                 /* Transfer Error Status Register */
0495             uint32_t R;
0496             struct {
0497                 uint32_t:30;
0498                 uint32_t TEAF:1;
0499                 uint32_t BMTF:1;
0500             } B;
0501         } TESR;
0502
0503         union {                 /* Bus Monitor Control Register */
0504             uint32_t R;
0505             struct {
0506                 uint32_t:16;
0507                 uint32_t BMT:8;
0508                 uint32_t BME:1;
0509                   uint32_t:7;
0510             } B;
0511         } BMCR;
0512
0513         struct EBI_CS_tag CS[4];
0514
0515         uint32_t EBI_reserved2[4];
0516
0517         struct EBI_CAL_CS_tag CAL_CS[4];
0518     };
0519 /****************************************************************************/
0520 /*                     MODULE : FLASH                                       */
0521 /****************************************************************************/
0522     struct FLASH_tag {
0523         union {                 /* Module Configuration Register */
0524             uint32_t R;
0525             struct {
0526                 uint32_t:4;
0527                 uint32_t SIZE:4;
0528                   uint32_t:1;
0529                 uint32_t LAS:3;
0530                   uint32_t:3;
0531                 uint32_t MAS:1;
0532                 uint32_t EER:1;
0533                 uint32_t RWE:1;
0534                 uint32_t BBEPE:1;
0535                 uint32_t EPE:1;
0536                 uint32_t PEAS:1;
0537                 uint32_t DONE:1;
0538                 uint32_t PEG:1;
0539
0540                   uint32_t:2;
0541
0542                 uint32_t STOP:1;
0543                   uint32_t:1;
0544                 uint32_t PGM:1;
0545                 uint32_t PSUS:1;
0546                 uint32_t ERS:1;
0547                 uint32_t ESUS:1;
0548                 uint32_t EHV:1;
0549             } B;
0550         } MCR;
0551
0552         union LMLR_tag {        /* LML Register */
0553             uint32_t R;
0554             struct {
0555                 uint32_t LME:1;
0556                   uint32_t:10;
0557                 uint32_t SLOCK:1;
0558                 uint32_t MLOCK:4;
0559                 uint32_t LLOCK:16;
0560             } B;
0561         } LMLR;
0562
0563         union HLR_tag {         /* HL Register */
0564             uint32_t R;
0565             struct {
0566                 uint32_t HBE:1;
0567                   uint32_t:3;
0568                 uint32_t HBLOCK:28;
0569             } B;
0570         } HLR;
0571
0572         union SLMLR_tag {       /* SLML Register */
0573             uint32_t R;
0574             struct {
0575                 uint32_t SLE:1;
0576                   uint32_t:10;
0577                 uint32_t SSLOCK:1;
0578                 uint32_t SMLOCK:4;
0579                 uint32_t SLLOCK:16;
0580             } B;
0581         } SLMLR;
0582
0583         union {                 /* LMS Register */
0584             uint32_t R;
0585             struct {
0586                 uint32_t:12;
0587                 uint32_t MSEL:4;
0588                 uint32_t LSEL:16;
0589             } B;
0590         } LMSR;
0591
0592         union {
0593             uint32_t R;
0594             struct {
0595                 uint32_t:4;
0596                 uint32_t HBSEL:28;
0597             } B;
0598         } HSR;
0599
0600         union {
0601             uint32_t R;
0602             struct {
0603                 uint32_t:10;
0604                 uint32_t ADDR:19;
0605                   uint32_t:3;
0606             } B;
0607         } AR;
0608
0609         union {
0610             uint32_t R;
0611             struct {
0612
0613                 uint32_t:11;
0614
0615                 uint32_t:1;
0616
0617                 uint32_t M3PFE:1;
0618                 uint32_t M2PFE:1;
0619                 uint32_t M1PFE:1;
0620                 uint32_t M0PFE:1;
0621                 uint32_t APC:3;
0622                 uint32_t WWSC:2;
0623                 uint32_t RWSC:3;
0624
0625                 uint32_t DPFEN:2;
0626                 uint32_t IPFEN:2;
0627
0628                 uint32_t PFLIM:3;
0629                 uint32_t BFEN:1;
0630             } B;
0631         } BIUCR;
0632
0633         union {
0634             uint32_t R;
0635             struct {
0636
0637                 uint32_t:22;
0638
0639                 uint32_t:2;
0640
0641                 uint32_t M3AP:2;
0642                 uint32_t M2AP:2;
0643                 uint32_t M1AP:2;
0644                 uint32_t M0AP:2;
0645             } B;
0646         } BIUAPR;
0647     };
0648 /****************************************************************************/
0649 /*                     MODULE : SIU                                         */
0650 /****************************************************************************/
0651     struct SIU_tag {
0652         int32_t SIU_reserved0;
0653
0654         union {                 /* MCU ID Register */
0655             uint32_t R;
0656             struct {
0657                 uint32_t PARTNUM:16;
0658                 uint32_t MASKNUM:16;
0659             } B;
0660         } MIDR;
0661         int32_t SIU_reserved00;
0662
0663         union {                 /* Reset Status Register */
0664             uint32_t R;
0665             struct {
0666                 uint32_t PORS:1;
0667                 uint32_t ERS:1;
0668                 uint32_t LLRS:1;
0669                 uint32_t LCRS:1;
0670                 uint32_t WDRS:1;
0671                 uint32_t CRS:1;
0672                   uint32_t:8;
0673                 uint32_t SSRS:1;
0674                 uint32_t SERF:1;
0675                 uint32_t WKPCFG:1;
0676                   uint32_t:12;
0677                 uint32_t BOOTCFG:2;
0678                 uint32_t RGF:1;
0679             } B;
0680         } RSR;
0681
0682         union {                 /* System Reset Control Register */
0683             uint32_t R;
0684             struct {
0685                 uint32_t SSR:1;
0686                 uint32_t SER:1;
0687                   uint32_t:14;
0688                 uint32_t CRE:1;
0689                   uint32_t:15;
0690             } B;
0691         } SRCR;
0692
0693         union SIU_EISR_tag {    /* External Interrupt Status Register */
0694             uint32_t R;
0695             struct {
0696                 uint32_t:16;
0697                 uint32_t EIF15:1;
0698                 uint32_t EIF14:1;
0699                 uint32_t EIF13:1;
0700                 uint32_t EIF12:1;
0701                 uint32_t EIF11:1;
0702                 uint32_t EIF10:1;
0703                 uint32_t EIF9:1;
0704                 uint32_t EIF8:1;
0705                 uint32_t EIF7:1;
0706                 uint32_t EIF6:1;
0707                 uint32_t EIF5:1;
0708                 uint32_t EIF4:1;
0709                 uint32_t EIF3:1;
0710                 uint32_t EIF2:1;
0711                 uint32_t EIF1:1;
0712                 uint32_t EIF0:1;
0713             } B;
0714         } EISR;
0715
0716         union SIU_DIRER_tag {   /* DMA/Interrupt Request Enable Register */
0717             uint32_t R;
0718             struct {
0719                 uint32_t:16;
0720                 uint32_t EIRE15:1;
0721                 uint32_t EIRE14:1;
0722                 uint32_t EIRE13:1;
0723                 uint32_t EIRE12:1;
0724                 uint32_t EIRE11:1;
0725                 uint32_t EIRE10:1;
0726                 uint32_t EIRE9:1;
0727                 uint32_t EIRE8:1;
0728                 uint32_t EIRE7:1;
0729                 uint32_t EIRE6:1;
0730                 uint32_t EIRE5:1;
0731                 uint32_t EIRE4:1;
0732                 uint32_t EIRE3:1;
0733                 uint32_t EIRE2:1;
0734                 uint32_t EIRE1:1;
0735                 uint32_t EIRE0:1;
0736             } B;
0737         } DIRER;
0738
0739         union SIU_DIRSR_tag {   /* DMA/Interrupt Select Register */
0740             uint32_t R;
0741             struct {
0742                 uint32_t:28;
0743                 uint32_t DIRS3:1;
0744                 uint32_t DIRS2:1;
0745                 uint32_t DIRS1:1;
0746                 uint32_t DIRS0:1;
0747             } B;
0748         } DIRSR;
0749
0750         union {                 /* Overrun Status Register */
0751             uint32_t R;
0752             struct {
0753                 uint32_t:16;
0754                 uint32_t OVF15:1;
0755                 uint32_t OVF14:1;
0756                 uint32_t OVF13:1;
0757                 uint32_t OVF12:1;
0758                 uint32_t OVF11:1;
0759                 uint32_t OVF10:1;
0760                 uint32_t OVF9:1;
0761                 uint32_t OVF8:1;
0762                 uint32_t OVF7:1;
0763                 uint32_t OVF6:1;
0764                 uint32_t OVF5:1;
0765                 uint32_t OVF4:1;
0766                 uint32_t OVF3:1;
0767                 uint32_t OVF2:1;
0768                 uint32_t OVF1:1;
0769                 uint32_t OVF0:1;
0770             } B;
0771         } OSR;
0772
0773         union SIU_ORER_tag {    /* Overrun Request Enable Register */
0774             uint32_t R;
0775             struct {
0776                 uint32_t:16;
0777                 uint32_t ORE15:1;
0778                 uint32_t ORE14:1;
0779                 uint32_t ORE13:1;
0780                 uint32_t ORE12:1;
0781                 uint32_t ORE11:1;
0782                 uint32_t ORE10:1;
0783                 uint32_t ORE9:1;
0784                 uint32_t ORE8:1;
0785                 uint32_t ORE7:1;
0786                 uint32_t ORE6:1;
0787                 uint32_t ORE5:1;
0788                 uint32_t ORE4:1;
0789                 uint32_t ORE3:1;
0790                 uint32_t ORE2:1;
0791                 uint32_t ORE1:1;
0792                 uint32_t ORE0:1;
0793             } B;
0794         } ORER;
0795
0796         union SIU_IREER_tag {   /* External IRQ Rising-Edge Event Enable Register */
0797             uint32_t R;
0798             struct {
0799                 uint32_t:16;
0800                 uint32_t IREE15:1;
0801                 uint32_t IREE14:1;
0802                 uint32_t IREE13:1;
0803                 uint32_t IREE12:1;
0804                 uint32_t IREE11:1;
0805                 uint32_t IREE10:1;
0806                 uint32_t IREE9:1;
0807                 uint32_t IREE8:1;
0808                 uint32_t IREE7:1;
0809                 uint32_t IREE6:1;
0810                 uint32_t IREE5:1;
0811                 uint32_t IREE4:1;
0812                 uint32_t IREE3:1;
0813                 uint32_t IREE2:1;
0814                 uint32_t IREE1:1;
0815                 uint32_t IREE0:1;
0816             } B;
0817         } IREER;
0818
0819         union SIU_IFEER_tag {   /* External IRQ Falling-Edge Event Enable Register */
0820             uint32_t R;
0821             struct {
0822                 uint32_t:16;
0823                 uint32_t IFEE15:1;
0824                 uint32_t IFEE14:1;
0825                 uint32_t IFEE13:1;
0826                 uint32_t IFEE12:1;
0827                 uint32_t IFEE11:1;
0828                 uint32_t IFEE10:1;
0829                 uint32_t IFEE9:1;
0830                 uint32_t IFEE8:1;
0831                 uint32_t IFEE7:1;
0832                 uint32_t IFEE6:1;
0833                 uint32_t IFEE5:1;
0834                 uint32_t IFEE4:1;
0835                 uint32_t IFEE3:1;
0836                 uint32_t IFEE2:1;
0837                 uint32_t IFEE1:1;
0838                 uint32_t IFEE0:1;
0839             } B;
0840         } IFEER;
0841
0842         union SIU_IDFR_tag {    /* External IRQ Digital Filter Register */
0843             uint32_t R;
0844             struct {
0845                 uint32_t:28;
0846                 uint32_t DFL:4;
0847             } B;
0848         } IDFR;
0849
0850         int32_t SIU_reserved1[3];
0851
0852         union SIU_PCR_tag {     /* Pad Configuration Registers */
0853             uint16_t R;
0854             struct {
0855                 uint16_t:3;
0856                 uint16_t PA:3;
0857                 uint16_t OBE:1;
0858                 uint16_t IBE:1;
0859                 uint16_t DSC:2;
0860                 uint16_t ODE:1;
0861                 uint16_t HYS:1;
0862                 uint16_t SRC:2;
0863                 uint16_t WPE:1;
0864                 uint16_t WPS:1;
0865             } B;
0866         } PCR[512];
0867
0868         int16_t SIU_reserved_0[224];
0869
0870         union {                 /* GPIO Pin Data Output Registers */
0871             uint8_t R;
0872             struct {
0873                 uint8_t:7;
0874                 uint8_t PDO:1;
0875             } B;
0876         } GPDO[256];
0877
0878         int32_t SIU_reserved_3[64];
0879
0880         union {                 /* GPIO Pin Data Input Registers */
0881             uint8_t R;
0882             struct {
0883                 uint8_t:7;
0884                 uint8_t PDI:1;
0885             } B;
0886         } GPDI[256];
0887
0888         union {                 /* IMUX Register */
0889             uint32_t R;
0890             struct {
0891                 uint32_t TSEL5:2;
0892                 uint32_t TSEL4:2;
0893                 uint32_t TSEL3:2;
0894                 uint32_t TSEL2:2;
0895                 uint32_t TSEL1:2;
0896                 uint32_t TSEL0:2;
0897                   uint32_t:20;
0898             } B;
0899         } ETISR;
0900
0901         union {                 /* IMUX Register */
0902             uint32_t R;
0903             struct {
0904                 uint32_t ESEL15:2;
0905                 uint32_t ESEL14:2;
0906                 uint32_t ESEL13:2;
0907                 uint32_t ESEL12:2;
0908                 uint32_t ESEL11:2;
0909                 uint32_t ESEL10:2;
0910                 uint32_t ESEL9:2;
0911                 uint32_t ESEL8:2;
0912                 uint32_t ESEL7:2;
0913                 uint32_t ESEL6:2;
0914                 uint32_t ESEL5:2;
0915                 uint32_t ESEL4:2;
0916                 uint32_t ESEL3:2;
0917                 uint32_t ESEL2:2;
0918                 uint32_t ESEL1:2;
0919                 uint32_t ESEL0:2;
0920             } B;
0921         } EIISR;
0922
0923         union {                 /* IMUX Register */
0924             uint32_t R;
0925             struct {
0926                 uint32_t SINSELA:2;
0927                 uint32_t SSSELA:2;
0928                 uint32_t SCKSELA:2;
0929                 uint32_t TRIGSELA:2;
0930                 uint32_t SINSELB:2;
0931                 uint32_t SSSELB:2;
0932                 uint32_t SCKSELB:2;
0933                 uint32_t TRIGSELB:2;
0934                 uint32_t SINSELC:2;
0935                 uint32_t SSSELC:2;
0936                 uint32_t SCKSELC:2;
0937                 uint32_t TRIGSELC:2;
0938                 uint32_t SINSELD:2;
0939                 uint32_t SSSELD:2;
0940                 uint32_t SCKSELD:2;
0941                 uint32_t TRIGSELD:2;
0942             } B;
0943         } DISR;
0944
0945         int32_t SIU_reserved2[29];
0946
0947         union {                 /* Chip Configuration Register Register */
0948             uint32_t R;
0949             struct {
0950                 uint32_t:14;
0951                 uint32_t MATCH:1;
0952                 uint32_t DISNEX:1;
0953                   uint32_t:16;
0954             } B;
0955         } CCR;
0956
0957         union {                 /* External Clock Configuration Register Register */
0958             uint32_t R;
0959             struct {
0960                 uint32_t:18;
0961                 uint32_t ENGDIV:6;
0962                   uint32_t:4;
0963                 uint32_t EBTS:1;
0964                   uint32_t:1;
0965                 uint32_t EBDF:2;
0966             } B;
0967         } ECCR;
0968
0969         union {
0970             uint32_t R;
0971         } CARH;
0972
0973         union {
0974             uint32_t R;
0975         } CARL;
0976
0977         union {
0978             uint32_t R;
0979         } CBRH;
0980
0981         union {
0982             uint32_t R;
0983         } CBRL;
0984
0985     };
0986 /****************************************************************************/
0987 /*                          MODULE : EMIOS                                  */
0988 /****************************************************************************/
0989     struct EMIOS_tag {
0990         union EMIOS_MCR_tag {
0991             uint32_t R;
0992             struct {
0993                 uint32_t:1;
0994                 uint32_t MDIS:1;
0995                 uint32_t FRZ:1;
0996                 uint32_t GTBE:1;
0997                 uint32_t ETB:1;
0998                 uint32_t GPREN:1;
0999                   uint32_t:6;
1000                 uint32_t SRV:4;
1001                 uint32_t GPRE:8;
1002                   uint32_t:8;
1003             } B;
1004         } MCR;                  /* Module Configuration Register */
1005
1006         union {
1007             uint32_t R;
1008             struct {
1009                 uint32_t:8;
1010                 uint32_t F23:1;
1011                 uint32_t F22:1;
1012                 uint32_t F21:1;
1013                 uint32_t F20:1;
1014                 uint32_t F19:1;
1015                 uint32_t F18:1;
1016                 uint32_t F17:1;
1017                 uint32_t F16:1;
1018                 uint32_t F15:1;
1019                 uint32_t F14:1;
1020                 uint32_t F13:1;
1021                 uint32_t F12:1;
1022                 uint32_t F11:1;
1023                 uint32_t F10:1;
1024                 uint32_t F9:1;
1025                 uint32_t F8:1;
1026                 uint32_t F7:1;
1027                 uint32_t F6:1;
1028                 uint32_t F5:1;
1029                 uint32_t F4:1;
1030                 uint32_t F3:1;
1031                 uint32_t F2:1;
1032                 uint32_t F1:1;
1033                 uint32_t F0:1;
1034             } B;
1035         } GFR;                  /* Global FLAG Register */
1036
1037         union {
1038             uint32_t R;
1039             struct {
1040                 uint32_t:8;
1041                 uint32_t OU23:1;
1042                 uint32_t OU22:1;
1043                 uint32_t OU21:1;
1044                 uint32_t OU20:1;
1045                 uint32_t OU19:1;
1046                 uint32_t OU18:1;
1047                 uint32_t OU17:1;
1048                 uint32_t OU16:1;
1049                 uint32_t OU15:1;
1050                 uint32_t OU14:1;
1051                 uint32_t OU13:1;
1052                 uint32_t OU12:1;
1053                 uint32_t OU11:1;
1054                 uint32_t OU10:1;
1055                 uint32_t OU9:1;
1056                 uint32_t OU8:1;
1057                 uint32_t OU7:1;
1058                 uint32_t OU6:1;
1059                 uint32_t OU5:1;
1060                 uint32_t OU4:1;
1061                 uint32_t OU3:1;
1062                 uint32_t OU2:1;
1063                 uint32_t OU1:1;
1064                 uint32_t OU0:1;
1065             } B;
1066         } OUDR;                 /* Output Update Disable Register */
1067
1068         uint32_t emios_reserved[5];
1069
1070         struct EMIOS_CH_tag {
1071             union {
1072                 uint32_t R;    /* Channel A Data Register */
1073             } CADR;
1074
1075             union {
1076                 uint32_t R;    /* Channel B Data Register */
1077             } CBDR;
1078
1079             union {
1080                 uint32_t R;    /* Channel Counter Register */
1081             } CCNTR;
1082
1083             union EMIOS_CCR_tag {
1084                 uint32_t R;
1085                 struct {
1086                     uint32_t FREN:1;
1087                     uint32_t ODIS:1;
1088                     uint32_t ODISSL:2;
1089                     uint32_t UCPRE:2;
1090                     uint32_t UCPREN:1;
1091                     uint32_t DMA:1;
1092                       uint32_t:1;
1093                     uint32_t IF:4;
1094                     uint32_t FCK:1;
1095                     uint32_t FEN:1;
1096                       uint32_t:3;
1097                     uint32_t FORCMA:1;
1098                     uint32_t FORCMB:1;
1099                       uint32_t:1;
1100                     uint32_t BSL:2;
1101                     uint32_t EDSEL:1;
1102                     uint32_t EDPOL:1;
1103                     uint32_t MODE:7;
1104                 } B;
1105             } CCR;              /* Channel Control Register */
1106
1107             union EMIOS_CSR_tag {
1108                 uint32_t R;
1109                 struct {
1110                     uint32_t OVR:1;
1111                       uint32_t:15;
1112                     uint32_t OVFL:1;
1113                       uint32_t:12;
1114                     uint32_t UCIN:1;
1115                     uint32_t UCOUT:1;
1116                     uint32_t FLAG:1;
1117                 } B;
1118             } CSR;              /* Channel Status Register */
1119             uint32_t emios_channel_reserved[3];
1120
1121         } CH[24];
1122
1123     };
1124 /****************************************************************************/
1125 /*                              MODULE :ETPU                                */
1126 /****************************************************************************/
1127
1128 /***************************Configuration Registers**************************/
1129
1130     struct ETPU_tag {
1131         union {                 /* MODULE CONFIGURATION REGISTER */
1132             uint32_t R;
1133             struct {
1134                 uint32_t GEC:1;        /* Global Exception Clear */
1135                   uint32_t:3;
1136                 uint32_t MGE1:1;       /* Microcode Global Exception-ETPU_A */
1137
1138                 uint32_t MGE2:1;       /* Microcode Global Exception-ETPU_B */
1139
1140                 uint32_t ILF1:1;       /* Illegal Instruction Flag-ETPU_A */
1141
1142                 uint32_t ILF2:1;       /* Illegal Instruction Flag-ETPU_B */
1143
1144                   uint32_t:3;
1145                 uint32_t SCMSIZE:5;    /* Shared Code Memory size */
1146                   uint32_t:5;
1147                 uint32_t SCMMISF:1;    /* SCM MISC Flag */
1148                 uint32_t SCMMISEN:1;   /* SCM MISC Enable */
1149                   uint32_t:2;
1150                 uint32_t VIS:1;        /* SCM Visability */
1151                   uint32_t:5;
1152                 uint32_t GTBE:1;       /* Global Time Base Enable */
1153             } B;
1154         } MCR;
1155
1156         union {                 /* COHERENT DUAL-PARAMETER CONTROL */
1157             uint32_t R;
1158             struct {
1159                 uint32_t STS:1;        /* Start Status bit */
1160                 uint32_t CTBASE:5;     /* Channel Transfer Base */
1161                 uint32_t PBASE:10;     /* Parameter Buffer Base Address */
1162                 uint32_t PWIDTH:1;     /* Parameter Width */
1163                 uint32_t PARAM0:7;     /* Channel Parameter 0 */
1164                 uint32_t WR:1;
1165                 uint32_t PARAM1:7;     /* Channel Parameter 1 */
1166             } B;
1167         } CDCR;
1168
1169         uint32_t etpu_reserved1;
1170
1171         union {                 /* MISC Compare Register */
1172             uint32_t R;
1173         } MISCCMPR;
1174
1175         union {                 /* SCM off-range Date Register */
1176             uint32_t R;
1177         } SCMOFFDATAR;
1178
1179         union {                 /* ETPU_A Configuration Register */
1180             uint32_t R;
1181             struct {
1182                 uint32_t FEND:1;       /* Force END */
1183                 uint32_t MDIS:1;       /* Low power Stop */
1184                   uint32_t:1;
1185                 uint32_t STF:1;        /* Stop Flag */
1186                   uint32_t:4;
1187                 uint32_t HLTF:1;       /* Halt Mode Flag */
1188                   uint32_t:4;
1189                 uint32_t FPSCK:3;      /* Filter Prescaler Clock Control */
1190                 uint32_t CDFC:2;
1191                   uint32_t:9;
1192                 uint32_t ETB:5;        /* Entry Table Base */
1193             } B;
1194         } ECR_A;
1195
1196         union {                 /* ETPU_B Configuration Register */
1197             uint32_t R;
1198             struct {
1199                 uint32_t FEND:1;       /* Force END */
1200                 uint32_t MDIS:1;       /* Low power Stop */
1201                   uint32_t:1;
1202                 uint32_t STF:1;        /* Stop Flag */
1203                   uint32_t:4;
1204                 uint32_t HLTF:1;       /* Halt Mode Flag */
1205                   uint32_t:4;
1206                 uint32_t FPSCK:3;      /* Filter Prescaler Clock Control */
1207                 uint32_t CDFC:2;
1208                   uint32_t:9;
1209                 uint32_t ETB:5;        /* Entry Table Base */
1210             } B;
1211         } ECR_B;
1212
1213         uint32_t etpu_reserved4;
1214
1215         union {                 /* ETPU_A Timebase Configuration Register */
1216             uint32_t R;
1217             struct {
1218                 uint32_t TCR2CTL:3;     /* TCR2 Clock/Gate Control */
1219                 uint32_t TCRCF:2;       /* TCRCLK Signal Filter Control */
1220                   uint32_t:1;
1221                 uint32_t AM:1;  /* Angle Mode */
1222                   uint32_t:3;
1223                 uint32_t TCR2P:6;       /* TCR2 Prescaler Control */
1224                 uint32_t TCR1CTL:2;     /* TCR1 Clock/Gate Control */
1225                   uint32_t:6;
1226                 uint32_t TCR1P:8;       /* TCR1 Prescaler Control */
1227             } B;
1228         } TBCR_A;
1229
1230         union {                 /* ETPU_A TCR1 Visibility Register */
1231             uint32_t R;
1232         } TB1R_A;
1233
1234         union {                 /* ETPU_A TCR2 Visibility Register */
1235             uint32_t R;
1236         } TB2R_A;
1237
1238         union {                 /* ETPU_A STAC Configuration Register */
1239             uint32_t R;
1240             struct {
1241                 uint32_t REN1:1;       /* Resource Enable TCR1 */
1242                 uint32_t RSC1:1;       /* Resource Control TCR1 */
1243                   uint32_t:2;
1244                 uint32_t SERVER_ID1:4;
1245                   uint32_t:4;
1246                 uint32_t SRV1:4;       /* Resource Server Slot */
1247                 uint32_t REN2:1;       /* Resource Enable TCR2 */
1248                 uint32_t RSC2:1;       /* Resource Control TCR2 */
1249                   uint32_t:2;
1250                 uint32_t SERVER_ID2:4;
1251                   uint32_t:4;
1252                 uint32_t SRV2:4;       /* Resource Server Slot */
1253             } B;
1254         } REDCR_A;
1255
1256         uint32_t etpu_reserved5[4];
1257
1258         union {                 /* ETPU_B Timebase Configuration Register */
1259             uint32_t R;
1260             struct {
1261                 uint32_t TCR2CTL:3;     /* TCR2 Clock/Gate Control */
1262                 uint32_t TCRCF:2;       /* TCRCLK Signal Filter Control */
1263                   uint32_t:1;
1264                 uint32_t AM:1;  /* Angle Mode */
1265                   uint32_t:3;
1266                 uint32_t TCR2P:6;       /* TCR2 Prescaler Control */
1267                 uint32_t TCR1CTL:2;     /* TCR1 Clock/Gate Control */
1268                   uint32_t:6;
1269                 uint32_t TCR1P:8;       /* TCR1 Prescaler Control */
1270             } B;
1271         } TBCR_B;
1272
1273         union {                 /* ETPU_B TCR1 Visibility Register */
1274             uint32_t R;
1275         } TB1R_B;
1276
1277         union {                 /* ETPU_B TCR2 Visibility Register */
1278             uint32_t R;
1279         } TB2R_B;
1280
1281         union {                 /* ETPU_B STAC Configuration Register */
1282             uint32_t R;
1283             struct {
1284                 uint32_t REN1:1;       /* Resource Enable TCR1 */
1285                 uint32_t RSC1:1;       /* Resource Control TCR1 */
1286                   uint32_t:2;
1287                 uint32_t SERVER_ID1:4;
1288                   uint32_t:4;
1289                 uint32_t SRV1:4;       /* Resource Server Slot */
1290                 uint32_t REN2:1;       /* Resource Enable TCR2 */
1291                 uint32_t RSC2:1;       /* Resource Control TCR2 */
1292                   uint32_t:2;
1293                 uint32_t SERVER_ID2:4;
1294                   uint32_t:4;
1295                 uint32_t SRV2:4;       /* Resource Server Slot */
1296             } B;
1297         } REDCR_B;
1298
1299         uint32_t etpu_reserved7[108];
1300
1301 /*****************************Status and Control Registers**************************/
1302
1303         union {                 /* ETPU_A Channel Interrut Status */
1304             uint32_t R;
1305             struct {
1306                 uint32_t CIS31:1;      /* Channel 31 Interrut Status */
1307                 uint32_t CIS30:1;      /* Channel 30 Interrut Status */
1308                 uint32_t CIS29:1;      /* Channel 29 Interrut Status */
1309                 uint32_t CIS28:1;      /* Channel 28 Interrut Status */
1310                 uint32_t CIS27:1;      /* Channel 27 Interrut Status */
1311                 uint32_t CIS26:1;      /* Channel 26 Interrut Status */
1312                 uint32_t CIS25:1;      /* Channel 25 Interrut Status */
1313                 uint32_t CIS24:1;      /* Channel 24 Interrut Status */
1314                 uint32_t CIS23:1;      /* Channel 23 Interrut Status */
1315                 uint32_t CIS22:1;      /* Channel 22 Interrut Status */
1316                 uint32_t CIS21:1;      /* Channel 21 Interrut Status */
1317                 uint32_t CIS20:1;      /* Channel 20 Interrut Status */
1318                 uint32_t CIS19:1;      /* Channel 19 Interrut Status */
1319                 uint32_t CIS18:1;      /* Channel 18 Interrut Status */
1320                 uint32_t CIS17:1;      /* Channel 17 Interrut Status */
1321                 uint32_t CIS16:1;      /* Channel 16 Interrut Status */
1322                 uint32_t CIS15:1;      /* Channel 15 Interrut Status */
1323                 uint32_t CIS14:1;      /* Channel 14 Interrut Status */
1324                 uint32_t CIS13:1;      /* Channel 13 Interrut Status */
1325                 uint32_t CIS12:1;      /* Channel 12 Interrut Status */
1326                 uint32_t CIS11:1;      /* Channel 11 Interrut Status */
1327                 uint32_t CIS10:1;      /* Channel 10 Interrut Status */
1328                 uint32_t CIS9:1;       /* Channel 9 Interrut Status */
1329                 uint32_t CIS8:1;       /* Channel 8 Interrut Status */
1330                 uint32_t CIS7:1;       /* Channel 7 Interrut Status */
1331                 uint32_t CIS6:1;       /* Channel 6 Interrut Status */
1332                 uint32_t CIS5:1;       /* Channel 5 Interrut Status */
1333                 uint32_t CIS4:1;       /* Channel 4 Interrut Status */
1334                 uint32_t CIS3:1;       /* Channel 3 Interrut Status */
1335                 uint32_t CIS2:1;       /* Channel 2 Interrut Status */
1336                 uint32_t CIS1:1;       /* Channel 1 Interrut Status */
1337                 uint32_t CIS0:1;       /* Channel 0 Interrut Status */
1338             } B;
1339         } CISR_A;
1340
1341         union {                 /* ETPU_B Channel Interruput Status */
1342             uint32_t R;
1343             struct {
1344                 uint32_t CIS31:1;      /* Channel 31 Interrut Status */
1345                 uint32_t CIS30:1;      /* Channel 30 Interrut Status */
1346                 uint32_t CIS29:1;      /* Channel 29 Interrut Status */
1347                 uint32_t CIS28:1;      /* Channel 28 Interrut Status */
1348                 uint32_t CIS27:1;      /* Channel 27 Interrut Status */
1349                 uint32_t CIS26:1;      /* Channel 26 Interrut Status */
1350                 uint32_t CIS25:1;      /* Channel 25 Interrut Status */
1351                 uint32_t CIS24:1;      /* Channel 24 Interrut Status */
1352                 uint32_t CIS23:1;      /* Channel 23 Interrut Status */
1353                 uint32_t CIS22:1;      /* Channel 22 Interrut Status */
1354                 uint32_t CIS21:1;      /* Channel 21 Interrut Status */
1355                 uint32_t CIS20:1;      /* Channel 20 Interrut Status */
1356                 uint32_t CIS19:1;      /* Channel 19 Interrut Status */
1357                 uint32_t CIS18:1;      /* Channel 18 Interrut Status */
1358                 uint32_t CIS17:1;      /* Channel 17 Interrut Status */
1359                 uint32_t CIS16:1;      /* Channel 16 Interrut Status */
1360                 uint32_t CIS15:1;      /* Channel 15 Interrut Status */
1361                 uint32_t CIS14:1;      /* Channel 14 Interrut Status */
1362                 uint32_t CIS13:1;      /* Channel 13 Interrut Status */
1363                 uint32_t CIS12:1;      /* Channel 12 Interrut Status */
1364                 uint32_t CIS11:1;      /* Channel 11 Interrut Status */
1365                 uint32_t CIS10:1;      /* Channel 10 Interrut Status */
1366                 uint32_t CIS9:1;       /* Channel 9 Interrut Status */
1367                 uint32_t CIS8:1;       /* Channel 8 Interrut Status */
1368                 uint32_t CIS7:1;       /* Channel 7 Interrut Status */
1369                 uint32_t CIS6:1;       /* Channel 6 Interrut Status */
1370                 uint32_t CIS5:1;       /* Channel 5 Interrut Status */
1371                 uint32_t CIS4:1;       /* Channel 4 Interrut Status */
1372                 uint32_t CIS3:1;       /* Channel 3 Interrut Status */
1373                 uint32_t CIS2:1;       /* Channel 2 Interrut Status */
1374                 uint32_t CIS1:1;       /* Channel 1 Interrupt Status */
1375                 uint32_t CIS0:1;       /* Channel 0 Interrupt Status */
1376             } B;
1377         } CISR_B;
1378
1379         uint32_t etpu_reserved9[2];
1380
1381         union {                 /* ETPU_A Data Transfer Request Status */
1382             uint32_t R;
1383             struct {
1384                 uint32_t DTRS31:1;     /* Channel 31 Data Transfer Request Status */
1385                 uint32_t DTRS30:1;     /* Channel 30 Data Transfer Request Status */
1386                 uint32_t DTRS29:1;     /* Channel 29 Data Transfer Request Status */
1387                 uint32_t DTRS28:1;     /* Channel 28 Data Transfer Request Status */
1388                 uint32_t DTRS27:1;     /* Channel 27 Data Transfer Request Status */
1389                 uint32_t DTRS26:1;     /* Channel 26 Data Transfer Request Status */
1390                 uint32_t DTRS25:1;     /* Channel 25 Data Transfer Request Status */
1391                 uint32_t DTRS24:1;     /* Channel 24 Data Transfer Request Status */
1392                 uint32_t DTRS23:1;     /* Channel 23 Data Transfer Request Status */
1393                 uint32_t DTRS22:1;     /* Channel 22 Data Transfer Request Status */
1394                 uint32_t DTRS21:1;     /* Channel 21 Data Transfer Request Status */
1395                 uint32_t DTRS20:1;     /* Channel 20 Data Transfer Request Status */
1396                 uint32_t DTRS19:1;     /* Channel 19 Data Transfer Request Status */
1397                 uint32_t DTRS18:1;     /* Channel 18 Data Transfer Request Status */
1398                 uint32_t DTRS17:1;     /* Channel 17 Data Transfer Request Status */
1399                 uint32_t DTRS16:1;     /* Channel 16 Data Transfer Request Status */
1400                 uint32_t DTRS15:1;     /* Channel 15 Data Transfer Request Status */
1401                 uint32_t DTRS14:1;     /* Channel 14 Data Transfer Request Status */
1402                 uint32_t DTRS13:1;     /* Channel 13 Data Transfer Request Status */
1403                 uint32_t DTRS12:1;     /* Channel 12 Data Transfer Request Status */
1404                 uint32_t DTRS11:1;     /* Channel 11 Data Transfer Request Status */
1405                 uint32_t DTRS10:1;     /* Channel 10 Data Transfer Request Status */
1406                 uint32_t DTRS9:1;      /* Channel 9 Data Transfer Request Status */
1407                 uint32_t DTRS8:1;      /* Channel 8 Data Transfer Request Status */
1408                 uint32_t DTRS7:1;      /* Channel 7 Data Transfer Request Status */
1409                 uint32_t DTRS6:1;      /* Channel 6 Data Transfer Request Status */
1410                 uint32_t DTRS5:1;      /* Channel 5 Data Transfer Request Status */
1411                 uint32_t DTRS4:1;      /* Channel 4 Data Transfer Request Status */
1412                 uint32_t DTRS3:1;      /* Channel 3 Data Transfer Request Status */
1413                 uint32_t DTRS2:1;      /* Channel 2 Data Transfer Request Status */
1414                 uint32_t DTRS1:1;      /* Channel 1 Data Transfer Request Status */
1415                 uint32_t DTRS0:1;      /* Channel 0 Data Transfer Request Status */
1416             } B;
1417         } CDTRSR_A;
1418
1419         union {                 /* ETPU_B Data Transfer Request Status */
1420             uint32_t R;
1421             struct {
1422                 uint32_t DTRS31:1;     /* Channel 31 Data Transfer Request Status */
1423                 uint32_t DTRS30:1;     /* Channel 30 Data Transfer Request Status */
1424                 uint32_t DTRS29:1;     /* Channel 29 Data Transfer Request Status */
1425                 uint32_t DTRS28:1;     /* Channel 28 Data Transfer Request Status */
1426                 uint32_t DTRS27:1;     /* Channel 27 Data Transfer Request Status */
1427                 uint32_t DTRS26:1;     /* Channel 26 Data Transfer Request Status */
1428                 uint32_t DTRS25:1;     /* Channel 25 Data Transfer Request Status */
1429                 uint32_t DTRS24:1;     /* Channel 24 Data Transfer Request Status */
1430                 uint32_t DTRS23:1;     /* Channel 23 Data Transfer Request Status */
1431                 uint32_t DTRS22:1;     /* Channel 22 Data Transfer Request Status */
1432                 uint32_t DTRS21:1;     /* Channel 21 Data Transfer Request Status */
1433                 uint32_t DTRS20:1;     /* Channel 20 Data Transfer Request Status */
1434                 uint32_t DTRS19:1;     /* Channel 19 Data Transfer Request Status */
1435                 uint32_t DTRS18:1;     /* Channel 18 Data Transfer Request Status */
1436                 uint32_t DTRS17:1;     /* Channel 17 Data Transfer Request Status */
1437                 uint32_t DTRS16:1;     /* Channel 16 Data Transfer Request Status */
1438                 uint32_t DTRS15:1;     /* Channel 15 Data Transfer Request Status */
1439                 uint32_t DTRS14:1;     /* Channel 14 Data Transfer Request Status */
1440                 uint32_t DTRS13:1;     /* Channel 13 Data Transfer Request Status */
1441                 uint32_t DTRS12:1;     /* Channel 12 Data Transfer Request Status */
1442                 uint32_t DTRS11:1;     /* Channel 11 Data Transfer Request Status */
1443                 uint32_t DTRS10:1;     /* Channel 10 Data Transfer Request Status */
1444                 uint32_t DTRS9:1;      /* Channel 9 Data Transfer Request Status */
1445                 uint32_t DTRS8:1;      /* Channel 8 Data Transfer Request Status */
1446                 uint32_t DTRS7:1;      /* Channel 7 Data Transfer Request Status */
1447                 uint32_t DTRS6:1;      /* Channel 6 Data Transfer Request Status */
1448                 uint32_t DTRS5:1;      /* Channel 5 Data Transfer Request Status */
1449                 uint32_t DTRS4:1;      /* Channel 4 Data Transfer Request Status */
1450                 uint32_t DTRS3:1;      /* Channel 3 Data Transfer Request Status */
1451                 uint32_t DTRS2:1;      /* Channel 2 Data Transfer Request Status */
1452                 uint32_t DTRS1:1;      /* Channel 1 Data Transfer Request Status */
1453                 uint32_t DTRS0:1;      /* Channel 0 Data Transfer Request Status */
1454             } B;
1455         } CDTRSR_B;
1456
1457         uint32_t etpu_reserved11[2];
1458
1459         union {                 /* ETPU_A Interruput Overflow Status */
1460             uint32_t R;
1461             struct {
1462                 uint32_t CIOS31:1;     /* Channel 31 Interruput Overflow Status */
1463                 uint32_t CIOS30:1;     /* Channel 30 Interruput Overflow Status */
1464                 uint32_t CIOS29:1;     /* Channel 29 Interruput Overflow Status */
1465                 uint32_t CIOS28:1;     /* Channel 28 Interruput Overflow Status */
1466                 uint32_t CIOS27:1;     /* Channel 27 Interruput Overflow Status */
1467                 uint32_t CIOS26:1;     /* Channel 26 Interruput Overflow Status */
1468                 uint32_t CIOS25:1;     /* Channel 25 Interruput Overflow Status */
1469                 uint32_t CIOS24:1;     /* Channel 24 Interruput Overflow Status */
1470                 uint32_t CIOS23:1;     /* Channel 23 Interruput Overflow Status */
1471                 uint32_t CIOS22:1;     /* Channel 22 Interruput Overflow Status */
1472                 uint32_t CIOS21:1;     /* Channel 21 Interruput Overflow Status */
1473                 uint32_t CIOS20:1;     /* Channel 20 Interruput Overflow Status */
1474                 uint32_t CIOS19:1;     /* Channel 19 Interruput Overflow Status */
1475                 uint32_t CIOS18:1;     /* Channel 18 Interruput Overflow Status */
1476                 uint32_t CIOS17:1;     /* Channel 17 Interruput Overflow Status */
1477                 uint32_t CIOS16:1;     /* Channel 16 Interruput Overflow Status */
1478                 uint32_t CIOS15:1;     /* Channel 15 Interruput Overflow Status */
1479                 uint32_t CIOS14:1;     /* Channel 14 Interruput Overflow Status */
1480                 uint32_t CIOS13:1;     /* Channel 13 Interruput Overflow Status */
1481                 uint32_t CIOS12:1;     /* Channel 12 Interruput Overflow Status */
1482                 uint32_t CIOS11:1;     /* Channel 11 Interruput Overflow Status */
1483                 uint32_t CIOS10:1;     /* Channel 10 Interruput Overflow Status */
1484                 uint32_t CIOS9:1;      /* Channel 9 Interruput Overflow Status */
1485                 uint32_t CIOS8:1;      /* Channel 8 Interruput Overflow Status */
1486                 uint32_t CIOS7:1;      /* Channel 7 Interruput Overflow Status */
1487                 uint32_t CIOS6:1;      /* Channel 6 Interruput Overflow Status */
1488                 uint32_t CIOS5:1;      /* Channel 5 Interruput Overflow Status */
1489                 uint32_t CIOS4:1;      /* Channel 4 Interruput Overflow Status */
1490                 uint32_t CIOS3:1;      /* Channel 3 Interruput Overflow Status */
1491                 uint32_t CIOS2:1;      /* Channel 2 Interruput Overflow Status */
1492                 uint32_t CIOS1:1;      /* Channel 1 Interruput Overflow Status */
1493                 uint32_t CIOS0:1;      /* Channel 0 Interruput Overflow Status */
1494             } B;
1495         } CIOSR_A;
1496
1497         union {                 /* ETPU_B Interruput Overflow Status */
1498             uint32_t R;
1499             struct {
1500                 uint32_t CIOS31:1;     /* Channel 31 Interruput Overflow Status */
1501                 uint32_t CIOS30:1;     /* Channel 30 Interruput Overflow Status */
1502                 uint32_t CIOS29:1;     /* Channel 29 Interruput Overflow Status */
1503                 uint32_t CIOS28:1;     /* Channel 28 Interruput Overflow Status */
1504                 uint32_t CIOS27:1;     /* Channel 27 Interruput Overflow Status */
1505                 uint32_t CIOS26:1;     /* Channel 26 Interruput Overflow Status */
1506                 uint32_t CIOS25:1;     /* Channel 25 Interruput Overflow Status */
1507                 uint32_t CIOS24:1;     /* Channel 24 Interruput Overflow Status */
1508                 uint32_t CIOS23:1;     /* Channel 23 Interruput Overflow Status */
1509                 uint32_t CIOS22:1;     /* Channel 22 Interruput Overflow Status */
1510                 uint32_t CIOS21:1;     /* Channel 21 Interruput Overflow Status */
1511                 uint32_t CIOS20:1;     /* Channel 20 Interruput Overflow Status */
1512                 uint32_t CIOS19:1;     /* Channel 19 Interruput Overflow Status */
1513                 uint32_t CIOS18:1;     /* Channel 18 Interruput Overflow Status */
1514                 uint32_t CIOS17:1;     /* Channel 17 Interruput Overflow Status */
1515                 uint32_t CIOS16:1;     /* Channel 16 Interruput Overflow Status */
1516                 uint32_t CIOS15:1;     /* Channel 15 Interruput Overflow Status */
1517                 uint32_t CIOS14:1;     /* Channel 14 Interruput Overflow Status */
1518                 uint32_t CIOS13:1;     /* Channel 13 Interruput Overflow Status */
1519                 uint32_t CIOS12:1;     /* Channel 12 Interruput Overflow Status */
1520                 uint32_t CIOS11:1;     /* Channel 11 Interruput Overflow Status */
1521                 uint32_t CIOS10:1;     /* Channel 10 Interruput Overflow Status */
1522                 uint32_t CIOS9:1;      /* Channel 9 Interruput Overflow Status */
1523                 uint32_t CIOS8:1;      /* Channel 8 Interruput Overflow Status */
1524                 uint32_t CIOS7:1;      /* Channel 7 Interruput Overflow Status */
1525                 uint32_t CIOS6:1;      /* Channel 6 Interruput Overflow Status */
1526                 uint32_t CIOS5:1;      /* Channel 5 Interruput Overflow Status */
1527                 uint32_t CIOS4:1;      /* Channel 4 Interruput Overflow Status */
1528                 uint32_t CIOS3:1;      /* Channel 3 Interruput Overflow Status */
1529                 uint32_t CIOS2:1;      /* Channel 2 Interruput Overflow Status */
1530                 uint32_t CIOS1:1;      /* Channel 1 Interruput Overflow Status */
1531                 uint32_t CIOS0:1;      /* Channel 0 Interruput Overflow Status */
1532             } B;
1533         } CIOSR_B;
1534
1535         uint32_t etpu_reserved13[2];
1536
1537         union {                 /* ETPU_A Data Transfer Overflow Status */
1538             uint32_t R;
1539             struct {
1540                 uint32_t DTROS31:1;    /* Channel 31 Data Transfer Overflow Status */
1541                 uint32_t DTROS30:1;    /* Channel 30 Data Transfer Overflow Status */
1542                 uint32_t DTROS29:1;    /* Channel 29 Data Transfer Overflow Status */
1543                 uint32_t DTROS28:1;    /* Channel 28 Data Transfer Overflow Status */
1544                 uint32_t DTROS27:1;    /* Channel 27 Data Transfer Overflow Status */
1545                 uint32_t DTROS26:1;    /* Channel 26 Data Transfer Overflow Status */
1546                 uint32_t DTROS25:1;    /* Channel 25 Data Transfer Overflow Status */
1547                 uint32_t DTROS24:1;    /* Channel 24 Data Transfer Overflow Status */
1548                 uint32_t DTROS23:1;    /* Channel 23 Data Transfer Overflow Status */
1549                 uint32_t DTROS22:1;    /* Channel 22 Data Transfer Overflow Status */
1550                 uint32_t DTROS21:1;    /* Channel 21 Data Transfer Overflow Status */
1551                 uint32_t DTROS20:1;    /* Channel 20 Data Transfer Overflow Status */
1552                 uint32_t DTROS19:1;    /* Channel 19 Data Transfer Overflow Status */
1553                 uint32_t DTROS18:1;    /* Channel 18 Data Transfer Overflow Status */
1554                 uint32_t DTROS17:1;    /* Channel 17 Data Transfer Overflow Status */
1555                 uint32_t DTROS16:1;    /* Channel 16 Data Transfer Overflow Status */
1556                 uint32_t DTROS15:1;    /* Channel 15 Data Transfer Overflow Status */
1557                 uint32_t DTROS14:1;    /* Channel 14 Data Transfer Overflow Status */
1558                 uint32_t DTROS13:1;    /* Channel 13 Data Transfer Overflow Status */
1559                 uint32_t DTROS12:1;    /* Channel 12 Data Transfer Overflow Status */
1560                 uint32_t DTROS11:1;    /* Channel 11 Data Transfer Overflow Status */
1561                 uint32_t DTROS10:1;    /* Channel 10 Data Transfer Overflow Status */
1562                 uint32_t DTROS9:1;     /* Channel 9 Data Transfer Overflow Status */
1563                 uint32_t DTROS8:1;     /* Channel 8 Data Transfer Overflow Status */
1564                 uint32_t DTROS7:1;     /* Channel 7 Data Transfer Overflow Status */
1565                 uint32_t DTROS6:1;     /* Channel 6 Data Transfer Overflow Status */
1566                 uint32_t DTROS5:1;     /* Channel 5 Data Transfer Overflow Status */
1567                 uint32_t DTROS4:1;     /* Channel 4 Data Transfer Overflow Status */
1568                 uint32_t DTROS3:1;     /* Channel 3 Data Transfer Overflow Status */
1569                 uint32_t DTROS2:1;     /* Channel 2 Data Transfer Overflow Status */
1570                 uint32_t DTROS1:1;     /* Channel 1 Data Transfer Overflow Status */
1571                 uint32_t DTROS0:1;     /* Channel 0 Data Transfer Overflow Status */
1572             } B;
1573         } CDTROSR_A;
1574
1575         union {                 /* ETPU_B Data Transfer Overflow Status */
1576             uint32_t R;
1577             struct {
1578                 uint32_t DTROS31:1;    /* Channel 31 Data Transfer Overflow Status */
1579                 uint32_t DTROS30:1;    /* Channel 30 Data Transfer Overflow Status */
1580                 uint32_t DTROS29:1;    /* Channel 29 Data Transfer Overflow Status */
1581                 uint32_t DTROS28:1;    /* Channel 28 Data Transfer Overflow Status */
1582                 uint32_t DTROS27:1;    /* Channel 27 Data Transfer Overflow Status */
1583                 uint32_t DTROS26:1;    /* Channel 26 Data Transfer Overflow Status */
1584                 uint32_t DTROS25:1;    /* Channel 25 Data Transfer Overflow Status */
1585                 uint32_t DTROS24:1;    /* Channel 24 Data Transfer Overflow Status */
1586                 uint32_t DTROS23:1;    /* Channel 23 Data Transfer Overflow Status */
1587                 uint32_t DTROS22:1;    /* Channel 22 Data Transfer Overflow Status */
1588                 uint32_t DTROS21:1;    /* Channel 21 Data Transfer Overflow Status */
1589                 uint32_t DTROS20:1;    /* Channel 20 Data Transfer Overflow Status */
1590                 uint32_t DTROS19:1;    /* Channel 19 Data Transfer Overflow Status */
1591                 uint32_t DTROS18:1;    /* Channel 18 Data Transfer Overflow Status */
1592                 uint32_t DTROS17:1;    /* Channel 17 Data Transfer Overflow Status */
1593                 uint32_t DTROS16:1;    /* Channel 16 Data Transfer Overflow Status */
1594                 uint32_t DTROS15:1;    /* Channel 15 Data Transfer Overflow Status */
1595                 uint32_t DTROS14:1;    /* Channel 14 Data Transfer Overflow Status */
1596                 uint32_t DTROS13:1;    /* Channel 13 Data Transfer Overflow Status */
1597                 uint32_t DTROS12:1;    /* Channel 12 Data Transfer Overflow Status */
1598                 uint32_t DTROS11:1;    /* Channel 11 Data Transfer Overflow Status */
1599                 uint32_t DTROS10:1;    /* Channel 10 Data Transfer Overflow Status */
1600                 uint32_t DTROS9:1;     /* Channel 9 Data Transfer Overflow Status */
1601                 uint32_t DTROS8:1;     /* Channel 8 Data Transfer Overflow Status */
1602                 uint32_t DTROS7:1;     /* Channel 7 Data Transfer Overflow Status */
1603                 uint32_t DTROS6:1;     /* Channel 6 Data Transfer Overflow Status */
1604                 uint32_t DTROS5:1;     /* Channel 5 Data Transfer Overflow Status */
1605                 uint32_t DTROS4:1;     /* Channel 4 Data Transfer Overflow Status */
1606                 uint32_t DTROS3:1;     /* Channel 3 Data Transfer Overflow Status */
1607                 uint32_t DTROS2:1;     /* Channel 2 Data Transfer Overflow Status */
1608                 uint32_t DTROS1:1;     /* Channel 1 Data Transfer Overflow Status */
1609                 uint32_t DTROS0:1;     /* Channel 0 Data Transfer Overflow Status */
1610             } B;
1611         } CDTROSR_B;
1612
1613         uint32_t etpu_reserved15[2];
1614
1615         union {                 /* ETPU_A Channel Interruput Enable */
1616             uint32_t R;
1617             struct {
1618                 uint32_t CIE31:1;      /* Channel 31 Interruput Enable */
1619                 uint32_t CIE30:1;      /* Channel 30 Interruput Enable */
1620                 uint32_t CIE29:1;      /* Channel 29 Interruput Enable */
1621                 uint32_t CIE28:1;      /* Channel 28 Interruput Enable */
1622                 uint32_t CIE27:1;      /* Channel 27 Interruput Enable */
1623                 uint32_t CIE26:1;      /* Channel 26 Interruput Enable */
1624                 uint32_t CIE25:1;      /* Channel 25 Interruput Enable */
1625                 uint32_t CIE24:1;      /* Channel 24 Interruput Enable */
1626                 uint32_t CIE23:1;      /* Channel 23 Interruput Enable */
1627                 uint32_t CIE22:1;      /* Channel 22 Interruput Enable */
1628                 uint32_t CIE21:1;      /* Channel 21 Interruput Enable */
1629                 uint32_t CIE20:1;      /* Channel 20 Interruput Enable */
1630                 uint32_t CIE19:1;      /* Channel 19 Interruput Enable */
1631                 uint32_t CIE18:1;      /* Channel 18 Interruput Enable */
1632                 uint32_t CIE17:1;      /* Channel 17 Interruput Enable */
1633                 uint32_t CIE16:1;      /* Channel 16 Interruput Enable */
1634                 uint32_t CIE15:1;      /* Channel 15 Interruput Enable */
1635                 uint32_t CIE14:1;      /* Channel 14 Interruput Enable */
1636                 uint32_t CIE13:1;      /* Channel 13 Interruput Enable */
1637                 uint32_t CIE12:1;      /* Channel 12 Interruput Enable */
1638                 uint32_t CIE11:1;      /* Channel 11 Interruput Enable */
1639                 uint32_t CIE10:1;      /* Channel 10 Interruput Enable */
1640                 uint32_t CIE9:1;       /* Channel 9 Interruput Enable */
1641                 uint32_t CIE8:1;       /* Channel 8 Interruput Enable */
1642                 uint32_t CIE7:1;       /* Channel 7 Interruput Enable */
1643                 uint32_t CIE6:1;       /* Channel 6 Interruput Enable */
1644                 uint32_t CIE5:1;       /* Channel 5 Interruput Enable */
1645                 uint32_t CIE4:1;       /* Channel 4 Interruput Enable */
1646                 uint32_t CIE3:1;       /* Channel 3 Interruput Enable */
1647                 uint32_t CIE2:1;       /* Channel 2 Interruput Enable */
1648                 uint32_t CIE1:1;       /* Channel 1 Interruput Enable */
1649                 uint32_t CIE0:1;       /* Channel 0 Interruput Enable */
1650             } B;
1651         } CIER_A;
1652
1653         union {                 /* ETPU_B Channel Interruput Enable */
1654             uint32_t R;
1655             struct {
1656                 uint32_t CIE31:1;      /* Channel 31 Interruput Enable */
1657                 uint32_t CIE30:1;      /* Channel 30 Interruput Enable */
1658                 uint32_t CIE29:1;      /* Channel 29 Interruput Enable */
1659                 uint32_t CIE28:1;      /* Channel 28 Interruput Enable */
1660                 uint32_t CIE27:1;      /* Channel 27 Interruput Enable */
1661                 uint32_t CIE26:1;      /* Channel 26 Interruput Enable */
1662                 uint32_t CIE25:1;      /* Channel 25 Interruput Enable */
1663                 uint32_t CIE24:1;      /* Channel 24 Interruput Enable */
1664                 uint32_t CIE23:1;      /* Channel 23 Interruput Enable */
1665                 uint32_t CIE22:1;      /* Channel 22 Interruput Enable */
1666                 uint32_t CIE21:1;      /* Channel 21 Interruput Enable */
1667                 uint32_t CIE20:1;      /* Channel 20 Interruput Enable */
1668                 uint32_t CIE19:1;      /* Channel 19 Interruput Enable */
1669                 uint32_t CIE18:1;      /* Channel 18 Interruput Enable */
1670                 uint32_t CIE17:1;      /* Channel 17 Interruput Enable */
1671                 uint32_t CIE16:1;      /* Channel 16 Interruput Enable */
1672                 uint32_t CIE15:1;      /* Channel 15 Interruput Enable */
1673                 uint32_t CIE14:1;      /* Channel 14 Interruput Enable */
1674                 uint32_t CIE13:1;      /* Channel 13 Interruput Enable */
1675                 uint32_t CIE12:1;      /* Channel 12 Interruput Enable */
1676                 uint32_t CIE11:1;      /* Channel 11 Interruput Enable */
1677                 uint32_t CIE10:1;      /* Channel 10 Interruput Enable */
1678                 uint32_t CIE9:1;       /* Channel 9 Interruput Enable */
1679                 uint32_t CIE8:1;       /* Channel 8 Interruput Enable */
1680                 uint32_t CIE7:1;       /* Channel 7 Interruput Enable */
1681                 uint32_t CIE6:1;       /* Channel 6 Interruput Enable */
1682                 uint32_t CIE5:1;       /* Channel 5 Interruput Enable */
1683                 uint32_t CIE4:1;       /* Channel 4 Interruput Enable */
1684                 uint32_t CIE3:1;       /* Channel 3 Interruput Enable */
1685                 uint32_t CIE2:1;       /* Channel 2 Interruput Enable */
1686                 uint32_t CIE1:1;       /* Channel 1 Interruput Enable */
1687                 uint32_t CIE0:1;       /* Channel 0 Interruput Enable */
1688             } B;
1689         } CIER_B;
1690
1691         uint32_t etpu_reserved17[2];
1692
1693         union {                 /* ETPU_A Channel Data Transfer Request Enable */
1694             uint32_t R;
1695             struct {
1696                 uint32_t DTRE31:1;     /* Channel 31 Data Transfer Request Enable */
1697                 uint32_t DTRE30:1;     /* Channel 30 Data Transfer Request Enable */
1698                 uint32_t DTRE29:1;     /* Channel 29 Data Transfer Request Enable */
1699                 uint32_t DTRE28:1;     /* Channel 28 Data Transfer Request Enable */
1700                 uint32_t DTRE27:1;     /* Channel 27 Data Transfer Request Enable */
1701                 uint32_t DTRE26:1;     /* Channel 26 Data Transfer Request Enable */
1702                 uint32_t DTRE25:1;     /* Channel 25 Data Transfer Request Enable */
1703                 uint32_t DTRE24:1;     /* Channel 24 Data Transfer Request Enable */
1704                 uint32_t DTRE23:1;     /* Channel 23 Data Transfer Request Enable */
1705                 uint32_t DTRE22:1;     /* Channel 22 Data Transfer Request Enable */
1706                 uint32_t DTRE21:1;     /* Channel 21 Data Transfer Request Enable */
1707                 uint32_t DTRE20:1;     /* Channel 20 Data Transfer Request Enable */
1708                 uint32_t DTRE19:1;     /* Channel 19 Data Transfer Request Enable */
1709                 uint32_t DTRE18:1;     /* Channel 18 Data Transfer Request Enable */
1710                 uint32_t DTRE17:1;     /* Channel 17 Data Transfer Request Enable */
1711                 uint32_t DTRE16:1;     /* Channel 16 Data Transfer Request Enable */
1712                 uint32_t DTRE15:1;     /* Channel 15 Data Transfer Request Enable */
1713                 uint32_t DTRE14:1;     /* Channel 14 Data Transfer Request Enable */
1714                 uint32_t DTRE13:1;     /* Channel 13 Data Transfer Request Enable */
1715                 uint32_t DTRE12:1;     /* Channel 12 Data Transfer Request Enable */
1716                 uint32_t DTRE11:1;     /* Channel 11 Data Transfer Request Enable */
1717                 uint32_t DTRE10:1;     /* Channel 10 Data Transfer Request Enable */
1718                 uint32_t DTRE9:1;      /* Channel 9 Data Transfer Request Enable */
1719                 uint32_t DTRE8:1;      /* Channel 8 Data Transfer Request Enable */
1720                 uint32_t DTRE7:1;      /* Channel 7 Data Transfer Request Enable */
1721                 uint32_t DTRE6:1;      /* Channel 6 Data Transfer Request Enable */
1722                 uint32_t DTRE5:1;      /* Channel 5 Data Transfer Request Enable */
1723                 uint32_t DTRE4:1;      /* Channel 4 Data Transfer Request Enable */
1724                 uint32_t DTRE3:1;      /* Channel 3 Data Transfer Request Enable */
1725                 uint32_t DTRE2:1;      /* Channel 2 Data Transfer Request Enable */
1726                 uint32_t DTRE1:1;      /* Channel 1 Data Transfer Request Enable */
1727                 uint32_t DTRE0:1;      /* Channel 0 Data Transfer Request Enable */
1728             } B;
1729         } CDTRER_A;
1730
1731         union {                 /* ETPU_B Channel Data Transfer Request Enable */
1732             uint32_t R;
1733             struct {
1734                 uint32_t DTRE31:1;     /* Channel 31 Data Transfer Request Enable */
1735                 uint32_t DTRE30:1;     /* Channel 30 Data Transfer Request Enable */
1736                 uint32_t DTRE29:1;     /* Channel 29 Data Transfer Request Enable */
1737                 uint32_t DTRE28:1;     /* Channel 28 Data Transfer Request Enable */
1738                 uint32_t DTRE27:1;     /* Channel 27 Data Transfer Request Enable */
1739                 uint32_t DTRE26:1;     /* Channel 26 Data Transfer Request Enable */
1740                 uint32_t DTRE25:1;     /* Channel 25 Data Transfer Request Enable */
1741                 uint32_t DTRE24:1;     /* Channel 24 Data Transfer Request Enable */
1742                 uint32_t DTRE23:1;     /* Channel 23 Data Transfer Request Enable */
1743                 uint32_t DTRE22:1;     /* Channel 22 Data Transfer Request Enable */
1744                 uint32_t DTRE21:1;     /* Channel 21 Data Transfer Request Enable */
1745                 uint32_t DTRE20:1;     /* Channel 20 Data Transfer Request Enable */
1746                 uint32_t DTRE19:1;     /* Channel 19 Data Transfer Request Enable */
1747                 uint32_t DTRE18:1;     /* Channel 18 Data Transfer Request Enable */
1748                 uint32_t DTRE17:1;     /* Channel 17 Data Transfer Request Enable */
1749                 uint32_t DTRE16:1;     /* Channel 16 Data Transfer Request Enable */
1750                 uint32_t DTRE15:1;     /* Channel 15 Data Transfer Request Enable */
1751                 uint32_t DTRE14:1;     /* Channel 14 Data Transfer Request Enable */
1752                 uint32_t DTRE13:1;     /* Channel 13 Data Transfer Request Enable */
1753                 uint32_t DTRE12:1;     /* Channel 12 Data Transfer Request Enable */
1754                 uint32_t DTRE11:1;     /* Channel 11 Data Transfer Request Enable */
1755                 uint32_t DTRE10:1;     /* Channel 10 Data Transfer Request Enable */
1756                 uint32_t DTRE9:1;      /* Channel 9 Data Transfer Request Enable */
1757                 uint32_t DTRE8:1;      /* Channel 8 Data Transfer Request Enable */
1758                 uint32_t DTRE7:1;      /* Channel 7 Data Transfer Request Enable */
1759                 uint32_t DTRE6:1;      /* Channel 6 Data Transfer Request Enable */
1760                 uint32_t DTRE5:1;      /* Channel 5 Data Transfer Request Enable */
1761                 uint32_t DTRE4:1;      /* Channel 4 Data Transfer Request Enable */
1762                 uint32_t DTRE3:1;      /* Channel 3 Data Transfer Request Enable */
1763                 uint32_t DTRE2:1;      /* Channel 2 Data Transfer Request Enable */
1764                 uint32_t DTRE1:1;      /* Channel 1 Data Transfer Request Enable */
1765                 uint32_t DTRE0:1;      /* Channel 0 Data Transfer Request Enable */
1766             } B;
1767         } CDTRER_B;
1768
1769         uint32_t etpu_reserved20[10];
1770         union {                 /* ETPU_A Channel Pending Service Status */
1771             uint32_t R;
1772             struct {
1773                 uint32_t SR31:1;       /* Channel 31 Pending Service Status */
1774                 uint32_t SR30:1;       /* Channel 30 Pending Service Status */
1775                 uint32_t SR29:1;       /* Channel 29 Pending Service Status */
1776                 uint32_t SR28:1;       /* Channel 28 Pending Service Status */
1777                 uint32_t SR27:1;       /* Channel 27 Pending Service Status */
1778                 uint32_t SR26:1;       /* Channel 26 Pending Service Status */
1779                 uint32_t SR25:1;       /* Channel 25 Pending Service Status */
1780                 uint32_t SR24:1;       /* Channel 24 Pending Service Status */
1781                 uint32_t SR23:1;       /* Channel 23 Pending Service Status */
1782                 uint32_t SR22:1;       /* Channel 22 Pending Service Status */
1783                 uint32_t SR21:1;       /* Channel 21 Pending Service Status */
1784                 uint32_t SR20:1;       /* Channel 20 Pending Service Status */
1785                 uint32_t SR19:1;       /* Channel 19 Pending Service Status */
1786                 uint32_t SR18:1;       /* Channel 18 Pending Service Status */
1787                 uint32_t SR17:1;       /* Channel 17 Pending Service Status */
1788                 uint32_t SR16:1;       /* Channel 16 Pending Service Status */
1789                 uint32_t SR15:1;       /* Channel 15 Pending Service Status */
1790                 uint32_t SR14:1;       /* Channel 14 Pending Service Status */
1791                 uint32_t SR13:1;       /* Channel 13 Pending Service Status */
1792                 uint32_t SR12:1;       /* Channel 12 Pending Service Status */
1793                 uint32_t SR11:1;       /* Channel 11 Pending Service Status */
1794                 uint32_t SR10:1;       /* Channel 10 Pending Service Status */
1795                 uint32_t SR9:1;        /* Channel 9 Pending Service Status */
1796                 uint32_t SR8:1;        /* Channel 8 Pending Service Status */
1797                 uint32_t SR7:1;        /* Channel 7 Pending Service Status */
1798                 uint32_t SR6:1;        /* Channel 6 Pending Service Status */
1799                 uint32_t SR5:1;        /* Channel 5 Pending Service Status */
1800                 uint32_t SR4:1;        /* Channel 4 Pending Service Status */
1801                 uint32_t SR3:1;        /* Channel 3 Pending Service Status */
1802                 uint32_t SR2:1;        /* Channel 2 Pending Service Status */
1803                 uint32_t SR1:1;        /* Channel 1 Pending Service Status */
1804                 uint32_t SR0:1;        /* Channel 0 Pending Service Status */
1805             } B;
1806         } CPSSR_A;
1807
1808         union {                 /* ETPU_B Channel Pending Service Status */
1809             uint32_t R;
1810             struct {
1811                 uint32_t SR31:1;       /* Channel 31 Pending Service Status */
1812                 uint32_t SR30:1;       /* Channel 30 Pending Service Status */
1813                 uint32_t SR29:1;       /* Channel 29 Pending Service Status */
1814                 uint32_t SR28:1;       /* Channel 28 Pending Service Status */
1815                 uint32_t SR27:1;       /* Channel 27 Pending Service Status */
1816                 uint32_t SR26:1;       /* Channel 26 Pending Service Status */
1817                 uint32_t SR25:1;       /* Channel 25 Pending Service Status */
1818                 uint32_t SR24:1;       /* Channel 24 Pending Service Status */
1819                 uint32_t SR23:1;       /* Channel 23 Pending Service Status */
1820                 uint32_t SR22:1;       /* Channel 22 Pending Service Status */
1821                 uint32_t SR21:1;       /* Channel 21 Pending Service Status */
1822                 uint32_t SR20:1;       /* Channel 20 Pending Service Status */
1823                 uint32_t SR19:1;       /* Channel 19 Pending Service Status */
1824                 uint32_t SR18:1;       /* Channel 18 Pending Service Status */
1825                 uint32_t SR17:1;       /* Channel 17 Pending Service Status */
1826                 uint32_t SR16:1;       /* Channel 16 Pending Service Status */
1827                 uint32_t SR15:1;       /* Channel 15 Pending Service Status */
1828                 uint32_t SR14:1;       /* Channel 14 Pending Service Status */
1829                 uint32_t SR13:1;       /* Channel 13 Pending Service Status */
1830                 uint32_t SR12:1;       /* Channel 12 Pending Service Status */
1831                 uint32_t SR11:1;       /* Channel 11 Pending Service Status */
1832                 uint32_t SR10:1;       /* Channel 10 Pending Service Status */
1833                 uint32_t SR9:1;        /* Channel 9 Pending Service Status */
1834                 uint32_t SR8:1;        /* Channel 8 Pending Service Status */
1835                 uint32_t SR7:1;        /* Channel 7 Pending Service Status */
1836                 uint32_t SR6:1;        /* Channel 6 Pending Service Status */
1837                 uint32_t SR5:1;        /* Channel 5 Pending Service Status */
1838                 uint32_t SR4:1;        /* Channel 4 Pending Service Status */
1839                 uint32_t SR3:1;        /* Channel 3 Pending Service Status */
1840                 uint32_t SR2:1;        /* Channel 2 Pending Service Status */
1841                 uint32_t SR1:1;        /* Channel 1 Pending Service Status */
1842                 uint32_t SR0:1;        /* Channel 0 Pending Service Status */
1843             } B;
1844         } CPSSR_B;
1845
1846         uint32_t etpu_reserved20a[2];
1847
1848         union {                 /* ETPU_A Channel Service Status */
1849             uint32_t R;
1850             struct {
1851                 uint32_t SS31:1;       /* Channel 31 Service Status */
1852                 uint32_t SS30:1;       /* Channel 30 Service Status */
1853                 uint32_t SS29:1;       /* Channel 29 Service Status */
1854                 uint32_t SS28:1;       /* Channel 28 Service Status */
1855                 uint32_t SS27:1;       /* Channel 27 Service Status */
1856                 uint32_t SS26:1;       /* Channel 26 Service Status */
1857                 uint32_t SS25:1;       /* Channel 25 Service Status */
1858                 uint32_t SS24:1;       /* Channel 24 Service Status */
1859                 uint32_t SS23:1;       /* Channel 23 Service Status */
1860                 uint32_t SS22:1;       /* Channel 22 Service Status */
1861                 uint32_t SS21:1;       /* Channel 21 Service Status */
1862                 uint32_t SS20:1;       /* Channel 20 Service Status */
1863                 uint32_t SS19:1;       /* Channel 19 Service Status */
1864                 uint32_t SS18:1;       /* Channel 18 Service Status */
1865                 uint32_t SS17:1;       /* Channel 17 Service Status */
1866                 uint32_t SS16:1;       /* Channel 16 Service Status */
1867                 uint32_t SS15:1;       /* Channel 15 Service Status */
1868                 uint32_t SS14:1;       /* Channel 14 Service Status */
1869                 uint32_t SS13:1;       /* Channel 13 Service Status */
1870                 uint32_t SS12:1;       /* Channel 12 Service Status */
1871                 uint32_t SS11:1;       /* Channel 11 Service Status */
1872                 uint32_t SS10:1;       /* Channel 10 Service Status */
1873                 uint32_t SS9:1;        /* Channel 9 Service Status */
1874                 uint32_t SS8:1;        /* Channel 8 Service Status */
1875                 uint32_t SS7:1;        /* Channel 7 Service Status */
1876                 uint32_t SS6:1;        /* Channel 6 Service Status */
1877                 uint32_t SS5:1;        /* Channel 5 Service Status */
1878                 uint32_t SS4:1;        /* Channel 4 Service Status */
1879                 uint32_t SS3:1;        /* Channel 3 Service Status */
1880                 uint32_t SS2:1;        /* Channel 2 Service Status */
1881                 uint32_t SS1:1;        /* Channel 1 Service Status */
1882                 uint32_t SS0:1;        /* Channel 0 Service Status */
1883             } B;
1884         } CSSR_A;
1885
1886         union {                 /* ETPU_B Channel Service Status */
1887             uint32_t R;
1888             struct {
1889                 uint32_t SS31:1;       /* Channel 31 Service Status */
1890                 uint32_t SS30:1;       /* Channel 30 Service Status */
1891                 uint32_t SS29:1;       /* Channel 29 Service Status */
1892                 uint32_t SS28:1;       /* Channel 28 Service Status */
1893                 uint32_t SS27:1;       /* Channel 27 Service Status */
1894                 uint32_t SS26:1;       /* Channel 26 Service Status */
1895                 uint32_t SS25:1;       /* Channel 25 Service Status */
1896                 uint32_t SS24:1;       /* Channel 24 Service Status */
1897                 uint32_t SS23:1;       /* Channel 23 Service Status */
1898                 uint32_t SS22:1;       /* Channel 22 Service Status */
1899                 uint32_t SS21:1;       /* Channel 21 Service Status */
1900                 uint32_t SS20:1;       /* Channel 20 Service Status */
1901                 uint32_t SS19:1;       /* Channel 19 Service Status */
1902                 uint32_t SS18:1;       /* Channel 18 Service Status */
1903                 uint32_t SS17:1;       /* Channel 17 Service Status */
1904                 uint32_t SS16:1;       /* Channel 16 Service Status */
1905                 uint32_t SS15:1;       /* Channel 15 Service Status */
1906                 uint32_t SS14:1;       /* Channel 14 Service Status */
1907                 uint32_t SS13:1;       /* Channel 13 Service Status */
1908                 uint32_t SS12:1;       /* Channel 12 Service Status */
1909                 uint32_t SS11:1;       /* Channel 11 Service Status */
1910                 uint32_t SS10:1;       /* Channel 10 Service Status */
1911                 uint32_t SS9:1;        /* Channel 9 Service Status */
1912                 uint32_t SS8:1;        /* Channel 8 Service Status */
1913                 uint32_t SS7:1;        /* Channel 7 Service Status */
1914                 uint32_t SS6:1;        /* Channel 6 Service Status */
1915                 uint32_t SS5:1;        /* Channel 5 Service Status */
1916                 uint32_t SS4:1;        /* Channel 4 Service Status */
1917                 uint32_t SS3:1;        /* Channel 3 Service Status */
1918                 uint32_t SS2:1;        /* Channel 2 Service Status */
1919                 uint32_t SS1:1;        /* Channel 1 Service Status */
1920                 uint32_t SS0:1;        /* Channel 0 Service Status */
1921             } B;
1922         } CSSR_B;
1923
1924         uint32_t etpu_reserved23[90];
1925
1926 /*****************************Channels********************************/
1927
1928         struct {
1929             union {
1930                 uint32_t R;    /* Channel Configuration Register */
1931                 struct {
1932                     uint32_t CIE:1;    /* Channel Interruput Enable */
1933                     uint32_t DTRE:1;   /* Data Transfer Request Enable */
1934                     uint32_t CPR:2;    /* Channel Priority */
1935                       uint32_t:3;
1936                     uint32_t ETCS:1;   /* Entry Table Condition Select */
1937                       uint32_t:3;
1938                     uint32_t CFS:5;    /* Channel Function Select */
1939                     uint32_t ODIS:1;   /* Output disable */
1940                     uint32_t OPOL:1;   /* output polarity */
1941                       uint32_t:3;
1942                     uint32_t CPBA:11;  /* Channel Parameter Base Address */
1943                 } B;
1944             } CR;
1945             union {
1946                 uint32_t R;    /* Channel Status Control Register */
1947                 struct {
1948                     uint32_t CIS:1;    /* Channel Interruput Status */
1949                     uint32_t CIOS:1;   /* Channel Interruput Overflow Status */
1950                       uint32_t:6;
1951                     uint32_t DTRS:1;   /* Data Transfer Status */
1952                     uint32_t DTROS:1;  /* Data Transfer Overflow Status */
1953                       uint32_t:6;
1954                     uint32_t IPS:1;    /* Input Pin State */
1955                     uint32_t OPS:1;    /* Output Pin State */
1956                     uint32_t OBE:1;    /* Output Buffer Enable */
1957                       uint32_t:11;
1958                     uint32_t FM1:1;    /* Function mode */
1959                     uint32_t FM0:1;    /* Function mode */
1960                 } B;
1961             } SCR;
1962             union {
1963                 uint32_t R;    /* Channel Host Service Request Register */
1964                 struct {
1965                     uint32_t:29;       /* Host Service Request */
1966                     uint32_t HSR:3;
1967                 } B;
1968             } HSRR;
1969             uint32_t etpu_reserved23;
1970         } CHAN[127];
1971
1972     };
1973 /****************************************************************************/
1974 /*                          MODULE : XBAR CrossBar                          */
1975 /****************************************************************************/
1976     struct XBAR_tag {
1977         union {
1978             uint32_t R;
1979             struct {
1980                 uint32_t:4;
1981
1982                 uint32_t:4;
1983
1984                 uint32_t:4;
1985
1986                 uint32_t:4;
1987
1988                 uint32_t:4;
1989
1990                 uint32_t:1;
1991                 uint32_t MSTR2:3;
1992                   uint32_t:1;
1993                 uint32_t MSTR1:3;
1994                   uint32_t:1;
1995                 uint32_t MSTR0:3;
1996             } B;
1997         } MPR0;                 /* Master Priority Register for Slave Port 0 */
1998
1999         uint32_t xbar_reserved1[3];
2000
2001         union {
2002             uint32_t R;
2003             struct {
2004                 uint32_t RO:1;
2005                   uint32_t:21;
2006                 uint32_t ARB:2;
2007                   uint32_t:2;
2008                 uint32_t PCTL:2;
2009                   uint32_t:1;
2010                 uint32_t PARK:3;
2011             } B;
2012         } SGPCR0;               /* General Purpose Control Register for Slave Port 0 */
2013
2014         uint32_t xbar_reserved2[59];
2015
2016         union {
2017             uint32_t R;
2018             struct {
2019                 uint32_t:4;
2020
2021                 uint32_t:4;
2022
2023                 uint32_t:4;
2024
2025                 uint32_t:4;
2026
2027                 uint32_t:4;
2028
2029                 uint32_t:1;
2030                 uint32_t MSTR2:3;
2031                   uint32_t:1;
2032                 uint32_t MSTR1:3;
2033                   uint32_t:1;
2034                 uint32_t MSTR0:3;
2035             } B;
2036         } MPR1;                 /* Master Priority Register for Slave Port 1 */
2037
2038         uint32_t xbar_reserved3[3];
2039
2040         union {
2041             uint32_t R;
2042             struct {
2043                 uint32_t RO:1;
2044                   uint32_t:21;
2045                 uint32_t ARB:2;
2046                   uint32_t:2;
2047                 uint32_t PCTL:2;
2048                   uint32_t:1;
2049                 uint32_t PARK:3;
2050             } B;
2051         } SGPCR1;               /* General Purpose Control Register for Slave Port 1 */
2052
2053         uint32_t xbar_reserved4[123];
2054
2055         union {
2056             uint32_t R;
2057             struct {
2058                 uint32_t:4;
2059
2060                 uint32_t:4;
2061
2062                 uint32_t:4;
2063
2064                 uint32_t:4;
2065
2066                 uint32_t:4;
2067
2068                 uint32_t:1;
2069                 uint32_t MSTR2:3;
2070                   uint32_t:1;
2071                 uint32_t MSTR1:3;
2072                   uint32_t:1;
2073                 uint32_t MSTR0:3;
2074             } B;
2075         } MPR3;                 /* Master Priority Register for Slave Port 3 */
2076
2077         uint32_t xbar_reserved5[3];
2078
2079         union {
2080             uint32_t R;
2081             struct {
2082                 uint32_t RO:1;
2083                   uint32_t:21;
2084                 uint32_t ARB:2;
2085                   uint32_t:2;
2086                 uint32_t PCTL:2;
2087                   uint32_t:1;
2088                 uint32_t PARK:3;
2089             } B;
2090         } SGPCR3;               /* General Purpose Control Register for Slave Port 3 */
2091         uint32_t xbar_reserved6[187];
2092
2093         union {
2094             uint32_t R;
2095             struct {
2096                 uint32_t:4;
2097
2098                 uint32_t:4;
2099
2100                 uint32_t:4;
2101
2102                 uint32_t:4;
2103
2104                 uint32_t:4;
2105
2106                 uint32_t:1;
2107                 uint32_t MSTR2:3;
2108                   uint32_t:1;
2109                 uint32_t MSTR1:3;
2110                   uint32_t:1;
2111                 uint32_t MSTR0:3;
2112             } B;
2113         } MPR6;                 /* Master Priority Register for Slave Port 6 */
2114
2115         uint32_t xbar_reserved7[3];
2116
2117         union {
2118             uint32_t R;
2119             struct {
2120                 uint32_t RO:1;
2121                   uint32_t:21;
2122                 uint32_t ARB:2;
2123                   uint32_t:2;
2124                 uint32_t PCTL:2;
2125                   uint32_t:1;
2126                 uint32_t PARK:3;
2127             } B;
2128         } SGPCR6;               /* General Purpose Control Register for Slave Port 6 */
2129
2130         uint32_t xbar_reserved8[59];
2131
2132         union {
2133             uint32_t R;
2134             struct {
2135                 uint32_t:4;
2136
2137                 uint32_t:4;
2138
2139                 uint32_t:4;
2140
2141                 uint32_t:4;
2142
2143                 uint32_t:4;
2144
2145                 uint32_t:1;
2146                 uint32_t MSTR2:3;
2147                   uint32_t:1;
2148                 uint32_t MSTR1:3;
2149                   uint32_t:1;
2150                 uint32_t MSTR0:3;
2151             } B;
2152         } MPR7;                 /* Master Priority Register for Slave Port 7 */
2153
2154         uint32_t xbar_reserved9[3];
2155
2156         union {
2157             uint32_t R;
2158             struct {
2159                 uint32_t RO:1;
2160                   uint32_t:21;
2161                 uint32_t ARB:2;
2162                   uint32_t:2;
2163                 uint32_t PCTL:2;
2164                   uint32_t:1;
2165                 uint32_t PARK:3;
2166             } B;
2167         } SGPCR7;               /* General Purpose Control Register for Slave Port 7 */
2168
2169     };
2170 /****************************************************************************/
2171 /*                     MODULE : ECSM                                        */
2172 /****************************************************************************/
2173     struct ECSM_tag {
2174
2175         uint32_t ecsm_reserved1[5];
2176
2177         uint16_t ecsm_reserved2;
2178
2179         union {
2180             uint16_t R;
2181         } SWTCR;                //Software Watchdog Timer Control
2182
2183         uint8_t ecsm_reserved3[3];
2184
2185         union {
2186             uint8_t R;
2187         } SWTSR;                //SWT Service Register
2188
2189         uint8_t ecsm_reserved4[3];
2190
2191         union {
2192             uint8_t R;
2193         } SWTIR;                //SWT Interrupt Register
2194
2195         uint32_t ecsm_reserved5a[1];
2196         uint32_t ecsm_reserved5b[1];
2197
2198         uint32_t ecsm_reserved5c[6];
2199
2200         uint8_t ecsm_reserved6[3];
2201
2202         union {
2203             uint8_t R;
2204             struct {
2205                 uint8_t:6;
2206                 uint8_t ERNCR:1;
2207                 uint8_t EFNCR:1;
2208             } B;
2209         } ECR;                  //ECC Configuration Register
2210
2211         uint8_t mcm_reserved8[3];
2212
2213         union {
2214             uint8_t R;
2215             struct {
2216                 uint8_t:6;
2217                 uint8_t RNCE:1;
2218                 uint8_t FNCE:1;
2219             } B;
2220         } ESR;                  //ECC Status Register
2221
2222         uint16_t ecsm_reserved9;
2223
2224         union {
2225             uint16_t R;
2226             struct {
2227                 uint16_t:6;
2228                 uint16_t FRCNCI:1;
2229                 uint16_t FR1NCI:1;
2230                   uint16_t:1;
2231                 uint16_t ERRBIT:7;
2232             } B;
2233         } EEGR;                 //ECC Error Generation Register
2234
2235         uint32_t ecsm_reserved10;
2236
2237         union {
2238             uint32_t R;
2239             struct {
2240                 uint32_t FEAR:32;
2241             } B;
2242         } FEAR;                 //Flash ECC Address Register
2243
2244         uint16_t ecsm_reserved11;
2245
2246         union {
2247             uint8_t R;
2248             struct {
2249                 uint8_t:4;
2250                 uint8_t FEMR:4;
2251             } B;
2252         } FEMR;                 //Flash ECC Master Register
2253
2254         union {
2255             uint8_t R;
2256             struct {
2257                 uint8_t WRITE:1;
2258                 uint8_t SIZE:3;
2259                 uint8_t PROT0:1;
2260                 uint8_t PROT1:1;
2261                 uint8_t PROT2:1;
2262                 uint8_t PROT3:1;
2263             } B;
2264         } FEAT;                 //Flash ECC Attributes Register
2265
2266         union {
2267             uint32_t R;
2268             struct {
2269                 uint32_t FEDH:32;
2270             } B;
2271         } FEDRH;                //Flash ECC Data High Register
2272
2273         union {
2274             uint32_t R;
2275             struct {
2276                 uint32_t FEDL:32;
2277             } B;
2278         } FEDRL;                //Flash ECC Data Low Register
2279
2280         union {
2281             uint32_t R;
2282             struct {
2283                 uint32_t REAR:32;
2284             } B;
2285         } REAR;                 //RAM ECC Address
2286
2287         uint8_t ecsm_reserved12[2];
2288
2289         union {
2290             uint8_t R;
2291             struct {
2292                 uint8_t:4;
2293                 uint8_t REMR:4;
2294             } B;
2295         } REMR;                 //RAM ECC Master
2296
2297         union {
2298             uint8_t R;
2299             struct {
2300                 uint8_t WRITE:1;
2301                 uint8_t SIZE:3;
2302                 uint8_t PROT0:1;
2303                 uint8_t PROT1:1;
2304                 uint8_t PROT2:1;
2305                 uint8_t PROT3:1;
2306             } B;
2307         } REAT;                 // RAM ECC Attributes Register
2308
2309         union {
2310             uint32_t R;
2311             struct {
2312                 uint32_t REDH:32;
2313             } B;
2314         } REDRH;                //RAM ECC Data High Register
2315
2316         union {
2317             uint32_t R;
2318             struct {
2319                 uint32_t REDL:32;
2320             } B;
2321         } REDRL;                //RAMECC Data Low Register
2322
2323     };
2324 /****************************************************************************/
2325 /*                          MODULE : INTC                                   */
2326 /****************************************************************************/
2327     struct INTC_tag {
2328         union {
2329             uint32_t R;
2330             struct {
2331                 uint32_t:26;
2332                 uint32_t VTES:1;
2333                   uint32_t:4;
2334                 uint32_t HVEN:1;
2335             } B;
2336         } MCR;                  /* Module Configuration Register */
2337
2338         int32_t INTC_reserved00;
2339
2340         union {
2341             uint32_t R;
2342             struct {
2343                 uint32_t:28;
2344                 uint32_t PRI:4;
2345             } B;
2346         } CPR;                  /* Current Priority Register */
2347
2348         uint32_t intc_reserved1;
2349
2350         union {
2351             uint32_t R;
2352             struct {
2353                 uint32_t VTBA:21;
2354                 uint32_t INTVEC:9;
2355                   uint32_t:2;
2356             } B;
2357         } IACKR;                /* Interrupt Acknowledge Register */
2358
2359         uint32_t intc_reserved2;
2360
2361         union {
2362             uint32_t R;
2363             struct {
2364                 uint32_t:32;
2365             } B;
2366         } EOIR;                 /* End of Interrupt Register */
2367
2368         uint32_t intc_reserved3;
2369
2370         union {
2371             uint8_t R;
2372             struct {
2373                 uint8_t:6;
2374                 uint8_t SET:1;
2375                 uint8_t CLR:1;
2376             } B;
2377         } SSCIR[8];             /* Software Set/Clear Interruput Register */
2378
2379         uint32_t intc_reserved4[6];
2380
2381         union {
2382             uint8_t R;
2383             struct {
2384                 uint8_t:4;
2385                 uint8_t PRI:4;
2386             } B;
2387         } PSR[358];             /* Software Set/Clear Interrupt Register */
2388
2389     };
2390 /****************************************************************************/
2391 /*                          MODULE : EQADC                                  */
2392 /****************************************************************************/
2393     struct EQADC_tag {
2394         union {
2395             uint32_t R;
2396             struct {
2397                 uint32_t:27;
2398                 uint32_t ESSIE:2;
2399                   uint32_t:1;
2400                 uint32_t DBG:2;
2401             } B;
2402         } MCR;                  /* Module Configuration Register */
2403
2404         int32_t EQADC_reserved00;
2405
2406         union {
2407             uint32_t R;
2408             struct {
2409                 uint32_t:6;
2410                 uint32_t NMF:26;
2411             } B;
2412         } NMSFR;                /* Null Message Send Format Register */
2413
2414         union {
2415             uint32_t R;
2416             struct {
2417                 uint32_t:28;
2418                 uint32_t DFL:4;
2419             } B;
2420         } ETDFR;                /* External Trigger Digital Filter Register */
2421
2422         union {
2423             uint32_t R;
2424             struct {
2425                 uint32_t CFPUSH:32;
2426             } B;
2427         } CFPR[6];              /* CFIFO Push Registers */
2428
2429         uint32_t eqadc_reserved1;
2430
2431         uint32_t eqadc_reserved2;
2432
2433         union {
2434             uint32_t R;
2435             struct {
2436                 uint32_t:16;
2437                 uint32_t RFPOP:16;
2438             } B;
2439         } RFPR[6];              /* Result FIFO Pop Registers */
2440
2441         uint32_t eqadc_reserved3;
2442
2443         uint32_t eqadc_reserved4;
2444
2445         union EQADC_CFCR_tag {
2446             uint16_t R;
2447             struct {
2448                 uint16_t:5;
2449                 uint16_t SSE:1;
2450                 uint16_t CFINV:1;
2451                   uint16_t:1;
2452                 uint16_t MODE:4;
2453                   uint16_t:4;
2454             } B;
2455         } CFCR[6];              /* CFIFO Control Registers */
2456
2457         uint32_t eqadc_reserved5;
2458
2459         union EQADC_IDCR_tag {
2460             uint16_t R;
2461             struct {
2462                 uint16_t NCIE:1;
2463                 uint16_t TORIE:1;
2464                 uint16_t PIE:1;
2465                 uint16_t EOQIE:1;
2466                 uint16_t CFUIE:1;
2467                   uint16_t:1;
2468                 uint16_t CFFE:1;
2469                 uint16_t CFFS:1;
2470                   uint16_t:4;
2471                 uint16_t RFOIE:1;
2472                   uint16_t:1;
2473                 uint16_t RFDE:1;
2474                 uint16_t RFDS:1;
2475             } B;
2476         } IDCR[6];              /* Interrupt and DMA Control Registers */
2477
2478         uint32_t eqadc_reserved6;
2479
2480         union EQADC_FISR_tag {
2481             uint32_t R;
2482             struct {
2483                 uint32_t NCF:1;
2484                 uint32_t TORF:1;
2485                 uint32_t PF:1;
2486                 uint32_t EOQF:1;
2487                 uint32_t CFUF:1;
2488                 uint32_t SSS:1;
2489                 uint32_t CFFF:1;
2490                   uint32_t:5;
2491                 uint32_t RFOF:1;
2492                   uint32_t:1;
2493                 uint32_t RFDF:1;
2494                   uint32_t:1;
2495                 uint32_t CFCTR:4;
2496                 uint32_t TNXTPTR:4;
2497                 uint32_t RFCTR:4;
2498                 uint32_t POPNXTPTR:4;
2499             } B;
2500         } FISR[6];              /* FIFO and Interrupt Status Registers */
2501
2502         uint32_t eqadc_reserved7;
2503
2504         uint32_t eqadc_reserved8;
2505
2506         union {
2507             uint16_t R;
2508             struct {
2509                 uint16_t:5;
2510                 uint16_t TCCF:11;
2511             } B;
2512         } CFTCR[6];             /* CFIFO Transfer Counter Registers */
2513
2514         uint32_t eqadc_reserved9;
2515
2516         union {
2517             uint32_t R;
2518             struct {
2519                 uint32_t CFS0:2;
2520                 uint32_t CFS1:2;
2521                 uint32_t CFS2:2;
2522                 uint32_t CFS3:2;
2523                 uint32_t CFS4:2;
2524                 uint32_t CFS5:2;
2525                   uint32_t:5;
2526                 uint32_t LCFTCB0:4;
2527                 uint32_t TC_LCFTCB0:11;
2528             } B;
2529         } CFSSR0;               /* CFIFO Status Register 0 */
2530
2531         union {
2532             uint32_t R;
2533             struct {
2534                 uint32_t CFS0:2;
2535                 uint32_t CFS1:2;
2536                 uint32_t CFS2:2;
2537                 uint32_t CFS3:2;
2538                 uint32_t CFS4:2;
2539                 uint32_t CFS5:2;
2540                   uint32_t:5;
2541                 uint32_t LCFTCB1:4;
2542                 uint32_t TC_LCFTCB1:11;
2543             } B;
2544         } CFSSR1;               /* CFIFO Status Register 1 */
2545
2546         union {
2547             uint32_t R;
2548             struct {
2549                 uint32_t CFS0:2;
2550                 uint32_t CFS1:2;
2551                 uint32_t CFS2:2;
2552                 uint32_t CFS3:2;
2553                 uint32_t CFS4:2;
2554                 uint32_t CFS5:2;
2555                   uint32_t:4;
2556                 uint32_t ECBNI:1;
2557                 uint32_t LCFTSSI:4;
2558                 uint32_t TC_LCFTSSI:11;
2559             } B;
2560         } CFSSR2;               /* CFIFO Status Register 2 */
2561
2562         union {
2563             uint32_t R;
2564             struct {
2565                 uint32_t CFS0:2;
2566                 uint32_t CFS1:2;
2567                 uint32_t CFS2:2;
2568                 uint32_t CFS3:2;
2569                 uint32_t CFS4:2;
2570                 uint32_t CFS5:2;
2571                   uint32_t:20;
2572             } B;
2573         } CFSR;
2574
2575         uint32_t eqadc_reserved11;
2576
2577         union {
2578             uint32_t R;
2579             struct {
2580                 uint32_t:21;
2581                 uint32_t MDT:3;
2582                   uint32_t:4;
2583                 uint32_t BR:4;
2584             } B;
2585         } SSICR;                /* SSI Control Register */
2586
2587         union {
2588             uint32_t R;
2589             struct {
2590                 uint32_t RDV:1;
2591                   uint32_t:5;
2592                 uint32_t RDATA:26;
2593             } B;
2594         } SSIRDR;               /* SSI Recieve Data Register */
2595
2596         uint32_t eqadc_reserved12[17];
2597
2598         struct {
2599             union {
2600                 uint32_t R;
2601                 struct {
2602                     uint32_t:32;
2603                 } B;
2604             } R[4];
2605
2606             uint32_t eqadc_reserved13[12];
2607
2608         } CF[6];
2609
2610         uint32_t eqadc_reserved14[32];
2611
2612         struct {
2613             union {
2614                 uint32_t R;
2615                 struct {
2616                     uint32_t:32;
2617                 } B;
2618             } R[4];
2619
2620             uint32_t eqadc_reserved15[12];
2621
2622         } RF[6];
2623
2624     };
2625
2626 /* Message Formats for On-Chip ADC Operation
2627  */
2628 union EQADC_CONVERSION_COMMAND_tag {
2629     uint32_t R;
2630     struct {
2631         uint32_t EOQ:1;
2632         uint32_t PAUSE:1;
2633             uint32_t:3;
2634         uint32_t EB:1;
2635         uint32_t BN:1;
2636         uint32_t CAL:1;
2637         uint32_t MESSAGE_TAG:4;
2638         uint32_t LST:2;
2639         uint32_t TSR:1;
2640         uint32_t FMT:1;
2641         uint32_t CHANNEL_NUMBER:8;
2642             uint32_t:8;
2643     } B;
2644 }; /* Conversion command */
2645
2646 union EQADC_WRITE_CONFIGURATION_COMMAND_tag {
2647     uint32_t R;
2648     struct {
2649         uint32_t EOQ:1;
2650         uint32_t PAUSE:1;
2651             uint32_t:3;
2652         uint32_t EB:1;
2653         uint32_t BN:1;
2654         uint32_t RW:1;
2655         uint32_t VALUE:16;
2656         uint32_t ADDR:8;
2657     } B;
2658 }; /* Write configuration command */
2659
2660 /****************************************************************************/
2661 /*                          MODULE : DSPI                                   */
2662 /****************************************************************************/
2663     struct DSPI_tag {
2664         union DSPI_MCR_tag {
2665             uint32_t R;
2666             struct {
2667                 uint32_t MSTR:1;
2668                 uint32_t CONT_SCKE:1;
2669                 uint32_t DCONF:2;
2670                 uint32_t FRZ:1;
2671                 uint32_t MTFE:1;
2672                 uint32_t PCSSE:1;
2673                 uint32_t ROOE:1;
2674                   uint32_t:2;
2675                 uint32_t PCSIS5:1;
2676                 uint32_t PCSIS4:1;
2677                 uint32_t PCSIS3:1;
2678                 uint32_t PCSIS2:1;
2679                 uint32_t PCSIS1:1;
2680                 uint32_t PCSIS0:1;
2681                 uint32_t DOZE:1;
2682                 uint32_t MDIS:1;
2683                 uint32_t DIS_TXF:1;
2684                 uint32_t DIS_RXF:1;
2685                 uint32_t CLR_TXF:1;
2686                 uint32_t CLR_RXF:1;
2687                 uint32_t SMPL_PT:2;
2688                   uint32_t:7;
2689                 uint32_t HALT:1;
2690             } B;
2691         } MCR;                  /* Module Configuration Register */
2692
2693         uint32_t dspi_reserved1;
2694
2695         union {
2696             uint32_t R;
2697             struct {
2698                 uint32_t TCNT:16;
2699                   uint32_t:16;
2700             } B;
2701         } TCR;
2702
2703         union DSPI_CTAR_tag {
2704             uint32_t R;
2705             struct {
2706                 uint32_t DBR:1;
2707                 uint32_t FMSZ:4;
2708                 uint32_t CPOL:1;
2709                 uint32_t CPHA:1;
2710                 uint32_t LSBFE:1;
2711                 uint32_t PCSSCK:2;
2712                 uint32_t PASC:2;
2713                 uint32_t PDT:2;
2714                 uint32_t PBR:2;
2715                 uint32_t CSSCK:4;
2716                 uint32_t ASC:4;
2717                 uint32_t DT:4;
2718                 uint32_t BR:4;
2719             } B;
2720         } CTAR[8];              /* Clock and Transfer Attributes Registers */
2721
2722         union DSPI_SR_tag {
2723             uint32_t R;
2724             struct {
2725                 uint32_t TCF:1;
2726                 uint32_t TXRXS:1;
2727                   uint32_t:1;
2728                 uint32_t EOQF:1;
2729                 uint32_t TFUF:1;
2730                   uint32_t:1;
2731                 uint32_t TFFF:1;
2732                   uint32_t:5;
2733                 uint32_t RFOF:1;
2734                   uint32_t:1;
2735                 uint32_t RFDF:1;
2736                   uint32_t:1;
2737                 uint32_t TXCTR:4;
2738                 uint32_t TXNXTPTR:4;
2739                 uint32_t RXCTR:4;
2740                 uint32_t POPNXTPTR:4;
2741             } B;
2742         } SR;                   /* Status Register */
2743
2744         union DSPI_RSER_tag {
2745             uint32_t R;
2746             struct {
2747                 uint32_t TCFRE:1;
2748                   uint32_t:2;
2749                 uint32_t EOQFRE:1;
2750                 uint32_t TFUFRE:1;
2751                   uint32_t:1;
2752                 uint32_t TFFFRE:1;
2753                 uint32_t TFFFDIRS:1;
2754                   uint32_t:4;
2755                 uint32_t RFOFRE:1;
2756                   uint32_t:1;
2757                 uint32_t RFDFRE:1;
2758                 uint32_t RFDFDIRS:1;
2759                   uint32_t:16;
2760             } B;
2761         } RSER;                 /* DMA/Interrupt Request Select and Enable Register */
2762
2763         union DSPI_PUSHR_tag {
2764             uint32_t R;
2765             struct {
2766                 uint32_t CONT:1;
2767                 uint32_t CTAS:3;
2768                 uint32_t EOQ:1;
2769                 uint32_t CTCNT:1;
2770                   uint32_t:4;
2771                 uint32_t PCS5:1;
2772                 uint32_t PCS4:1;
2773                 uint32_t PCS3:1;
2774                 uint32_t PCS2:1;
2775                 uint32_t PCS1:1;
2776                 uint32_t PCS0:1;
2777                 uint32_t TXDATA:16;
2778             } B;
2779         } PUSHR;                /* PUSH TX FIFO Register */
2780
2781         union DSPI_POPR_tag {
2782             uint32_t R;
2783             struct {
2784                 uint32_t:16;
2785                 uint32_t RXDATA:16;
2786             } B;
2787         } POPR;                 /* POP RX FIFO Register */
2788
2789         union {
2790             uint32_t R;
2791             struct {
2792                 uint32_t TXCMD:16;
2793                 uint32_t TXDATA:16;
2794             } B;
2795         } TXFR[4];              /* Transmit FIFO Registers */
2796
2797         uint32_t DSPI_reserved_txf[12];
2798
2799         union {
2800             uint32_t R;
2801             struct {
2802                 uint32_t:16;
2803                 uint32_t RXDATA:16;
2804             } B;
2805         } RXFR[4];              /* Transmit FIFO Registers */
2806
2807         uint32_t DSPI_reserved_rxf[12];
2808
2809         union {
2810             uint32_t R;
2811             struct {
2812                 uint32_t MTOE:1;
2813                   uint32_t:1;
2814                 uint32_t MTOCNT:6;
2815                   uint32_t:4;
2816                 uint32_t TXSS:1;
2817                 uint32_t TPOL:1;
2818                 uint32_t TRRE:1;
2819                 uint32_t CID:1;
2820                 uint32_t DCONT:1;
2821                 uint32_t DSICTAS:3;
2822                   uint32_t:6;
2823                 uint32_t DPCS5:1;
2824                 uint32_t DPCS4:1;
2825                 uint32_t DPCS3:1;
2826                 uint32_t DPCS2:1;
2827                 uint32_t DPCS1:1;
2828                 uint32_t DPCS0:1;
2829             } B;
2830         } DSICR;                /* DSI Configuration Register */
2831
2832         union {
2833             uint32_t R;
2834             struct {
2835                 uint32_t:16;
2836                 uint32_t SER_DATA:16;
2837             } B;
2838         } SDR;                  /* DSI Serialization Data Register */
2839
2840         union {
2841             uint32_t R;
2842             struct {
2843                 uint32_t:16;
2844                 uint32_t ASER_DATA:16;
2845             } B;
2846         } ASDR;                 /* DSI Alternate Serialization Data Register */
2847
2848         union {
2849             uint32_t R;
2850             struct {
2851                 uint32_t:16;
2852                 uint32_t COMP_DATA:16;
2853             } B;
2854         } COMPR;                /* DSI Transmit Comparison Register */
2855
2856         union {
2857             uint32_t R;
2858             struct {
2859                 uint32_t:16;
2860                 uint32_t DESER_DATA:16;
2861             } B;
2862         } DDR;                  /* DSI deserialization Data Register */
2863
2864     };
2865 /****************************************************************************/
2866 /*                          MODULE : eSCI                                   */
2867 /****************************************************************************/
2868     struct ESCI_tag {
2869         union ESCI_CR1_tag {
2870             uint32_t R;
2871             struct {
2872                 uint32_t:3;
2873                 uint32_t SBR:13;
2874                 uint32_t LOOPS:1;
2875                 uint32_t SCISDOZ:1;
2876                 uint32_t RSRC:1;
2877                 uint32_t M:1;
2878                 uint32_t WAKE:1;
2879                 uint32_t ILT:1;
2880                 uint32_t PE:1;
2881                 uint32_t PT:1;
2882                 uint32_t TIE:1;
2883                 uint32_t TCIE:1;
2884                 uint32_t RIE:1;
2885                 uint32_t ILIE:1;
2886                 uint32_t TE:1;
2887                 uint32_t RE:1;
2888                 uint32_t RWU:1;
2889                 uint32_t SBK:1;
2890             } B;
2891         } CR1;                  /* Control Register 1 */
2892
2893         union ESCI_CR2_tag {
2894             uint16_t R;
2895             struct {
2896                 uint16_t MDIS:1;
2897                 uint16_t FBR:1;
2898                 uint16_t BSTP:1;
2899                 uint16_t IEBERR:1;
2900                 uint16_t RXDMA:1;
2901                 uint16_t TXDMA:1;
2902                 uint16_t BRK13:1;
2903                   uint16_t:1;
2904                 uint16_t BESM13:1;
2905                 uint16_t SBSTP:1;
2906                   uint16_t:2;
2907                 uint16_t ORIE:1;
2908                 uint16_t NFIE:1;
2909                 uint16_t FEIE:1;
2910                 uint16_t PFIE:1;
2911             } B;
2912         } CR2;                  /* Control Register 2 */
2913
2914         union ESCI_DR_tag {
2915             uint16_t R;
2916             struct {
2917                 uint16_t R8:1;
2918                 uint16_t T8:1;
2919                   uint16_t:6;
2920                 uint8_t D;
2921             } B;
2922         } DR;                   /* Data Register */
2923
2924         union ESCI_SR_tag {
2925             uint32_t R;
2926             struct {
2927                 uint32_t TDRE:1;
2928                 uint32_t TC:1;
2929                 uint32_t RDRF:1;
2930                 uint32_t IDLE:1;
2931                 uint32_t OR:1;
2932                 uint32_t NF:1;
2933                 uint32_t FE:1;
2934                 uint32_t PF:1;
2935                   uint32_t:3;
2936                 uint32_t BERR:1;
2937                   uint32_t:3;
2938                 uint32_t RAF:1;
2939                 uint32_t RXRDY:1;
2940                 uint32_t TXRDY:1;
2941                 uint32_t LWAKE:1;
2942                 uint32_t STO:1;
2943                 uint32_t PBERR:1;
2944                 uint32_t CERR:1;
2945                 uint32_t CKERR:1;
2946                 uint32_t FRC:1;
2947                   uint32_t:7;
2948                 uint32_t OVFL:1;
2949             } B;
2950         } SR;                   /* Status Register */
2951
2952         union {
2953             uint32_t R;
2954             struct {
2955                 uint32_t LRES:1;
2956                 uint32_t WU:1;
2957                 uint32_t WUD0:1;
2958                 uint32_t WUD1:1;
2959                 uint32_t LDBG:1;
2960                 uint32_t DSF:1;
2961                 uint32_t PRTY:1;
2962                 uint32_t LIN:1;
2963                 uint32_t RXIE:1;
2964                 uint32_t TXIE:1;
2965                 uint32_t WUIE:1;
2966                 uint32_t STIE:1;
2967                 uint32_t PBIE:1;
2968                 uint32_t CIE:1;
2969                 uint32_t CKIE:1;
2970                 uint32_t FCIE:1;
2971                   uint32_t:7;
2972                 uint32_t OFIE:1;
2973                   uint32_t:8;
2974             } B;
2975         } LCR;                  /* LIN Control Register */
2976
2977         union {
2978             uint32_t R;
2979         } LTR;                  /* LIN Transmit Register */
2980
2981         union {
2982             uint32_t R;
2983         } LRR;                  /* LIN Recieve Register */
2984
2985         union {
2986             uint32_t R;
2987         } LPR;                  /* LIN CRC Polynom Register  */
2988
2989     };
2990 /****************************************************************************/
2991 /*                          MODULE : FlexCAN                                */
2992 /****************************************************************************/
2993     struct FLEXCAN2_tag {
2994         union {
2995             uint32_t R;
2996             struct {
2997                 uint32_t MDIS:1;
2998                 uint32_t FRZ:1;
2999                   uint32_t:1;
3000                 uint32_t HALT:1;
3001                 uint32_t NOTRDY:1;
3002                   uint32_t:1;
3003                 uint32_t SOFTRST:1;
3004                 uint32_t FRZACK:1;
3005                   uint32_t:1;
3006                   uint32_t:1;
3007
3008                   uint32_t:1;
3009
3010                 uint32_t MDISACK:1;
3011                   uint32_t:1;
3012                   uint32_t:1;
3013
3014                   uint32_t:12;
3015
3016                 uint32_t MAXMB:6;
3017             } B;
3018         } MCR;                  /* Module Configuration Register */
3019
3020         union {
3021             uint32_t R;
3022             struct {
3023                 uint32_t PRESDIV:8;
3024                 uint32_t RJW:2;
3025                 uint32_t PSEG1:3;
3026                 uint32_t PSEG2:3;
3027                 uint32_t BOFFMSK:1;
3028                 uint32_t ERRMSK:1;
3029                 uint32_t CLKSRC:1;
3030                 uint32_t LPB:1;
3031
3032                   uint32_t:4;
3033
3034                 uint32_t SMP:1;
3035                 uint32_t BOFFREC:1;
3036                 uint32_t TSYN:1;
3037                 uint32_t LBUF:1;
3038                 uint32_t LOM:1;
3039                 uint32_t PROPSEG:3;
3040             } B;
3041         } CR;                   /* Control Register */
3042
3043         union {
3044             uint32_t R;
3045         } TIMER;                /* Free Running Timer */
3046         int32_t FLEXCAN_reserved00;
3047
3048         union {
3049             uint32_t R;
3050             struct {
3051                 uint32_t:3;
3052                 uint32_t MI:29;
3053             } B;
3054         } RXGMASK;              /* RX Global Mask */
3055
3056         union {
3057             uint32_t R;
3058             struct {
3059                 uint32_t:3;
3060                 uint32_t MI:29;
3061             } B;
3062         } RX14MASK;             /* RX 14 Mask */
3063
3064         union {
3065             uint32_t R;
3066             struct {
3067                 uint32_t:3;
3068                 uint32_t MI:29;
3069             } B;
3070         } RX15MASK;             /* RX 15 Mask */
3071
3072         union {
3073             uint32_t R;
3074             struct {
3075                 uint32_t:16;
3076                 uint32_t RXECNT:8;
3077                 uint32_t TXECNT:8;
3078             } B;
3079         } ECR;                  /* Error Counter Register */
3080
3081         union {
3082             uint32_t R;
3083             struct {
3084                 uint32_t:14;
3085
3086                 uint32_t:2;
3087
3088                 uint32_t BIT1ERR:1;
3089                 uint32_t BIT0ERR:1;
3090                 uint32_t ACKERR:1;
3091                 uint32_t CRCERR:1;
3092                 uint32_t FRMERR:1;
3093                 uint32_t STFERR:1;
3094                 uint32_t TXWRN:1;
3095                 uint32_t RXWRN:1;
3096                 uint32_t IDLE:1;
3097                 uint32_t TXRX:1;
3098                 uint32_t FLTCONF:2;
3099                   uint32_t:1;
3100                 uint32_t BOFFINT:1;
3101                 uint32_t ERRINT:1;
3102                   uint32_t:1;
3103             } B;
3104         } ESR;                  /* Error and Status Register */
3105
3106         union {
3107             uint32_t R;
3108             struct {
3109                 uint32_t BUF63M:1;
3110                 uint32_t BUF62M:1;
3111                 uint32_t BUF61M:1;
3112                 uint32_t BUF60M:1;
3113                 uint32_t BUF59M:1;
3114                 uint32_t BUF58M:1;
3115                 uint32_t BUF57M:1;
3116                 uint32_t BUF56M:1;
3117                 uint32_t BUF55M:1;
3118                 uint32_t BUF54M:1;
3119                 uint32_t BUF53M:1;
3120                 uint32_t BUF52M:1;
3121                 uint32_t BUF51M:1;
3122                 uint32_t BUF50M:1;
3123                 uint32_t BUF49M:1;
3124                 uint32_t BUF48M:1;
3125                 uint32_t BUF47M:1;
3126                 uint32_t BUF46M:1;
3127                 uint32_t BUF45M:1;
3128                 uint32_t BUF44M:1;
3129                 uint32_t BUF43M:1;
3130                 uint32_t BUF42M:1;
3131                 uint32_t BUF41M:1;
3132                 uint32_t BUF40M:1;
3133                 uint32_t BUF39M:1;
3134                 uint32_t BUF38M:1;
3135                 uint32_t BUF37M:1;
3136                 uint32_t BUF36M:1;
3137                 uint32_t BUF35M:1;
3138                 uint32_t BUF34M:1;
3139                 uint32_t BUF33M:1;
3140                 uint32_t BUF32M:1;
3141             } B;
3142         } IMRH;                 /* Interruput Masks Register */
3143
3144         union {
3145             uint32_t R;
3146             struct {
3147                 uint32_t BUF31M:1;
3148                 uint32_t BUF30M:1;
3149                 uint32_t BUF29M:1;
3150                 uint32_t BUF28M:1;
3151                 uint32_t BUF27M:1;
3152                 uint32_t BUF26M:1;
3153                 uint32_t BUF25M:1;
3154                 uint32_t BUF24M:1;
3155                 uint32_t BUF23M:1;
3156                 uint32_t BUF22M:1;
3157                 uint32_t BUF21M:1;
3158                 uint32_t BUF20M:1;
3159                 uint32_t BUF19M:1;
3160                 uint32_t BUF18M:1;
3161                 uint32_t BUF17M:1;
3162                 uint32_t BUF16M:1;
3163                 uint32_t BUF15M:1;
3164                 uint32_t BUF14M:1;
3165                 uint32_t BUF13M:1;
3166                 uint32_t BUF12M:1;
3167                 uint32_t BUF11M:1;
3168                 uint32_t BUF10M:1;
3169                 uint32_t BUF09M:1;
3170                 uint32_t BUF08M:1;
3171                 uint32_t BUF07M:1;
3172                 uint32_t BUF06M:1;
3173                 uint32_t BUF05M:1;
3174                 uint32_t BUF04M:1;
3175                 uint32_t BUF03M:1;
3176                 uint32_t BUF02M:1;
3177                 uint32_t BUF01M:1;
3178                 uint32_t BUF00M:1;
3179             } B;
3180         } IMRL;                 /* Interruput Masks Register */
3181
3182         union {
3183             uint32_t R;
3184             struct {
3185                 uint32_t BUF63I:1;
3186                 uint32_t BUF62I:1;
3187                 uint32_t BUF61I:1;
3188                 uint32_t BUF60I:1;
3189                 uint32_t BUF59I:1;
3190                 uint32_t BUF58I:1;
3191                 uint32_t BUF57I:1;
3192                 uint32_t BUF56I:1;
3193                 uint32_t BUF55I:1;
3194                 uint32_t BUF54I:1;
3195                 uint32_t BUF53I:1;
3196                 uint32_t BUF52I:1;
3197                 uint32_t BUF51I:1;
3198                 uint32_t BUF50I:1;
3199                 uint32_t BUF49I:1;
3200                 uint32_t BUF48I:1;
3201                 uint32_t BUF47I:1;
3202                 uint32_t BUF46I:1;
3203                 uint32_t BUF45I:1;
3204                 uint32_t BUF44I:1;
3205                 uint32_t BUF43I:1;
3206                 uint32_t BUF42I:1;
3207                 uint32_t BUF41I:1;
3208                 uint32_t BUF40I:1;
3209                 uint32_t BUF39I:1;
3210                 uint32_t BUF38I:1;
3211                 uint32_t BUF37I:1;
3212                 uint32_t BUF36I:1;
3213                 uint32_t BUF35I:1;
3214                 uint32_t BUF34I:1;
3215                 uint32_t BUF33I:1;
3216                 uint32_t BUF32I:1;
3217             } B;
3218         } IFRH;                 /* Interruput Flag Register */
3219
3220         union {
3221             uint32_t R;
3222             struct {
3223                 uint32_t BUF31I:1;
3224                 uint32_t BUF30I:1;
3225                 uint32_t BUF29I:1;
3226                 uint32_t BUF28I:1;
3227                 uint32_t BUF27I:1;
3228                 uint32_t BUF26I:1;
3229                 uint32_t BUF25I:1;
3230                 uint32_t BUF24I:1;
3231                 uint32_t BUF23I:1;
3232                 uint32_t BUF22I:1;
3233                 uint32_t BUF21I:1;
3234                 uint32_t BUF20I:1;
3235                 uint32_t BUF19I:1;
3236                 uint32_t BUF18I:1;
3237                 uint32_t BUF17I:1;
3238                 uint32_t BUF16I:1;
3239                 uint32_t BUF15I:1;
3240                 uint32_t BUF14I:1;
3241                 uint32_t BUF13I:1;
3242                 uint32_t BUF12I:1;
3243                 uint32_t BUF11I:1;
3244                 uint32_t BUF10I:1;
3245                 uint32_t BUF09I:1;
3246                 uint32_t BUF08I:1;
3247                 uint32_t BUF07I:1;
3248                 uint32_t BUF06I:1;
3249                 uint32_t BUF05I:1;
3250                 uint32_t BUF04I:1;
3251                 uint32_t BUF03I:1;
3252                 uint32_t BUF02I:1;
3253                 uint32_t BUF01I:1;
3254                 uint32_t BUF00I:1;
3255             } B;
3256         } IFRL;                 /* Interruput Flag Register */
3257
3258         uint32_t flexcan2_reserved2[19];
3259
3260         struct canbuf_t {
3261             union {
3262                 uint32_t R;
3263                 struct {
3264                     uint32_t:4;
3265                     uint32_t CODE:4;
3266                       uint32_t:1;
3267                     uint32_t SRR:1;
3268                     uint32_t IDE:1;
3269                     uint32_t RTR:1;
3270                     uint32_t LENGTH:4;
3271                     uint32_t TIMESTAMP:16;
3272                 } B;
3273             } CS;
3274
3275             union {
3276                 uint32_t R;
3277                 struct {
3278                     uint32_t:3;
3279                     uint32_t STD_ID:11;
3280                     uint32_t EXT_ID:18;
3281                 } B;
3282             } ID;
3283
3284             union {
3285                 uint8_t B[8];  /* Data buffer in Bytes (8 bits) */
3286                 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
3287                 uint32_t W[2]; /* Data buffer in words (32 bits) */
3288                 uint32_t R[2]; /* Data buffer in words (32 bits) */
3289             } DATA;
3290
3291         } BUF[64];
3292     };
3293
3294 /* Define memories */
3295
3296 #define SRAM_START  0x40000000
3297 #define SRAM_SIZE      0x10000
3298 #define SRAM_END    0x4000FFFF
3299
3300 #define FLASH_START         0x0
3301 #define FLASH_SIZE     0x200000
3302 #define FLASH_END      0x1FFFFF
3303
3304 /* Define instances of modules */
3305 #define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000)
3306 #define FMPLL     (*(volatile struct FMPLL_tag *)     0xC3F80000)
3307 #define EBI       (*(volatile struct EBI_tag *)       0xC3F84000)
3308 #define FLASH     (*(volatile struct FLASH_tag *)     0xC3F88000)
3309 #define SIU       (*(volatile struct SIU_tag *)       0xC3F90000)
3310
3311 #define EMIOS     (*(volatile struct EMIOS_tag *)     0xC3FA0000)
3312 #define ETPU      (*(volatile struct ETPU_tag *)      0xC3FC0000)
3313 #define ETPU_DATA_RAM  (*( uint32_t *)        0xC3FC8000)
3314 #define ETPU_DATA_RAM_EXT  (*( uint32_t *)    0xC3FCC000)
3315 #define ETPU_DATA_RAM_END  0xC3FC8BFC
3316 #define CODE_RAM       (*( uint32_t *)        0xC3FD0000)
3317 #define ETPU_CODE_RAM  (*( uint32_t *)        0xC3FD0000)
3318
3319 #define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000)
3320 #define XBAR      (*(volatile struct XBAR_tag *)      0xFFF04000)
3321 #define ECSM      (*(volatile struct ECSM_tag *)      0xFFF40000)
3322 #define EDMA      (*(volatile struct EDMA_tag *)      0xFFF44000)
3323 #define INTC      (*(volatile struct INTC_tag *)      0xFFF48000)
3324
3325 #define EQADC     (*(volatile struct EQADC_tag *)     0xFFF80000)
3326
3327 #define DSPI_A    (*(volatile struct DSPI_tag *)      0xFFF90000)
3328 #define DSPI_B    (*(volatile struct DSPI_tag *)      0xFFF94000)
3329 #define DSPI_C    (*(volatile struct DSPI_tag *)      0xFFF98000)
3330 #define DSPI_D    (*(volatile struct DSPI_tag *)      0xFFF9C000)
3331
3332 #define ESCI_A    (*(volatile struct ESCI_tag *)      0xFFFB0000)
3333 #define ESCI_B    (*(volatile struct ESCI_tag *)      0xFFFB4000)
3334
3335 #define CAN_A     (*(volatile struct FLEXCAN2_tag *)  0xFFFC0000)
3336 #define CAN_B     (*(volatile struct FLEXCAN2_tag *)  0xFFFC4000)
3337 #define CAN_C     (*(volatile struct FLEXCAN2_tag *)  0xFFFC8000)
3338
3339 #ifdef __MWERKS__
3340 #pragma pop
3341 #endif
3342
3343 #ifdef  __cplusplus
3344 }
3345 #endif
3346 #endif /* ASM */
3347 #endif                          /* ifdef _MPC5554_H */
3348 /*********************************************************************
3349  *
3350  * Copyright:
3351  *  Freescale Semiconductor, INC. All Rights Reserved.
3352  *  You are hereby granted a copyright license to use, modify, and
3353  *  distribute the SOFTWARE so long as this entire notice is
3354  *  retained without alteration in any modified and/or redistributed
3355  *  versions, and that such modified versions are clearly identified
3356  *  as such. No licenses are granted by implication, estoppel or
3357  *  otherwise under any patents or trademarks of Freescale
3358  *  Semiconductor, Inc. This software is provided on an "AS IS"
3359  *  basis and without warranty.
3360  *
3361  *  To the maximum extent permitted by applicable law, Freescale
3362  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
3363  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
3364  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
3365  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
3366  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
3367  *
3368  *  To the maximum extent permitted by applicable law, IN NO EVENT
3369  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
3370  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
3371  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
3372  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
3373  *
3374  *  Freescale Semiconductor assumes no responsibility for the
3375  *  maintenance and support of this software
3376  *
3377  ********************************************************************/