include/mpc55xx/fsl-mpc551x.h

0001 /*
0002  * Modifications of the original file provided by Freescale are:
0003  *
0004  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0016  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0017  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0018  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0019  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0020  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0021  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0022  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0023  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0024  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0025  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 /**************************************************************************/
0029 /* FILE NAME: mpc5510.h                      COPYRIGHT (c) Freescale 2008 */
0030 /* REVISION:  2.2                                  All Rights Reserved    */
0031 /*                                                                        */
0032 /* DESCRIPTION:                                                           */
0033 /* This file contain all of the register and bit field definitions for    */
0034 /* MPC5510.                                                               */
0035 /**************************************************************************/
0036 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
0037
0038 /*************************************************/
0039 /* Example register & bit field write:           */
0040 /*                                               */
0041 /*  <MODULE>.<REGISTER>.B.<BIT> = 1;             */
0042 /*  <MODULE>.<REGISTER>.R       = 0x10000000;    */
0043 /*                                               */
0044 /*************************************************/
0045
0046 #ifndef _MPC5510_H_
0047 #define _MPC5510_H_
0048
0049 #ifndef ASM
0050
0051 #include <stdint.h>
0052
0053 #include <mpc55xx/regs-edma.h>
0054
0055 #ifdef  __cplusplus
0056 extern "C" {
0057 #endif
0058
0059 #ifdef __MWERKS__
0060 #pragma push
0061 #pragma ANSI_strict off
0062 #endif
0063
0064 /****************************************************************************/
0065 /*                     MODULE : CRP                                         */
0066 /****************************************************************************/
0067     struct CRP_tag {
0068
0069         union {
0070             uint32_t R;
0071             struct {
0072                 uint32_t:12;
0073                 uint32_t IRC32KEN:1;
0074                 uint32_t XOSCEN:1;
0075                   uint32_t:1;
0076                 uint32_t OSC32KEN:1;
0077                 uint32_t TRIM32IRC:8;
0078                 uint32_t TRIMIRC:8;
0079             } B;
0080         } CLKSRC;               /* Clock Source Register */
0081
0082         uint32_t crp_reserved1[3];
0083
0084         union {
0085             uint32_t R;
0086             struct {
0087                 uint32_t CNTEN:1;
0088                 uint32_t RTCIE:1;
0089                 uint32_t RTCF:1;
0090                 uint32_t ROVRF:1;
0091                 uint32_t RTCVAL:12;
0092                 uint32_t APIEN:1;
0093                 uint32_t APIIE:1;
0094                 uint32_t APIF:1;
0095                 uint32_t CLKSEL:2;
0096                 uint32_t ROVREN:1;
0097                 uint32_t APIVAL:10;
0098             } B;
0099         } RTCSC;                /* RTC Status and Control Register */
0100
0101         union {
0102             uint32_t R;
0103             struct {
0104                 uint32_t RTCCNT:32;
0105             } B;
0106         } RTCCNT;               /* RTC Counter Register */
0107
0108         uint32_t crp_reserved2[10];
0109
0110         union {
0111             uint32_t R;
0112             struct {
0113                 uint32_t:1;
0114                 uint32_t WKPSEL7:3;
0115                   uint32_t:1;
0116                 uint32_t WKPSEL6:3;
0117                   uint32_t:1;
0118                 uint32_t WKPSEL5:3;
0119                   uint32_t:1;
0120                 uint32_t WKPSEL4:3;
0121                   uint32_t:1;
0122                 uint32_t WKPSEL3:3;
0123                   uint32_t:1;
0124                 uint32_t WKPSEL2:3;
0125                   uint32_t:1;
0126                 uint32_t WKPSEL1:3;
0127                   uint32_t:1;
0128                 uint32_t WKPSEL0:3;
0129             } B;
0130         } WKPINSEL;             /* Wakeup Pin Source Select Register */
0131
0132         union {
0133             uint32_t R;
0134             struct {
0135                 uint32_t WKPDET7:2;
0136                 uint32_t WKPDET6:2;
0137                 uint32_t WKPDET5:2;
0138                 uint32_t WKPDET4:2;
0139                 uint32_t WKPDET3:2;
0140                 uint32_t WKPDET2:2;
0141                 uint32_t WKPDET1:2;
0142                 uint32_t WKPDET0:2;
0143                   uint32_t:5;
0144                 uint32_t RTCOVREN:1;
0145                 uint32_t RTCWKEN:1;
0146                 uint32_t APIWKEN:1;
0147                   uint32_t:7;
0148                 uint32_t WKCLKSEL:1;
0149             } B;
0150         } WKSE;                 /* Wakeup Source Enable Register */
0151
0152         uint32_t crp_reserved3[2];
0153
0154         union {
0155             uint32_t R;
0156             struct {
0157                 uint32_t Z1VEC:30;
0158                 uint32_t Z1RST:1;
0159                 uint32_t VLE:1;
0160             } B;
0161         } Z1VEC;                /* Z1 Reset Vector Register */
0162
0163         union {
0164             uint32_t R;
0165             struct {
0166                 uint32_t Z0VEC:30;
0167                 uint32_t Z0RST:1;
0168                   uint32_t:1;
0169             } B;
0170         } Z0VEC;                /* Z0 Reset Vector Register */
0171
0172         union {
0173             uint32_t R;
0174             struct {
0175                 uint32_t RECPTR:30;
0176                 uint32_t FASTREC:1;
0177                   uint32_t:1;
0178             } B;
0179         } RECPTR;               /* Reset Recovery Pointer Register */
0180
0181         uint32_t crp_reserved4;
0182
0183         union {
0184             uint32_t R;
0185             struct {
0186                 uint32_t SLEEPF:1;
0187                 uint32_t STOPF:1;
0188                   uint32_t:3;
0189                 uint32_t WKRLLOVRF:1;
0190                 uint32_t WKAPIF:1;
0191                 uint32_t WKRTCF:1;
0192                 uint32_t PWKSCRF:8;
0193                 uint32_t SLEEP:1;
0194                 uint32_t STOP:1;
0195                   uint32_t:1;
0196                 uint32_t PKREL:1;
0197                 uint32_t SLP12EN:1;
0198                 uint32_t RAMSEL:3;
0199                 uint32_t PWKSRIE:8;
0200             } B;
0201         } PSCR;                 /* Power Status and Control Register */
0202
0203         uint32_t crp_reserved5[3];
0204
0205         union {
0206             uint32_t R;
0207             struct {
0208                 uint32_t LVI5IE:1;
0209                 uint32_t LVI5HIE:1;
0210                 uint32_t LVI5F:1;
0211                 uint32_t LVI5HF:1;
0212                 uint32_t LVI5LOCK:1;
0213                 uint32_t LVI5RE:1;
0214                   uint32_t:9;
0215                 uint32_t BYPDIS:1;
0216                   uint32_t:16;
0217             } B;
0218         } SOCSC;                /* LVI Status and Control Register */
0219
0220     };
0221 /****************************************************************************/
0222 /*                          MODULE : DMAMUX                                 */
0223 /****************************************************************************/
0224     struct DMAMUX_tag {
0225         union {
0226             uint8_t R;
0227             struct {
0228                 uint8_t ENBL:1;
0229                 uint8_t TRIG:1;
0230                 uint8_t SOURCE:6;
0231             } B;
0232         } CHCONFIG[16];         /* DMA Channel Configuration Register */
0233
0234     };
0235 /****************************************************************************/
0236 /*                          MODULE : DSPI                                   */
0237 /****************************************************************************/
0238     struct DSPI_tag {
0239         union DSPI_MCR_tag {
0240             uint32_t R;
0241             struct {
0242                 uint32_t MSTR:1;
0243                 uint32_t CONT_SCKE:1;
0244                 uint32_t DCONF:2;
0245                 uint32_t FRZ:1;
0246                 uint32_t MTFE:1;
0247                 uint32_t PCSSE:1;
0248                 uint32_t ROOE:1;
0249                   uint32_t:2;
0250                 uint32_t PCSIS5:1;
0251                 uint32_t PCSIS4:1;
0252                 uint32_t PCSIS3:1;
0253                 uint32_t PCSIS2:1;
0254                 uint32_t PCSIS1:1;
0255                 uint32_t PCSIS0:1;
0256                   uint32_t:1;
0257                 uint32_t MDIS:1;
0258                 uint32_t DIS_TXF:1;
0259                 uint32_t DIS_RXF:1;
0260                 uint32_t CLR_TXF:1;
0261                 uint32_t CLR_RXF:1;
0262                 uint32_t SMPL_PT:2;
0263                   uint32_t:7;
0264                 uint32_t HALT:1;
0265             } B;
0266         } MCR;                  /* Module Configuration Register */
0267
0268         uint32_t dspi_reserved1;
0269
0270         union {
0271             uint32_t R;
0272             struct {
0273                 uint32_t SPI_TCNT:16;
0274                   uint32_t:16;
0275             } B;
0276         } TCR;
0277
0278         union DSPI_CTAR_tag {
0279             uint32_t R;
0280             struct {
0281                 uint32_t DBR:1;
0282                 uint32_t FMSZ:4;
0283                 uint32_t CPOL:1;
0284                 uint32_t CPHA:1;
0285                 uint32_t LSBFE:1;
0286                 uint32_t PCSSCK:2;
0287                 uint32_t PASC:2;
0288                 uint32_t PDT:2;
0289                 uint32_t PBR:2;
0290                 uint32_t CSSCK:4;
0291                 uint32_t ASC:4;
0292                 uint32_t DT:4;
0293                 uint32_t BR:4;
0294             } B;
0295         } CTAR[8];              /* Clock and Transfer Attributes Registers */
0296
0297         union DSPI_SR_tag {
0298             uint32_t R;
0299             struct {
0300                 uint32_t TCF:1;
0301                 uint32_t TXRXS:1;
0302                   uint32_t:1;
0303                 uint32_t EOQF:1;
0304                 uint32_t TFUF:1;
0305                   uint32_t:1;
0306                 uint32_t TFFF:1;
0307                   uint32_t:5;
0308                 uint32_t RFOF:1;
0309                   uint32_t:1;
0310                 uint32_t RFDF:1;
0311                   uint32_t:1;
0312                 uint32_t TXCTR:4;
0313                 uint32_t TXNXTPTR:4;
0314                 uint32_t RXCTR:4;
0315                 uint32_t POPNXTPTR:4;
0316             } B;
0317         } SR;                   /* Status Register */
0318
0319         union DSPI_RSER_tag {
0320             uint32_t R;
0321             struct {
0322                 uint32_t TCF_RE:1;
0323                   uint32_t:2;
0324                 uint32_t EOQFRE:1;
0325                 uint32_t TFUFRE:1;
0326                   uint32_t:1;
0327                 uint32_t TFFFRE:1;
0328                 uint32_t TFFFDIRS:1;
0329                   uint32_t:4;
0330                 uint32_t RFOFRE:1;
0331                   uint32_t:1;
0332                 uint32_t RFDFRE:1;
0333                 uint32_t RFDFDIRS:1;
0334                   uint32_t:16;
0335             } B;
0336         } RSER;                 /* DMA/Interrupt Request Select and Enable Register */
0337
0338         union DSPI_PUSHR_tag {
0339             uint32_t R;
0340             struct {
0341                 uint32_t CONT:1;
0342                 uint32_t CTAS:3;
0343                 uint32_t EOQ:1;
0344                 uint32_t CTCNT:1;
0345                   uint32_t:4;
0346                 uint32_t PCS5:1;
0347                 uint32_t PCS4:1;
0348                 uint32_t PCS3:1;
0349                 uint32_t PCS2:1;
0350                 uint32_t PCS1:1;
0351                 uint32_t PCS0:1;
0352                 uint32_t TXDATA:16;
0353             } B;
0354         } PUSHR;                /* PUSH TX FIFO Register */
0355
0356         union DSPI_POPR_tag {
0357             uint32_t R;
0358             struct {
0359                 uint32_t:16;
0360                 uint32_t RXDATA:16;
0361             } B;
0362         } POPR;                 /* POP RX FIFO Register */
0363
0364         union {
0365             uint32_t R;
0366             struct {
0367                 uint32_t TXCMD:16;
0368                 uint32_t TXDATA:16;
0369             } B;
0370         } TXFR[4];              /* Transmit FIFO Registers */
0371
0372         uint32_t DSPI_reserved_txf[12];
0373
0374         union {
0375             uint32_t R;
0376             struct {
0377                 uint32_t:16;
0378                 uint32_t RXDATA:16;
0379             } B;
0380         } RXFR[4];              /* Transmit FIFO Registers */
0381
0382         uint32_t DSPI_reserved_rxf[12];
0383
0384         union {
0385             uint32_t R;
0386             struct {
0387                 uint32_t:12;
0388                 uint32_t TXSS:1;
0389                   uint32_t:2;
0390                 uint32_t CID:1;
0391                 uint32_t DCONT:1;
0392                 uint32_t DSICTAS:3;
0393                   uint32_t:6;
0394                 uint32_t DPCS5:1;
0395                 uint32_t DPCS4:1;
0396                 uint32_t DPCS3:1;
0397                 uint32_t DPCS2:1;
0398                 uint32_t DPCS1:1;
0399                 uint32_t DPCS0:1;
0400             } B;
0401         } DSICR;                /* DSI Configuration Register */
0402
0403         union {
0404             uint32_t R;
0405             struct {
0406                 uint32_t:16;
0407                 uint32_t SER_DATA:16;
0408             } B;
0409         } SDR;                  /* DSI Serialization Data Register */
0410
0411         union {
0412             uint32_t R;
0413             struct {
0414                 uint32_t:16;
0415                 uint32_t ASER_DATA:16;
0416             } B;
0417         } ASDR;                 /* DSI Alternate Serialization Data Register */
0418
0419         union {
0420             uint32_t R;
0421             struct {
0422                 uint32_t:16;
0423                 uint32_t COMP_DATA:16;
0424             } B;
0425         } COMPR;                /* DSI Transmit Comparison Register */
0426
0427         union {
0428             uint32_t R;
0429             struct {
0430                 uint32_t:16;
0431                 uint32_t DESER_DATA:16;
0432             } B;
0433         } DDR;                  /* DSI deserialization Data Register */
0434
0435     };
0436 /****************************************************************************/
0437 /*                     MODULE : External Bus Interface (EBI)                */
0438 /****************************************************************************/
0439
0440 /* CS_tag instantiated within EBI_tag */
0441     struct EBI_CS_tag {
0442         union {                 /* Base Register Bank */
0443             uint32_t R;
0444             struct {
0445                 uint32_t BA:17;
0446                   uint32_t:3;
0447                 uint32_t PS:1;
0448                   uint32_t:3;
0449                 uint32_t AD_MUX:1;
0450                 uint32_t BL:1;
0451                 uint32_t WEBS:1;
0452                 uint32_t TBDIP:1;
0453                   uint32_t:1;
0454                 uint32_t SETA:1;
0455                 uint32_t BI:1;
0456                 uint32_t V:1;
0457             } B;
0458         } BR;
0459
0460         union {                 /* Option Register Bank */
0461             uint32_t R;
0462             struct {
0463                 uint32_t AM:17;
0464                   uint32_t:7;
0465                 uint32_t SCY:4;
0466                   uint32_t:1;
0467                 uint32_t BSCY:2;
0468                   uint32_t:1;
0469             } B;
0470         } OR;
0471     };
0472
0473     struct EBI_CAL_CS_tag {
0474         uint32_t ebi_cal_cs_reserved [2];
0475     };
0476
0477     struct EBI_tag {
0478         union EBI_MCR_tag {     /* Module Configuration Register */
0479             uint32_t R;
0480             struct {
0481                 uint32_t:16;
0482                 uint32_t ACGE:1;
0483                 uint32_t EXTM:1;
0484                 uint32_t EARB:1;
0485                   uint32_t:6;
0486                 uint32_t MDIS:1;
0487                   uint32_t:3;
0488                 uint32_t D16_31:1;
0489                 uint32_t AD_MUX:1;
0490                 uint32_t DBM:1;
0491             } B;
0492         } MCR;
0493
0494         uint32_t EBI_reserved1;
0495
0496         union {                 /* Transfer Error Status Register */
0497             uint32_t R;
0498             struct {
0499                 uint32_t:30;
0500                 uint32_t TEAF:1;
0501                 uint32_t BMTF:1;
0502             } B;
0503         } TESR;
0504
0505         union {                 /* Bus Monitor Control Register */
0506             uint32_t R;
0507             struct {
0508                 uint32_t:16;
0509                 uint32_t BMT:8;
0510                 uint32_t BME:1;
0511                   uint32_t:7;
0512             } B;
0513         } BMCR;
0514
0515         /* Roll in 3x CS registers */
0516         struct EBI_CS_tag CS[4];
0517
0518         uint32_t EBI_reserved2[4];
0519
0520         struct EBI_CAL_CS_tag CAL_CS[4];
0521     };
0522 /****************************************************************************/
0523 /*                          MODULE : EMIOS                                  */
0524 /****************************************************************************/
0525     struct EMIOS_tag {
0526         union EMIOS_MCR_tag {
0527             uint32_t R;
0528             struct {
0529                 uint32_t:1;
0530                 uint32_t MDIS:1;
0531                 uint32_t FRZ:1;
0532                 uint32_t GTBE:1;
0533                   uint32_t:1;
0534                 uint32_t GPREN:1;
0535                   uint32_t:10;
0536                 uint32_t GPRE:8;
0537                   uint32_t:8;
0538             } B;
0539         } MCR;                  /* Module Configuration Register */
0540
0541         union {
0542             uint32_t R;
0543             struct {
0544                 uint32_t:8;
0545                 uint32_t F23:1;
0546                 uint32_t F22:1;
0547                 uint32_t F21:1;
0548                 uint32_t F20:1;
0549                 uint32_t F19:1;
0550                 uint32_t F18:1;
0551                 uint32_t F17:1;
0552                 uint32_t F16:1;
0553                 uint32_t F15:1;
0554                 uint32_t F14:1;
0555                 uint32_t F13:1;
0556                 uint32_t F12:1;
0557                 uint32_t F11:1;
0558                 uint32_t F10:1;
0559                 uint32_t F9:1;
0560                 uint32_t F8:1;
0561                 uint32_t F7:1;
0562                 uint32_t F6:1;
0563                 uint32_t F5:1;
0564                 uint32_t F4:1;
0565                 uint32_t F3:1;
0566                 uint32_t F2:1;
0567                 uint32_t F1:1;
0568                 uint32_t F0:1;
0569             } B;
0570         } GFG;                  /* Global FLAG Register */
0571
0572         union {
0573             uint32_t R;
0574             struct {
0575                 uint32_t:8;
0576                 uint32_t OU23:1;
0577                 uint32_t OU22:1;
0578                 uint32_t OU21:1;
0579                 uint32_t OU20:1;
0580                 uint32_t OU19:1;
0581                 uint32_t OU18:1;
0582                 uint32_t OU17:1;
0583                 uint32_t OU16:1;
0584                 uint32_t OU15:1;
0585                 uint32_t OU14:1;
0586                 uint32_t OU13:1;
0587                 uint32_t OU12:1;
0588                 uint32_t OU11:1;
0589                 uint32_t OU10:1;
0590                 uint32_t OU9:1;
0591                 uint32_t OU8:1;
0592                 uint32_t OU7:1;
0593                 uint32_t OU6:1;
0594                 uint32_t OU5:1;
0595                 uint32_t OU4:1;
0596                 uint32_t OU3:1;
0597                 uint32_t OU2:1;
0598                 uint32_t OU1:1;
0599                 uint32_t OU0:1;
0600             } B;
0601         } OUDR;                 /* Output Update Disable Register */
0602
0603         union {
0604             uint32_t R;
0605             struct {
0606                 uint32_t:8;
0607                 uint32_t UC23:1;
0608                 uint32_t UC22:1;
0609                 uint32_t UC21:1;
0610                 uint32_t UC20:1;
0611                 uint32_t UC19:1;
0612                 uint32_t UC18:1;
0613                 uint32_t UC17:1;
0614                 uint32_t UC16:1;
0615                 uint32_t UC15:1;
0616                 uint32_t UC14:1;
0617                 uint32_t UC13:1;
0618                 uint32_t UC12:1;
0619                 uint32_t UC11:1;
0620                 uint32_t UC10:1;
0621                 uint32_t UC9:1;
0622                 uint32_t UC8:1;
0623                 uint32_t UC7:1;
0624                 uint32_t UC6:1;
0625                 uint32_t UC5:1;
0626                 uint32_t UC4:1;
0627                 uint32_t UC3:1;
0628                 uint32_t UC2:1;
0629                 uint32_t UC1:1;
0630                 uint32_t UC0:1;
0631             } B;
0632         } UCDIS;                /* Disable Channel Register */
0633
0634         uint32_t emios_reserved1[4];
0635
0636         struct EMIOS_CH_tag {
0637             union {
0638                 uint32_t R;
0639                 struct {
0640                     uint32_t:16;
0641                     uint32_t A:16;     /* Channel A Data Register */
0642                 } B;
0643             } CADR;
0644
0645             union {
0646                 uint32_t R;
0647                 struct {
0648                     uint32_t:16;
0649                     uint32_t B:16;     /* Channel B Data Register */
0650                 } B;
0651             } CBDR;
0652
0653             union {
0654                 uint32_t R;    /* Channel Counter Register */
0655                 struct {
0656                     uint32_t:16;
0657                     uint32_t C:16;     /* Channel C Data Register */
0658                 } B;
0659             } CCNTR;
0660
0661             union EMIOS_CCR_tag {
0662                 uint32_t R;
0663                 struct {
0664                     uint32_t FREN:1;
0665                     uint32_t ODIS:1;
0666                     uint32_t ODISSL:2;
0667                     uint32_t UCPRE:2;
0668                     uint32_t UCPREN:1;
0669                     uint32_t DMA:1;
0670                       uint32_t:1;
0671                     uint32_t IF:4;
0672                     uint32_t FCK:1;
0673                     uint32_t FEN:1;
0674                       uint32_t:3;
0675                     uint32_t FORCMA:1;
0676                     uint32_t FORCMB:1;
0677                       uint32_t:1;
0678                     uint32_t BSL:2;
0679                     uint32_t EDSEL:1;
0680                     uint32_t EDPOL:1;
0681                     uint32_t MODE:7;
0682                 } B;
0683             } CCR;              /* Channel Control Register */
0684
0685             union EMIOS_CSR_tag {
0686                 uint32_t R;
0687                 struct {
0688                     uint32_t OVR:1;
0689                       uint32_t:15;
0690                     uint32_t OVFL:1;
0691                       uint32_t:12;
0692                     uint32_t UCIN:1;
0693                     uint32_t UCOUT:1;
0694                     uint32_t FLAG:1;
0695                 } B;
0696             } CSR;              /* Channel Status Register */
0697
0698             union {
0699                 uint32_t R;    /* Alternate Channel A Data Register */
0700             } ALTA;
0701
0702             uint32_t emios_channel_reserved[2];
0703
0704         } CH[24];
0705
0706     };
0707 /****************************************************************************/
0708 /*                          MODULE : EQADC                                  */
0709 /****************************************************************************/
0710     struct EQADC_tag {
0711         union {
0712             uint32_t R;
0713             struct {
0714                 uint32_t:30;
0715                 uint32_t DBG:2;
0716             } B;
0717         } MCR;                  /* Module Configuration Register */
0718
0719         uint32_t eqadc_reserved0;
0720
0721         union {
0722             uint32_t R;
0723             struct {
0724                 uint32_t:6;
0725                 uint32_t NMF:26;
0726             } B;
0727         } NMSFR;                /* Null Message Send Format Register */
0728
0729         union {
0730             uint32_t R;
0731             struct {
0732                 uint32_t:28;
0733                 uint32_t DFL:4;
0734             } B;
0735         } ETDFR;                /* External Trigger Digital Filter Register */
0736
0737         union {
0738             uint32_t R;
0739             struct {
0740                 uint32_t CF_PUSH:32;
0741             } B;
0742         } CFPR[6];              /* CFIFO Push Registers */
0743
0744         uint32_t eqadc_reserved1;
0745
0746         uint32_t eqadc_reserved2;
0747
0748         union {
0749             uint32_t R;
0750             struct {
0751                 uint32_t:16;
0752                 uint32_t RF_POP:16;
0753             } B;
0754         } RFPR[6];              /* Result FIFO Pop Registers */
0755
0756         uint32_t eqadc_reserved3;
0757
0758         uint32_t eqadc_reserved4;
0759
0760         union {
0761             uint16_t R;
0762             struct {
0763                 uint16_t:5;
0764                 uint16_t SSE:1;
0765                 uint16_t CFINV:1;
0766                   uint16_t:1;
0767                 uint16_t MODE:4;
0768                   uint16_t:4;
0769             } B;
0770         } CFCR[6];              /* CFIFO Control Registers */
0771
0772         uint32_t eqadc_reserved5;
0773
0774         union {
0775             uint16_t R;
0776             struct {
0777                 uint16_t NCIE:1;
0778                 uint16_t TORIE:1;
0779                 uint16_t PIE:1;
0780                 uint16_t EOQIE:1;
0781                 uint16_t CFUIE:1;
0782                   uint16_t:1;
0783                 uint16_t CFFE:1;
0784                 uint16_t CFFS:1;
0785                   uint16_t:4;
0786                 uint16_t RFOIE:1;
0787                   uint16_t:1;
0788                 uint16_t RFDE:1;
0789                 uint16_t RFDS:1;
0790             } B;
0791         } IDCR[6];              /* Interrupt and DMA Control Registers */
0792
0793         uint32_t eqadc_reserved6;
0794
0795         union {
0796             uint32_t R;
0797             struct {
0798                 uint32_t NCF:1;
0799                 uint32_t TORF:1;
0800                 uint32_t PF:1;
0801                 uint32_t EOQF:1;
0802                 uint32_t CFUF:1;
0803                 uint32_t SSS:1;
0804                 uint32_t CFFF:1;
0805                   uint32_t:5;
0806                 uint32_t RFOF:1;
0807                   uint32_t:1;
0808                 uint32_t RFDF:1;
0809                   uint32_t:1;
0810                 uint32_t CFCTR:4;
0811                 uint32_t TNXTPTR:4;
0812                 uint32_t RFCTR:4;
0813                 uint32_t POPNXTPTR:4;
0814             } B;
0815         } FISR[6];              /* FIFO and Interrupt Status Registers */
0816
0817         uint32_t eqadc_reserved7;
0818
0819         uint32_t eqadc_reserved8;
0820
0821         union {
0822             uint16_t R;
0823             struct {
0824                 uint16_t:5;
0825                 uint16_t TC_CF:11;
0826             } B;
0827         } CFTCR[6];             /* CFIFO Transfer Counter Registers */
0828
0829         uint32_t eqadc_reserved9;
0830
0831         union {
0832             uint32_t R;
0833             struct {
0834                 uint32_t CFS0_T0:2;
0835                 uint32_t CFS1_T0:2;
0836                 uint32_t CFS2_T0:2;
0837                 uint32_t CFS3_T0:2;
0838                 uint32_t CFS4_T0:2;
0839                 uint32_t CFS5_T0:2;
0840                   uint32_t:5;
0841                 uint32_t LCFT0:4;
0842                 uint32_t TC_LCFT0:11;
0843             } B;
0844         } CFSSR0;               /* CFIFO Status Register 0 */
0845
0846         uint32_t eqadc_reserved10[2];
0847
0848         union {
0849             uint32_t R;
0850             struct {
0851                 uint32_t CFS0:2;
0852                 uint32_t CFS1:2;
0853                 uint32_t CFS2:2;
0854                 uint32_t CFS3:2;
0855                 uint32_t CFS4:2;
0856                 uint32_t CFS5:2;
0857                   uint32_t:20;
0858             } B;
0859         } CFSR;
0860
0861         uint32_t eqadc_reserved11[20];
0862
0863         struct {
0864             union {
0865                 uint32_t R;
0866                 struct {
0867                     uint32_t:32;
0868                 } B;
0869             } R[4];
0870
0871             uint32_t eqadc_reserved12[12];
0872
0873         } CF[6];
0874
0875         uint32_t eqadc_reserved13[32];
0876
0877         struct {
0878             union {
0879                 uint32_t R;
0880                 struct {
0881                     uint32_t:32;
0882                 } B;
0883             } R[4];
0884
0885             uint32_t eqadc_reserved14[12];
0886
0887         } RF[6];
0888
0889     };
0890 /****************************************************************************/
0891 /*                          MODULE : eSCI                                   */
0892 /****************************************************************************/
0893     struct ESCI_tag {
0894         union ESCI_CR1_tag {
0895             uint32_t R;
0896             struct {
0897                 uint32_t:3;
0898                 uint32_t SBR:13;
0899                 uint32_t LOOPS:1;
0900                   uint32_t:1;
0901                 uint32_t RSRC:1;
0902                 uint32_t M:1;
0903                 uint32_t WAKE:1;
0904                 uint32_t ILT:1;
0905                 uint32_t PE:1;
0906                 uint32_t PT:1;
0907                 uint32_t TIE:1;
0908                 uint32_t TCIE:1;
0909                 uint32_t RIE:1;
0910                 uint32_t ILIE:1;
0911                 uint32_t TE:1;
0912                 uint32_t RE:1;
0913                 uint32_t RWU:1;
0914                 uint32_t SBK:1;
0915             } B;
0916         } CR1;                  /* Control Register 1 */
0917
0918         union ESCI_CR2_tag {
0919             uint16_t R;
0920             struct {
0921                 uint16_t MDIS:1;
0922                 uint16_t FBR:1;
0923                 uint16_t BSTP:1;
0924                 uint16_t IEBERR:1;
0925                 uint16_t RXDMA:1;
0926                 uint16_t TXDMA:1;
0927                 uint16_t BRK13:1;
0928                 uint16_t TXDIR:1;
0929                 uint16_t BESM13:1;
0930                 uint16_t SBSTP:1;
0931                   uint16_t:1;
0932                 uint16_t PMSK:1;
0933                 uint16_t ORIE:1;
0934                 uint16_t NFIE:1;
0935                 uint16_t FEIE:1;
0936                 uint16_t PFIE:1;
0937             } B;
0938         } CR2;                  /* Control Register 2 */
0939
0940         union ESCI_DR_tag {
0941             uint16_t R;
0942             struct {
0943                 uint16_t R8:1;
0944                 uint16_t T8:1;
0945                   uint16_t:6;
0946                 uint8_t D;
0947             } B;
0948         } DR;                   /* Data Register */
0949
0950         union ESCI_SR_tag {
0951             uint32_t R;
0952             struct {
0953                 uint32_t TDRE:1;
0954                 uint32_t TC:1;
0955                 uint32_t RDRF:1;
0956                 uint32_t IDLE:1;
0957                 uint32_t OR:1;
0958                 uint32_t NF:1;
0959                 uint32_t FE:1;
0960                 uint32_t PF:1;
0961                   uint32_t:3;
0962                 uint32_t BERR:1;
0963                   uint32_t:3;
0964                 uint32_t RAF:1;
0965                 uint32_t RXRDY:1;
0966                 uint32_t TXRDY:1;
0967                 uint32_t LWAKE:1;
0968                 uint32_t STO:1;
0969                 uint32_t PBERR:1;
0970                 uint32_t CERR:1;
0971                 uint32_t CKERR:1;
0972                 uint32_t FRC:1;
0973                   uint32_t:6;
0974                 uint32_t UREQ:1;
0975                 uint32_t OVFL:1;
0976             } B;
0977         } SR;                   /* Status Register */
0978
0979         union {
0980             uint32_t R;
0981             struct {
0982                 uint32_t LRES:1;
0983                 uint32_t WU:1;
0984                 uint32_t WUD0:1;
0985                 uint32_t WUD1:1;
0986                 uint32_t LDBG:1;
0987                 uint32_t DSF:1;
0988                 uint32_t PRTY:1;
0989                 uint32_t LIN:1;
0990                 uint32_t RXIE:1;
0991                 uint32_t TXIE:1;
0992                 uint32_t WUIE:1;
0993                 uint32_t STIE:1;
0994                 uint32_t PBIE:1;
0995                 uint32_t CIE:1;
0996                 uint32_t CKIE:1;
0997                 uint32_t FCIE:1;
0998                   uint32_t:6;
0999                 uint32_t UQIE:1;
1000                 uint32_t OFIE:1;
1001                   uint32_t:8;
1002             } B;
1003         } LCR;                  /* LIN Control Register */
1004
1005         union {
1006             uint32_t R;
1007         } LTR;                  /* LIN Transmit Register */
1008
1009         union {
1010             uint32_t R;
1011         } LRR;                  /* LIN Recieve Register */
1012
1013         union {
1014             uint32_t R;
1015         } LPR;                  /* LIN CRC Polynom Register  */
1016
1017     };
1018 /****************************************************************************/
1019 /*                     MODULE : FLASH                                       */
1020 /****************************************************************************/
1021     struct FLASH_tag {
1022         union {                 /* Module Configuration Register */
1023             uint32_t R;
1024             struct {
1025                 uint32_t:3;
1026                 uint32_t SFS:1;
1027                 uint32_t SIZE:4;
1028                   uint32_t:1;
1029                 uint32_t LAS:3;
1030                   uint32_t:3;
1031                 uint32_t MAS:1;
1032                 uint32_t EER:1;
1033                 uint32_t RWE:1;
1034                 uint32_t BBEPE:1;
1035                 uint32_t EPE:1;
1036                 uint32_t PEAS:1;
1037                 uint32_t DONE:1;
1038                 uint32_t PEG:1;
1039                   uint32_t:1;
1040                 uint32_t PRD:1;
1041                 uint32_t STOP:1;
1042                   uint32_t:1;
1043                 uint32_t PGM:1;
1044                 uint32_t PSUS:1;
1045                 uint32_t ERS:1;
1046                 uint32_t ESUS:1;
1047                 uint32_t EHV:1;
1048             } B;
1049         } MCR;
1050
1051         union LMLR_tag {        /* Low/Mid Address Space Block Locking Register */
1052             uint32_t R;
1053             struct {
1054                 uint32_t LME:1;
1055                   uint32_t:10;
1056                 uint32_t SLOCK:1;
1057                   uint32_t:2;
1058                 uint32_t MLOCK:2;
1059                   uint32_t:6;
1060                 uint32_t LLOCK:10;
1061             } B;
1062         } LMLR; /* Legacy naming - refer to LML in Reference Manual */
1063
1064         union HLR_tag {         /* High Address Space Block Locking Register */
1065             uint32_t R;
1066             struct {
1067                 uint32_t HBE:1;
1068                   uint32_t:23;
1069                 uint32_t HBLOCK:8;
1070             } B;
1071         } HLR; /* Legacy naming - refer to HBL in Reference Manual */
1072
1073         union SLMLR_tag {       /* Secondary Low/Mid Block Locking Register */
1074             uint32_t R;
1075             struct {
1076                 uint32_t SLE:1;
1077                   uint32_t:10;
1078                 uint32_t SSLOCK:1;
1079                   uint32_t:2;
1080                 uint32_t SMLOCK:2;
1081                   uint32_t:6;
1082                 uint32_t SLLOCK:10;
1083             } B;
1084         } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */
1085
1086         union {                 /* Low/Mid Address Space Block Select Register */
1087             uint32_t R;
1088             struct {
1089                 uint32_t:14;
1090                 uint32_t MSEL:2;
1091                   uint32_t:6;
1092                 uint32_t LSEL:10;
1093             } B;
1094         } LMSR; /* Legacy naming - refer to LMS in Reference Manual */
1095
1096         union {                 /* High Address Space Block Select Register */
1097             uint32_t R;
1098             struct {
1099                 uint32_t:28;
1100                 uint32_t HBSEL:4;
1101             } B;
1102         } HSR; /* Legacy naming - refer to HBS in Reference Manual */
1103
1104         union {                 /* Address Register */
1105             uint32_t R;
1106             struct {
1107                 uint32_t:10;
1108                 uint32_t ADDR:19;
1109                   uint32_t:3;
1110             } B;
1111         } AR; /* Legacy naming - refer to ADR in Reference Manual */
1112
1113         union {                 /* Platform Flash Configuration Register for Port 0 */
1114             uint32_t R;
1115             struct {
1116                 uint32_t LBCFG:4;
1117                 uint32_t ARB:1;
1118                 uint32_t PRI:1;
1119                   uint32_t:5;
1120                 uint32_t M4PFE:1;
1121                 uint32_t M3PFE:1;
1122                 uint32_t M2PFE:1;
1123                 uint32_t M1PFE:1;
1124                 uint32_t M0PFE:1;
1125                 uint32_t APC:3;
1126                 uint32_t WWSC:2;
1127                 uint32_t RWSC:3;
1128                   uint32_t:1;
1129                 uint32_t DPFEN:1;
1130                   uint32_t:1;
1131                 uint32_t IPFEN:1;
1132                   uint32_t:1;
1133                 uint32_t PFLIM:2;
1134                 uint32_t BFEN:1;
1135             } B;
1136         } PFCRP0;
1137
1138         union {                 /* Platform Flash Configuration Register for Port 1 */
1139             uint32_t R;
1140             struct {
1141                 uint32_t LBCFG:4;
1142                   uint32_t:7;
1143                 uint32_t M4PFE:1;
1144                 uint32_t M3PFE:1;
1145                 uint32_t M2PFE:1;
1146                 uint32_t M1PFE:1;
1147                 uint32_t M0PFE:1;
1148                 uint32_t APC:3;
1149                 uint32_t WWSC:2;
1150                 uint32_t RWSC:3;
1151                   uint32_t:1;
1152                 uint32_t DPFEN:1;
1153                   uint32_t:1;
1154                 uint32_t IPFEN:1;
1155                   uint32_t:1;
1156                 uint32_t PFLIM:2;
1157                 uint32_t BFEN:1;
1158             } B;
1159         } PFCRP1;
1160
1161     };
1162 /****************************************************************************/
1163 /*                          MODULE : FlexCAN                                */
1164 /****************************************************************************/
1165     struct FLEXCAN_tag {
1166         union {
1167             uint32_t R;
1168             struct {
1169                 uint32_t MDIS:1;
1170                 uint32_t FRZ:1;
1171                 uint32_t FEN:1;
1172                 uint32_t HALT:1;
1173                 uint32_t NOTRDY:1;
1174                 uint32_t WAKMSK:1;
1175                 uint32_t SOFTRST:1;
1176                 uint32_t FRZACK:1;
1177                 uint32_t SUPV:1;
1178                 uint32_t SLFWAK:1;
1179                 uint32_t WRNEN:1;
1180                 uint32_t LPMACK:1;
1181                 uint32_t WAKSRC:1;
1182                 uint32_t DOZE:1;
1183                 uint32_t SRXDIS:1;
1184                 uint32_t BCC:1;
1185                   uint32_t:2;
1186                 uint32_t LPRIO_EN:1;
1187                 uint32_t AEN:1;
1188                   uint32_t:2;
1189                 uint32_t IDAM:2;
1190                   uint32_t:2;
1191                 uint32_t MAXMB:6;
1192             } B;
1193         } MCR;                  /* Module Configuration Register */
1194
1195         union {
1196             uint32_t R;
1197             struct {
1198                 uint32_t PRESDIV:8;
1199                 uint32_t RJW:2;
1200                 uint32_t PSEG1:3;
1201                 uint32_t PSEG2:3;
1202                 uint32_t BOFFMSK:1;
1203                 uint32_t ERRMSK:1;
1204                 uint32_t CLKSRC:1;
1205                 uint32_t LPB:1;
1206                 uint32_t TWRNMSK:1;
1207                 uint32_t RWRNMSK:1;
1208                   uint32_t:2;
1209                 uint32_t SMP:1;
1210                 uint32_t BOFFREC:1;
1211                 uint32_t TSYN:1;
1212                 uint32_t LBUF:1;
1213                 uint32_t LOM:1;
1214                 uint32_t PROPSEG:3;
1215             } B;
1216         } CTRL;                 /* Control Register */
1217
1218         union {
1219             uint32_t R;
1220         } TIMER;                /* Free Running Timer */
1221
1222         uint32_t FLEXCAN_reserved1;
1223
1224         union {
1225             uint32_t R;
1226             struct {
1227                 uint32_t MI:32;
1228             } B;
1229         } RXGMASK;              /* RX Global Mask */
1230
1231         union {
1232             uint32_t R;
1233             struct {
1234                 uint32_t MI:32;
1235             } B;
1236         } RX14MASK;             /* RX 14 Mask */
1237
1238         union {
1239             uint32_t R;
1240             struct {
1241                 uint32_t MI:32;
1242             } B;
1243         } RX15MASK;             /* RX 15 Mask */
1244
1245         union {
1246             uint32_t R;
1247             struct {
1248                 uint32_t:16;
1249                 uint32_t RXECNT:8;
1250                 uint32_t TXECNT:8;
1251             } B;
1252         } ECR;                  /* Error Counter Register */
1253
1254         union {
1255             uint32_t R;
1256             struct {
1257                 uint32_t:14;
1258                 uint32_t TWRNINT:1;
1259                 uint32_t RWRNINT:1;
1260                 uint32_t BIT1ERR:1;
1261                 uint32_t BIT0ERR:1;
1262                 uint32_t ACKERR:1;
1263                 uint32_t CRCERR:1;
1264                 uint32_t FRMERR:1;
1265                 uint32_t STFERR:1;
1266                 uint32_t TXWRN:1;
1267                 uint32_t RXWRN:1;
1268                 uint32_t IDLE:1;
1269                 uint32_t TXRX:1;
1270                 uint32_t FLTCONF:2;
1271                   uint32_t:1;
1272                 uint32_t BOFFINT:1;
1273                 uint32_t ERRINT:1;
1274                 uint32_t WAKINT:1;
1275             } B;
1276         } ESR;                  /* Error and Status Register */
1277
1278         union {
1279             uint32_t R;
1280             struct {
1281                 uint32_t BUF63M:1;
1282                 uint32_t BUF62M:1;
1283                 uint32_t BUF61M:1;
1284                 uint32_t BUF60M:1;
1285                 uint32_t BUF59M:1;
1286                 uint32_t BUF58M:1;
1287                 uint32_t BUF57M:1;
1288                 uint32_t BUF56M:1;
1289                 uint32_t BUF55M:1;
1290                 uint32_t BUF54M:1;
1291                 uint32_t BUF53M:1;
1292                 uint32_t BUF52M:1;
1293                 uint32_t BUF51M:1;
1294                 uint32_t BUF50M:1;
1295                 uint32_t BUF49M:1;
1296                 uint32_t BUF48M:1;
1297                 uint32_t BUF47M:1;
1298                 uint32_t BUF46M:1;
1299                 uint32_t BUF45M:1;
1300                 uint32_t BUF44M:1;
1301                 uint32_t BUF43M:1;
1302                 uint32_t BUF42M:1;
1303                 uint32_t BUF41M:1;
1304                 uint32_t BUF40M:1;
1305                 uint32_t BUF39M:1;
1306                 uint32_t BUF38M:1;
1307                 uint32_t BUF37M:1;
1308                 uint32_t BUF36M:1;
1309                 uint32_t BUF35M:1;
1310                 uint32_t BUF34M:1;
1311                 uint32_t BUF33M:1;
1312                 uint32_t BUF32M:1;
1313             } B;
1314         } IMASK2;               /* Interruput Masks Register */
1315
1316         union {
1317             uint32_t R;
1318             struct {
1319                 uint32_t BUF31M:1;
1320                 uint32_t BUF30M:1;
1321                 uint32_t BUF29M:1;
1322                 uint32_t BUF28M:1;
1323                 uint32_t BUF27M:1;
1324                 uint32_t BUF26M:1;
1325                 uint32_t BUF25M:1;
1326                 uint32_t BUF24M:1;
1327                 uint32_t BUF23M:1;
1328                 uint32_t BUF22M:1;
1329                 uint32_t BUF21M:1;
1330                 uint32_t BUF20M:1;
1331                 uint32_t BUF19M:1;
1332                 uint32_t BUF18M:1;
1333                 uint32_t BUF17M:1;
1334                 uint32_t BUF16M:1;
1335                 uint32_t BUF15M:1;
1336                 uint32_t BUF14M:1;
1337                 uint32_t BUF13M:1;
1338                 uint32_t BUF12M:1;
1339                 uint32_t BUF11M:1;
1340                 uint32_t BUF10M:1;
1341                 uint32_t BUF09M:1;
1342                 uint32_t BUF08M:1;
1343                 uint32_t BUF07M:1;
1344                 uint32_t BUF06M:1;
1345                 uint32_t BUF05M:1;
1346                 uint32_t BUF04M:1;
1347                 uint32_t BUF03M:1;
1348                 uint32_t BUF02M:1;
1349                 uint32_t BUF01M:1;
1350                 uint32_t BUF00M:1;
1351             } B;
1352         } IMASK1;               /* Interruput Masks Register */
1353
1354         union {
1355             uint32_t R;
1356             struct {
1357                 uint32_t BUF63I:1;
1358                 uint32_t BUF62I:1;
1359                 uint32_t BUF61I:1;
1360                 uint32_t BUF60I:1;
1361                 uint32_t BUF59I:1;
1362                 uint32_t BUF58I:1;
1363                 uint32_t BUF57I:1;
1364                 uint32_t BUF56I:1;
1365                 uint32_t BUF55I:1;
1366                 uint32_t BUF54I:1;
1367                 uint32_t BUF53I:1;
1368                 uint32_t BUF52I:1;
1369                 uint32_t BUF51I:1;
1370                 uint32_t BUF50I:1;
1371                 uint32_t BUF49I:1;
1372                 uint32_t BUF48I:1;
1373                 uint32_t BUF47I:1;
1374                 uint32_t BUF46I:1;
1375                 uint32_t BUF45I:1;
1376                 uint32_t BUF44I:1;
1377                 uint32_t BUF43I:1;
1378                 uint32_t BUF42I:1;
1379                 uint32_t BUF41I:1;
1380                 uint32_t BUF40I:1;
1381                 uint32_t BUF39I:1;
1382                 uint32_t BUF38I:1;
1383                 uint32_t BUF37I:1;
1384                 uint32_t BUF36I:1;
1385                 uint32_t BUF35I:1;
1386                 uint32_t BUF34I:1;
1387                 uint32_t BUF33I:1;
1388                 uint32_t BUF32I:1;
1389             } B;
1390         } IFLAG2;               /* Interruput Flag Register */
1391
1392         union {
1393             uint32_t R;
1394             struct {
1395                 uint32_t BUF31I:1;
1396                 uint32_t BUF30I:1;
1397                 uint32_t BUF29I:1;
1398                 uint32_t BUF28I:1;
1399                 uint32_t BUF27I:1;
1400                 uint32_t BUF26I:1;
1401                 uint32_t BUF25I:1;
1402                 uint32_t BUF24I:1;
1403                 uint32_t BUF23I:1;
1404                 uint32_t BUF22I:1;
1405                 uint32_t BUF21I:1;
1406                 uint32_t BUF20I:1;
1407                 uint32_t BUF19I:1;
1408                 uint32_t BUF18I:1;
1409                 uint32_t BUF17I:1;
1410                 uint32_t BUF16I:1;
1411                 uint32_t BUF15I:1;
1412                 uint32_t BUF14I:1;
1413                 uint32_t BUF13I:1;
1414                 uint32_t BUF12I:1;
1415                 uint32_t BUF11I:1;
1416                 uint32_t BUF10I:1;
1417                 uint32_t BUF09I:1;
1418                 uint32_t BUF08I:1;
1419                 uint32_t BUF07I:1;
1420                 uint32_t BUF06I:1;
1421                 uint32_t BUF05I:1;
1422                 uint32_t BUF04I:1;
1423                 uint32_t BUF03I:1;
1424                 uint32_t BUF02I:1;
1425                 uint32_t BUF01I:1;
1426                 uint32_t BUF00I:1;
1427             } B;
1428         } IFLAG1;               /* Interruput Flag Register */
1429
1430         uint32_t FLEXCAN_reserved2[19];
1431
1432         struct canbuf_t {
1433             union {
1434                 uint32_t R;
1435                 struct {
1436                     uint32_t:4;
1437                     uint32_t CODE:4;
1438                       uint32_t:1;
1439                     uint32_t SRR:1;
1440                     uint32_t IDE:1;
1441                     uint32_t RTR:1;
1442                     uint32_t LENGTH:4;
1443                     uint32_t TIMESTAMP:16;
1444                 } B;
1445             } CS;
1446
1447             union {
1448                 uint32_t R;
1449                 struct {
1450                     uint32_t PRIO:3;
1451                     uint32_t STD_ID:11;
1452                     uint32_t EXT_ID:18;
1453                 } B;
1454             } ID;
1455
1456             union {
1457                 uint8_t B[8];  /* Data buffer in Bytes (8 bits) */
1458                 uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
1459                 uint32_t W[2]; /* Data buffer in words (32 bits) */
1460                 uint32_t R[2]; /* Data buffer in words (32 bits) */
1461             } DATA;
1462
1463         } BUF[64];
1464
1465         uint32_t FLEXCAN_reserved3[256];
1466
1467         union {
1468             uint32_t R;
1469             struct {
1470                 uint32_t MI:32;
1471             } B;
1472         } RXIMR[64];            /* RX Individual Mask Registers */
1473
1474     };
1475 /****************************************************************************/
1476 /*                     MODULE : FMPLL                                       */
1477 /****************************************************************************/
1478     struct FMPLL_tag {
1479
1480         uint32_t FMPLL_reserved0;
1481
1482         union FMPLL_SYNSR_tag { /* Synthesiser Status Register */
1483             uint32_t R;
1484             struct {
1485                 uint32_t:22;
1486                 uint32_t LOLF:1;
1487                 uint32_t LOC:1;
1488                 uint32_t MODE:1;
1489                 uint32_t PLLSEL:1;
1490                 uint32_t PLLREF:1;
1491                 uint32_t LOCKS:1;
1492                 uint32_t LOCK:1;
1493                 uint32_t LOCF:1;
1494                 uint32_t CALDONE:1;
1495                 uint32_t CALPASS:1;
1496             } B;
1497         } SYNSR;
1498
1499         union FMPLL_ESYNCR1_tag {
1500             uint32_t R;
1501             struct {
1502                 uint32_t:1;
1503                 uint32_t CLKCFG:3;
1504                   uint32_t:8;
1505                 uint32_t EPREDIV:4;
1506                   uint32_t:8;
1507                 uint32_t EMFD:8;
1508             } B;
1509         } ESYNCR1;
1510
1511         union FMPLL_ESYNCR2_tag {
1512             uint32_t R;
1513             struct {
1514                 uint32_t:8;
1515                 uint32_t LOCEN:1;
1516                 uint32_t LOLRE:1;
1517                 uint32_t LOCRE:1;
1518                 uint32_t LOLIRQ:1;
1519                 uint32_t LOCIRQ:1;
1520                   uint32_t:1;
1521                 uint32_t ERATE:2;
1522                   uint32_t:5;
1523                 uint32_t EDEPTH:3;
1524                   uint32_t:2;
1525                 uint32_t ERFD:6;
1526             } B;
1527         } ESYNCR2;
1528
1529     };
1530 /****************************************************************************/
1531 /*                          MODULE : i2c                                    */
1532 /****************************************************************************/
1533     struct I2C_tag {
1534         union {
1535             uint8_t R;
1536             struct {
1537                 uint8_t AD:7;
1538                   uint8_t:1;
1539             } B;
1540         } IBAD;                 /* Module Bus Address Register */
1541
1542         union {
1543             uint8_t R;
1544             struct {
1545                 uint8_t MULT:2;
1546                 uint8_t ICR:6;
1547             } B;
1548         } IBFD;                 /* Module Bus Frequency Register */
1549
1550         union {
1551             uint8_t R;
1552             struct {
1553                 uint8_t MDIS:1;
1554                 uint8_t IBIE:1;
1555                 uint8_t MS:1;
1556                 uint8_t TX:1;
1557                 uint8_t NOACK:1;
1558                 uint8_t RSTA:1;
1559                 uint8_t DMAEN:1;
1560                   uint8_t:1;
1561             } B;
1562         } IBCR;                 /* Module Bus Control Register */
1563
1564         union {
1565             uint8_t R;
1566             struct {
1567                 uint8_t TCF:1;
1568                 uint8_t IAAS:1;
1569                 uint8_t IBB:1;
1570                 uint8_t IBAL:1;
1571                   uint8_t:1;
1572                 uint8_t SRW:1;
1573                 uint8_t IBIF:1;
1574                 uint8_t RXAK:1;
1575             } B;
1576         } IBSR;                 /* Module Status Register */
1577
1578         union {
1579             uint8_t R;
1580             struct {
1581                 uint8_t DATA:8;
1582             } B;
1583         } IBDR;                 /* Module Data Register */
1584
1585         union {
1586             uint8_t R;
1587             struct {
1588                 uint8_t BIIE:1;
1589                   uint8_t:7;
1590             } B;
1591         } IBIC;                 /* Module Interrupt Configuration Register */
1592
1593     };
1594 /****************************************************************************/
1595 /*                          MODULE : INTC                                   */
1596 /****************************************************************************/
1597     struct INTC_tag {
1598         union {
1599             uint32_t R;
1600             struct {
1601                 uint32_t:18;
1602                 uint32_t VTES_PRC1:1;
1603                   uint32_t:4;
1604                 uint32_t HVEN_PRC1:1;
1605                   uint32_t:2;
1606                 uint32_t VTES:1;
1607                   uint32_t:4;
1608                 uint32_t HVEN:1;
1609             } B;
1610         } MCR;                  /* Module Configuration Register */
1611
1612         int32_t INTC_reserved1;
1613
1614         union {
1615             uint32_t R;
1616             struct {
1617                 uint32_t:28;
1618                 uint32_t PRI:4;
1619             } B;
1620         } CPR;             /* Processor 0 Current Priority Register */
1621
1622         union {
1623             uint32_t R;
1624             struct {
1625                 uint32_t:28;
1626                 uint32_t PRI:4;
1627             } B;
1628         } CPR_PRC1;             /* Processor 1 Current Priority Register */
1629
1630         union {
1631             uint32_t R;
1632             struct {
1633                 uint32_t VTBA:21;
1634                 uint32_t INTVEC:9;
1635                   uint32_t:2;
1636             } B;
1637         } IACKR;           /* Processor 0 Interrupt Acknowledge Register */
1638
1639         union {
1640             uint32_t R;
1641             struct {
1642                 uint32_t VTBA_PRC1:21;
1643                 uint32_t INTVEC_PRC1:9;
1644                   uint32_t:2;
1645             } B;
1646         } IACKR_PRC1;           /* Processor 1 Interrupt Acknowledge Register */
1647
1648         union {
1649             uint32_t R;
1650             struct {
1651                 uint32_t:32;
1652             } B;
1653         } EOIR;            /* Processor 0 End of Interrupt Register */
1654
1655         union {
1656             uint32_t R;
1657             struct {
1658                 uint32_t:32;
1659             } B;
1660         } EOIR_PRC1;            /* Processor 1 End of Interrupt Register */
1661
1662         union {
1663             uint8_t R;
1664             struct {
1665                 uint8_t:6;
1666                 uint8_t SET:1;
1667                 uint8_t CLR:1;
1668             } B;
1669         } SSCIR[8];             /* Software Set/Clear Interruput Register */
1670
1671         uint32_t intc_reserved2[6];
1672
1673         union {
1674             uint8_t R;
1675             struct {
1676                 uint8_t PRC_SEL:2;
1677                   uint8_t:2;
1678                 uint8_t PRI:4;
1679             } B;
1680         } PSR[294];             /* Software Set/Clear Interrupt Register */
1681
1682     };
1683 /****************************************************************************/
1684 /*                     MODULE : MCM                                         */
1685 /****************************************************************************/
1686     struct MCM_tag {
1687
1688         uint32_t mcm_reserved1[5];
1689
1690         uint16_t mcm_reserved2;
1691
1692         union {
1693             uint16_t R;
1694             struct {
1695                 uint16_t RO:1;
1696                   uint16_t:6;
1697                 uint16_t SWRWH:1;
1698                 uint16_t SWE:1;
1699                 uint16_t SWRI:2;
1700                 uint16_t SWT:5;
1701             } B;
1702         } SWTCR;                /* Software Watchdog Timer Control */
1703
1704         uint8_t mcm_reserved3[3];
1705
1706         union {
1707             uint8_t R;
1708         } SWTSR;                /* SWT Service Register */
1709
1710         uint8_t mcm_reserved4[3];
1711
1712         union {
1713             uint8_t R;
1714             struct {
1715                 uint8_t:7;
1716                 uint8_t SWTIC:1;
1717             } B;
1718         } SWTIR;                /* SWT Interrupt Register */
1719
1720         uint32_t mcm_reserved5[1];
1721
1722         union {
1723             uint32_t R;
1724             struct {
1725                 uint32_t PRI:1;
1726                   uint32_t:31;
1727             } B;
1728         } MUDCR;                /* Misc. User Defined Control Register */
1729
1730         uint32_t mcm_reserved6[6];
1731         uint8_t mcm_reserved7[3];
1732
1733         union {
1734             uint8_t R;
1735             struct {
1736                 uint8_t:6;
1737                 uint8_t ERNCR:1;
1738                 uint8_t EFNCR:1;
1739             } B;
1740         } ECR;                  /* ECC Configuration Register */
1741
1742         uint8_t mcm_reserved8[3];
1743
1744         union {
1745             uint8_t R;
1746             struct {
1747                 uint8_t:6;
1748                 uint8_t RNCE:1;
1749                 uint8_t FNCE:1;
1750             } B;
1751         } ESR;                  /* ECC Status Register */
1752
1753         uint16_t mcm_reserved9;
1754
1755         union {
1756             uint16_t R;
1757             struct {
1758                 uint16_t:6;
1759                 uint16_t FRCNCI:1;
1760                 uint16_t FR1NCI:1;
1761                   uint16_t:1;
1762                 uint16_t ERRBIT:7;
1763             } B;
1764         } EEGR;                 /* ECC Error Generation Register */
1765
1766         uint32_t mcm_reserved10;
1767
1768         union {
1769             uint32_t R;
1770         } FEAR;                 /* Flash ECC Address Register */
1771
1772         uint16_t mcm_reserved11;
1773
1774         union {
1775             uint8_t R;
1776             struct {
1777                 uint8_t:4;
1778                 uint8_t FEMR:4;
1779             } B;
1780         } FEMR;                 /* Flash ECC Master Register */
1781
1782         union {
1783             uint8_t R;
1784             struct {
1785                 uint8_t WRITE:1;
1786                 uint8_t SIZE:3;
1787                 uint8_t PROTECTION:4;
1788             } B;
1789         } FEAT;                 /* Flash ECC Attributes Register */
1790
1791         union {
1792             uint32_t R;
1793         } FEDRH;                /* Flash ECC Data High Register */
1794
1795         union {
1796             uint32_t R;
1797         } FEDRL;                /* Flash ECC Data Low Register */
1798
1799         union {
1800             uint32_t R;
1801             struct {
1802                 uint32_t REAR:32;
1803             } B;
1804         } REAR;                 /* RAM ECC Address */
1805
1806         uint16_t mcm_reserved12;
1807
1808         union {
1809             uint8_t R;
1810             struct {
1811                 uint8_t:4;
1812                 uint8_t REMR:4;
1813             } B;
1814         } REMR;                 /* RAM ECC Master */
1815
1816         union {
1817             uint8_t R;
1818             struct {
1819                 uint8_t WRITE:1;
1820                 uint8_t SIZE:3;
1821                 uint8_t PROTECTION:4;
1822             } B;
1823         } REAT;                 /*  RAM ECC Attributes Register */
1824
1825         union {
1826             uint32_t R;
1827         } REDRH;                /* RAM ECC Data High Register */
1828
1829         union {
1830             uint32_t R;
1831         } REDRL;                /* RAMECC Data Low Register */
1832
1833     };
1834 /****************************************************************************/
1835 /*                          MODULE : MPU                                    */
1836 /****************************************************************************/
1837     struct MPU_tag {
1838         union {
1839             uint32_t R;
1840             struct {
1841                 uint32_t SPERR:8;
1842                   uint32_t:4;
1843                 uint32_t HRL:4;
1844                 uint32_t NSP:4;
1845                 uint32_t NGRD:4;
1846                   uint32_t:7;
1847                 uint32_t VLD:1;
1848             } B;
1849         } CESR;                 /* Module Control/Error Status Register */
1850
1851         uint32_t mpu_reserved1[3];
1852
1853         union {
1854             uint32_t R;
1855             struct {
1856                 uint32_t EADDR:32;
1857             } B;
1858         } EAR0;
1859
1860         union {
1861             uint32_t R;
1862             struct {
1863                 uint32_t EACD:16;
1864                 uint32_t EPID:8;
1865                 uint32_t EMN:4;
1866                 uint32_t EATTR:3;
1867                 uint32_t ERW:1;
1868             } B;
1869         } EDR0;
1870
1871         union {
1872             uint32_t R;
1873             struct {
1874                 uint32_t EADDR:32;
1875             } B;
1876         } EAR1;
1877
1878         union {
1879             uint32_t R;
1880             struct {
1881                 uint32_t EACD:16;
1882                 uint32_t EPID:8;
1883                 uint32_t EMN:4;
1884                 uint32_t EATTR:3;
1885                 uint32_t ERW:1;
1886             } B;
1887         } EDR1;
1888
1889         union {
1890             uint32_t R;
1891             struct {
1892                 uint32_t EADDR:32;
1893             } B;
1894         } EAR2;
1895
1896         union {
1897             uint32_t R;
1898             struct {
1899                 uint32_t EACD:16;
1900                 uint32_t EPID:8;
1901                 uint32_t EMN:4;
1902                 uint32_t EATTR:3;
1903                 uint32_t ERW:1;
1904             } B;
1905         } EDR2;
1906
1907         uint32_t mpu_reserved2[246];
1908
1909         struct {
1910             union {
1911                 uint32_t R;
1912                 struct {
1913                     uint32_t SRTADDR:27;
1914                       uint32_t:5;
1915                 } B;
1916             } WORD0;            /* Region Descriptor n Word 0 */
1917
1918             union {
1919                 uint32_t R;
1920                 struct {
1921                     uint32_t ENDADDR:27;
1922                       uint32_t:5;
1923                 } B;
1924             } WORD1;            /* Region Descriptor n Word 1 */
1925
1926             union {
1927                 uint32_t R;
1928                 struct {
1929                     uint32_t:6;
1930                     uint32_t M4RE0:1;
1931                     uint32_t M4WE:1;
1932                     uint32_t M3PE:1;
1933                     uint32_t M3SM:2;
1934                     uint32_t M3UM:3;
1935                     uint32_t M2PE:1;
1936                     uint32_t M2SM:2;
1937                     uint32_t M2UM:3;
1938                     uint32_t M1PE:1;
1939                     uint32_t M1SM:2;
1940                     uint32_t M1UM:3;
1941                     uint32_t M0PE:1;
1942                     uint32_t M0SM:2;
1943                     uint32_t M0UM:3;
1944                 } B;
1945             } WORD2;            /* Region Descriptor n Word 2 */
1946
1947             union {
1948                 uint32_t R;
1949                 struct {
1950                     uint32_t PID:8;
1951                     uint32_t PIDMASK:8;
1952                       uint32_t:15;
1953                     uint32_t VLD:1;
1954                 } B;
1955             } WORD3;            /* Region Descriptor n Word 3 */
1956
1957         } RGD[16];
1958
1959         uint32_t mpu_reserved3[192];
1960
1961         union {
1962             uint32_t R;
1963             struct {
1964                 uint32_t:6;
1965                 uint32_t M4RE:1;
1966                 uint32_t M4WE:1;
1967                 uint32_t M3PE:1;
1968                 uint32_t M3SM:2;
1969                 uint32_t M3UM:3;
1970                 uint32_t M2PE:1;
1971                 uint32_t M2SM:2;
1972                 uint32_t M2UM:3;
1973                 uint32_t M1PE:1;
1974                 uint32_t M1SM:2;
1975                 uint32_t M1UM:3;
1976                 uint32_t M0PE:1;
1977                 uint32_t M0SM:2;
1978                 uint32_t M0UM:3;
1979             } B;
1980         } RGDAAC[16];           /* Region Descriptor Alternate Access Control n */
1981     };
1982 /****************************************************************************/
1983 /*                          MODULE : pit                                    */
1984 /****************************************************************************/
1985     struct PIT_tag {
1986         union {
1987             uint32_t R;
1988             struct {
1989                 uint32_t TSV:32;
1990             } B;
1991         } TLVAL[9];
1992
1993         uint32_t pit_reserved1[23];
1994
1995         union {
1996             uint32_t R;
1997             struct {
1998                 uint32_t TVL:32;
1999             } B;
2000         } TVAL[9];
2001
2002         uint32_t pit_reserved2[23];
2003
2004         union {
2005             uint32_t R;
2006             struct {
2007                 uint32_t:23;
2008                 uint32_t TIF8:1;
2009                 uint32_t TIF7:1;
2010                 uint32_t TIF6:1;
2011                 uint32_t TIF5:1;
2012                 uint32_t TIF4:1;
2013                 uint32_t TIF3:1;
2014                 uint32_t TIF2:1;
2015                 uint32_t TIF1:1;
2016                 uint32_t RTIF:1;
2017             } B;
2018         } PITFLG;
2019
2020         union {
2021             uint32_t R;
2022             struct {
2023                 uint32_t:23;
2024                 uint32_t TIE8:1;
2025                 uint32_t TIE7:1;
2026                 uint32_t TIE6:1;
2027                 uint32_t TIE5:1;
2028                 uint32_t TIE4:1;
2029                 uint32_t TIE3:1;
2030                 uint32_t TIE2:1;
2031                 uint32_t TIE1:1;
2032                 uint32_t RTIE:1;
2033             } B;
2034         } PITINTEN;
2035
2036         union {
2037             uint32_t R;
2038             struct {
2039                 uint32_t:23;
2040                 uint32_t ISEL8:1;
2041                 uint32_t ISEL7:1;
2042                 uint32_t ISEL6:1;
2043                 uint32_t ISEL5:1;
2044                 uint32_t ISEL4:1;
2045                 uint32_t ISEL3:1;
2046                 uint32_t ISEL2:1;
2047                 uint32_t ISEL1:1;
2048                   uint32_t:1;
2049             } B;
2050         } PITINTSEL;
2051
2052         union {
2053             uint32_t R;
2054             struct {
2055                 uint32_t:23;
2056                 uint32_t PEN8:1;
2057                 uint32_t PEN7:1;
2058                 uint32_t PEN6:1;
2059                 uint32_t PEN5:1;
2060                 uint32_t PEN4:1;
2061                 uint32_t PEN3:1;
2062                 uint32_t PEN2:1;
2063                 uint32_t PEN1:1;
2064                 uint32_t PEN0:1;
2065             } B;
2066         } PITEN;
2067
2068         union {
2069             uint32_t R;
2070             struct {
2071                 uint32_t:7;
2072                 uint32_t MDIS:1;
2073                   uint32_t:24;
2074             } B;
2075         } PITCTRL;
2076
2077     };
2078 /****************************************************************************/
2079 /*                          MODULE : sem4                                   */
2080 /****************************************************************************/
2081     struct SEMA4_tag {
2082         union {
2083             uint8_t R;
2084             struct {
2085                 uint8_t:6;
2086                 uint8_t GTFSM:2;
2087             } B;
2088         } GATE[16];             /* Gate n Register */
2089
2090         uint32_t sema4_reserved1[12];   /* {0x40-0x10}/4 = 0x0C */
2091
2092         union {
2093             uint16_t R;
2094             struct {
2095                 uint16_t INE0:1;
2096                 uint16_t INE1:1;
2097                 uint16_t INE2:1;
2098                 uint16_t INE3:1;
2099                 uint16_t INE4:1;
2100                 uint16_t INE5:1;
2101                 uint16_t INE6:1;
2102                 uint16_t INE7:1;
2103                 uint16_t INE8:1;
2104                 uint16_t INE9:1;
2105                 uint16_t INE10:1;
2106                 uint16_t INE11:1;
2107                 uint16_t INE12:1;
2108                 uint16_t INE13:1;
2109                 uint16_t INE14:1;
2110                 uint16_t INE15:1;
2111             } B;
2112         } CP0INE;
2113
2114         uint16_t sema4_reserved2[3];    /* {0x48-0x42}/2 = 0x03 */
2115
2116         union {
2117             uint16_t R;
2118             struct {
2119                 uint16_t INE0:1;
2120                 uint16_t INE1:1;
2121                 uint16_t INE2:1;
2122                 uint16_t INE3:1;
2123                 uint16_t INE4:1;
2124                 uint16_t INE5:1;
2125                 uint16_t INE6:1;
2126                 uint16_t INE7:1;
2127                 uint16_t INE8:1;
2128                 uint16_t INE9:1;
2129                 uint16_t INE10:1;
2130                 uint16_t INE11:1;
2131                 uint16_t INE12:1;
2132                 uint16_t INE13:1;
2133                 uint16_t INE14:1;
2134                 uint16_t INE15:1;
2135             } B;
2136         } CP1INE;
2137
2138         uint16_t sema4_reserved3[27];   /* {0x80-0x4A}/2 = 0x1B */
2139
2140         union {
2141             uint16_t R;
2142             struct {
2143                 uint16_t GN0:1;
2144                 uint16_t GN1:1;
2145                 uint16_t GN2:1;
2146                 uint16_t GN3:1;
2147                 uint16_t GN4:1;
2148                 uint16_t GN5:1;
2149                 uint16_t GN6:1;
2150                 uint16_t GN7:1;
2151                 uint16_t GN8:1;
2152                 uint16_t GN9:1;
2153                 uint16_t GN10:1;
2154                 uint16_t GN11:1;
2155                 uint16_t GN12:1;
2156                 uint16_t GN13:1;
2157                 uint16_t GN14:1;
2158                 uint16_t GN15:1;
2159             } B;
2160         } CP0NTF;
2161
2162         uint16_t sema4_reserved4[3];    /* {0x88-0x82}/2 = 0x03 */
2163
2164         union {
2165             uint16_t R;
2166             struct {
2167                 uint16_t GN0:1;
2168                 uint16_t GN1:1;
2169                 uint16_t GN2:1;
2170                 uint16_t GN3:1;
2171                 uint16_t GN4:1;
2172                 uint16_t GN5:1;
2173                 uint16_t GN6:1;
2174                 uint16_t GN7:1;
2175                 uint16_t GN8:1;
2176                 uint16_t GN9:1;
2177                 uint16_t GN10:1;
2178                 uint16_t GN11:1;
2179                 uint16_t GN12:1;
2180                 uint16_t GN13:1;
2181                 uint16_t GN14:1;
2182                 uint16_t GN15:1;
2183             } B;
2184         } CP1NTF;
2185
2186         uint16_t sema4_reserved5[59];   /* {0x100-0x8A}/2 = 0x3B */
2187
2188         union {
2189             uint16_t R;
2190             struct {
2191                 uint16_t:2;
2192                 uint16_t RSTGSM:2;
2193                   uint16_t:1;
2194                 uint16_t RSTGMS:3;
2195                 uint16_t RSTGTN:8;
2196             } B;
2197         } RSTGT;
2198
2199         uint16_t sema4_reserved6;
2200
2201         union {
2202             uint16_t R;
2203             struct {
2204                 uint16_t:2;
2205                 uint16_t RSTNSM:2;
2206                   uint16_t:1;
2207                 uint16_t RSTNMS:3;
2208                 uint16_t RSTNTN:8;
2209             } B;
2210         } RSTNTF;
2211     };
2212 /****************************************************************************/
2213 /*                     MODULE : SIU                                         */
2214 /****************************************************************************/
2215     struct SIU_tag {
2216
2217         int32_t SIU_reserved0;
2218
2219         union {                 /* MCU ID Register */
2220             uint32_t R;
2221             struct {
2222                 uint32_t PARTNUM:16;
2223                 uint32_t CSP:1;
2224                 uint32_t PKG:5;
2225                   uint32_t:2;
2226                 uint32_t MASKNUM_MAJOR:4;
2227                 uint32_t MASKNUM_MINOR:4;
2228             } B;
2229         } MIDR;
2230
2231         int32_t SIU_reserved1;
2232
2233         union {                 /* Reset Status Register */
2234             uint32_t R;
2235             struct {
2236                 uint32_t PORS:1;
2237                 uint32_t ERS:1;
2238                 uint32_t LLRS:1;
2239                 uint32_t LCRS:1;
2240                 uint32_t WDRS:1;
2241                 uint32_t CRS:1;
2242                   uint32_t:8;
2243                 uint32_t SSRS:1;
2244                   uint32_t:15;
2245                 uint32_t BOOTCFG:1;
2246                   uint32_t:1;
2247             } B;
2248         } RSR;
2249
2250         union {                 /* System Reset Control Register */
2251             uint32_t R;
2252             struct {
2253                 uint32_t SSR:1;
2254                   uint32_t:15;
2255                 uint32_t CRE0:1;
2256                 uint32_t CRE1:1;
2257                   uint32_t:6;
2258                 uint32_t SSRL:1;
2259                   uint32_t:7;
2260             } B;
2261         } SRCR;
2262
2263         union SIU_EISR_tag {    /* External Interrupt Status Register */
2264             uint32_t R;
2265             struct {
2266                 uint32_t NMI0:1;
2267                 uint32_t NMI1:1;
2268                   uint32_t:14;
2269                 uint32_t EIF15:1;
2270                 uint32_t EIF14:1;
2271                 uint32_t EIF13:1;
2272                 uint32_t EIF12:1;
2273                 uint32_t EIF11:1;
2274                 uint32_t EIF10:1;
2275                 uint32_t EIF9:1;
2276                 uint32_t EIF8:1;
2277                 uint32_t EIF7:1;
2278                 uint32_t EIF6:1;
2279                 uint32_t EIF5:1;
2280                 uint32_t EIF4:1;
2281                 uint32_t EIF3:1;
2282                 uint32_t EIF2:1;
2283                 uint32_t EIF1:1;
2284                 uint32_t EIF0:1;
2285             } B;
2286         } EISR;
2287
2288         union SIU_DIRER_tag {   /* DMA/Interrupt Request Enable Register */
2289             uint32_t R;
2290             struct {
2291                 uint32_t:16;
2292                 uint32_t EIRE15:1;
2293                 uint32_t EIRE14:1;
2294                 uint32_t EIRE13:1;
2295                 uint32_t EIRE12:1;
2296                 uint32_t EIRE11:1;
2297                 uint32_t EIRE10:1;
2298                 uint32_t EIRE9:1;
2299                 uint32_t EIRE8:1;
2300                 uint32_t EIRE7:1;
2301                 uint32_t EIRE6:1;
2302                 uint32_t EIRE5:1;
2303                 uint32_t EIRE4:1;
2304                 uint32_t EIRE3:1;
2305                 uint32_t EIRE2:1;
2306                 uint32_t EIRE1:1;
2307                 uint32_t EIRE0:1;
2308             } B;
2309         } DIRER;
2310
2311         union SIU_DIRSR_tag {   /* DMA/Interrupt Select Register */
2312             uint32_t R;
2313             struct {
2314                 uint32_t:27;
2315                 uint32_t DIRS4:1;
2316                 uint32_t DIRS3:1;
2317                 uint32_t DIRS2:1;
2318                 uint32_t DIRS1:1;
2319                   uint32_t:1;
2320             } B;
2321         } DIRSR;
2322
2323         union {                 /* Overrun Status Register */
2324             uint32_t R;
2325             struct {
2326                 uint32_t:16;
2327                 uint32_t OVF15:1;
2328                 uint32_t OVF14:1;
2329                 uint32_t OVF13:1;
2330                 uint32_t OVF12:1;
2331                 uint32_t OVF11:1;
2332                 uint32_t OVF10:1;
2333                 uint32_t OVF9:1;
2334                 uint32_t OVF8:1;
2335                 uint32_t OVF7:1;
2336                 uint32_t OVF6:1;
2337                 uint32_t OVF5:1;
2338                 uint32_t OVF4:1;
2339                 uint32_t OVF3:1;
2340                 uint32_t OVF2:1;
2341                 uint32_t OVF1:1;
2342                 uint32_t OVF0:1;
2343             } B;
2344         } OSR;
2345
2346         union SIU_ORER_tag {    /* Overrun Request Enable Register */
2347             uint32_t R;
2348             struct {
2349                 uint32_t:16;
2350                 uint32_t ORE15:1;
2351                 uint32_t ORE14:1;
2352                 uint32_t ORE13:1;
2353                 uint32_t ORE12:1;
2354                 uint32_t ORE11:1;
2355                 uint32_t ORE10:1;
2356                 uint32_t ORE9:1;
2357                 uint32_t ORE8:1;
2358                 uint32_t ORE7:1;
2359                 uint32_t ORE6:1;
2360                 uint32_t ORE5:1;
2361                 uint32_t ORE4:1;
2362                 uint32_t ORE3:1;
2363                 uint32_t ORE2:1;
2364                 uint32_t ORE1:1;
2365                 uint32_t ORE0:1;
2366             } B;
2367         } ORER;
2368
2369         union SIU_IREER_tag {   /* External IRQ Rising-Edge Event Enable Register */
2370             uint32_t R;
2371             struct {
2372                 uint32_t NREE0:1;
2373                 uint32_t NREE1:1;
2374                   uint32_t:14;
2375                 uint32_t IREE15:1;
2376                 uint32_t IREE14:1;
2377                 uint32_t IREE13:1;
2378                 uint32_t IREE12:1;
2379                 uint32_t IREE11:1;
2380                 uint32_t IREE10:1;
2381                 uint32_t IREE9:1;
2382                 uint32_t IREE8:1;
2383                 uint32_t IREE7:1;
2384                 uint32_t IREE6:1;
2385                 uint32_t IREE5:1;
2386                 uint32_t IREE4:1;
2387                 uint32_t IREE3:1;
2388                 uint32_t IREE2:1;
2389                 uint32_t IREE1:1;
2390                 uint32_t IREE0:1;
2391             } B;
2392         } IREER;
2393
2394         union SIU_IFEER_tag {   /* External IRQ Falling-Edge Event Enable Register */
2395             uint32_t R;
2396             struct {
2397                 uint32_t NFEE0:1;
2398                 uint32_t NFEE1:1;
2399                   uint32_t:14;
2400                 uint32_t IFEE15:1;
2401                 uint32_t IFEE14:1;
2402                 uint32_t IFEE13:1;
2403                 uint32_t IFEE12:1;
2404                 uint32_t IFEE11:1;
2405                 uint32_t IFEE10:1;
2406                 uint32_t IFEE9:1;
2407                 uint32_t IFEE8:1;
2408                 uint32_t IFEE7:1;
2409                 uint32_t IFEE6:1;
2410                 uint32_t IFEE5:1;
2411                 uint32_t IFEE4:1;
2412                 uint32_t IFEE3:1;
2413                 uint32_t IFEE2:1;
2414                 uint32_t IFEE1:1;
2415                 uint32_t IFEE0:1;
2416             } B;
2417         } IFEER;
2418
2419         union SIU_IDFR_tag {    /* External IRQ Digital Filter Register */
2420             uint32_t R;
2421             struct {
2422                 uint32_t:28;
2423                 uint32_t DFL:4;
2424             } B;
2425         } IDFR;
2426
2427         union {                 /* External IRQ Filtered Input Register */
2428             uint32_t R;
2429             struct {
2430                 uint32_t FNMI0:1;
2431                 uint32_t FNMI1:1;
2432                   uint32_t:14;
2433                 uint32_t FI15:1;
2434                 uint32_t FI14:1;
2435                 uint32_t FI13:1;
2436                 uint32_t FI12:1;
2437                 uint32_t FI11:1;
2438                 uint32_t FI10:1;
2439                 uint32_t FI9:1;
2440                 uint32_t FI8:1;
2441                 uint32_t FI7:1;
2442                 uint32_t FI6:1;
2443                 uint32_t FI5:1;
2444                 uint32_t FI4:1;
2445                 uint32_t FI3:1;
2446                 uint32_t FI2:1;
2447                 uint32_t FI1:1;
2448                 uint32_t FI0:1;
2449             } B;
2450         } IFIR;
2451
2452         int32_t SIU_reserved2[2];
2453
2454         union SIU_PCR_tag {     /* Pad Configuration Registers */
2455             uint16_t R;
2456             struct {
2457                 uint16_t:4;
2458                 uint16_t PA:2;
2459                 uint16_t OBE:1;
2460                 uint16_t IBE:1;
2461                   uint16_t:2;
2462                 uint16_t ODE:1;
2463                 uint16_t HYS:1;
2464                 uint16_t SRC:2;
2465                 uint16_t WPE:1;
2466                 uint16_t WPS:1;
2467             } B;
2468         } PCR[146];
2469
2470         int32_t SIU_reserved3[295];
2471
2472         union {                 /* GPIO Pin Data Output Registers */
2473             uint8_t R;
2474             struct {
2475                 uint8_t:7;
2476                 uint8_t PDO:1;
2477             } B;
2478         } GPDO[146];
2479
2480         int32_t SIU_reserved4[91];
2481
2482         union {                 /* GPIO Pin Data Input Registers */
2483             uint8_t R;
2484             struct {
2485                 uint8_t:7;
2486                 uint8_t PDI:1;
2487             } B;
2488         } GPDI[146];
2489
2490         int32_t SIU_reserved5[27];
2491
2492         union {                 /* IMUX Register */
2493             uint32_t R;
2494             struct {
2495                 uint32_t TSEL3:2;
2496                 uint32_t TSEL2:2;
2497                 uint32_t TSEL1:2;
2498                 uint32_t TSEL0:2;
2499                   uint32_t:24;
2500             } B;
2501         } ISEL0;
2502
2503         union {                 /* IMUX Register */
2504             uint32_t R;
2505             struct {
2506                 uint32_t ESEL15:2;
2507                 uint32_t ESEL14:2;
2508                 uint32_t ESEL13:2;
2509                 uint32_t ESEL12:2;
2510                 uint32_t ESEL11:2;
2511                 uint32_t ESEL10:2;
2512                 uint32_t ESEL9:2;
2513                 uint32_t ESEL8:2;
2514                 uint32_t ESEL7:2;
2515                 uint32_t ESEL6:2;
2516                 uint32_t ESEL5:2;
2517                 uint32_t ESEL4:2;
2518                 uint32_t ESEL3:2;
2519                 uint32_t ESEL2:2;
2520                 uint32_t ESEL1:2;
2521                 uint32_t ESEL0:2;
2522             } B;
2523         } ISEL1;
2524
2525         union {                 /* IMUX Register */
2526             uint32_t R;
2527             struct {
2528                 uint32_t SELEMIOS15:2;
2529                 uint32_t SELEMIOS14:2;
2530                 uint32_t SELEMIOS13:2;
2531                 uint32_t SELEMIOS12:2;
2532                 uint32_t SELEMIOS11:2;
2533                 uint32_t SELEMIOS10:2;
2534                 uint32_t SELEMIOS9:2;
2535                 uint32_t SELEMIOS8:2;
2536                 uint32_t SELEMIOS7:2;
2537                 uint32_t SELEMIOS6:2;
2538                 uint32_t SELEMIOS5:2;
2539                 uint32_t SELEMIOS4:2;
2540                 uint32_t SELEMIOS3:2;
2541                 uint32_t SELEMIOS2:2;
2542                 uint32_t SELEMIOS1:2;
2543                 uint32_t SELEMIOS0:2;
2544             } B;
2545         } ISEL2;
2546
2547         int32_t SIU_reserved6[29];
2548
2549         union {                 /* Chip Configuration Register Register */
2550             uint32_t R;
2551             struct {
2552                 uint32_t:14;
2553                 uint32_t MATCH:1;
2554                 uint32_t DISNEX:1;
2555                   uint32_t:16;
2556             } B;
2557         } CCR;
2558
2559         union {                 /* External Clock Configuration Register Register */
2560             uint32_t R;
2561             struct {
2562                 uint32_t:30;
2563                 uint32_t EBDF:2;
2564             } B;
2565         } ECCR;
2566
2567         union {                 /* Compare A High Register */
2568             uint32_t R;
2569         } CMPAH;
2570
2571         union {                 /* Compare A Low Register */
2572             uint32_t R;
2573         } CMPAL;
2574
2575         union {                 /* Compare B High Register */
2576             uint32_t R;
2577         } CMPBH;
2578
2579         union {                 /* Compare B Low Register */
2580             uint32_t R;
2581         } CMPBL;
2582
2583         int32_t SIU_reserved7[2];
2584
2585         union {                 /* System CLock Register */
2586             uint32_t R;
2587             struct {
2588                 uint32_t SYSCLKSEL:2;
2589                 uint32_t SYSCLKDIV:2;
2590                 uint32_t SWTCLKSEL:1;
2591                   uint32_t:11;
2592                 uint32_t LPCLKDIV7:2;
2593                 uint32_t LPCLKDIV6:2;
2594                 uint32_t LPCLKDIV5:2;
2595                 uint32_t LPCLKDIV4:2;
2596                 uint32_t LPCLKDIV3:2;
2597                 uint32_t LPCLKDIV2:2;
2598                 uint32_t LPCLKDIV1:2;
2599                 uint32_t LPCLKDIV0:2;
2600             } B;
2601         } SYSCLK;
2602
2603         union {                 /* Halt Register */
2604             uint32_t R;
2605         } HLT;
2606
2607         union {                 /* Halt Acknowledge Register */
2608             uint32_t R;
2609         } HLTACK;
2610
2611         int32_t SIU_reserved8[149];
2612
2613         union {                 /* Parallel GPIO Pin Data Output Register */
2614             uint32_t R;
2615             struct {
2616                 uint32_t:16;
2617                 uint32_t PB:16;
2618             } B;
2619         } PGPDO0;
2620
2621         union {                 /* Parallel GPIO Pin Data Output Register */
2622             uint32_t R;
2623             struct {
2624                 uint32_t PC:16;
2625                 uint32_t PD:16;
2626             } B;
2627         } PGPDO1;
2628
2629         union {                 /* Parallel GPIO Pin Data Output Register */
2630             uint32_t R;
2631             struct {
2632                 uint32_t PE:16;
2633                 uint32_t PF:16;
2634             } B;
2635         } PGPDO2;
2636
2637         union {                 /* Parallel GPIO Pin Data Output Register */
2638             uint32_t R;
2639             struct {
2640                 uint32_t PG:16;
2641                 uint32_t PH:16;
2642             } B;
2643         } PGPDO3;
2644
2645         union {                 /* Parallel GPIO Pin Data Output Register */
2646             uint32_t R;
2647             struct {
2648                 uint32_t PJ:16;
2649                   uint32_t:16;
2650             } B;
2651         } PGPDO4;
2652
2653         int32_t SIU_reserved9[11];
2654
2655         union {                 /* Parallel GPIO Pin Data Input Register */
2656             uint32_t R;
2657             struct {
2658                 uint32_t PA:16;
2659                 uint32_t PB:16;
2660             } B;
2661         } PGPDI0;
2662
2663         union {                 /* Parallel GPIO Pin Data Input Register */
2664             uint32_t R;
2665             struct {
2666                 uint32_t PC:16;
2667                 uint32_t PD:16;
2668             } B;
2669         } PGPDI1;
2670
2671         union {                 /* Parallel GPIO Pin Data Input Register */
2672             uint32_t R;
2673             struct {
2674                 uint32_t PE:16;
2675                 uint32_t PF:16;
2676             } B;
2677         } PGPDI2;
2678
2679         union {                 /* Parallel GPIO Pin Data Input Register */
2680             uint32_t R;
2681             struct {
2682                 uint32_t PG:16;
2683                 uint32_t PH:16;
2684             } B;
2685         } PGPDI3;
2686
2687         union {                 /* Parallel GPIO Pin Data Input Register */
2688             uint32_t R;
2689             struct {
2690                 uint32_t PJ:16;
2691                 uint32_t PK:2;
2692                   uint32_t:14;
2693             } B;
2694         } PGPDI4;
2695
2696         int32_t SIU_reserved10[12];
2697
2698         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2699             uint32_t R;
2700             struct {
2701                 uint32_t PB_MASK:16;
2702                 uint32_t PB:16;
2703             } B;
2704         } MPGPDO1;
2705
2706         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2707             uint32_t R;
2708             struct {
2709                 uint32_t PC_MASK:16;
2710                 uint32_t PC:16;
2711             } B;
2712         } MPGPDO2;
2713
2714         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2715             uint32_t R;
2716             struct {
2717                 uint32_t PD_MASK:16;
2718                 uint32_t PD:16;
2719             } B;
2720         } MPGPDO3;
2721
2722         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2723             uint32_t R;
2724             struct {
2725                 uint32_t PE_MASK:16;
2726                 uint32_t PE:16;
2727             } B;
2728         } MPGPDO4;
2729
2730         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2731             uint32_t R;
2732             struct {
2733                 uint32_t PF_MASK:16;
2734                 uint32_t PF:16;
2735             } B;
2736         } MPGPDO5;
2737
2738         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2739             uint32_t R;
2740             struct {
2741                 uint32_t PG_MASK:16;
2742                 uint32_t PG:16;
2743             } B;
2744         } MPGPDO6;
2745
2746         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2747             uint32_t R;
2748             struct {
2749                 uint32_t PH_MASK:16;
2750                 uint32_t PH:16;
2751             } B;
2752         } MPGPDO7;
2753
2754         union {                 /* Masked Parallel GPIO Pin Data Input Register */
2755             uint32_t R;
2756             struct {
2757                 uint32_t PJ_MASK:16;
2758                 uint32_t PJ:16;
2759             } B;
2760         } MPGPDO8;
2761
2762     };
2763 /****************************************************************************/
2764 /*                          MODULE : FlexRay                                */
2765 /****************************************************************************/
2766
2767     typedef union uMVR {
2768         uint16_t R;
2769         struct {
2770             uint16_t CHIVER:8; /* CHI Version Number */
2771             uint16_t PEVER:8;  /* PE Version Number */
2772         } B;
2773     } MVR_t;
2774
2775     typedef union uMCR {
2776         uint16_t R;
2777         struct {
2778             uint16_t MEN:1;    /* module enable */
2779               uint16_t:1;
2780             uint16_t SCMD:1;   /* single channel mode */
2781             uint16_t CHB:1;    /* channel B enable */
2782             uint16_t CHA:1;    /* channel A enable */
2783             uint16_t SFFE:1;   /* synchronization frame filter enable */
2784               uint16_t:5;
2785             uint16_t CLKSEL:1; /* protocol engine clock source select */
2786             uint16_t PRESCALE:3;       /* protocol engine clock prescaler */
2787               uint16_t:1;
2788         } B;
2789     } MCR_t;
2790     typedef union uSTBSCR {
2791         uint16_t R;
2792         struct {
2793             uint16_t WMD:1;    /* write mode */
2794             uint16_t STBSSEL:7;        /* strobe signal select */
2795               uint16_t:3;
2796             uint16_t ENB:1;    /* strobe signal enable */
2797               uint16_t:2;
2798             uint16_t STBPSEL:2;        /* strobe port select */
2799         } B;
2800     } STBSCR_t;
2801     typedef union uMBDSR {
2802         uint16_t R;
2803         struct {
2804             uint16_t:1;
2805             uint16_t MBSEG2DS:7;       /* message buffer segment 2 data size */
2806               uint16_t:1;
2807             uint16_t MBSEG1DS:7;       /* message buffer segment 1 data size */
2808         } B;
2809     } MBDSR_t;
2810
2811     typedef union uMBSSUTR {
2812         uint16_t R;
2813         struct {
2814
2815             uint16_t:2;
2816             uint16_t LAST_MB_SEG1:6;   /* last message buffer control register for message buffer segment 1 */
2817               uint16_t:2;
2818             uint16_t LAST_MB_UTIL:6;   /* last message buffer utilized */
2819         } B;
2820     } MBSSUTR_t;
2821
2822     typedef union uPOCR {
2823         uint16_t R;
2824         uint8_t byte[2];
2825         struct {
2826             uint16_t WME:1;    /* write mode external correction command */
2827               uint16_t:3;
2828             uint16_t EOC_AP:2; /* external offset correction application */
2829             uint16_t ERC_AP:2; /* external rate correction application */
2830             uint16_t BSY:1;    /* command write busy / write mode command */
2831               uint16_t:3;
2832             uint16_t POCCMD:4; /* protocol command */
2833         } B;
2834     } POCR_t;
2835 /* protocol commands */
2836     typedef union uGIFER {
2837         uint16_t R;
2838         struct {
2839             uint16_t MIF:1;    /* module interrupt flag */
2840             uint16_t PRIF:1;   /* protocol interrupt flag */
2841             uint16_t CHIF:1;   /* CHI interrupt flag */
2842             uint16_t WKUPIF:1; /* wakeup interrupt flag */
2843             uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
2844             uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
2845             uint16_t RBIF:1;   /* receive message buffer interrupt flag */
2846             uint16_t TBIF:1;   /* transmit buffer interrupt flag */
2847             uint16_t MIE:1;    /* module interrupt enable */
2848             uint16_t PRIE:1;   /* protocol interrupt enable */
2849             uint16_t CHIE:1;   /* CHI interrupt enable */
2850             uint16_t WKUPIE:1; /* wakeup interrupt enable */
2851             uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
2852             uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
2853             uint16_t RBIE:1;   /* receive message buffer interrupt enable */
2854             uint16_t TBIE:1;   /* transmit buffer interrupt enable */
2855         } B;
2856     } GIFER_t;
2857     typedef union uPIFR0 {
2858         uint16_t R;
2859         struct {
2860             uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
2861             uint16_t INTLIF:1; /* internal protocol error interrupt flag */
2862             uint16_t ILCFIF:1; /* illegal protocol configuration flag */
2863             uint16_t CSAIF:1;  /* cold start abort interrupt flag */
2864             uint16_t MRCIF:1;  /* missing rate correctio interrupt flag */
2865             uint16_t MOCIF:1;  /* missing offset correctio interrupt flag */
2866             uint16_t CCLIF:1;  /* clock correction limit reached interrupt flag */
2867             uint16_t MXSIF:1;  /* max sync frames detected interrupt flag */
2868             uint16_t MTXIF:1;  /* media access test symbol received flag */
2869             uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
2870             uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
2871             uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
2872             uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
2873             uint16_t TI2IF:1;  /* timer 2 expired interrupt flag */
2874             uint16_t TI1IF:1;  /* timer 1 expired interrupt flag */
2875             uint16_t CYSIF:1;  /* cycle start interrupt flag */
2876         } B;
2877     } PIFR0_t;
2878     typedef union uPIFR1 {
2879         uint16_t R;
2880         struct {
2881             uint16_t EMCIF:1;  /* error mode changed interrupt flag */
2882             uint16_t IPCIF:1;  /* illegal protocol command interrupt flag */
2883             uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
2884             uint16_t PSCIF:1;  /* Protocol State Changed Interrupt Flag */
2885             uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
2886             uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
2887             uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
2888             uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
2889               uint16_t:2;
2890             uint16_t EVTIF:1;  /* even cycle table written interrupt flag */
2891             uint16_t ODTIF:1;  /* odd cycle table written interrupt flag */
2892               uint16_t:4;
2893         } B;
2894     } PIFR1_t;
2895     typedef union uPIER0 {
2896         uint16_t R;
2897         struct {
2898             uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
2899             uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable  */
2900             uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
2901             uint16_t CSAIE:1;  /* cold start abort interrupt enable */
2902             uint16_t MRCIE:1;  /* missing rate correctio interrupt enable */
2903             uint16_t MOCIE:1;  /* missing offset correctio interrupt enable */
2904             uint16_t CCLIE:1;  /* clock correction limit reached interrupt enable */
2905             uint16_t MXSIE:1;  /* max sync frames detected interrupt enable */
2906             uint16_t MTXIE:1;  /* media access test symbol received interrupt enable */
2907             uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
2908             uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
2909             uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
2910             uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
2911             uint16_t TI2IE:1;  /* timer 2 expired interrupt enable */
2912             uint16_t TI1IE:1;  /* timer 1 expired interrupt enable */
2913             uint16_t CYSIE:1;  /* cycle start interrupt enable */
2914         } B;
2915     } PIER0_t;
2916     typedef union uPIER1 {
2917         uint16_t R;
2918         struct {
2919             uint16_t EMCIE:1;  /* error mode changed interrupt enable */
2920             uint16_t IPCIE:1;  /* illegal protocol command interrupt enable */
2921             uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
2922             uint16_t PSCIE:1;  /* Protocol State Changed Interrupt enable */
2923             uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
2924             uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
2925             uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
2926             uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
2927               uint16_t:2;
2928             uint16_t EVTIE:1;  /* even cycle table written interrupt enable */
2929             uint16_t ODTIE:1;  /* odd cycle table written interrupt enable */
2930               uint16_t:4;
2931         } B;
2932     } PIER1_t;
2933     typedef union uCHIERFR {
2934         uint16_t R;
2935         struct {
2936             uint16_t FRLBEF:1; /* flame lost channel B error flag */
2937             uint16_t FRLAEF:1; /* frame lost channel A error flag */
2938             uint16_t PCMIEF:1; /* command ignored error flag */
2939             uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
2940             uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
2941             uint16_t MSBEF:1;  /* message buffer search error flag */
2942             uint16_t MBUEF:1;  /* message buffer utilization error flag */
2943             uint16_t LCKEF:1;  /* lock error flag */
2944             uint16_t DBLEF:1;  /* double transmit message buffer lock error flag */
2945             uint16_t SBCFEF:1; /* system bus communication failure error flag */
2946             uint16_t FIDEF:1;  /* frame ID error flag */
2947             uint16_t DPLEF:1;  /* dynamic payload length error flag */
2948             uint16_t SPLEF:1;  /* static payload length error flag */
2949             uint16_t NMLEF:1;  /* network management length error flag */
2950             uint16_t NMFEF:1;  /* network management frame error flag */
2951             uint16_t ILSAEF:1; /* illegal access error flag */
2952         } B;
2953     } CHIERFR_t;
2954     typedef union uMBIVEC {
2955         uint16_t R;
2956         struct {
2957
2958             uint16_t:2;
2959             uint16_t TBIVEC:6; /* transmit buffer interrupt vector */
2960               uint16_t:2;
2961             uint16_t RBIVEC:6; /* receive buffer interrupt vector */
2962         } B;
2963     } MBIVEC_t;
2964
2965     typedef union uPSR0 {
2966         uint16_t R;
2967         struct {
2968             uint16_t ERRMODE:2;        /* error mode */
2969             uint16_t SLOTMODE:2;       /* slot mode */
2970               uint16_t:1;
2971             uint16_t PROTSTATE:3;      /* protocol state */
2972             uint16_t SUBSTATE:4;       /* protocol sub state */
2973               uint16_t:1;
2974             uint16_t WAKEUPSTATUS:3;   /* wakeup status */
2975         } B;
2976     } PSR0_t;
2977
2978 /* protocol states */
2979 /* protocol sub-states */
2980 /* wakeup status */
2981     typedef union uPSR1 {
2982         uint16_t R;
2983         struct {
2984             uint16_t CSAA:1;   /* cold start attempt abort flag */
2985             uint16_t SCP:1;    /* cold start path */
2986               uint16_t:1;
2987             uint16_t REMCSAT:5;        /* remanining coldstart attempts */
2988             uint16_t CPN:1;    /* cold start noise path */
2989             uint16_t HHR:1;    /* host halt request pending */
2990             uint16_t FRZ:1;    /* freeze occured */
2991             uint16_t APTAC:5;  /* allow passive to active counter */
2992         } B;
2993     } PSR1_t;
2994     typedef union uPSR2 {
2995         uint16_t R;
2996         struct {
2997             uint16_t NBVB:1;   /* NIT boundary violation on channel B */
2998             uint16_t NSEB:1;   /* NIT syntax error on channel B */
2999             uint16_t STCB:1;   /* symbol window transmit conflict on channel B */
3000             uint16_t SBVB:1;   /* symbol window boundary violation on channel B */
3001             uint16_t SSEB:1;   /* symbol window syntax error on channel B */
3002             uint16_t MTB:1;    /* media access test symbol MTS received on channel B */
3003             uint16_t NBVA:1;   /* NIT boundary violation on channel A */
3004             uint16_t NSEA:1;   /* NIT syntax error on channel A */
3005             uint16_t STCA:1;   /* symbol window transmit conflict on channel A */
3006             uint16_t SBVA:1;   /* symbol window boundary violation on channel A */
3007             uint16_t SSEA:1;   /* symbol window syntax error on channel A */
3008             uint16_t MTA:1;    /* media access test symbol MTS received on channel A */
3009             uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3010         } B;
3011     } PSR2_t;
3012     typedef union uPSR3 {
3013         uint16_t R;
3014         struct {
3015             uint16_t:2;
3016             uint16_t WUB:1;    /* wakeup symbol received on channel B */
3017             uint16_t ABVB:1;   /* aggregated boundary violation on channel B */
3018             uint16_t AACB:1;   /* aggregated additional communication on channel B */
3019             uint16_t ACEB:1;   /* aggregated content error on channel B */
3020             uint16_t ASEB:1;   /* aggregated syntax error on channel B */
3021             uint16_t AVFB:1;   /* aggregated valid frame on channel B */
3022               uint16_t:2;
3023             uint16_t WUA:1;    /* wakeup symbol received on channel A */
3024             uint16_t ABVA:1;   /* aggregated boundary violation on channel A */
3025             uint16_t AACA:1;   /* aggregated additional communication on channel A */
3026             uint16_t ACEA:1;   /* aggregated content error on channel A */
3027             uint16_t ASEA:1;   /* aggregated syntax error on channel A */
3028             uint16_t AVFA:1;   /* aggregated valid frame on channel A */
3029         } B;
3030     } PSR3_t;
3031     typedef union uCIFRR {
3032         uint16_t R;
3033         struct {
3034             uint16_t:8;
3035             uint16_t MIFR:1;   /* module interrupt flag */
3036             uint16_t PRIFR:1;  /* protocol interrupt flag */
3037             uint16_t CHIFR:1;  /* CHI interrupt flag */
3038             uint16_t WUPIFR:1; /* wakeup interrupt flag */
3039             uint16_t FNEBIFR:1;        /* receive fifo channel B no empty interrupt flag */
3040             uint16_t FNEAIFR:1;        /* receive fifo channel A no empty interrupt flag */
3041             uint16_t RBIFR:1;  /* receive message buffer interrupt flag */
3042             uint16_t TBIFR:1;  /* transmit buffer interrupt flag */
3043         } B;
3044     } CIFRR_t;
3045     typedef union uSYMATOR {
3046         uint16_t R;
3047         struct {
3048             uint16_t:11;
3049             uint16_t TIMEOUT:5;        /* system memory time out value */
3050         } B;
3051     } SYMATOR_t;
3052
3053     typedef union uSFCNTR {
3054         uint16_t R;
3055         struct {
3056             uint16_t SFEVB:4;  /* sync frames channel B, even cycle */
3057             uint16_t SFEVA:4;  /* sync frames channel A, even cycle */
3058             uint16_t SFODB:4;  /* sync frames channel B, odd cycle */
3059             uint16_t SFODA:4;  /* sync frames channel A, odd cycle */
3060         } B;
3061     } SFCNTR_t;
3062
3063     typedef union uSFTCCSR {
3064         uint16_t R;
3065         struct {
3066             uint16_t ELKT:1;   /* even cycle tables lock and unlock trigger */
3067             uint16_t OLKT:1;   /* odd cycle tables lock and unlock trigger */
3068             uint16_t CYCNUM:6; /* cycle number */
3069             uint16_t ELKS:1;   /* even cycle tables lock status */
3070             uint16_t OLKS:1;   /* odd cycle tables lock status */
3071             uint16_t EVAL:1;   /* even cycle tables valid */
3072             uint16_t OVAL:1;   /* odd cycle tables valid */
3073               uint16_t:1;
3074             uint16_t OPT:1;    /*one pair trigger */
3075             uint16_t SDVEN:1;  /* sync frame deviation table enable */
3076             uint16_t SIDEN:1;  /* sync frame ID table enable */
3077         } B;
3078     } SFTCCSR_t;
3079     typedef union uSFIDRFR {
3080         uint16_t R;
3081         struct {
3082             uint16_t:6;
3083             uint16_t SYNFRID:10;       /* sync frame rejection ID */
3084         } B;
3085     } SFIDRFR_t;
3086
3087     typedef union uTICCR {
3088         uint16_t R;
3089         struct {
3090             uint16_t:2;
3091             uint16_t T2CFG:1;  /* timer 2 configuration */
3092             uint16_t T2REP:1;  /* timer 2 repetitive mode */
3093               uint16_t:1;
3094             uint16_t T2SP:1;   /* timer 2 stop */
3095             uint16_t T2TR:1;   /* timer 2 trigger */
3096             uint16_t T2ST:1;   /* timer 2 state */
3097               uint16_t:3;
3098             uint16_t T1REP:1;  /* timer 1 repetitive mode */
3099               uint16_t:1;
3100             uint16_t T1SP:1;   /* timer 1 stop */
3101             uint16_t T1TR:1;   /* timer 1 trigger */
3102             uint16_t T1ST:1;   /* timer 1 state */
3103
3104         } B;
3105     } TICCR_t;
3106     typedef union uTI1CYSR {
3107         uint16_t R;
3108         struct {
3109             uint16_t:2;
3110             uint16_t TI1CYCVAL:6;      /* timer 1 cycle filter value */
3111               uint16_t:2;
3112             uint16_t TI1CYCMSK:6;      /* timer 1 cycle filter mask */
3113
3114         } B;
3115     } TI1CYSR_t;
3116
3117     typedef union uSSSR {
3118         uint16_t R;
3119         struct {
3120             uint16_t WMD:1;    /* write mode */
3121               uint16_t:1;
3122             uint16_t SEL:2;    /* static slot number */
3123               uint16_t:1;
3124             uint16_t SLOTNUMBER:11;    /* selector */
3125         } B;
3126     } SSSR_t;
3127
3128     typedef union uSSCCR {
3129         uint16_t R;
3130         struct {
3131             uint16_t WMD:1;    /* write mode */
3132               uint16_t:1;
3133             uint16_t SEL:2;    /* selector */
3134               uint16_t:1;
3135             uint16_t CNTCFG:2; /* counter configuration */
3136             uint16_t MCY:1;    /* multi cycle selection */
3137             uint16_t VFR:1;    /* valid frame selection */
3138             uint16_t SYF:1;    /* sync frame selection */
3139             uint16_t NUF:1;    /* null frame selection  */
3140             uint16_t SUF:1;    /* startup frame selection */
3141             uint16_t STATUSMASK:4;     /* slot status mask */
3142         } B;
3143     } SSCCR_t;
3144     typedef union uSSR {
3145         uint16_t R;
3146         struct {
3147             uint16_t VFB:1;    /* valid frame on channel B */
3148             uint16_t SYB:1;    /* valid sync frame on channel B */
3149             uint16_t NFB:1;    /* valid null frame on channel B */
3150             uint16_t SUB:1;    /* valid startup frame on channel B */
3151             uint16_t SEB:1;    /* syntax error on channel B */
3152             uint16_t CEB:1;    /* content error on channel B */
3153             uint16_t BVB:1;    /* boundary violation on channel B */
3154             uint16_t TCB:1;    /* tx conflict on channel B */
3155             uint16_t VFA:1;    /* valid frame on channel A */
3156             uint16_t SYA:1;    /* valid sync frame on channel A */
3157             uint16_t NFA:1;    /* valid null frame on channel A */
3158             uint16_t SUA:1;    /* valid startup frame on channel A */
3159             uint16_t SEA:1;    /* syntax error on channel A */
3160             uint16_t CEA:1;    /* content error on channel A */
3161             uint16_t BVA:1;    /* boundary violation on channel A */
3162             uint16_t TCA:1;    /* tx conflict on channel A */
3163         } B;
3164     } SSR_t;
3165     typedef union uMTSCFR {
3166         uint16_t R;
3167         struct {
3168             uint16_t MTE:1;    /* media access test symbol transmission enable */
3169               uint16_t:1;
3170             uint16_t CYCCNTMSK:6;      /* cycle counter mask */
3171               uint16_t:2;
3172             uint16_t CYCCNTVAL:6;      /* cycle counter value */
3173         } B;
3174     } MTSCFR_t;
3175
3176     typedef union uRSBIR {
3177         uint16_t R;
3178         struct {
3179             uint16_t WMD:1;    /* write mode */
3180               uint16_t:1;
3181             uint16_t SEL:2;    /* selector */
3182               uint16_t:5;
3183             uint16_t RSBIDX:7; /* receive shadow buffer index */
3184         } B;
3185     } RSBIR_t;
3186
3187     typedef union uRFDSR {
3188         uint16_t R;
3189         struct {
3190             uint16_t FIFODEPTH:8;      /* fifo depth */
3191               uint16_t:1;
3192             uint16_t ENTRYSIZE:7;      /* entry size */
3193         } B;
3194     } RFDSR_t;
3195
3196     typedef union uRFRFCFR {
3197         uint16_t R;
3198         struct {
3199             uint16_t WMD:1;    /* write mode */
3200             uint16_t IBD:1;    /* interval boundary */
3201             uint16_t SEL:2;    /* filter number */
3202               uint16_t:1;
3203             uint16_t SID:11;   /* slot ID */
3204         } B;
3205     } RFRFCFR_t;
3206
3207     typedef union uRFRFCTR {
3208         uint16_t R;
3209         struct {
3210             uint16_t:4;
3211             uint16_t F3MD:1;   /* filter mode */
3212             uint16_t F2MD:1;   /* filter mode */
3213             uint16_t F1MD:1;   /* filter mode */
3214             uint16_t F0MD:1;   /* filter mode */
3215               uint16_t:4;
3216             uint16_t F3EN:1;   /* filter enable */
3217             uint16_t F2EN:1;   /* filter enable */
3218             uint16_t F1EN:1;   /* filter enable */
3219             uint16_t F0EN:1;   /* filter enable */
3220         } B;
3221     } RFRFCTR_t;
3222     typedef union uPCR0 {
3223         uint16_t R;
3224         struct {
3225             uint16_t ACTION_POINT_OFFSET:6;
3226             uint16_t STATIC_SLOT_LENGTH:10;
3227         } B;
3228     } PCR0_t;
3229
3230     typedef union uPCR1 {
3231         uint16_t R;
3232         struct {
3233             uint16_t:2;
3234             uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3235         } B;
3236     } PCR1_t;
3237
3238     typedef union uPCR2 {
3239         uint16_t R;
3240         struct {
3241             uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3242             uint16_t NUMBER_OF_STATIC_SLOTS:10;
3243         } B;
3244     } PCR2_t;
3245
3246     typedef union uPCR3 {
3247         uint16_t R;
3248         struct {
3249             uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3250             uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3251             uint16_t COLDSTART_ATTEMPTS:5;
3252         } B;
3253     } PCR3_t;
3254
3255     typedef union uPCR4 {
3256         uint16_t R;
3257         struct {
3258             uint16_t CAS_RX_LOW_MAX:7;
3259             uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3260         } B;
3261     } PCR4_t;
3262
3263     typedef union uPCR5 {
3264         uint16_t R;
3265         struct {
3266             uint16_t TSS_TRANSMITTER:4;
3267             uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3268             uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3269         } B;
3270     } PCR5_t;
3271
3272     typedef union uPCR6 {
3273         uint16_t R;
3274         struct {
3275             uint16_t:1;
3276             uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3277             uint16_t MACRO_INITIAL_OFFSET_A:7;
3278         } B;
3279     } PCR6_t;
3280
3281     typedef union uPCR7 {
3282         uint16_t R;
3283         struct {
3284             uint16_t DECODING_CORRECTION_B:9;
3285             uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3286         } B;
3287     } PCR7_t;
3288
3289     typedef union uPCR8 {
3290         uint16_t R;
3291         struct {
3292             uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3293             uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3294             uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3295         } B;
3296     } PCR8_t;
3297
3298     typedef union uPCR9 {
3299         uint16_t R;
3300         struct {
3301             uint16_t MINISLOT_EXISTS:1;
3302             uint16_t SYMBOL_WINDOW_EXISTS:1;
3303             uint16_t OFFSET_CORRECTION_OUT:14;
3304         } B;
3305     } PCR9_t;
3306
3307     typedef union uPCR10 {
3308         uint16_t R;
3309         struct {
3310             uint16_t SINGLE_SLOT_ENABLED:1;
3311             uint16_t WAKEUP_CHANNEL:1;
3312             uint16_t MACRO_PER_CYCLE:14;
3313         } B;
3314     } PCR10_t;
3315
3316     typedef union uPCR11 {
3317         uint16_t R;
3318         struct {
3319             uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
3320             uint16_t KEY_SLOT_USED_FOR_SYNC:1;
3321             uint16_t OFFSET_CORRECTION_START:14;
3322         } B;
3323     } PCR11_t;
3324
3325     typedef union uPCR12 {
3326         uint16_t R;
3327         struct {
3328             uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
3329             uint16_t KEY_SLOT_HEADER_CRC:11;
3330         } B;
3331     } PCR12_t;
3332
3333     typedef union uPCR13 {
3334         uint16_t R;
3335         struct {
3336             uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
3337             uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
3338         } B;
3339     } PCR13_t;
3340
3341     typedef union uPCR14 {
3342         uint16_t R;
3343         struct {
3344             uint16_t RATE_CORRECTION_OUT:11;
3345             uint16_t LISTEN_TIMEOUT_H:5;
3346         } B;
3347     } PCR14_t;
3348
3349     typedef union uPCR15 {
3350         uint16_t R;
3351         struct {
3352             uint16_t LISTEN_TIMEOUT_L:16;
3353         } B;
3354     } PCR15_t;
3355
3356     typedef union uPCR16 {
3357         uint16_t R;
3358         struct {
3359             uint16_t MACRO_INITIAL_OFFSET_B:7;
3360             uint16_t NOISE_LISTEN_TIMEOUT_H:9;
3361         } B;
3362     } PCR16_t;
3363
3364     typedef union uPCR17 {
3365         uint16_t R;
3366         struct {
3367             uint16_t NOISE_LISTEN_TIMEOUT_L:16;
3368         } B;
3369     } PCR17_t;
3370
3371     typedef union uPCR18 {
3372         uint16_t R;
3373         struct {
3374             uint16_t WAKEUP_PATTERN:6;
3375             uint16_t KEY_SLOT_ID:10;
3376         } B;
3377     } PCR18_t;
3378
3379     typedef union uPCR19 {
3380         uint16_t R;
3381         struct {
3382             uint16_t DECODING_CORRECTION_A:9;
3383             uint16_t PAYLOAD_LENGTH_STATIC:7;
3384         } B;
3385     } PCR19_t;
3386
3387     typedef union uPCR20 {
3388         uint16_t R;
3389         struct {
3390             uint16_t MICRO_INITIAL_OFFSET_B:8;
3391             uint16_t MICRO_INITIAL_OFFSET_A:8;
3392         } B;
3393     } PCR20_t;
3394
3395     typedef union uPCR21 {
3396         uint16_t R;
3397         struct {
3398             uint16_t EXTERN_RATE_CORRECTION:3;
3399             uint16_t LATEST_TX:13;
3400         } B;
3401     } PCR21_t;
3402
3403     typedef union uPCR22 {
3404         uint16_t R;
3405         struct {
3406             uint16_t:1;
3407             uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
3408             uint16_t MICRO_PER_CYCLE_H:4;
3409         } B;
3410     } PCR22_t;
3411
3412     typedef union uPCR23 {
3413         uint16_t R;
3414         struct {
3415             uint16_t micro_per_cycle_l:16;
3416         } B;
3417     } PCR23_t;
3418
3419     typedef union uPCR24 {
3420         uint16_t R;
3421         struct {
3422             uint16_t CLUSTER_DRIFT_DAMPING:5;
3423             uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
3424             uint16_t MICRO_PER_CYCLE_MIN_H:4;
3425         } B;
3426     } PCR24_t;
3427
3428     typedef union uPCR25 {
3429         uint16_t R;
3430         struct {
3431             uint16_t MICRO_PER_CYCLE_MIN_L:16;
3432         } B;
3433     } PCR25_t;
3434
3435     typedef union uPCR26 {
3436         uint16_t R;
3437         struct {
3438             uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
3439             uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
3440             uint16_t MICRO_PER_CYCLE_MAX_H:4;
3441         } B;
3442     } PCR26_t;
3443
3444     typedef union uPCR27 {
3445         uint16_t R;
3446         struct {
3447             uint16_t MICRO_PER_CYCLE_MAX_L:16;
3448         } B;
3449     } PCR27_t;
3450
3451     typedef union uPCR28 {
3452         uint16_t R;
3453         struct {
3454             uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
3455             uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
3456         } B;
3457     } PCR28_t;
3458
3459     typedef union uPCR29 {
3460         uint16_t R;
3461         struct {
3462             uint16_t EXTERN_OFFSET_CORRECTION:3;
3463             uint16_t MINISLOTS_MAX:13;
3464         } B;
3465     } PCR29_t;
3466
3467     typedef union uPCR30 {
3468         uint16_t R;
3469         struct {
3470             uint16_t:12;
3471             uint16_t SYNC_NODE_MAX:4;
3472         } B;
3473     } PCR30_t;
3474
3475     typedef struct uMSG_BUFF_CCS {
3476         union {
3477             uint16_t R;
3478             struct {
3479                 uint16_t:1;
3480                 uint16_t MCM:1;        /* message buffer commit mode */
3481                 uint16_t MBT:1;        /* message buffer type */
3482                 uint16_t MTD:1;        /* message buffer direction */
3483                 uint16_t CMT:1;        /* commit for transmission */
3484                 uint16_t EDT:1;        /* enable / disable trigger */
3485                 uint16_t LCKT:1;       /* lock request trigger */
3486                 uint16_t MBIE:1;       /* message buffer interrupt enable */
3487                   uint16_t:3;
3488                 uint16_t DUP:1;        /* data updated  */
3489                 uint16_t DVAL:1;       /* data valid */
3490                 uint16_t EDS:1;        /* lock status */
3491                 uint16_t LCKS:1;       /* enable / disable status */
3492                 uint16_t MBIF:1;       /* message buffer interrupt flag */
3493             } B;
3494         } MBCCSR;
3495         union {
3496             uint16_t R;
3497             struct {
3498                 uint16_t MTM:1;        /* message buffer transmission mode */
3499                 uint16_t CHNLA:1;      /* channel assignement */
3500                 uint16_t CHNLB:1;      /* channel assignement */
3501                 uint16_t CCFE:1;       /* cycle counter filter enable */
3502                 uint16_t CCFMSK:6;     /* cycle counter filter mask */
3503                 uint16_t CCFVAL:6;     /* cycle counter filter value */
3504             } B;
3505         } MBCCFR;
3506         union {
3507             uint16_t R;
3508             struct {
3509                 uint16_t:5;
3510                 uint16_t FID:11;       /* frame ID */
3511             } B;
3512         } MBFIDR;
3513
3514         union {
3515             uint16_t R;
3516             struct {
3517                 uint16_t:9;
3518                 uint16_t MBIDX:7;      /* message buffer index */
3519             } B;
3520         } MBIDXR;
3521     } MSG_BUFF_CCS_t;
3522     typedef union uSYSBADHR {
3523         uint16_t R;
3524     } SYSBADHR_t;
3525     typedef union uSYSBADLR {
3526         uint16_t R;
3527     } SYSBADLR_t;
3528     typedef union uPADR {
3529         uint16_t R;
3530     } PADR_t;
3531     typedef union uPDAR {
3532         uint16_t R;
3533     } PDAR_t;
3534     typedef union uCASERCR {
3535         uint16_t R;
3536     } CASERCR_t;
3537     typedef union uCBSERCR {
3538         uint16_t R;
3539     } CBSERCR_t;
3540     typedef union uCYCTR {
3541         uint16_t R;
3542     } CYCTR_t;
3543     typedef union uMTCTR {
3544         uint16_t R;
3545     } MTCTR_t;
3546     typedef union uSLTCTAR {
3547         uint16_t R;
3548     } SLTCTAR_t;
3549     typedef union uSLTCTBR {
3550         uint16_t R;
3551     } SLTCTBR_t;
3552     typedef union uRTCORVR {
3553         uint16_t R;
3554     } RTCORVR_t;
3555     typedef union uOFCORVR {
3556         uint16_t R;
3557     } OFCORVR_t;
3558     typedef union uSFTOR {
3559         uint16_t R;
3560     } SFTOR_t;
3561     typedef union uSFIDAFVR {
3562         uint16_t R;
3563     } SFIDAFVR_t;
3564     typedef union uSFIDAFMR {
3565         uint16_t R;
3566     } SFIDAFMR_t;
3567     typedef union uNMVR {
3568         uint16_t R;
3569     } NMVR_t;
3570     typedef union uNMVLR {
3571         uint16_t R;
3572     } NMVLR_t;
3573     typedef union uT1MTOR {
3574         uint16_t R;
3575     } T1MTOR_t;
3576     typedef union uTI2CR0 {
3577         uint16_t R;
3578     } TI2CR0_t;
3579     typedef union uTI2CR1 {
3580         uint16_t R;
3581     } TI2CR1_t;
3582     typedef union uSSCR {
3583         uint16_t R;
3584     } SSCR_t;
3585     typedef union uRFSR {
3586         uint16_t R;
3587     } RFSR_t;
3588     typedef union uRFSIR {
3589         uint16_t R;
3590     } RFSIR_t;
3591     typedef union uRFARIR {
3592         uint16_t R;
3593     } RFARIR_t;
3594     typedef union uRFBRIR {
3595         uint16_t R;
3596     } RFBRIR_t;
3597     typedef union uRFMIDAFVR {
3598         uint16_t R;
3599     } RFMIDAFVR_t;
3600     typedef union uRFMIAFMR {
3601         uint16_t R;
3602     } RFMIAFMR_t;
3603     typedef union uRFFIDRFVR {
3604         uint16_t R;
3605     } RFFIDRFVR_t;
3606     typedef union uRFFIDRFMR {
3607         uint16_t R;
3608     } RFFIDRFMR_t;
3609     typedef union uLDTXSLAR {
3610         uint16_t R;
3611     } LDTXSLAR_t;
3612     typedef union uLDTXSLBR {
3613         uint16_t R;
3614     } LDTXSLBR_t;
3615
3616     typedef struct FR_tag {
3617         volatile MVR_t MVR;     /*module version register *//*0  */
3618         volatile MCR_t MCR;     /*module configuration register *//*2  */
3619         volatile SYSBADHR_t SYSBADHR;   /*system memory base address high register *//*4        */
3620         volatile SYSBADLR_t SYSBADLR;   /*system memory base address low register *//*6         */
3621         volatile STBSCR_t STBSCR;       /*strobe signal control register *//*8      */
3622         uint16_t reserved0[1]; /*A    */
3623         volatile MBDSR_t MBDSR; /*message buffer data size register *//*C  */
3624         volatile MBSSUTR_t MBSSUTR;     /*message buffer segment size and utilization register *//*E  */
3625         uint16_t reserved1[1]; /*10 */
3626         uint16_t reserved2[1]; /*12 */
3627         volatile POCR_t POCR;   /*Protocol operation control register *//*14 */
3628         volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
3629         volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
3630         volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
3631         volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
3632         volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
3633         volatile CHIERFR_t CHIERFR;     /*CHI error flag register *//*20 */
3634         volatile MBIVEC_t MBIVEC;       /*message buffer interrupt vector register *//*22 */
3635         volatile CASERCR_t CASERCR;     /*channel A status error counter register *//*24 */
3636         volatile CBSERCR_t CBSERCR;     /*channel B status error counter register *//*26 */
3637         volatile PSR0_t PSR0;   /*protocol status register 0 *//*28 */
3638         volatile PSR1_t PSR1;   /*protocol status register 1 *//*2A */
3639         volatile PSR2_t PSR2;   /*protocol status register 2 *//*2C */
3640         volatile PSR3_t PSR3;   /*protocol status register 3 *//*2E */
3641         volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
3642         volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
3643         volatile SLTCTAR_t SLTCTAR;     /*slot counter channel A register *//*34 */
3644         volatile SLTCTBR_t SLTCTBR;     /*slot counter channel B register *//*36 */
3645         volatile RTCORVR_t RTCORVR;     /*rate correction value register *//*38 */
3646         volatile OFCORVR_t OFCORVR;     /*offset correction value register *//*3A */
3647         volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
3648         volatile SYMATOR_t SYMATOR;     /*system memory acess time-out register *//*3E */
3649         volatile SFCNTR_t SFCNTR;       /*sync frame counter register *//*40 */
3650         volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
3651         volatile SFTCCSR_t SFTCCSR;     /*sync frame table configuration, control, status register *//*44 */
3652         volatile SFIDRFR_t SFIDRFR;     /*sync frame ID rejection filter register *//*46 */
3653         volatile SFIDAFVR_t SFIDAFVR;   /*sync frame ID acceptance filter value regiater *//*48 */
3654         volatile SFIDAFMR_t SFIDAFMR;   /*sync frame ID acceptance filter mask register *//*4A */
3655         volatile NMVR_t NMVR[6];        /*network management vector registers (12 bytes) *//*4C */
3656         volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
3657         volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
3658         volatile TI1CYSR_t TI1CYSR;     /*timer 1 cycle set register *//*5C */
3659         volatile T1MTOR_t T1MTOR;       /*timer 1 macrotick offset register *//*5E */
3660         volatile TI2CR0_t TI2CR0;       /*timer 2 configuration register 0 *//*60 */
3661         volatile TI2CR1_t TI2CR1;       /*timer 2 configuration register 1 *//*62 */
3662         volatile SSSR_t SSSR;   /*slot status selection register *//*64 */
3663         volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
3664         volatile SSR_t SSR[8];  /*slot status registers 0-7 *//*68 */
3665         volatile SSCR_t SSCR[4];        /*slot status counter registers 0-3 *//*78 */
3666         volatile MTSCFR_t MTSACFR;      /*mts a config register *//*80 */
3667         volatile MTSCFR_t MTSBCFR;      /*mts b config register *//*82 */
3668         volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
3669         volatile RFSR_t RFSR;   /*receive fifo selection register *//*86 */
3670         volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
3671         volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
3672         volatile RFARIR_t RFARIR;       /*receive fifo a read index register *//*8C */
3673         volatile RFBRIR_t RFBRIR;       /*receive fifo b read index register *//*8E */
3674         volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
3675         volatile RFMIAFMR_t RFMIAFMR;   /*receive fifo message ID acceptance filter mask register *//*92 */
3676         volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
3677         volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
3678         volatile RFRFCFR_t RFRFCFR;     /*receive fifo range filter configuration register *//*98 */
3679         volatile RFRFCTR_t RFRFCTR;     /*receive fifo range filter control register *//*9A */
3680         volatile LDTXSLAR_t LDTXSLAR;   /*last dynamic transmit slot channel A register *//*9C */
3681         volatile LDTXSLBR_t LDTXSLBR;   /*last dynamic transmit slot channel B register *//*9E */
3682         volatile PCR0_t PCR0;   /*protocol configuration register 0 *//*A0 */
3683         volatile PCR1_t PCR1;   /*protocol configuration register 1 *//*A2 */
3684         volatile PCR2_t PCR2;   /*protocol configuration register 2 *//*A4 */
3685         volatile PCR3_t PCR3;   /*protocol configuration register 3 *//*A6 */
3686         volatile PCR4_t PCR4;   /*protocol configuration register 4 *//*A8 */
3687         volatile PCR5_t PCR5;   /*protocol configuration register 5 *//*AA */
3688         volatile PCR6_t PCR6;   /*protocol configuration register 6 *//*AC */
3689         volatile PCR7_t PCR7;   /*protocol configuration register 7 *//*AE */
3690         volatile PCR8_t PCR8;   /*protocol configuration register 8 *//*B0 */
3691         volatile PCR9_t PCR9;   /*protocol configuration register 9 *//*B2 */
3692         volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
3693         volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
3694         volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
3695         volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
3696         volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
3697         volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
3698         volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
3699         volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
3700         volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
3701         volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
3702         volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
3703         volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
3704         volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
3705         volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
3706         volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
3707         volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
3708         volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
3709         volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
3710         volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
3711         volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
3712         volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
3713         uint16_t reserved3[17];
3714         volatile MSG_BUFF_CCS_t MBCCS[128];     /* message buffer configuration, control & status registers 0-31 *//*100 */
3715     } FR_tag_t;
3716
3717     typedef union uF_HEADER     /* frame header */
3718     {
3719         struct {
3720             uint16_t:5;
3721             uint16_t HDCRC:11; /* Header CRC */
3722               uint16_t:2;
3723             uint16_t CYCCNT:6; /* Cycle Count */
3724               uint16_t:1;
3725             uint16_t PLDLEN:7; /* Payload Length */
3726               uint16_t:1;
3727             uint16_t PPI:1;    /* Payload Preamble Indicator */
3728             uint16_t NUF:1;    /* Null Frame Indicator */
3729             uint16_t SYF:1;    /* Sync Frame Indicator */
3730             uint16_t SUF:1;    /* Startup Frame Indicator */
3731             uint16_t FID:11;   /* Frame ID */
3732         } B;
3733         uint16_t WORDS[3];
3734     } F_HEADER_t;
3735     typedef union uS_STSTUS     /* slot status */
3736     {
3737         struct {
3738             uint16_t VFB:1;    /* Valid Frame on channel B */
3739             uint16_t SYB:1;    /* Sync Frame Indicator channel B */
3740             uint16_t NFB:1;    /* Null Frame Indicator channel B */
3741             uint16_t SUB:1;    /* Startup Frame Indicator channel B */
3742             uint16_t SEB:1;    /* Syntax Error on channel B */
3743             uint16_t CEB:1;    /* Content Error on channel B */
3744             uint16_t BVB:1;    /* Boundary Violation on channel B */
3745             uint16_t CH:1;     /* Channel */
3746             uint16_t VFA:1;    /* Valid Frame on channel A */
3747             uint16_t SYA:1;    /* Sync Frame Indicator channel A */
3748             uint16_t NFA:1;    /* Null Frame Indicator channel A */
3749             uint16_t SUA:1;    /* Startup Frame Indicator channel A */
3750             uint16_t SEA:1;    /* Syntax Error on channel A */
3751             uint16_t CEA:1;    /* Content Error on channel A */
3752             uint16_t BVA:1;    /* Boundary Violation on channel A */
3753               uint16_t:1;
3754         } RX;
3755         struct {
3756             uint16_t VFB:1;    /* Valid Frame on channel B */
3757             uint16_t SYB:1;    /* Sync Frame Indicator channel B */
3758             uint16_t NFB:1;    /* Null Frame Indicator channel B */
3759             uint16_t SUB:1;    /* Startup Frame Indicator channel B */
3760             uint16_t SEB:1;    /* Syntax Error on channel B */
3761             uint16_t CEB:1;    /* Content Error on channel B */
3762             uint16_t BVB:1;    /* Boundary Violation on channel B */
3763             uint16_t TCB:1;    /* Tx Conflict on channel B */
3764             uint16_t VFA:1;    /* Valid Frame on channel A */
3765             uint16_t SYA:1;    /* Sync Frame Indicator channel A */
3766             uint16_t NFA:1;    /* Null Frame Indicator channel A */
3767             uint16_t SUA:1;    /* Startup Frame Indicator channel A */
3768             uint16_t SEA:1;    /* Syntax Error on channel A */
3769             uint16_t CEA:1;    /* Content Error on channel A */
3770             uint16_t BVA:1;    /* Boundary Violation on channel A */
3771             uint16_t TCA:1;    /* Tx Conflict on channel A */
3772         } TX;
3773         uint16_t R;
3774     } S_STATUS_t;
3775
3776     typedef struct uMB_HEADER   /* message buffer header */
3777     {
3778         F_HEADER_t FRAME_HEADER;
3779         uint16_t DATA_OFFSET;
3780         S_STATUS_t SLOT_STATUS;
3781     } MB_HEADER_t;
3782 /****************************************************************************/
3783 /*                     MODULE : MLB                                         */
3784 /****************************************************************************/
3785     struct MLB_tag {
3786
3787         union {                 /* MLB Module Configuration Register */
3788             uint32_t R;
3789             struct {
3790                 uint32_t MDIS:1;
3791                   uint32_t:15;
3792                 uint32_t MDATOBSE:1;
3793                 uint32_t MSIGOBS:1;
3794                 uint32_t MSLOTE:1;
3795                   uint32_t:2;
3796                 uint32_t MSVRQIE:1;
3797                 uint32_t MDATRQE:1;
3798                   uint32_t:2;
3799                 uint32_t MSVRQDL:3;
3800                 uint32_t MSVRQCIE:1;
3801                 uint32_t MIFSEL:1;
3802                 uint32_t MSBFEPOL:1;
3803                 uint32_t MDBFEPOL:1;
3804             } B;
3805         } MCR;
3806
3807         union {                 /* MLB Blank Register */
3808             uint32_t R;
3809             struct {
3810                 uint32_t:31;
3811                 uint32_t BLANK:1;
3812             } B;
3813         } MBR;
3814
3815         union {                 /* MLB Status Register */
3816             uint32_t R;
3817             struct {
3818                 uint32_t:29;
3819                 uint32_t MDATRQS:1;
3820                 uint32_t MSYSS:1;
3821                 uint32_t MSVRQS:1;
3822             } B;
3823         } MSR;
3824
3825         union {                 /* RX Control Channel Address Register */
3826             uint32_t R;
3827             struct {
3828                 uint32_t RXCCHA_ACEN:1;
3829                   uint32_t:25;
3830                 uint32_t RXCCHA:5;
3831                   uint32_t:1;
3832             } B;
3833         } RXCCHAR;
3834
3835         union {                 /* RX Async Channel Address Register */
3836             uint32_t R;
3837             struct {
3838                 uint32_t RXACHA_ACEN:1;
3839                   uint32_t:25;
3840                 uint32_t RXACHA:5;
3841                   uint32_t:1;
3842             } B;
3843         } RXACHAR;
3844
3845         union {                 /* TX Control Channel Address Register */
3846             uint32_t R;
3847             struct {
3848                 uint32_t TXCCHA_ACEN:1;
3849                   uint32_t:25;
3850                 uint32_t TXCCHA:5;
3851                   uint32_t:1;
3852             } B;
3853         } TXCCHAR;
3854
3855         union {                 /* TX Async Channel Address Register */
3856             uint32_t R;
3857             struct {
3858                 uint32_t TXACHA_ACEN:1;
3859                   uint32_t:25;
3860                 uint32_t TXACHA:5;
3861                   uint32_t:1;
3862             } B;
3863         } TXACHAR;
3864
3865         union {                 /* TX Sync Channel Address Register */
3866             uint32_t R;
3867             struct {
3868                 uint32_t TXSCHA_ACEN:1;
3869                   uint32_t:25;
3870                 uint32_t TXSCHA:5;
3871                   uint32_t:1;
3872             } B;
3873         } TXSCHAR;
3874
3875         union {                 /* TX Sync Channel Address Mask Register */
3876             uint32_t R;
3877             struct {
3878                 uint32_t:26;
3879                 uint32_t TXSCHAM:5;
3880                   uint32_t:1;
3881             } B;
3882         } TXSCHAMR;
3883
3884         union {                 /* Clock Adjust Control Register */
3885             uint32_t R;
3886             struct {
3887                 uint32_t:16;
3888                 uint32_t PDLY:16;
3889             } B;
3890         } CLKACR;
3891
3892         union {                 /* RX Isochronous Channel Address Register */
3893             uint32_t R;
3894             struct {
3895                 uint32_t RXICHA_ACEN:1;
3896                   uint32_t:25;
3897                 uint32_t RXICHA:5;
3898                   uint32_t:1;
3899             } B;
3900         } RXICHAR;
3901
3902         union {                 /* TX Isochronous Channel Address Register */
3903             uint32_t R;
3904             struct {
3905                 uint32_t TXICHA_ACEN:1;
3906                   uint32_t:25;
3907                 uint32_t TXICHA:5;
3908                   uint32_t:1;
3909             } B;
3910         } TXICHAR;
3911
3912     };
3913
3914 /* Define memories */
3915
3916 #define SRAM_START   0x40000000UL
3917 #define SRAM_SIZE       0x14000UL
3918 #define SRAM_END     0x40013FFFUL
3919
3920 #define FLASH_START         0x0UL
3921 #define FLASH_SIZE     0x180000UL
3922 #define FLASH_END      0x17FFFFUL
3923
3924 /* Define instances of modules */
3925 #define SEMA4     (*(volatile struct SEMA4_tag *)     0xFFF10000UL)
3926 #define MPU       (*(volatile struct MPU_tag *)       0xFFF14000UL)
3927 #define MCM       (*(volatile struct MCM_tag *)       0xFFF40000UL)
3928 #define EDMA      (*(volatile struct EDMA_tag *)      0xFFF44000UL)
3929 #define INTC      (*(volatile struct INTC_tag *)      0xFFF48000UL)
3930 #define EQADC     (*(volatile struct EQADC_tag *)     0xFFF80000UL)
3931 #define MLB       (*(volatile struct MLB_tag *)       0xFFF84000UL)
3932 #define I2C       (*(volatile struct I2C_tag *)       0xFFF88000UL)
3933 #define DSPI_A    (*(volatile struct DSPI_tag *)      0xFFF90000UL)
3934 #define DSPI_B    (*(volatile struct DSPI_tag *)      0xFFF94000UL)
3935 #define DSPI_C    (*(volatile struct DSPI_tag *)      0xFFF98000UL)
3936 #define DSPI_D    (*(volatile struct DSPI_tag *)      0xFFF9C000UL)
3937 #define ESCI_A    (*(volatile struct ESCI_tag *)      0xFFFA0000UL)
3938 #define ESCI_B    (*(volatile struct ESCI_tag *)      0xFFFA4000UL)
3939 #define ESCI_C    (*(volatile struct ESCI_tag *)      0xFFFA8000UL)
3940 #define ESCI_D    (*(volatile struct ESCI_tag *)      0xFFFAC000UL)
3941 #define ESCI_E    (*(volatile struct ESCI_tag *)      0xFFFB0000UL)
3942 #define ESCI_F    (*(volatile struct ESCI_tag *)      0xFFFB4000UL)
3943 #define ESCI_G    (*(volatile struct ESCI_tag *)      0xFFFB8000UL)
3944 #define ESCI_H    (*(volatile struct ESCI_tag *)      0xFFFBC000UL)
3945 #define CAN_A     (*(volatile struct FLEXCAN_tag *)   0xFFFC0000UL)
3946 #define CAN_B     (*(volatile struct FLEXCAN_tag *)   0xFFFC4000UL)
3947 #define CAN_C     (*(volatile struct FLEXCAN_tag *)   0xFFFC8000UL)
3948 #define CAN_D     (*(volatile struct FLEXCAN_tag *)   0xFFFCC000UL)
3949 #define CAN_E     (*(volatile struct FLEXCAN_tag *)   0xFFFD0000UL)
3950 #define CAN_F     (*(volatile struct FLEXCAN_tag *)   0xFFFD4000UL)
3951 #define FR        (*(volatile struct FR_tag *)        0xFFFD8000UL)
3952 #define DMAMUX    (*(volatile struct DMAMUX_tag *)    0xFFFDC000UL)
3953 #define PIT       (*(volatile struct PIT_tag *)       0xFFFE0000UL)
3954 #define EMIOS     (*(volatile struct EMIOS_tag *)     0xFFFE4000UL)
3955 #define SIU       (*(volatile struct SIU_tag *)       0xFFFE8000UL)
3956 #define CRP       (*(volatile struct CRP_tag *)       0xFFFEC000UL)
3957 #define FMPLL     (*(volatile struct FMPLL_tag *)     0xFFFF0000UL)
3958 #define EBI       (*(volatile struct EBI_tag *)       0xFFFF4000UL)
3959 #define FLASH     (*(volatile struct FLASH_tag *)     0xFFFF8000UL)
3960
3961 #ifdef __MWERKS__
3962 #pragma pop
3963 #endif
3964
3965 #ifdef  __cplusplus
3966 }
3967 #endif
3968 #endif /* ASM */
3969 #endif                          /* ifdef _MPC5510_H */
3970 /*********************************************************************
3971  *
3972  * Copyright:
3973  *  Freescale Semiconductor, INC. All Rights Reserved.
3974  *  You are hereby granted a copyright license to use, modify, and
3975  *  distribute the SOFTWARE so long as this entire notice is
3976  *  retained without alteration in any modified and/or redistributed
3977  *  versions, and that such modified versions are clearly identified
3978  *  as such. No licenses are granted by implication, estoppel or
3979  *  otherwise under any patents or trademarks of Freescale
3980  *  Semiconductor, Inc. This software is provided on an "AS IS"
3981  *  basis and without warranty.
3982  *
3983  *  To the maximum extent permitted by applicable law, Freescale
3984  *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
3985  *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
3986  *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
3987  *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
3988  *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
3989  *
3990  *  To the maximum extent permitted by applicable law, IN NO EVENT
3991  *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
3992  *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
3993  *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
3994  *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
3995  *
3996  *  Freescale Semiconductor assumes no responsibility for the
3997  *  maintenance and support of this software
3998  *
3999  ********************************************************************/