include/bsp/smsc9218i.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief SMSC - LAN9218i
0009  */
0010
0011 /*
0012  * Copyright (C) 2009, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp.h>
0037
0038 /**
0039  * @name Memory Map
0040  * @{
0041  */
0042
0043 typedef struct {
0044   uint32_t rx_fifo_data;
0045   uint32_t rx_fifo_data_aliases [7];
0046   uint32_t tx_fifo_data;
0047   uint32_t tx_fifo_data_aliases [7];
0048   uint32_t rx_fifo_status;
0049   uint32_t rx_fifo_status_peek;
0050   uint32_t tx_fifo_status;
0051   uint32_t tx_fifo_status_peek;
0052   uint32_t id_rev;
0053   uint32_t irq_cfg;
0054   uint32_t int_sts;
0055   uint32_t int_en;
0056   uint32_t reserved_0;
0057   uint32_t byte_test;
0058   uint32_t fifo_int;
0059   uint32_t rx_cfg;
0060   uint32_t tx_cfg;
0061   uint32_t hw_cfg;
0062   uint32_t rx_dp_ctl;
0063   uint32_t rx_fifo_inf;
0064   uint32_t tx_fifo_inf;
0065   uint32_t pmt_ctrl;
0066   uint32_t gpio_cfg;
0067   uint32_t gpt_cfg;
0068   uint32_t gpt_cnt;
0069   uint32_t reserved_1;
0070   uint32_t word_swap;
0071   uint32_t free_run;
0072   uint32_t rx_drop;
0073   uint32_t mac_csr_cmd;
0074   uint32_t mac_csr_data;
0075   uint32_t afc_cfg;
0076   uint32_t e2p_cmd;
0077   uint32_t e2p_data;
0078 } smsc9218i_registers;
0079
0080 /*
0081  * SMSC9218 registers are accessed little-endian (address 0x3fff8000, A22 used
0082  * as END_SEL).
0083  */
0084 #ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
0085   volatile smsc9218i_registers *const smsc9218i =
0086     (volatile smsc9218i_registers *) 0x3fff8000;
0087   volatile smsc9218i_registers *const smsc9218i_dma =
0088     (volatile smsc9218i_registers *) 0x3fff8200;
0089 #else
0090   volatile smsc9218i_registers *const smsc9218i =
0091     (volatile smsc9218i_registers *) 0x3fff8000;
0092   volatile smsc9218i_registers *const smsc9218i_dma =
0093     (volatile smsc9218i_registers *) 0x3fff8000;
0094 #endif
0095
0096 /** @} */
0097
0098 #ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
0099   #define SMSC9218I_BIT_POS(pos) (pos)
0100 #else
0101   #define SMSC9218I_BIT_POS(pos) \
0102     ((pos) > 15 ? \
0103       ((pos) > 23 ? (pos) - 24 : (pos) - 8) \
0104         : ((pos) > 7 ? (pos) + 8 : (pos) + 24))
0105 #endif
0106
0107 #define SMSC9218I_FLAG(pos) \
0108   (1U << SMSC9218I_BIT_POS(pos))
0109
0110 #define SMSC9218I_FIELD_8(val, pos) \
0111   (((val) & 0xff) << SMSC9218I_BIT_POS(pos))
0112
0113 #define SMSC9218I_GET_FIELD_8(reg, pos) \
0114   (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff)
0115
0116 #define SMSC9218I_FIELD_16(val, pos) \
0117   (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \
0118     | SMSC9218I_FIELD_8((val), pos))
0119
0120 #define SMSC9218I_GET_FIELD_16(reg, pos) \
0121   ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \
0122     | SMSC9218I_GET_FIELD_8(reg, pos))
0123
0124 #ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
0125   #define SMSC9218I_SWAP(val) (val)
0126 #else
0127   #define SMSC9218I_SWAP(val) \
0128     ((((val) >> 24) & 0xff) \
0129       | ((((val) >> 16) & 0xff) << 8) \
0130       | ((((val) >> 8) & 0xff) << 16) \
0131       | (((val) & 0xff) << 24))
0132 #endif
0133
0134 /**
0135  * @name Receive Status
0136  * @{
0137  */
0138
0139 #define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30)
0140 #define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff)
0141 #define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15)
0142 #define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13)
0143 #define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12)
0144 #define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11)
0145 #define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10)
0146 #define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7)
0147 #define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6)
0148 #define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5)
0149 #define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4)
0150 #define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3)
0151 #define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2)
0152 #define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1)
0153
0154 /** @} */
0155
0156 /**
0157  * @name Transmit Status
0158  * @{
0159  */
0160
0161 #define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
0162 #define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15)
0163 #define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11)
0164 #define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10)
0165 #define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9)
0166 #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8)
0167 #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2)
0168 #define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0)
0169
0170 /** @} */
0171
0172 /**
0173  * @name Transmit Command A
0174  * @{
0175  */
0176
0177 #define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31)
0178 #define SMSC9218I_TX_A_END_ALIGN_4 0
0179 #define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24)
0180 #define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25)
0181 #define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16)
0182 #define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13)
0183 #define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12)
0184 #define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
0185
0186 /** @} */
0187
0188 /**
0189  * @name Transmit Command B
0190  * @{
0191  */
0192
0193 #define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16)
0194 #define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
0195 #define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13)
0196 #define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12)
0197 #define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
0198
0199 /** @} */
0200
0201 /**
0202  * @name Chip ID and Revision
0203  * @{
0204  */
0205
0206 #define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16)
0207 #define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0)
0208 #define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U
0209 #define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU
0210
0211 /** @} */
0212
0213 /**
0214  * @name Interrupt Configuration
0215  * @{
0216  */
0217
0218 #define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24)
0219 #define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24)
0220 #define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14)
0221 #define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13)
0222 #define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12)
0223 #define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8)
0224 #define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4)
0225 #define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0)
0226
0227 /** @} */
0228
0229 /**
0230  * @name Interrupt Enable and Status
0231  * @{
0232  */
0233
0234 #define SMSC9218I_INT_SW SMSC9218I_FLAG(31)
0235 #define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25)
0236 #define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24)
0237 #define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23)
0238 #define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21)
0239 #define SMSC9218I_INT_RXD SMSC9218I_FLAG(20)
0240 #define SMSC9218I_INT_GPT SMSC9218I_FLAG(19)
0241 #define SMSC9218I_INT_PHY SMSC9218I_FLAG(18)
0242 #define SMSC9218I_INT_PME SMSC9218I_FLAG(17)
0243 #define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16)
0244 #define SMSC9218I_INT_RWT SMSC9218I_FLAG(15)
0245 #define SMSC9218I_INT_RXE SMSC9218I_FLAG(14)
0246 #define SMSC9218I_INT_TXE SMSC9218I_FLAG(13)
0247 #define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10)
0248 #define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9)
0249 #define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8)
0250 #define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7)
0251 #define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4)
0252 #define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3)
0253 #define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2)
0254 #define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1)
0255 #define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0)
0256
0257 /** @} */
0258
0259 /**
0260  * @name Byte Order Testing
0261  * @{
0262  */
0263
0264 #define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U)
0265
0266 /** @} */
0267
0268 /**
0269  * @name FIFO Level Interrupts
0270  * @{
0271  */
0272
0273 #define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24)
0274 #define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24)
0275 #define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16)
0276 #define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16)
0277 #define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0)
0278 #define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0)
0279
0280 /** @} */
0281
0282 /**
0283  * @name Receive Configuration
0284  * @{
0285  */
0286
0287 #define SMSC9218I_RX_CFG_END_ALIGN_4 0
0288 #define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30)
0289 #define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31)
0290 #define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24)
0291 #define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24)
0292 #define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15)
0293 #define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8)
0294 #define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8)
0295
0296 /** @} */
0297
0298 /**
0299  * @name Transmit Configuration
0300  * @{
0301  */
0302
0303 #define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15)
0304 #define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14)
0305 #define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2)
0306 #define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1)
0307 #define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0)
0308
0309 /** @} */
0310
0311 /**
0312  * @name Hardware Configuration
0313  * @{
0314  */
0315
0316 #define SMSC9218I_HW_CFG_LED_3 SMSC9218I_FLAG(30)
0317 #define SMSC9218I_HW_CFG_LED_2 SMSC9218I_FLAG(29)
0318 #define SMSC9218I_HW_CFG_LED_1 SMSC9218I_FLAG(28)
0319 #define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24)
0320 #define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20)
0321 #define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16)
0322 #define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16)
0323 #define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2)
0324 #define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1)
0325 #define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0)
0326
0327 /** @} */
0328
0329 /**
0330  * @name Receive Datapath Control
0331  * @{
0332  */
0333
0334 #define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31)
0335
0336 /** @} */
0337
0338 /**
0339  * @name Receive FIFO Information
0340  * @{
0341  */
0342
0343 #define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
0344 #define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0)
0345
0346 /** @} */
0347
0348 /**
0349  * @name Transmit FIFO Information
0350  * @{
0351  */
0352
0353 #define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
0354 #define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0)
0355
0356 /** @} */
0357
0358 /**
0359  * @name Power Management Control
0360  * @{
0361  */
0362
0363 #define SMSC9218I_PMT_CTRL_PM_MODE_D0 0
0364 #define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12)
0365 #define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13)
0366 #define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10)
0367 #define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9)
0368 #define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8)
0369 #define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6)
0370 #define SMSC9218I_PMT_CTRL_WUPS_NO 0
0371 #define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4)
0372 #define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5)
0373 #define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3)
0374 #define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2)
0375 #define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1)
0376 #define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0)
0377
0378 /** @} */
0379
0380 /**
0381  * @name General Purpose IO Configuration
0382  * @{
0383  */
0384
0385 #define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30)
0386 #define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29)
0387 #define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28)
0388 #define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26)
0389 #define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25)
0390 #define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24)
0391 #define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18)
0392 #define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17)
0393 #define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16)
0394 #define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10)
0395 #define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9)
0396 #define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8)
0397 #define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4)
0398 #define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3)
0399 #define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0)
0400 #define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2)
0401 #define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1)
0402
0403 /** @} */
0404
0405 /**
0406  * @name General Purpose Timer Configuration
0407  * @{
0408  */
0409
0410 #define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29)
0411 #define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0)
0412 #define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0)
0413
0414 /** @} */
0415
0416 /**
0417  * @name General Purpose Timer Count
0418  * @{
0419  */
0420
0421 #define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0)
0422
0423 /** @} */
0424
0425 /**
0426  * @name Word Swap
0427  * @{
0428  */
0429
0430 #define SMSC9218I_ENDIAN_BIG 0xffffffffU
0431
0432 /** @} */
0433
0434 /**
0435  * @name Free Run Counter
0436  * @{
0437  */
0438
0439 #define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg)
0440
0441 /** @} */
0442
0443 /**
0444  * @name Receiver Dropped Frames Counter
0445  * @{
0446  */
0447
0448 #define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg)
0449
0450 /** @} */
0451
0452 /**
0453  * @name EEPROM Command Register
0454  * @{
0455  */
0456
0457 #define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31)
0458
0459 /** @} */
0460
0461 /**
0462  * @name MAC Control and Status Synchronizer Command
0463  * @{
0464  */
0465
0466 #define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31)
0467 #define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30)
0468 #define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0)
0469 #define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0)
0470
0471 /** @} */
0472
0473 /**
0474  * @name MAC Control Register
0475  * @{
0476  */
0477
0478 #define SMSC9218I_MAC_CR 0x00000001U
0479 #define SMSC9218I_MAC_CR_RXALL 0x80000000U
0480 #define SMSC9218I_MAC_CR_HBDIS 0x10000000U
0481 #define SMSC9218I_MAC_CR_RCVOWN 0x00800000U
0482 #define SMSC9218I_MAC_CR_LOOPBK 0x00200000U
0483 #define SMSC9218I_MAC_CR_FDPX 0x00100000U
0484 #define SMSC9218I_MAC_CR_MCPAS 0x00080000U
0485 #define SMSC9218I_MAC_CR_PRMS 0x00040000U
0486 #define SMSC9218I_MAC_CR_INVFILT 0x00020000U
0487 #define SMSC9218I_MAC_CR_PASSBAD 0x00010000U
0488 #define SMSC9218I_MAC_CR_HFILT 0x00008000U
0489 #define SMSC9218I_MAC_CR_HPFILT 0x00002000U
0490 #define SMSC9218I_MAC_CR_LCOLL 0x00001000U
0491 #define SMSC9218I_MAC_CR_BCAST 0x00000800U
0492 #define SMSC9218I_MAC_CR_DISRTY 0x00000400U
0493 #define SMSC9218I_MAC_CR_PADSTR 0x00000100U
0494 #define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U
0495 #define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U
0496 #define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U
0497 #define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U
0498 #define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U
0499 #define SMSC9218I_MAC_CR_DFCHK 0x00000020U
0500 #define SMSC9218I_MAC_CR_TXEN 0x00000008U
0501 #define SMSC9218I_MAC_CR_RXEN 0x00000004U
0502
0503 /** @} */
0504
0505 /**
0506  * @name MAC Address High
0507  * @{
0508  */
0509
0510 #define SMSC9218I_MAC_ADDRH 0x00000002U
0511 #define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU
0512
0513 /** @} */
0514
0515 /**
0516  * @name MAC Address Low
0517  * @{
0518  */
0519
0520 #define SMSC9218I_MAC_ADDRL 0x00000003U
0521 #define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU
0522
0523 /** @} */
0524
0525 /**
0526  * @name Multicast Hash Table High
0527  * @{
0528  */
0529
0530 #define SMSC9218I_MAC_HASHH 0x00000004U
0531 #define SMSC9218I_MAC_HASHH_MASK 0xffffffffU
0532
0533 /** @} */
0534
0535 /**
0536  * @name Multicast Hash Table Low
0537  * @{
0538  */
0539
0540 #define SMSC9218I_MAC_HASHL 0x00000005U
0541 #define SMSC9218I_MAC_HASHL_MASK 0xffffffffU
0542
0543 /** @} */
0544
0545 /**
0546  * @name MII Access
0547  * @{
0548  */
0549
0550 #define SMSC9218I_MAC_MII_ACC 0x00000006U
0551 #define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11)
0552 #define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1)
0553 #define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0)
0554 #define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6)
0555
0556 /** @} */
0557
0558 /**
0559  * @name MII Data
0560  * @{
0561  */
0562
0563 #define SMSC9218I_MAC_MII_DATA 0x00000007U
0564
0565 /** @} */
0566
0567 /**
0568  * @name Flow Control
0569  * @{
0570  */
0571
0572 #define SMSC9218I_MAC_FLOW 0x00000008U
0573 #define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U
0574 #define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U
0575 #define SMSC9218I_MAC_FLOW_FCEN 0x00000002U
0576 #define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U
0577
0578 /** @} */
0579
0580 /**
0581  * @name VLAN1 Tag
0582  * @{
0583  */
0584
0585 #define SMSC9218I_MAC_VLAN1 0x00000009U
0586
0587 /** @} */
0588
0589 /**
0590  * @name VLAN2 Tag
0591  * @{
0592  */
0593
0594 #define SMSC9218I_MAC_VLAN2 0x0000000aU
0595
0596 /** @} */
0597
0598 /**
0599  * @name Wake-up Frame Filter
0600  * @{
0601  */
0602
0603 #define SMSC9218I_MAC_WUFF 0x0000000bU
0604
0605 /** @} */
0606
0607 /**
0608  * @name Wake-up Control and Status
0609  * @{
0610  */
0611
0612 #define SMSC9218I_MAC_WUCSR 0x0000000cU
0613 #define SMSC9218I_MAC_WUCSR_GUE 0x00000200U
0614 #define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U
0615 #define SMSC9218I_MAC_WUCSR_MPR 0x00000020U
0616 #define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U
0617 #define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U
0618
0619 /** @} */
0620
0621 /**
0622  * @name PHY Identifier 1
0623  * @{
0624  */
0625
0626 #define SMSC9218I_PHY_ID1_LAN9118 0x7
0627
0628 /** @} */
0629
0630 /**
0631  * @name PHY Identifier 2
0632  * @{
0633  */
0634
0635 #define SMSC9218I_PHY_ID2_LAN9218 0xc0c3
0636
0637 /** @} */
0638
0639 /**
0640  * @name Mode Control and Status
0641  * @{
0642  */
0643
0644 #define SMSC9218I_PHY_MCSR 0x00000011U
0645 #define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U
0646 #define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U
0647
0648 /** @} */
0649
0650 /**
0651  * @name Special Modes
0652  * @{
0653  */
0654
0655 #define SMSC9218I_PHY_SPMODES 0x00000012U
0656
0657 /** @} */
0658
0659 /**
0660  * @name Special Control and Status Indications
0661  * @{
0662  */
0663
0664 #define SMSC9218I_PHY_CSIR 0x0000001bU
0665 #define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U
0666 #define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U
0667 #define SMSC9218I_PHY_CSIR_XPOL 0x00000010U
0668
0669 /** @} */
0670
0671 /**
0672  * @name Interrupt Source Flag
0673  * @{
0674  */
0675
0676 #define SMSC9218I_PHY_ISR 0x0000001dU
0677 #define SMSC9218I_PHY_ISR_INT7 0x00000080U
0678 #define SMSC9218I_PHY_ISR_INT6 0x00000040U
0679 #define SMSC9218I_PHY_ISR_INT5 0x00000020U
0680 #define SMSC9218I_PHY_ISR_INT4 0x00000010U
0681 #define SMSC9218I_PHY_ISR_INT3 0x00000008U
0682 #define SMSC9218I_PHY_ISR_INT2 0x00000004U
0683 #define SMSC9218I_PHY_ISR_INT1 0x00000002U
0684
0685 /** @} */
0686
0687 /**
0688  * @name Interrupt Mask
0689  * @{
0690  */
0691
0692 #define SMSC9218I_PHY_IMR 0x0000001eU
0693 #define SMSC9218I_PHY_IMR_INT7 0x00000080U
0694 #define SMSC9218I_PHY_IMR_INT6 0x00000040U
0695 #define SMSC9218I_PHY_IMR_INT5 0x00000020U
0696 #define SMSC9218I_PHY_IMR_INT4 0x00000010U
0697 #define SMSC9218I_PHY_IMR_INT3 0x00000008U
0698 #define SMSC9218I_PHY_IMR_INT2 0x00000004U
0699 #define SMSC9218I_PHY_IMR_INT1 0x00000002U
0700
0701 /** @} */
0702
0703 /**
0704  * @name PHY Special Control and Status
0705  * @{
0706  */
0707
0708 #define SMSC9218I_PHY_PHYSCSR 0x0000001fU
0709 #define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U
0710 #define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U
0711 #define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU
0712 #define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U
0713 #define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U
0714 #define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U
0715 #define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U
0716
0717 /** @} */