include/bsp/irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCMPC55XX
0007  *
0008  * @brief IRQ
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_POWERPC_IRQ_H
0037 #define LIBBSP_POWERPC_IRQ_H
0038
0039 #include <rtems/irq-extension.h>
0040 #include <rtems/irq.h>
0041
0042 #include <bspopts.h>
0043
0044 #ifdef __cplusplus
0045 extern "C" {
0046 #endif /* __cplusplus */
0047
0048 /*
0049  * Interrupt numbers
0050  */
0051
0052 #define MPC55XX_IRQ_INVALID 0x10000U
0053 #define MPC55XX_IRQ_MIN 0U
0054
0055 /* Software interrupts */
0056 #define MPC55XX_IRQ_SOFTWARE_MIN 0U
0057 #define MPC55XX_IRQ_SOFTWARE_MAX 7U
0058 #define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
0059 #define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
0060 #define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
0061
0062 #if MPC55XX_CHIP_FAMILY == 551
0063   #define MPC55XX_IRQ_MAX 293U
0064
0065   /* eDMA */
0066   #define MPC55XX_IRQ_EDMA_ERROR(group) \
0067     ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
0068   #define MPC55XX_IRQ_EDMA(ch) \
0069     ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
0070
0071   /* I2C */
0072   #define MPC55XX_IRQ_I2C(mod) \
0073     ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
0074
0075   /* SIU external interrupts */
0076   #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
0077   #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
0078   #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
0079   #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
0080   #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
0081
0082   /* PIT */
0083   #define MPC55XX_IRQ_RTI 148U
0084   #define MPC55XX_IRQ_PIT(timer) (148U + (timer))
0085
0086   /* eTPU */
0087   #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
0088
0089   /* DSPI */
0090   #define MPC55XX_IRQ_DSPI_BASE(mod) \
0091     ((mod) == 0 ? 117U : \
0092       ((mod) == 1 ? 122U : \
0093         ((mod) == 2 ? 274U : \
0094           ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
0095
0096   /* eMIOS */
0097   #define MPC55XX_IRQ_EMIOS(ch) \
0098     ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
0099
0100   /* eQADC */
0101   #define MPC55XX_IRQ_EQADC_BASE(mod) \
0102     ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
0103
0104   /* eSCI */
0105   #define MPC55XX_IRQ_ESCI(mod) \
0106     ((mod) == 0 ? 113U : \
0107       ((mod) == 1 ? 114U : \
0108         ((mod) == 2 ? 115U : \
0109           ((mod) == 3 ? 116U : \
0110             ((mod) == 4 ? 270U : \
0111               ((mod) == 5 ? 271U : \
0112                 ((mod) == 6 ? 272U : \
0113                   ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
0114
0115   /* FlexCAN */
0116   #define MPC55XX_IRQ_CAN_BASE(mod) \
0117     ((mod) == 0 ? 127U : \
0118       ((mod) == 1 ? 157U : \
0119         ((mod) == 2 ? 178U : \
0120           ((mod) == 3 ? 199U : \
0121             ((mod) == 4 ? 220U : \
0122               ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
0123
0124   /* FlexRay */
0125   #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
0126     ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
0127 #elif MPC55XX_CHIP_FAMILY == 564
0128   #define MPC55XX_IRQ_MAX 255U
0129
0130   /* eDMA */
0131   #define MPC55XX_IRQ_EDMA_ERROR(group) \
0132     ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
0133   #define MPC55XX_IRQ_EDMA(ch) \
0134     ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
0135
0136   /* SWT */
0137   #define MPC55XX_IRQ_SWT_0 28U
0138   #define MPC55XX_IRQ_SWT_1 29U
0139
0140   /* STM */
0141   #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
0142
0143   /* ECSM */
0144   #define MPC55XX_IRQ_ECSM_FAS 9U
0145   #define MPC55XX_IRQ_ECSM_NCE 35U
0146   #define MPC55XX_IRQ_ECSM_COR 36U
0147
0148   /* MC */
0149   #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
0150   #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
0151   #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
0152   #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
0153   #define MPC55XX_IRQ_MC_RGM_FRAE 56U
0154
0155   /* XOSC */
0156   #define MPC55XX_IRQ_XOSC 57U
0157
0158   /* PIT */
0159   #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
0160     ((ch) == 3 ? 127U : ((ch) + 59U))
0161
0162   /* SIU external interrupts */
0163   #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
0164   #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
0165   #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
0166   #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
0167
0168   /* ADC */
0169   #define MPC55XX_IRQ_ADC_BASE(mod) \
0170     ((mod) == 0 ? 62U : \
0171       ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
0172
0173   /* DSPI */
0174   #define MPC55XX_IRQ_DSPI_BASE(mod) \
0175     ((mod) == 0 ? 74U : \
0176       ((mod) == 1 ? 94U : \
0177         ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
0178
0179   /* FlexCAN */
0180   #define MPC55XX_IRQ_CAN_BASE(mod) \
0181     ((mod) == 0 ? 65U : \
0182       ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
0183
0184   /* FlexPWM */
0185   #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
0186     ((mod) == 0 ? 179U : \
0187       ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
0188
0189   /* FlexRay */
0190   #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
0191     ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
0192
0193   /* LINFlexD */
0194   #define MPC55XX_IRQ_LINFLEX_BASE(mod) \
0195     ((mod) == 0 ? 79U : \
0196       ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
0197
0198   /* eTimer */
0199   #define MPC55XX_IRQ_ETIMER_BASE(mod) \
0200     ((mod) == 0 ? 157U : \
0201       ((mod) == 1 ? 168U : \
0202         ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
0203
0204   /* CTU */
0205   #define MPC55XX_IRQ_CTU_MRS 193U
0206   #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
0207   #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
0208   #define MPC55XX_IRQ_CTU_ADC 206U
0209   #define MPC55XX_IRQ_CTU_ERR 207U
0210
0211   /* SEMA */
0212   #define MPC55XX_IRQ_SEMA_0 247U
0213   #define MPC55XX_IRQ_SEMA_1 248U
0214
0215   /* FCCU */
0216   #define MPC55XX_IRQ_FCCU_ALRM 250U
0217   #define MPC55XX_IRQ_FCCU_CFG_TO 251U
0218   #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
0219   #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
0220
0221   /* PMU */
0222   #define MPC55XX_IRQ_PMU 254U
0223
0224   /* SWG */
0225   #define MPC55XX_IRQ_SWG 255U
0226 #elif MPC55XX_CHIP_FAMILY == 566
0227   #define MPC55XX_IRQ_MAX 315U
0228
0229   /* eDMA */
0230   #define MPC55XX_IRQ_EDMA_ERROR(group) \
0231     ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
0232   #define MPC55XX_IRQ_EDMA(ch) \
0233     ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
0234
0235   /* PIT */
0236   #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
0237     ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID)
0238
0239   /* SIU external interrupts */
0240   #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
0241   #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
0242   #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
0243   #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
0244
0245   /* eMIOS */
0246   #define MPC55XX_IRQ_EMIOS(ch) \
0247     ((unsigned) (ch) < 24U ? 58U + (ch) : \
0248       ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID))
0249
0250   /* eSCI */
0251   #define MPC55XX_IRQ_ESCI(mod) \
0252     ((unsigned) (mod) < 4U ? 113U + (mod) : \
0253       ((unsigned) (mod) < 8U ? 270U + (mod) : \
0254         ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID)))
0255 #else
0256   #if MPC55XX_CHIP_FAMILY == 555
0257     #define MPC55XX_IRQ_MAX 307U
0258   #elif MPC55XX_CHIP_FAMILY == 556
0259     #define MPC55XX_IRQ_MAX 360U
0260   #elif MPC55XX_CHIP_FAMILY == 567
0261     #define MPC55XX_IRQ_MAX 479U
0262   #else
0263     #error "unsupported chip type"
0264   #endif
0265
0266   /* eDMA */
0267   #define MPC55XX_IRQ_EDMA_ERROR(group) \
0268     ((group) == 0 ? 10U : \
0269       ((group) == 1 ? 210U : \
0270         ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
0271   #define MPC55XX_IRQ_EDMA(ch) \
0272     ((unsigned) (ch) < 32U ? 11U + (ch) : \
0273       ((unsigned) (ch) < 64U ? 179U + (ch) : \
0274         ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
0275
0276   /* I2C */
0277   #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
0278
0279   /* SIU external interrupts */
0280   #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
0281   #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
0282   #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
0283   #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
0284   #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
0285
0286   /* PIT */
0287   #define MPC55XX_IRQ_RTI 305U
0288   #define MPC55XX_IRQ_PIT(ch) (301U + (ch))
0289
0290   /* eTPU */
0291   #define MPC55XX_IRQ_ETPU_BASE(mod) \
0292     ((mod) == 0 ? 67U : \
0293       ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
0294
0295   /* DSPI */
0296   #define MPC55XX_IRQ_DSPI_BASE(mod) \
0297     ((mod) == 0 ? 275U : \
0298       ((mod) == 1 ? 131U : \
0299         ((mod) == 2 ? 136U : \
0300           ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
0301
0302   /* eMIOS */
0303   #define MPC55XX_IRQ_EMIOS(ch) \
0304     ((unsigned) (ch) < 16U ? 51U + (ch) : \
0305       ((unsigned) (ch) < 24U ? 186U + (ch) : \
0306         ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
0307
0308   /* eQADC */
0309   #define MPC55XX_IRQ_EQADC_BASE(mod) \
0310     ((mod) == 0 ? 100U : \
0311       ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
0312
0313   /* eSCI */
0314   #define MPC55XX_IRQ_ESCI(mod) \
0315     ((mod) == 0 ? 146U : \
0316       ((mod) == 1 ? 149U : \
0317         ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
0318
0319   /* FlexCAN */
0320   #define MPC55XX_IRQ_CAN_BASE(mod) \
0321     ((mod) == 0 ? 152U : \
0322       ((mod) == 1 ? 280U : \
0323         ((mod) == 2 ? 173U : \
0324           ((mod) == 3 ? 308U : \
0325             ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
0326
0327   /* FlexRay */
0328   #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
0329     ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
0330 #endif
0331
0332 #define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
0333
0334 /* ADC */
0335 #define MPC55XX_IRQ_ADC_EOC(mod) \
0336   (MPC55XX_IRQ_ADC_BASE(mod) + 0U)
0337 #define MPC55XX_IRQ_ADC_ER(mod) \
0338   (MPC55XX_IRQ_ADC_BASE(mod) + 1U)
0339 #define MPC55XX_IRQ_ADC_WD(mod) \
0340   (MPC55XX_IRQ_ADC_BASE(mod) + 2U)
0341
0342 /* eTimer */
0343 #define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
0344   (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
0345 #define MPC55XX_IRQ_ETIMER_WTIF(mod) \
0346   (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
0347 #define MPC55XX_IRQ_ETIMER_RCF(mod) \
0348   (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
0349
0350 /* eTPU */
0351 #define MPC55XX_IRQ_ETPU(mod) \
0352   (MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
0353 #define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
0354   (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
0355
0356 /* DSPI */
0357 #define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
0358 #define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
0359 #define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
0360 #define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
0361 #define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
0362
0363 /* eQADC */
0364 #define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
0365   (MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
0366 #define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
0367   (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
0368 #define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
0369   (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
0370 #define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
0371   (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
0372 #define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
0373   (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
0374 #define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
0375   (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
0376
0377 /* FlexCAN */
0378 #if MPC55XX_CHIP_FAMILY == 564
0379   #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
0380   #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
0381   #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
0382   #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
0383   #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
0384   #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
0385   #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
0386 #else
0387   #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
0388   #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
0389   #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
0390   #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
0391   #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
0392   #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
0393   #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
0394   #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
0395   #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
0396   #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
0397   #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
0398   #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
0399   #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
0400   #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
0401   #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
0402   #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
0403   #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
0404   #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
0405   #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
0406   #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
0407 #endif
0408
0409 /* FlexPWM */
0410 #define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
0411 #define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
0412 #define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
0413 #define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
0414 #define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
0415
0416 /* FlexRay */
0417 #if MPC55XX_CHIP_FAMILY == 564
0418   #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
0419   #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
0420   #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
0421   #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
0422   #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
0423   #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
0424   #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
0425   #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
0426   #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
0427   #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
0428 #else
0429   #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
0430   #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
0431   #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
0432   #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
0433   #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
0434   #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
0435   #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
0436   #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
0437 #endif
0438
0439 /* LINFlexD */
0440 #define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
0441 #define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
0442 #define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
0443
0444 /* Checks */
0445 #define MPC55XX_IRQ_IS_VALID(v) \
0446   ((v) >= MPC55XX_IRQ_MIN && \
0447    (v) <= MPC55XX_IRQ_MAX)
0448 #define MPC55XX_IRQ_IS_SOFTWARE(v) \
0449   ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
0450    (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
0451
0452 /*
0453  * Interrupt controller
0454  */
0455
0456 /*
0457  * These are RTEMS API priority values, not INTC priority values.  We have:
0458  *   15 - API-priority == INTC-priority
0459  *
0460  * The API-priority value 15 (which is INTC-priority 0) effectively disables
0461  * the interrupt.
0462  */
0463 #define MPC55XX_INTC_MIN_PRIORITY 14U
0464 #define MPC55XX_INTC_MAX_PRIORITY 0U
0465 #define MPC55XX_INTC_DISABLED_PRIORITY 15U
0466 #define MPC55XX_INTC_INVALID_PRIORITY 16U
0467 #define MPC55XX_INTC_DEFAULT_PRIORITY 13U
0468 #define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
0469   (((uint32_t) (p)) <= MPC55XX_INTC_DISABLED_PRIORITY)
0470
0471 rtems_status_code mpc55xx_interrupt_handler_install(
0472   rtems_vector_number vector,
0473   const char *info,
0474   rtems_option options,
0475   unsigned priority,
0476   rtems_interrupt_handler handler,
0477   void *arg
0478 );
0479
0480 rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector);
0481
0482 rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
0483
0484 /**
0485  * @addtogroup RTEMSImplClassicIntr
0486  *
0487  * @{
0488  */
0489
0490 #define BSP_INTERRUPT_VECTOR_COUNT (MPC55XX_IRQ_MAX + 1)
0491
0492 #ifdef BSP_INTERRUPT_DISPATCH_TABLE_SIZE
0493   #define BSP_INTERRUPT_USE_INDEX_TABLE
0494 #endif
0495
0496 /** @} */
0497
0498 /* Legacy API */
0499 #define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
0500 #define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
0501
0502 #ifdef __cplusplus
0503 };
0504 #endif /* __cplusplus */
0505
0506 #endif /* LIBBSP_POWERPC_IRQ_H */