include/bsp/irq.h

0001 /* irq.h
0002  *
0003  *  This include file describe the data structure and the functions implemented
0004  *  by RTEMS to write interrupt handlers.
0005  *
0006  *  Copyright (C) 1999 valette@crf.canon.fr
0007  *
0008  *  This code is heavilly inspired by the public specification of STREAM V2
0009  *  that can be found at :
0010  *
0011  *      <http://www.chorus.com/Documentation/index.html> by following
0012  *  the STREAM API Specification Document link.
0013  *
0014  *  The license and distribution terms for this file may be
0015  *  found in the file LICENSE in this distribution or at
0016  *  http://www.rtems.org/license/LICENSE.
0017  */
0018
0019 #ifndef BSP_POWERPC_IRQ_H
0020 #define BSP_POWERPC_IRQ_H
0021
0022 #ifndef BSP_SHARED_HANDLER_SUPPORT
0023 #define BSP_SHARED_HANDLER_SUPPORT      1
0024 #endif
0025
0026 #include <rtems/irq.h>
0027
0028 /*
0029  * Switch to using the generic support. Remove this when all BSPs have
0030  * been converted.
0031  */
0032 #define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
0033
0034 /*
0035  * 8259 edge/level control definitions at VIA
0036  */
0037 #define ISA8259_M_ELCR      0x4d0
0038 #define ISA8259_S_ELCR      0x4d1
0039
0040 #define ELCRS_INT15_LVL         0x80
0041 #define ELCRS_INT14_LVL         0x40
0042 #define ELCRS_INT13_LVL         0x20
0043 #define ELCRS_INT12_LVL         0x10
0044 #define ELCRS_INT11_LVL         0x08
0045 #define ELCRS_INT10_LVL         0x04
0046 #define ELCRS_INT9_LVL          0x02
0047 #define ELCRS_INT8_LVL          0x01
0048 #define ELCRM_INT7_LVL          0x80
0049 #define ELCRM_INT6_LVL          0x40
0050 #define ELCRM_INT5_LVL          0x20
0051 #define ELCRM_INT4_LVL          0x10
0052 #define ELCRM_INT3_LVL          0x8
0053 #define ELCRM_INT2_LVL          0x4
0054 #define ELCRM_INT1_LVL          0x2
0055 #define ELCRM_INT0_LVL          0x1
0056
0057     /* PIC's command and mask registers */
0058 #define PIC_MASTER_COMMAND_IO_PORT      0x20    /* Master PIC command register */
0059 #define PIC_SLAVE_COMMAND_IO_PORT       0xa0    /* Slave PIC command register */
0060 #define PIC_MASTER_IMR_IO_PORT          0x21    /* Master PIC Interrupt Mask Register */
0061 #define PIC_SLAVE_IMR_IO_PORT           0xa1    /* Slave PIC Interrupt Mask Register */
0062
0063     /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
0064 #define PIC_EOSI    0x60    /* End of Specific Interrupt (EOSI) */
0065 #define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
0066 #define PIC_EOI     0x20    /* Generic End of Interrupt (EOI) */
0067
0068 #ifndef ASM
0069
0070 #ifdef __cplusplus
0071 extern "C" {
0072 #endif
0073
0074 /*
0075  * rtems_irq_number Definitions
0076  */
0077
0078 /*
0079  * ISA IRQ handler related definitions
0080  */
0081 #define BSP_ISA_IRQ_NUMBER      (16)
0082 #define BSP_ISA_IRQ_LOWEST_OFFSET   (0)
0083 #define BSP_ISA_IRQ_MAX_OFFSET      (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
0084 /*
0085  * PCI IRQ handlers related definitions
0086  * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
0087  */
0088 #ifndef qemu
0089 #define BSP_PCI_IRQ_NUMBER      (16)
0090 #else
0091 #define BSP_PCI_IRQ_NUMBER      (0)
0092 #endif
0093 #define BSP_PCI_IRQ_LOWEST_OFFSET   (BSP_ISA_IRQ_NUMBER)
0094 #define BSP_PCI_IRQ_MAX_OFFSET      (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
0095 /*
0096  * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
0097  * handler might be connected
0098  */
0099 #define BSP_PROCESSOR_IRQ_NUMBER    (1)
0100 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
0101 #define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
0102 /* Misc vectors for OPENPIC irqs (IPI, timers)
0103  */
0104 #ifndef qemu
0105 #define BSP_MISC_IRQ_NUMBER     (8)
0106 #else
0107 #define BSP_MISC_IRQ_NUMBER     (0)
0108 #endif
0109
0110 #define BSP_MISC_IRQ_LOWEST_OFFSET  (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
0111 #define BSP_MISC_IRQ_MAX_OFFSET     (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
0112 /*
0113  * Summary
0114  */
0115 #define BSP_IRQ_NUMBER          (BSP_MISC_IRQ_MAX_OFFSET + 1)
0116 #define BSP_LOWEST_OFFSET       (BSP_ISA_IRQ_LOWEST_OFFSET)
0117 #define BSP_MAX_OFFSET          (BSP_MISC_IRQ_MAX_OFFSET)
0118 #define BSP_INTERRUPT_VECTOR_COUNT  (BSP_MAX_OFFSET + 1)
0119 /*
0120  * Some ISA IRQ symbolic name definition
0121  */
0122 #define BSP_ISA_PERIODIC_TIMER          (0)
0123 #define BSP_ISA_KEYBOARD            (1)
0124 #define BSP_ISA_UART_COM2_IRQ       (3)
0125 #define BSP_ISA_UART_COM1_IRQ       (4)
0126 #define BSP_ISA_RT_TIMER1           (8)
0127 #define BSP_ISA_RT_TIMER3       (10)
0128 /*
0129  * Some PCI IRQ symbolic name definition
0130  */
0131 #define BSP_PCI_IRQ0            (BSP_PCI_IRQ_LOWEST_OFFSET)
0132 #if     BSP_PCI_IRQ_NUMBER > 0
0133 #define BSP_PCI_ISA_BRIDGE_IRQ      (BSP_PCI_IRQ0)
0134 #endif
0135
0136 #if defined(mot_ppc_mvme2100)
0137 #define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
0138 #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
0139 #define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
0140 #define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
0141 #define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
0142 #define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
0143 #define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
0144 #define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
0145 #define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
0146 #define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
0147 #define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
0148 #define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
0149 #else
0150 #define BSP_UART_COM1_IRQ       BSP_ISA_UART_COM1_IRQ
0151 #define BSP_UART_COM2_IRQ       BSP_ISA_UART_COM2_IRQ
0152 #endif
0153
0154 /*
0155  * Some Processor execption handled as RTEMS IRQ symbolic name definition
0156  */
0157 #define BSP_DECREMENTER         (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
0158
0159
0160 /*
0161  * Type definition for RTEMS managed interrupts
0162  */
0163 typedef unsigned short rtems_i8259_masks;
0164
0165 extern  volatile rtems_i8259_masks i8259s_cache;
0166
0167 /*-------------------------------------------------------------------------+
0168 | Function Prototypes.
0169 +--------------------------------------------------------------------------*/
0170 /*
0171  * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
0172  */
0173 void BSP_i8259s_init(void);
0174
0175 /*
0176  * function to disable a particular irq at 8259 level. After calling
0177  * this function, even if the device asserts the interrupt line it will
0178  * not be propagated further to the processor
0179  *
0180  * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
0181  *          a value < 0 on error.
0182  */
0183 int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
0184 /*
0185  * function to enable a particular irq at 8259 level. After calling
0186  * this function, if the device asserts the interrupt line it will
0187  * be propagated further to the processor
0188  */
0189 int BSP_irq_enable_at_i8259s        (const rtems_irq_number irqLine);
0190 /*
0191  * function to acknowledge a particular irq at 8259 level. After calling
0192  * this function, if a device asserts an enabled interrupt line it will
0193  * be propagated further to the processor. Mainly usefull for people
0194  * writing raw handlers as this is automagically done for RTEMS managed
0195  * handlers.
0196  */
0197 int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
0198 /*
0199  * function to check if a particular irq is enabled at 8259 level. After calling
0200  */
0201 int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
0202
0203 unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
0204 void BSP_irq_resume_i8259s(unsigned short in_progress_save);
0205
0206 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
0207 extern void BSP_i8259s_init(void);
0208
0209 /* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
0210 #include <bsp/irq_supp.h>
0211
0212 #ifdef __cplusplus
0213 };
0214 #endif
0215
0216 #endif
0217 #endif