motorola_powerpc/include/bsp.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsPowerPCMotorola
0005  *
0006  * @brief Global BSP definitions.
0007  */
0008
0009 /*
0010  *
0011  *  The license and distribution terms for this file may be
0012  *  found in the file LICENSE in this distribution or at
0013  *  http://www.rtems.org/license/LICENSE.
0014  */
0015 #ifndef LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H
0016 #define LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H
0017
0018 /**
0019  * @defgroup RTEMSBSPsPowerPCMotorola Motorola
0020  *
0021  * @ingroup RTEMSBSPsPowerPC
0022  *
0023  * @brief Motorola Board Support Package.
0024  *
0025  * @{
0026  */
0027
0028 #include <bspopts.h>
0029 #include <bsp/default-initial-extension.h>
0030
0031 #include <rtems.h>
0032 #include <libcpu/io.h>
0033 #include <bsp/vectors.h>
0034
0035 #ifdef qemu
0036 #include <rtems/bspcmdline.h>
0037 #endif
0038
0039 #ifdef __cplusplus
0040 extern "C" {
0041 #endif
0042
0043 /*
0044  * diagram illustrating the role of the configuration
0045  * constants
0046  *  PCI_MEM_WIN0:        CPU starting addr where PCI memory space is visible
0047  *  PCI_MEM_BASE:        CPU address of PCI mem addr. zero. (regardless of this
0048  *                       address being 'visible' or not!).
0049  * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME
0050  * _VME_A32_WIN0_ON_VME: VME address of that same window
0051  *
0052  * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between
0053  * CPU and PCI addresses). The mvme2307/mvme2700 'ppcbug' firmware configures the
0054  * PCI bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
0055  * the base address read from PCI config.space in order to translate that
0056  * into a CPU address.
0057  *
0058  * NOTE: VME addresses should NEVER be translated using these constants!
0059  *       they are strictly for BSP internal use. Drivers etc. should use
0060  *       the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
0061  *
0062  *           CPU ADDR                  PCI_ADDR                                VME ADDR
0063  *
0064  *           00000000                  XXXXXXXX                                XXXXXXXX
0065  *    ^  ^   ........
0066  *    |  |
0067  *    |  |  e.g., RAM                  XXXXXXXX
0068  *    |  |                                                                     00000000
0069  *    |  |  .........                                                          ^
0070  *    |  |            (possible offset                                         |
0071  *    |  |             between pci and XXXXXXXX                                | ......
0072  *    |  |             cpu addresses)                                          |
0073  *    |  v                                                                     |
0074  *    |  PCI_MEM_BASE  ------------->  00000000 ---------------                |
0075  *    |     ........                   ........               ^                |
0076  *    |                                invisible              |                |
0077  *    |     ........                   from CPU               |                |
0078  *    v                                                       |                |
0079  *       PCI_MEM_WIN0 =============  first visible PCI addr   |                |
0080  *                                                            |                |
0081  *        pci devices   pci window                            |                |
0082  *       visible here                                         v                v
0083  *                      mapped by   ========== _VME_A32_WIN0_ON_PCI =======  _VME_A32_WIN0_ON_VME
0084  *                                                 vme window
0085  *        VME devices   hostbridge                 mapped by
0086  *       visible here                              universe
0087  *                    =====================================================
0088  *
0089  */
0090
0091 /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
0092 #if defined(mot_ppc_mvme2100)
0093 #define _IO_BASE        CHRP_ISA_IO_BASE
0094 #define _ISA_MEM_BASE       CHRP_ISA_MEM_BASE
0095 /* address of our ram on the PCI bus   */
0096 #define PCI_DRAM_OFFSET     CHRP_PCI_DRAM_OFFSET
0097 /* offset of pci memory as seen from the CPU */
0098 #define PCI_MEM_BASE        0
0099 /* where (in CPU addr. space) does the PCI window start */
0100 #define PCI_MEM_WIN0        0x80000000
0101
0102 #else
0103 #define _IO_BASE        PREP_ISA_IO_BASE
0104 #define _ISA_MEM_BASE       PREP_ISA_MEM_BASE
0105 #ifndef qemu
0106 /* address of our ram on the PCI bus   */
0107 #define PCI_DRAM_OFFSET     PREP_PCI_DRAM_OFFSET
0108 /* offset of pci memory as seen from the CPU */
0109 #define PCI_MEM_BASE        PREP_ISA_MEM_BASE
0110 #define PCI_MEM_WIN0        0
0111 #else
0112 #define PCI_DRAM_OFFSET     0
0113 #define PCI_MEM_BASE        0
0114 #define PCI_MEM_WIN0        PREP_ISA_MEM_BASE
0115 #endif
0116 #endif
0117
0118 /*
0119  * The BSP has PCI devices. Enable support in LibBSD.
0120  */
0121 #define BSP_HAS_PC_PCI
0122
0123 /*
0124  * Remap the PCI address space for LibBSD
0125  */
0126 #define RTEMS_BSP_PCI_IO_REGION_BASE  0
0127 #define RTEMS_BSP_PCI_MEM_REGION_BASE PCI_DRAM_OFFSET
0128
0129 /*
0130  * Remap the PCI address space for LibBSD
0131  */
0132 #define RTEMS_BSP_ADDR_PTR(_type) uint ## _type ## _t __volatile*
0133 #define RTEMS_BSP_ADDR_CPTR(_type) const RTEMS_BSP_ADDR_PTR(_type)
0134 #define RTEMS_BSP_ADDRESS_READ(_addr, _type) \
0135        *((RTEMS_BSP_ADDR_CPTR(_type)) (((RTEMS_BSP_ADDR_CPTR(8)) _addr) + PCI_DRAM_OFFSET))
0136 #define RTEMS_BSP_ADDRESS_WRITE(_addr, _val, _type) \
0137        *((RTEMS_BSP_ADDR_PTR(_type)) (((RTEMS_BSP_ADDR_PTR(8)) _addr) + PCI_DRAM_OFFSET)) = (_val)
0138
0139 #define RTEMS_BSP_READ_1(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 8)
0140 #define RTEMS_BSP_READ_2(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 16)
0141 #define RTEMS_BSP_READ_4(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 32)
0142 #define RTEMS_BSP_READ_8(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 64)
0143
0144 #define RTEMS_BSP_WRITE_1(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 8)
0145 #define RTEMS_BSP_WRITE_2(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 16)
0146 #define RTEMS_BSP_WRITE_4(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 32)
0147 #define RTEMS_BSP_WRITE_8(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 64)
0148
0149 /*
0150  *  Base address definitions for several devices
0151  *
0152  *  MVME2100 is very similar but has fewer devices and uses on-CPU EPIC
0153  *  implementation of OpenPIC controller.  It also cannot be probed to
0154  *  find out what it is which is VERY different from other Motorola boards.
0155  */
0156
0157 #if defined(mot_ppc_mvme2100)
0158 #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000)
0159 /* #define BSP_UART_IOBASE_COM1     (0xffe10000) */
0160 #define BSP_OPEN_PIC_BASE_OFFSET 0x40000
0161
0162 #define MVME_HAS_DEC21140
0163 #else
0164 #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
0165 #define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
0166
0167 #if ! defined(qemu)
0168 #define BSP_KBD_IOBASE       ((_IO_BASE)+0x60)
0169 #define BSP_VGA_IOBASE       ((_IO_BASE)+0x3c0)
0170 #endif
0171
0172 #if defined(mvme2300) || defined(mot_ppc_mvme2307) || defined(mot_ppc_mvme2700)
0173 #define MVME_HAS_DEC21140
0174 #endif
0175 #endif
0176
0177 #define BSP_CONSOLE_PORT    BSP_UART_COM1
0178 #define BSP_UART_BAUD_BASE  115200
0179
0180 struct rtems_bsdnet_ifconfig;
0181
0182 #if defined(MVME_HAS_DEC21140)
0183 #define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1"
0184 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach
0185 extern int rtems_dec21140_driver_attach(struct rtems_bsdnet_ifconfig *, int);
0186 #endif
0187
0188 #ifdef qemu
0189 #define RTEMS_BSP_NETWORK_DRIVER_NAME "ne1"
0190 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach
0191 extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int);
0192
0193 static inline const char* bsp_cmdline_arg(const char* arg)
0194 {
0195   return rtems_bsp_cmdline_get_param_raw(arg);
0196 }
0197 #endif
0198
0199 #ifdef qemu
0200 #define BSP_IDLE_TASK_BODY bsp_ppc_idle_task_body
0201 extern void *bsp_ppc_idle_task_body(uintptr_t arg);
0202 #endif
0203
0204 #include <bsp/openpic.h>
0205 /* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
0206  * to implement VME IRQ priorities in software.
0207  * Note that this requires support by the interrupt controller
0208  * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)
0209  * and the BSP-specific universe initialization/configuration
0210  * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)
0211  *
0212  * ********* IMPORTANT NOTE ********
0213  * When deriving from this file (new BSPs)
0214  * DO NOT define "BSP_PIC_DO_EOI" if you don't know what
0215  * you are doing i.e., w/o implementing the required pieces
0216  * mentioned above.
0217  * ********* IMPORTANT NOTE ********
0218  */
0219 #define BSP_PIC_DO_EOI openpic_eoi(0)
0220
0221 #ifndef ASM
0222 #define outport_byte(port,value) outb(value,port)
0223 #define outport_word(port,value) outw(value,port)
0224 #define outport_long(port,value) outl(value,port)
0225
0226 #define inport_byte(port,value) (value = inb(port))
0227 #define inport_word(port,value) (value = inw(port))
0228 #define inport_long(port,value) (value = inl(port))
0229
0230 /*
0231  * Vital Board data Start using DATA RESIDUAL
0232  */
0233
0234 /*
0235  * Total memory using RESIDUAL DATA
0236  */
0237 extern unsigned int BSP_mem_size;
0238 /*
0239  * Start of the heap
0240  */
0241 extern unsigned int BSP_heap_start;
0242 /*
0243  * PCI Bus Frequency
0244  */
0245 extern unsigned int BSP_bus_frequency;
0246 /*
0247  * processor clock frequency
0248  */
0249 extern unsigned int BSP_processor_frequency;
0250 /*
0251  * Time base divisior (how many tick for 1 second).
0252  */
0253 extern unsigned int BSP_time_base_divisor;
0254
0255 /*
0256  * String passed by the bootloader.
0257  */
0258 extern char *BSP_commandline_string;
0259
0260 #define BSP_Convert_decrementer( _value ) \
0261   ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
0262
0263 /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */
0264 extern int BSP_disconnect_clock_handler (void);
0265 extern int BSP_connect_clock_handler (void);
0266
0267 /* clear hostbridge errors
0268  *
0269  * NOTE: The routine returns always (-1) if 'enableMCP==1'
0270  *       [semantics needed by libbspExt] if the MCP input is not wired.
0271  *       It returns and clears the error bits of the PCI status register.
0272  *       MCP support is disabled because:
0273  *         a) the 2100 has no raven chip
0274  *         b) the raven (2300, 2307, 2700) would raise machine check interrupts
0275  *            on PCI config space access to empty slots.
0276  */
0277 extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
0278
0279 /*
0280  * Prototypes for methods called only from .S for dependency tracking
0281  */
0282 char *save_boot_params(
0283   void *r3,
0284   void *r4,
0285   void *r5,
0286   char *cmdline_start,
0287   char *cmdline_end
0288 );
0289 void zero_bss(void);
0290
0291 /*
0292  * Prototypes for BSP methods which cross file boundaries
0293  */
0294 void VIA_isa_bridge_interrupts_setup(void);
0295
0296 #endif
0297
0298 #ifdef __cplusplus
0299 };
0300 #endif
0301
0302 /** @} */
0303
0304 #endif