include/ppc4xx/ppc405gp.h

0001
0002 /* SDRAM DCRs */
0003 enum {
0004     SDRAM0_BESR0    =   0,
0005     SDRAM0_BESR1    =   8,
0006     SDRAM0_BEAR     =   0x10,
0007     SDRAM0_CFG      =   0x20,
0008     SDRAM0_STATUS   =   0x24,
0009     SDRAM0_RTR      =   0x30,
0010     SDRAM0_PMIT     =   0x34,
0011     SDRAM0_TR       =   0x80
0012 };
0013
0014
0015 /* EBC DCRs */
0016 enum {
0017     EBC0_B0CR   =   0,
0018     EBC0_B1CR   =   1,
0019     EBC0_B2CR   =   2,
0020     EBC0_B3CR   =   3,
0021     EBC0_B4CR   =   4,
0022     EBC0_B5CR   =   5,
0023     EBC0_B6CR   =   6,
0024     EBC0_B7CR   =   7,
0025     EBC0_B0AP   =   0x10,
0026     EBC0_B1AP   =   0x11,
0027     EBC0_B2AP   =   0x12,
0028     EBC0_B3AP   =   0x13,
0029     EBC0_B4AP   =   0x14,
0030     EBC0_B5AP   =   0x15,
0031     EBC0_B6AP   =   0x16,
0032     EBC0_B7AP   =   0x17,
0033     EBC0_BEAR   =   0x20,
0034     EBC0_BESR0  =   0x21,
0035     EBC0_BESR1  =   0x22,
0036     EBC0_CFG    =   0x23
0037 };
0038
0039 /* MAL DCRs, have to be #defines */
0040 #define MAL0_CFG        0x180
0041 #define MAL0_ESR        0x181
0042 #define MAL0_IER        0x182
0043 #define MAL0_TXCASR     0x184
0044 #define MAL0_TXCARR     0x185
0045 #define MAL0_TXEOBISR   0x186
0046 #define MAL0_TXDEIR     0x187
0047 #define MAL0_RXCASR     0x190
0048 #define MAL0_RXCARR     0x191
0049 #define MAL0_RXEOBISR   0x192
0050 #define MAL0_RXDEIR     0x193
0051 #define MAL0_TXCTP0R    0x1A0
0052 #define MAL0_TXCTP1R    0x1A1
0053 #define MAL0_RXCTP0R    0x1C0
0054 #define MAL0_RXCTP1R    0x1C1
0055 #define MAL0_RCBS0      0x1E0
0056 #define MAL0_RCBS1      0x1E1
0057
0058 /* Memory-mapped registers */
0059
0060 typedef struct EthernetRegisters_GP {
0061     uint32_t mode0;
0062     uint32_t mode1;
0063     uint32_t xmtMode0;
0064     uint32_t xmtMode1;
0065     uint32_t rcvMode;
0066     uint32_t intStatus;
0067     uint32_t intEnable;
0068     uint32_t addrHi;
0069     uint32_t addrLo;
0070     uint32_t VLANTPID;
0071     uint32_t VLANTCI;
0072     uint32_t pauseTimer;
0073     uint32_t g_indivHash[4];  /* EX non-IP multicast addr/mask */
0074     uint32_t g_groupHash[4];
0075     uint32_t lastSrcLo;
0076     uint32_t lastSrcHi;
0077     uint32_t IPGap;
0078     uint32_t STAcontrol;
0079     uint32_t xmtReqThreshold;
0080     uint32_t rcvWatermarks;
0081     uint32_t bytesXmtd;
0082     uint32_t bytesRcvd;
0083     uint32_t e_unused2;
0084     uint32_t e_revID;
0085     uint32_t e_unused3[2];
0086     uint32_t e_indivHash[8];
0087     uint32_t e_groupHash[8];
0088     uint32_t e_xmtPause;
0089 } EthernetRegisters_GP;
0090
0091 typedef struct EthernetRegisters_GP EthernetRegisters_EX;
0092
0093 enum { EMACAddress = 0xEF600800 };
0094 enum { EMAC0GPAddress = 0xEF600800 };
0095
0096 enum {
0097     // Mode 0 bits
0098     kEMACRxIdle   = 0x80000000,
0099     kEMACTxIdle   = 0x40000000,
0100     kEMACSoftRst  = 0x20000000,
0101     kEMACTxEnable = 0x10000000,
0102     kEMACRxEnable = 0x08000000,
0103
0104     // Mode 1 bits
0105     kEMACFullDuplex = 0x80000000,
0106     kEMACDoFlowControl = 0x10000000,
0107     kEMACIgnoreSQE  = 0x01000000,
0108     kEMAC100MBbps    = 0x00400000,
0109     kEMAC4KRxFIFO   = 0x00300000,
0110     kEMAC2KTxFIFO    = 0x00080000,
0111     kEMACTx0Multi    = 0x00008000,
0112     kEMACTxDependent= 0x00014000,
0113     kEMAC100Mbps     = 0x00400000,
0114     kgEMAC4KRxFIFO   = 0x00300000,
0115     kgEMAC2KTxFIFO   = 0x00080000,
0116     kgEMACTx0Multi   = 0x00008000,
0117     kgEMACTxDependent= 0x00014000,
0118
0119
0120     // Tx mode bits
0121     kEMACNewPacket0 = 0x80000000,
0122     kEMACNewPacket1 = 0x40000000,
0123
0124     // Receive mode bits
0125     kEMACStripPadding = 0x80000000,
0126     kEMACStripFCS     = 0x40000000,
0127     kEMACRcvRunts       = 0x20000000,
0128     kEMACRcvFCSErrs = 0x10000000,
0129     kEMACRcvOversize  = 0x08000000,
0130     kEMACPromiscRcv = 0x01000000,
0131     kEMACPromMultRcv  = 0x00800000,
0132     kEMACIndivRcv       = 0x00400000,
0133     kEMACHashRcv        = 0x00200000,
0134     kEMACBrcastRcv      = 0x00100000,
0135     kEMACMultcastRcv    = 0x00080000,
0136     keEMACNonIPMultcast = 0x00040000,
0137     keEMACRxFIFOAFMax   = 7,
0138
0139     // EMAC_STACR bits
0140     kgSTAComplete   = 0x8000,
0141     kSTAErr     = 0x4000,
0142
0143     // Interrupt status bits
0144     kEMACIOverrun = 0x02000000,
0145     kEMACIPause   = 0x01000000,
0146     kEMACIBadPkt  = 0x00800000,
0147     kEMACIRuntPkt = 0x00400000,
0148     kEMACIShortEvt= 0x00200000,
0149     kEMACIAlignErr= 0x00100000,
0150     kEMACIBadFCS  = 0x00080000,
0151     kEMACIOverSize= 0x00040000,
0152     kEMACILLCRange= 0x00020000,
0153     kEMACISQEErr  = 0x00000080,
0154     kEMACITxErr   = 0x00000040,
0155
0156     // Buffer descriptor control bits
0157     kMALTxReady         = 0x8000,
0158     kMALRxEmpty         = 0x8000,
0159     kMALWrap                = 0x4000,
0160     kMALContinuous      = 0x2000,
0161     kMALLast                = 0x1000,
0162     kMALRxFirst         = 0x0800,
0163     kMALInterrupt       = 0x0400,
0164
0165     kMALReset           = 0x80000000,
0166     kMALLowPriority    = 0,
0167     kMALMedLowPriority = 0x00400000,
0168     kMALMedHiPriority  = 0x00800000,
0169     kMALHighPriority   = 0x00C00000,
0170     kMALLatency8       = 0x00040000,
0171     kMALLockErr     = 0x8000,
0172     kMALCanBurst    = 0x4000,
0173     kMALLocksOPB    = 0x80,
0174     kMALLocksErrs   = 0x2,
0175
0176     // MAL channel masks
0177     kMALChannel0 = 0x80000000,
0178     kMALChannel1 = 0x40000000,
0179
0180     // EMAC Tx descriptor bits sent
0181     kEMACGenFCS         = 0x200,
0182     kEMACGenPad         = 0x100,
0183     kEMACInsSrcAddr = 0x080,
0184     kEMACRepSrcAddr = 0x040,
0185     kEMACInsVLAN        = 0x020,
0186     kEMACRepVLAN        = 0x010,
0187
0188     // EMAC TX descriptor bits returned
0189     kEMACErrMask      = 0x3FF,
0190     kEMACFCSWrong       = 0x200,
0191     kEMACBadPrev        = 0x100,
0192     kEMACLostCarrier    = 0x080,
0193     kEMACDeferred       = 0x040,
0194     kEMACCollFail       = 0x020,
0195     kEMACLateColl       = 0x010,
0196     kEMACMultColl       = 0x008,
0197     kEMACOneColl        = 0x004,
0198     kEMACUnderrun       = 0x002,
0199     kEMACSQEFail        = 0x001,
0200
0201     // EMAC Rx descriptor bits returned
0202     kEMACOverrun        = 0x200,
0203     kEMACPausePkt       = 0x100,
0204     kEMACBadPkt         = 0x080,
0205     kEMACRuntPkt        = 0x040,
0206     kEMACShortEvt       = 0x020,
0207     kEMACAlignErr       = 0x010,
0208     kEMACBadFCS         = 0x008,
0209     kEMACPktLong        = 0x004,
0210     kEMACPktOOR         = 0x002,
0211     kEMACPktIRL         = 0x001
0212 };
0213
0214