include/ppc4xx/ppc405ex.h

0001 /*
0002
0003 Constants for manipulating system registers of PPC 405EX in C
0004
0005 Michael Hamel ADInstruments May 2008
0006
0007 */
0008
0009 #include <libcpu/powerpc-utility.h>
0010 /* Indirect access to Clocking/Power-On registers */
0011 #define CPR0_DCR_BASE   0x0C
0012 #define cprcfga     (CPR0_DCR_BASE+0x0)
0013 #define cprcfgd     (CPR0_DCR_BASE+0x1)
0014
0015 #define mtcpr(reg, d)                   \
0016   do {                          \
0017     PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg);   \
0018     PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d);     \
0019   } while (0)
0020
0021 #define mfcpr(reg, d)                   \
0022   do {                          \
0023     PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg);   \
0024     d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd);       \
0025   } while (0)
0026
0027
0028 /* Indirect access to System registers */
0029 #define SDR_DCR_BASE    0x0E
0030 #define sdrcfga     (SDR_DCR_BASE+0x0)
0031 #define sdrcfgd     (SDR_DCR_BASE+0x1)
0032
0033 #define mtsdr(reg, d)                   \
0034   do {                          \
0035     PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg);   \
0036     PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d);     \
0037   } while (0)
0038
0039 #define mfsdr(reg, d)                   \
0040     do {                        \
0041       PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \
0042       d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd);     \
0043     } while (0)
0044
0045 /* Indirect access to EBC registers */
0046 #define EBC_DCR_BASE    0x12
0047 #define ebccfga     (EBC_DCR_BASE+0x0)
0048 #define ebccfgd     (EBC_DCR_BASE+0x1)
0049
0050 #define mtebc(reg, d)                   \
0051   do {                          \
0052     PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg);   \
0053     PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d);     \
0054   } while (0)
0055
0056 #define mfebc(reg, d)                   \
0057   do {                          \
0058     PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg);   \
0059     d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd);       \
0060   } while (0)
0061
0062 /* EBC DCRs */
0063 enum {
0064     /*
0065     EBC0_B0CR   =   0,
0066     EBC0_B1CR   =   1,
0067     EBC0_B2CR   =   2,
0068     EBC0_B3CR   =   3,
0069     EBC0_B0AP   =   0x10,
0070     EBC0_B1AP   =   0x11,
0071     EBC0_B2AP   =   0x12,
0072     EBC0_B3AP   =   0x13,
0073     EBC0_BEAR   =   0x20,
0074     EBC0_BESR   =   0x21,
0075     EBC0_CFG    =   0x23,
0076     */
0077     EBC0_CID    =   0x24
0078 };
0079
0080 enum {
0081     SDR0_PINSTP = 0x40,
0082     SDR0_UART0  = 0x120,
0083     SDR0_UART1  = 0x121,
0084     SDR0_C405   = 0x180,
0085     SDR0_SRST0  = 0x200,
0086     SDR0_MALTBL = 0x280,
0087     SDR0_MALRBL = 0x2A0,
0088     SDR0_MALTBS = 0x2C0,
0089     SDR0_MALRBS = 0x2E0,
0090     SDR0_PFC2   = 0x4102,
0091     SDR0_MFR    = 0x4300,
0092     SDR0_EMAC0RXST = 0x4301,
0093     SDR0_HSF    = 0x4400
0094 };
0095
0096 enum {
0097     CPR0_CLKUPD = 0x20,
0098     CPR0_PLLC = 0x40,
0099     CPR0_PLLD = 0x60,
0100     CPR0_CPUD = 0x80,
0101     CPR0_PLBD = 0xA0,
0102     CPR0_OPBD = 0xC0,
0103     CPR0_PERD = 0xE0,
0104     CPR0_AHBD = 0x100,
0105     CPR0_ICFG = 0x140
0106 };
0107
0108 /* Memory-mapped registers */
0109
0110
0111 /*======================= Ethernet =================== */
0112
0113 enum {
0114     EMAC0EXAddress = 0xEF600900,
0115     EMAC1EXAddress = 0xEF600A00,
0116
0117     /* 405EX-specific bits in EMAC_MR1 */
0118     keEMAC1000Mbps = 0x00800000,
0119     keEMAC16KRxFIFO = 0x00280000,
0120     keEMAC8KRxFIFO  = 0x00200000,
0121     keEMAC4KRxFIFO  = 0x00180000,
0122     keEMAC2KRxFIFO  = 0x00100000,
0123     keEMAC1KRxFIFO  = 0x00080000,
0124     keEMAC16KTxFIFO = 0x00050000,
0125     keEMAC8KTxFIFO  = 0x00040000,
0126     keEMAC4KTxFIFO  = 0x00030000,
0127     keEMAC2KTxFIFO  = 0x00020000,
0128     keEMAC1KTxFIFO  = 0x00010000,
0129     keEMACJumbo     = 0x00000800,
0130     keEMACIPHYAddr4 = 0x180,
0131     keEMACOPB50MHz  = 0x00,
0132     keEMACOPB66MHz  = 0x08,
0133     keEMACOPB83MHz  = 0x10,
0134     keEMACOPB100MHz = 0x18,
0135     keEMACOPBGt100  = 0x20,
0136
0137     /* 405EX-specific bits in MAL0_CFG */
0138     keMALRdMaxBurst4  = 0,
0139     keMALRdMaxBurst8  = 0x00100000,
0140     keMALRdMaxBurst16 = 0x00200000,
0141     keMALRdMaxBurst32 = 0x00300000,
0142
0143     keMALWrLowPriority    = 0,
0144     keMALWrMedLowPriority = 0x00040000,
0145     keMALWrMedHiPriority  = 0x00080000,
0146     keMALWrHighPriority   = 0x000C0000,
0147
0148     keMALWrMaxBurst4  = 0,
0149     keMALWrMaxBurst8  = 0x00010000,
0150     keMALWrMaxBurst16 = 0x00020000,
0151     keMALWrMaxBurst32 = 0x00030000,
0152
0153     /* 405EX-specific STA bits */
0154     keSTARun      = 0x8000,
0155     keSTADirectRd = 0x1000,
0156     keSTADirectWr = 0x0800,
0157     keSTAIndirAddr = 0x2000,
0158     keSTAIndirRd  = 0x3000,
0159     keSTAIndirWr  = 0x2800
0160 };
0161
0162 typedef struct GPIORegisters {
0163     uint32_t OR;
0164     uint32_t GPIO_TCR;      /* Note that TCR is defined as a DCR name */
0165     uint32_t OSRL;
0166     uint32_t OSRH;
0167     uint32_t TSRL;
0168     uint32_t TSRH;
0169     uint32_t ODR;
0170     uint32_t IR;
0171     uint32_t RR1;
0172     uint32_t RR2;
0173     uint32_t RR3;
0174     uint32_t unknown;
0175     uint32_t ISR1L;
0176     uint32_t ISR1H;
0177     uint32_t ISR2L;
0178     uint32_t ISR2H;
0179     uint32_t ISR3L;
0180     uint32_t ISR3H;
0181 } GPIORegisters;
0182
0183 enum { GPIOAddress = 0xEF600800 };
0184
0185 typedef struct RGMIIRegisters {
0186     uint32_t FER;
0187     uint32_t SSR;
0188 } RGMIIRegisters;
0189
0190 enum { RGMIIAddress = 0xEF600B00 };
0191