powerpc/include/mpc8xx.h

0001 /*
0002 **************************************************************************
0003 **************************************************************************
0004 **                                                                      **
0005 **       MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR         **
0006 **                                                                      **
0007 **                        HARDWARE DECLARATIONS                         **
0008 **                                                                      **
0009 **                                                                      **
0010 **  Submitted By:                                                       **
0011 **                                                                      **
0012 **      Eric Norum <eric.norum.ca>                                      **
0013 **                                                                      **
0014 **  Modified for use with the MPC860 (original code was for MC68360)    **
0015 **  by                                                                  **
0016 **      Jay Monkman                                                     **
0017 **      Frasca International, Inc.                                      **
0018 **      906 E. Airport Rd.                                              **
0019 **      Urbana, IL, 61801                                               **
0020 **                                                                      **
0021 **      jmonkman@frasca.com                                             **
0022 **                                                                      **
0023 **  Modified further for use with the MPC821 by:                        **
0024 **      Andrew Bray <andy@chaos.org.uk>                                 **
0025 **                                                                      **
0026 **  With some corrections/additions by:                                 **
0027 **      Darlene A. Stewart and                                          **
0028 **      Charles-Antoine Gauthier                                        **
0029 **      Institute for Information Technology                            **
0030 **      National Research Council of Canada                             **
0031 **      Ottawa, ON  K1A 0R6                                             **
0032 **                                                                      **
0033 **      Darlene.Stewart@iit.nrc.ca                                      **
0034 **      charles.gauthier@iit.nrc.ca                                     **
0035 **                                                                      **
0036 **      Corrections/additions:                                          **
0037 **        Copyright (c) 1999, National Research Council of Canada       **
0038 **************************************************************************
0039 **************************************************************************
0040 */
0041 #ifndef _MPC8XX_H
0042 #define _MPC8XX_H
0043
0044 #ifndef ASM
0045
0046 #ifdef __cplusplus
0047 extern "C" {
0048 #endif
0049
0050 /*
0051  * Macros for accessing Special Purpose Registers (SPRs)
0052  */
0053 #define _mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
0054 #define _mfspr(_reg,_spr)   __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) )
0055
0056 #define _isync   __asm__ volatile ("isync\n"::)
0057
0058 /*
0059  * Core Registers (SPRs)
0060  */
0061 #define M8xx_DEC        22      /* Decrementer Register */
0062 #define M8xx_DER        149     /* Debug Enable Register */
0063 #define M8xx_ICTRL      158     /* Instruction Support Control Register */
0064 #define M8xx_TBL_WR     284     /* Timebase Lower Write Register */
0065 #define M8xx_TBU_WR     285     /* Timebase Upper Write Register */
0066 #define M8xx_IMMR       638     /* Internal Memory Map Register */
0067
0068 /*
0069  * Cache Control Registers (SPRs)
0070  */
0071 #define M8xx_IC_CST     560     /* Instruction Cache Control and Status Register */
0072 #define M8xx_DC_CST     568     /* Data Cache Control and Status Register */
0073 #define M8xx_IC_ADR     561     /* Instruction Cache Address Register */
0074 #define M8xx_DC_ADR     569     /* Data Cache Address Register */
0075 #define M8xx_IC_DAT     562     /* Instruction Cache Data Port Register */
0076 #define M8xx_DC_DAT     570     /* Data Cache Data Port Register */
0077
0078 /*
0079  * MMU Registers (SPRs)
0080  */
0081 /* Control Registers */
0082 #define M8xx_MI_CTR     784     /* IMMU Control Register */
0083 #define M8xx_MD_CTR     792     /* DMMU Control Register */
0084 /* TLB Source Registers */
0085 #define M8xx_MI_EPN     787     /* IMMU Effective Page Number Register (EPN) */
0086 #define M8xx_MD_EPN     795     /* DMMU Effective Page Number Register (EPN) */
0087 #define M8xx_MI_TWC     789     /* IMMU Tablewalk Control Register (TWC) */
0088 #define M8xx_MD_TWC     797     /* DMMU Tablewalk Control Register (TWC) */
0089 #define M8xx_MI_RPN     790     /* IMMU Real (physical) Page Number Register (RPN) */
0090 #define M8xx_MD_RPN     798     /* DMMU Real (physical) Page Number Register (RPN) */
0091 /* Tablewalk Assist Registers */
0092 #define M8xx_M_TWB      796     /* MMU Tablewalk Base Register (TWB) */
0093 /* Protection Registers */
0094 #define M8xx_M_CASID    793     /* MMU Current Address Space ID Register */
0095 #define M8xx_MI_AP      786     /* IMMU Access Protection Register */
0096 #define M8xx_MD_AP      794     /* DMMU Access Protection Register */
0097 /* Scratch Register */
0098 #define M8xx_M_TW       799     /* MMU Tablewalk Special Register */
0099 /* Debug Registers */
0100 #define M8xx_MI_CAM     816     /* IMMU CAM Entry Read Register */
0101 #define M8xx_MI_RAM0    817     /* IMMU RAM Entry Read Register 0 */
0102 #define M8xx_MI_RAM1    818     /* IMMU RAM Entry Read Register 1 */
0103 #define M8xx_MD_CAM     824     /* DMMU CAM Entry Read Register */
0104 #define M8xx_MD_RAM0    825     /* DMMU RAM Entry Read Register 0 */
0105 #define M8xx_MD_RAM1    826     /* DMMU RAM Entry Read Register 1 */
0106
0107 #define M8xx_MI_CTR_GPM       (1<<31)
0108 #define M8xx_MI_CTR_PPM       (1<<30)
0109 #define M8xx_MI_CTR_CIDEF     (1<<29)
0110 #define M8xx_MI_CTR_RSV4I     (1<<27)
0111 #define M8xx_MI_CTR_PPCS      (1<<25)
0112 #define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8)   /* ITLB index */
0113
0114 #define M8xx_MD_CTR_GPM       (1<<31)
0115 #define M8xx_MD_CTR_PPM       (1<<30)
0116 #define M8xx_MD_CTR_CIDEF     (1<<29)
0117 #define M8xx_MD_CTR_WTDEF     (1<<28)
0118 #define M8xx_MD_CTR_RSV4D     (1<<27)
0119 #define M8xx_MD_CTR_TWAM      (1<<26)
0120 #define M8xx_MD_CTR_PPCS      (1<<25)
0121 #define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8)   /* DTLB index */
0122
0123 #define M8xx_MI_EPN_VALID     (1<<9)
0124
0125 #define M8xx_MD_EPN_VALID     (1<<9)
0126
0127 #define M8xx_MI_TWC_G         (1<<4)
0128 #define M8xx_MI_TWC_PSS       (0<<2)
0129 #define M8xx_MI_TWC_PS512     (1<<2)
0130 #define M8xx_MI_TWC_PS8       (3<<2)
0131 #define M8xx_MI_TWC_VALID     (1)
0132
0133 #define M8xx_MD_TWC_G         (1<<4)
0134 #define M8xx_MD_TWC_PSS       (0<<2)
0135 #define M8xx_MD_TWC_PS512     (1<<2)
0136 #define M8xx_MD_TWC_PS8       (3<<2)
0137 #define M8xx_MD_TWC_WT        (1<<1)
0138 #define M8xx_MD_TWC_VALID     (1)
0139
0140 #define M8xx_MI_RPN_F         (0xf<<4)
0141 #define M8xx_MI_RPN_16K       (1<<3)
0142 #define M8xx_MI_RPN_SHARED    (1<<2)
0143 #define M8xx_MI_RPN_CI        (1<<1)
0144 #define M8xx_MI_RPN_VALID     (1)
0145
0146 #define M8xx_MD_RPN_CHANGE    (1<<8)
0147 #define M8xx_MD_RPN_F         (0xf<<4)
0148 #define M8xx_MD_RPN_16K       (1<<3)
0149 #define M8xx_MD_RPN_SHARED    (1<<2)
0150 #define M8xx_MD_RPN_CI        (1<<1)
0151 #define M8xx_MD_RPN_VALID     (1)
0152
0153 #define M8xx_MI_AP_Kp         (1)
0154
0155 #define M8xx_MD_AP_Kp         (1)
0156
0157 #define M8xx_CACHE_CMD_SFWT          (0x1<<24)
0158 #define M8xx_CACHE_CMD_ENABLE        (0x2<<24)
0159 #define M8xx_CACHE_CMD_CFWT          (0x3<<24)
0160 #define M8xx_CACHE_CMD_DISABLE       (0x4<<24)
0161 #define M8xx_CACHE_CMD_STLES         (0x5<<24)
0162 #define M8xx_CACHE_CMD_LLCB          (0x6<<24)
0163 #define M8xx_CACHE_CMD_CLES          (0x7<<24)
0164 #define M8xx_CACHE_CMD_UNLOCK        (0x8<<24)
0165 #define M8xx_CACHE_CMD_UNLOCKALL     (0xa<<24)
0166 #define M8xx_CACHE_CMD_INVALIDATE    (0xc<<24)
0167 #define M8xx_CACHE_CMD_FLUSH         (0xe<<24)
0168
0169 /*
0170 *************************************************************************
0171 *                         REGISTER SUBBLOCKS                            *
0172 *************************************************************************
0173 */
0174
0175 /*
0176  * Memory controller registers
0177  */
0178 typedef struct m8xxMEMCRegisters_ {
0179   uint32_t          _br;
0180   uint32_t          _or;    /* Used to be called 'or'; reserved ANSI C++ keyword */
0181 } m8xxMEMCRegisters_t;
0182
0183 /*
0184  * Serial Communications Controller registers
0185  */
0186 typedef struct m8xxSCCRegisters_ {
0187   uint32_t          gsmr_l;
0188   uint32_t          gsmr_h;
0189   uint16_t          psmr;
0190   uint16_t          _pad0;
0191   uint16_t          todr;
0192   uint16_t          dsr;
0193   uint16_t          scce;
0194   uint16_t          _pad1;
0195   uint16_t          sccm;
0196   uint8_t           _pad2;
0197   uint8_t           sccs;
0198   uint32_t          _pad3[2];
0199 } m8xxSCCRegisters_t;
0200
0201 /*
0202  * Serial Management Controller registers
0203  */
0204 typedef struct m8xxSMCRegisters_ {
0205   uint16_t          _pad0;
0206   uint16_t          smcmr;
0207   uint16_t          _pad1;
0208   uint8_t           smce;
0209   uint8_t           _pad2;
0210   uint16_t          _pad3;
0211   uint8_t           smcm;
0212   uint8_t           _pad4;
0213   uint32_t          _pad5;
0214 } m8xxSMCRegisters_t;
0215
0216 /*
0217  * Fast Ethernet Controller registers (Only on MPC8xxT)
0218  */
0219 typedef struct m8xxFECRegisters_ {
0220   uint32_t      addr_low;
0221   uint32_t      addr_high;
0222   uint32_t      hash_table_high;
0223   uint32_t      hash_table_low;
0224   uint32_t      r_des_start;
0225   uint32_t      x_des_start;
0226   uint32_t      r_buf_size;
0227   uint32_t      _pad0[9];
0228   uint32_t      ecntrl;
0229   uint32_t      ievent;
0230   uint32_t      imask;
0231   uint32_t      ivec;
0232   uint32_t      r_des_active;
0233   uint32_t      x_des_active;
0234   uint32_t      _pad1[10];
0235   uint32_t      mii_data;
0236   uint32_t      mii_speed;
0237   uint32_t      _pad2[17];
0238   uint32_t      r_bound;
0239   uint32_t      r_fstart;
0240   uint32_t      _pad3[6];
0241   uint32_t      x_fstart;
0242   uint32_t      _pad4[17];
0243   uint32_t      fun_code;
0244   uint32_t      _pad5[3];
0245   uint32_t      r_cntrl;
0246   uint32_t      r_hash;
0247   uint32_t      _pad6[14];
0248   uint32_t      x_cntrl;
0249   uint32_t      _pad7[30];
0250
0251 } m8xxFECRegisters_t;
0252
0253 #define M8xx_FEC_IEVENT_HBERR  (1 << 31)
0254 #define M8xx_FEC_IEVENT_BABR   (1 << 30)
0255 #define M8xx_FEC_IEVENT_BABT   (1 << 29)
0256 #define M8xx_FEC_IEVENT_GRA    (1 << 28)
0257 #define M8xx_FEC_IEVENT_TFINT  (1 << 27)
0258 #define M8xx_FEC_IEVENT_TXB    (1 << 26)
0259 #define M8xx_FEC_IEVENT_RFINT  (1 << 25)
0260 #define M8xx_FEC_IEVENT_RXB    (1 << 24)
0261 #define M8xx_FEC_IEVENT_MII    (1 << 23)
0262 #define M8xx_FEC_IEVENT_EBERR  (1 << 22)
0263 #define M8xx_FEC_IMASK_HBEEN   (1 << 31)
0264 #define M8xx_FEC_IMASK_BREEN   (1 << 30)
0265 #define M8xx_FEC_IMASK_BTEN    (1 << 29)
0266 #define M8xx_FEC_IMASK_GRAEN   (1 << 28)
0267 #define M8xx_FEC_IMASK_TFIEN   (1 << 27)
0268 #define M8xx_FEC_IMASK_TBIEN   (1 << 26)
0269 #define M8xx_FEC_IMASK_RFIEN   (1 << 25)
0270 #define M8xx_FEC_IMASK_RBIEN   (1 << 24)
0271 #define M8xx_FEC_IMASK_MIIEN   (1 << 23)
0272 #define M8xx_FEC_IMASK_EBERREN (1 << 22)
0273
0274   /*
0275    * access macros to write to mii_data register
0276    */
0277 #define M8xx_FEC_MII_DATA_ST       ( 1           << (31- 1))
0278 #define M8xx_FEC_MII_DATA_OP_RD    ( 2           << (31- 3))
0279 #define M8xx_FEC_MII_DATA_OP_WR    ( 1           << (31- 3))
0280 #define M8xx_FEC_MII_DATA_PHYAD(n) (((n) & 0x3f) << (31- 8))
0281 #define M8xx_FEC_MII_DATA_PHYRA(n) (((n) & 0x3f) << (31-13))
0282 #define M8xx_FEC_MII_DATA_TA       ( 2           << (31-15))
0283 #define M8xx_FEC_MII_DATA_WDATA(n) ((n) & 0xffff           )
0284 #define M8xx_FEC_MII_DATA_RDATA(reg) ((reg) & 0xffff       )
0285   /*
0286    * bits for FEC ECNTRL register
0287    */
0288 #define M8xx_FEC_ECNTRL_FEC_PINMUX ( 1           << (31-29))
0289 #define M8xx_FEC_ECNTRL_ETHER_EN   ( 1           << (31-30))
0290 #define M8xx_FEC_ECNTRL_RESET      ( 1           << (31-31))
0291
0292   /*
0293    * bits for FEC R_CNTRL register
0294    */
0295 #define M8xx_FEC_R_CNTRL_BC_REJ     ( 1           << (31-27))
0296 #define M8xx_FEC_R_CNTRL_PROM       ( 1           << (31-28))
0297 #define M8xx_FEC_R_CNTRL_MII_MODE   ( 1           << (31-29))
0298 #define M8xx_FEC_R_CNTRL_DRT        ( 1           << (31-30))
0299 #define M8xx_FEC_R_CNTRL_LOOP       ( 1           << (31-31))
0300
0301   /*
0302    * bits for FEC X_CNTRL register
0303    */
0304 #define M8xx_FEC_X_CNTRL_FDEN       ( 1           << (31-29))
0305 #define M8xx_FEC_X_CNTRL_HBC        ( 1           << (31-30))
0306 #define M8xx_FEC_X_CNTRL_GTS        ( 1           << (31-31))
0307 /*
0308 *************************************************************************
0309 *                         Miscellaneous Parameters                      *
0310 *************************************************************************
0311 */
0312 typedef struct m8xxMiscParms_ {
0313   uint16_t          rev_num;
0314   uint16_t          _res1;
0315   uint32_t          _res2;
0316   uint32_t          _res3;
0317 } m8xxMiscParms_t;
0318
0319 /*
0320 *************************************************************************
0321 *                              RISC Timers                              *
0322 *************************************************************************
0323 */
0324 typedef struct m8xxTimerParms_ {
0325   uint16_t          tm_base;
0326   uint16_t          _tm_ptr;
0327   uint16_t          _r_tmr;
0328   uint16_t          _r_tmv;
0329   uint32_t          tm_cmd;
0330   uint32_t          tm_cnt;
0331 } m8xxTimerParms_t;
0332
0333 /*
0334  * RISC Controller Configuration Register (RCCR)
0335  * All other bits in this register are reserved.
0336  */
0337 #define M8xx_RCCR_TIME          (1<<15)    /* Enable timer */
0338 #define M8xx_RCCR_TIMEP(x)      ((x)<<8)   /* Timer period */
0339 #define M8xx_RCCR_DR1M          (1<<7)     /* IDMA Rqst 1 Mode */
0340 #define M8xx_RCCR_DR0M          (1<<6)     /* IDMA Rqst 0 Mode */
0341 #define M8xx_RCCR_DRQP(x)       ((x)<<4)   /* IDMA Rqst Priority */
0342 #define M8xx_RCCR_EIE           (1<<3)     /* External Interrupt Enable */
0343 #define M8xx_RCCR_SCD           (1<<2)     /* Scheduler Configuration */
0344 #define M8xx_RCCR_ERAM(x)       (x)        /* Enable RAM Microcode */
0345
0346 /*
0347  * Command register
0348  * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command.
0349  */
0350 #define M8xx_TM_CMD_V           (1<<31)         /* Set to enable timer */
0351 #define M8xx_TM_CMD_R           (1<<30)         /* Set for automatic restart */
0352 #define M8xx_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
0353 #define M8xx_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
0354 #define M8xx_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */
0355
0356 /*
0357 *************************************************************************
0358 *                               DMA Controllers                         *
0359 *************************************************************************
0360 */
0361 typedef struct m8xxIDMAparms_ {
0362   uint16_t          ibase;
0363   uint16_t          dcmr;
0364   uint32_t          _sapr;
0365   uint32_t          _dapr;
0366   uint16_t          ibptr;
0367   uint16_t          _write_sp;
0368   uint32_t          _s_byte_c;
0369   uint32_t          _d_byte_c;
0370   uint32_t          _s_state;
0371   uint32_t          _itemp[4];
0372   uint32_t          _sr_mem;
0373   uint16_t          _read_sp;
0374   uint16_t          _res0;
0375   uint16_t          _res1;
0376   uint16_t          _res2;
0377   uint32_t          _d_state;
0378 } m8xxIDMAparms_t;
0379
0380
0381 /*
0382 *************************************************************************
0383 *                               DSP                                     *
0384 *************************************************************************
0385 */
0386 typedef struct m8xxDSPparms_ {
0387   uint32_t          fdbase;
0388   uint32_t          _fd_ptr;
0389   uint32_t          _dstate;
0390   uint32_t          _pad0;
0391   uint16_t          _dstatus;
0392   uint16_t          _i;
0393   uint16_t          _tap;
0394   uint16_t          _cbase;
0395   uint16_t          _pad1;
0396   uint16_t          _xptr;
0397   uint16_t          _pad2;
0398   uint16_t          _yptr;
0399   uint16_t          _m;
0400   uint16_t          _pad3;
0401   uint16_t          _n;
0402   uint16_t          _pad4;
0403   uint16_t          _k;
0404   uint16_t          _pad5;
0405 } m8xxDSPparms_t;
0406
0407 /*
0408 *************************************************************************
0409 *                   Serial Communication Controllers                    *
0410 *************************************************************************
0411 */
0412 typedef struct m8xxSCCparms_ {
0413   uint16_t          rbase;
0414   uint16_t          tbase;
0415   uint8_t           rfcr;
0416   uint8_t           tfcr;
0417   uint16_t          mrblr;
0418   uint32_t          _rstate;
0419   uint32_t          _pad0;
0420   uint16_t          _rbptr;
0421   uint16_t          _pad1;
0422   uint32_t          _pad2;
0423   uint32_t          _tstate;
0424   uint32_t          _pad3;
0425   uint16_t          _tbptr;
0426   uint16_t          _pad4;
0427   uint32_t          _pad5;
0428   uint32_t          _rcrc;
0429   uint32_t          _tcrc;
0430   union {
0431     struct {
0432       uint32_t          _res0;
0433       uint32_t          _res1;
0434       uint16_t          max_idl;
0435       uint16_t          _idlc;
0436       uint16_t          brkcr;
0437       uint16_t          parec;
0438       uint16_t          frmec;
0439       uint16_t          nosec;
0440       uint16_t          brkec;
0441       uint16_t          brkln;
0442       uint16_t          uaddr[2];
0443       uint16_t          _rtemp;
0444       uint16_t          toseq;
0445       uint16_t          character[8];
0446       uint16_t          rccm;
0447       uint16_t          rccr;
0448       uint16_t          rlbc;
0449     } uart;
0450   } un;
0451 } m8xxSCCparms_t;
0452
0453 typedef struct m8xxSCCENparms_ {
0454   uint16_t          rbase;
0455   uint16_t          tbase;
0456   uint8_t           rfcr;
0457   uint8_t           tfcr;
0458   uint16_t          mrblr;
0459   uint32_t          _rstate;
0460   uint32_t          _pad0;
0461   uint16_t          _rbptr;
0462   uint16_t          _pad1;
0463   uint32_t          _pad2;
0464   uint32_t          _tstate;
0465   uint32_t          _pad3;
0466   uint16_t          _tbptr;
0467   uint16_t          _pad4;
0468   uint32_t          _pad5;
0469   uint32_t          _rcrc;
0470   uint32_t          _tcrc;
0471   union {
0472     struct {
0473       uint32_t          _res0;
0474       uint32_t          _res1;
0475       uint16_t          max_idl;
0476       uint16_t          _idlc;
0477       uint16_t          brkcr;
0478       uint16_t          parec;
0479       uint16_t          frmec;
0480       uint16_t          nosec;
0481       uint16_t          brkec;
0482       uint16_t          brkln;
0483       uint16_t          uaddr[2];
0484       uint16_t          _rtemp;
0485       uint16_t          toseq;
0486       uint16_t          character[8];
0487       uint16_t          rccm;
0488       uint16_t          rccr;
0489       uint16_t          rlbc;
0490     } uart;
0491     struct {
0492       uint32_t          c_pres;
0493       uint32_t          c_mask;
0494       uint32_t          crcec;
0495       uint32_t          alec;
0496       uint32_t          disfc;
0497       uint16_t          pads;
0498       uint16_t          ret_lim;
0499       uint16_t          _ret_cnt;
0500       uint16_t          mflr;
0501       uint16_t          minflr;
0502       uint16_t          maxd1;
0503       uint16_t          maxd2;
0504       uint16_t          _maxd;
0505       uint16_t          dma_cnt;
0506       uint16_t          _max_b;
0507       uint16_t          gaddr1;
0508       uint16_t          gaddr2;
0509       uint16_t          gaddr3;
0510       uint16_t          gaddr4;
0511       uint32_t          _tbuf0data0;
0512       uint32_t          _tbuf0data1;
0513       uint32_t          _tbuf0rba0;
0514       uint32_t          _tbuf0crc;
0515       uint16_t          _tbuf0bcnt;
0516       uint16_t          paddr_h;
0517       uint16_t          paddr_m;
0518       uint16_t          paddr_l;
0519       uint16_t          p_per;
0520       uint16_t          _rfbd_ptr;
0521       uint16_t          _tfbd_ptr;
0522       uint16_t          _tlbd_ptr;
0523       uint32_t          _tbuf1data0;
0524       uint32_t          _tbuf1data1;
0525       uint32_t          _tbuf1rba0;
0526       uint32_t          _tbuf1crc;
0527       uint16_t          _tbuf1bcnt;
0528       uint16_t          _tx_len;
0529       uint16_t          iaddr1;
0530       uint16_t          iaddr2;
0531       uint16_t          iaddr3;
0532       uint16_t          iaddr4;
0533       uint16_t          _boff_cnt;
0534       uint16_t          taddr_m;
0535       uint16_t          taddr_l;
0536       uint16_t          taddr_h;
0537     } ethernet;
0538   } un;
0539 } m8xxSCCENparms_t;
0540
0541 /*
0542  * Receive and transmit function code register bits
0543  * These apply to the function code registers of all devices, not just SCC.
0544  */
0545 #define M8xx_RFCR_BO(x)         ((x)<<3)
0546 #define M8xx_RFCR_MOT           (2<<3)
0547 #define M8xx_RFCR_DMA_SPACE(x)  (x)
0548 #define M8xx_TFCR_BO(x)         ((x)<<3)
0549 #define M8xx_TFCR_MOT           (2<<3)
0550 #define M8xx_TFCR_DMA_SPACE(x)  (x)
0551
0552 /*
0553  * Event and mask registers (SCCE, SCCM)
0554  */
0555 #define M8xx_SCCE_BRKE  (1<<6)
0556 #define M8xx_SCCE_BRK   (1<<4)
0557 #define M8xx_SCCE_BSY   (1<<2)
0558 #define M8xx_SCCE_TX    (1<<1)
0559 #define M8xx_SCCE_RX    (1<<0)
0560
0561 /*
0562 *************************************************************************
0563 *                     Serial Management Controllers                     *
0564 *************************************************************************
0565 */
0566 typedef struct m8xxSMCparms_ {
0567   uint16_t          rbase;
0568   uint16_t          tbase;
0569   uint8_t           rfcr;
0570   uint8_t           tfcr;
0571   uint16_t          mrblr;
0572   uint32_t          _rstate;
0573   uint32_t          _pad0;
0574   uint16_t          _rbptr;
0575   uint16_t          _pad1;
0576   uint32_t          _pad2;
0577   uint32_t          _tstate;
0578   uint32_t          _pad3;
0579   uint16_t          _tbptr;
0580   uint16_t          _pad4;
0581   uint32_t          _pad5;
0582   union {
0583     struct {
0584       uint16_t          max_idl;
0585       uint16_t          _idlc;
0586       uint16_t          brkln;
0587       uint16_t          brkec;
0588       uint16_t          brkcr;
0589       uint16_t          _r_mask;
0590     } uart;
0591     struct {
0592       uint16_t          _pad0[5];
0593     } transparent;
0594   } un;
0595 } m8xxSMCparms_t;
0596
0597 /*
0598  * Mode register
0599  */
0600 #define M8xx_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
0601 #define M8xx_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
0602 #define M8xx_SMCMR_PARITY               (1<<9)       /* Enable parity */
0603 #define M8xx_SMCMR_EVEN                 (1<<8)       /* Even parity */
0604 #define M8xx_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
0605 #define M8xx_SMCMR_SM_UART              (2<<4)       /* UART Mode */
0606 #define M8xx_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
0607 #define M8xx_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
0608 #define M8xx_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
0609 #define M8xx_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
0610 #define M8xx_SMCMR_REN                  (1<<0)       /* Enable receiver */
0611
0612 /*
0613  * Event and mask registers (SMCE, SMCM)
0614  */
0615 #define M8xx_SMCE_BRKE  (1<<6)
0616 #define M8xx_SMCE_BRK   (1<<4)
0617 #define M8xx_SMCE_BSY   (1<<2)
0618 #define M8xx_SMCE_TX    (1<<1)
0619 #define M8xx_SMCE_RX    (1<<0)
0620
0621 /*
0622 *************************************************************************
0623 *                      Serial Peripheral Interface                      *
0624 *************************************************************************
0625 */
0626 typedef struct m8xxSPIparms_ {
0627   uint16_t          rbase;
0628   uint16_t          tbase;
0629   uint8_t           rfcr;
0630   uint8_t           tfcr;
0631   uint16_t          mrblr;
0632   uint32_t          _rstate;
0633   uint32_t          _pad0;
0634   uint16_t          _rbptr;
0635   uint16_t          _pad1;
0636   uint32_t          _pad2;
0637   uint32_t          _tstate;
0638   uint32_t          _pad3;
0639   uint16_t          _tbptr;
0640   uint16_t          _pad4;
0641   uint32_t          _pad5;
0642 } m8xxSPIparms_t;
0643
0644 /*
0645  * Mode register (SPMODE)
0646  */
0647 #define M8xx_SPMODE_LOOP                (1<<14) /* Local loopback mode */
0648 #define M8xx_SPMODE_CI                  (1<<13) /* Clock invert */
0649 #define M8xx_SPMODE_CP                  (1<<12) /* Clock phase */
0650 #define M8xx_SPMODE_DIV16               (1<<11) /* Divide BRGCLK by 16 */
0651 #define M8xx_SPMODE_REV                 (1<<10) /* Reverse data */
0652 #define M8xx_SPMODE_MASTER              (1<<9)  /* SPI is master */
0653 #define M8xx_SPMODE_EN                  (1<<8)  /* Enable SPI */
0654 #define M8xx_SPMODE_CLEN(x)             ((x)<<4)        /* Character length */
0655 #define M8xx_SPMODE_PM(x)               (x)     /* Prescaler modulus */
0656
0657 /*
0658  * Mode register (SPCOM)
0659  */
0660 #define M8xx_SPCOM_STR                  (1<<7)  /* Start transmit */
0661
0662 /*
0663  * Event and mask registers (SPIE, SPIM)
0664  */
0665 #define M8xx_SPIE_MME   (1<<5)          /* Multi-master error */
0666 #define M8xx_SPIE_TXE   (1<<4)          /* Tx error */
0667 #define M8xx_SPIE_BSY   (1<<2)          /* Busy condition*/
0668 #define M8xx_SPIE_TXB   (1<<1)          /* Tx buffer */
0669 #define M8xx_SPIE_RXB   (1<<0)          /* Rx buffer */
0670
0671 /*
0672 *************************************************************************
0673 *                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
0674 *************************************************************************
0675 */
0676 typedef struct m8xxBufferDescriptor_ {
0677   volatile uint16_t          status;
0678   uint16_t                 length;
0679   void                 *buffer;
0680 } m8xxBufferDescriptor_t;
0681
0682 /*
0683  * Bits in receive buffer descriptor status word
0684  */
0685 #define M8xx_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
0686 #define M8xx_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
0687 #define M8xx_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
0688 #define M8xx_BD_LAST            (1<<11) /* Ethernet, SPI */
0689 #define M8xx_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
0690 #define M8xx_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
0691 #define M8xx_BD_ADDRESS         (1<<10) /* SCC UART */
0692 #define M8xx_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
0693 #define M8xx_BD_MISS            (1<<8)  /* Ethernet */
0694 #define M8xx_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
0695 #define M8xx_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
0696 #define M8xx_BD_LONG            (1<<5)  /* Ethernet */
0697 #define M8xx_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
0698 #define M8xx_BD_NONALIGNED      (1<<4)  /* Ethernet */
0699 #define M8xx_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
0700 #define M8xx_BD_SHORT           (1<<3)  /* Ethernet */
0701 #define M8xx_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
0702 #define M8xx_BD_CRC_ERROR       (1<<2)  /* Ethernet */
0703 #define M8xx_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
0704 #define M8xx_BD_COLLISION       (1<<0)  /* Ethernet */
0705 #define M8xx_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
0706 #define M8xx_BD_MASTER_ERROR    (1<<0)  /* SPI */
0707
0708 /*
0709  * Bits in transmit buffer descriptor status word
0710  * Many bits have the same meaning as those in receiver buffer descriptors.
0711  */
0712 #define M8xx_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
0713 #define M8xx_BD_PAD             (1<<14) /* Ethernet */
0714 #define M8xx_BD_CTS_REPORT      (1<<11) /* SCC UART */
0715 #define M8xx_BD_TX_CRC          (1<<10) /* Ethernet */
0716 #define M8xx_BD_DEFER           (1<<9)  /* Ethernet */
0717 #define M8xx_BD_HEARTBEAT       (1<<8)  /* Ethernet */
0718 #define M8xx_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
0719 #define M8xx_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
0720 #define M8xx_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
0721 #define M8xx_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
0722 #define M8xx_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
0723 #define M8xx_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI */
0724 #define M8xx_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
0725 #define M8xx_BD_CTS_LOST        (1<<0)  /* SCC UART */
0726
0727 /*
0728 *************************************************************************
0729 *                           IDMA Buffer Descriptors                     *
0730 *************************************************************************
0731 */
0732 typedef struct m8xxIDMABufferDescriptor_ {
0733   uint16_t          status;
0734   uint8_t           dfcr;
0735   uint8_t           sfcr;
0736   uint32_t          length;
0737   void                    *source;
0738   void                    *destination;
0739 } m8xxIDMABufferDescriptor_t;
0740
0741 /*
0742 *************************************************************************
0743 *       RISC Communication Processor Module Command Register (CR)       *
0744 *************************************************************************
0745 */
0746 #define M8xx_CR_RST             (1<<15) /* Reset communication processor */
0747 #define M8xx_CR_OP_INIT_RX_TX   (0<<8)  /* SCC, SMC UART, SMC GCI, SPI */
0748 #define M8xx_CR_OP_INIT_RX      (1<<8)  /* SCC, SMC UART, SPI */
0749 #define M8xx_CR_OP_INIT_TX      (2<<8)  /* SCC, SMC UART, SPI */
0750 #define M8xx_CR_OP_INIT_HUNT    (3<<8)  /* SCC, SMC UART */
0751 #define M8xx_CR_OP_STOP_TX      (4<<8)  /* SCC, SMC UART */
0752 #define M8xx_CR_OP_GR_STOP_TX   (5<<8)  /* SCC */
0753 #define M8xx_CR_OP_INIT_IDMA    (5<<8)  /* IDMA */
0754 #define M8xx_CR_OP_RESTART_TX   (6<<8)  /* SCC, SMC UART */
0755 #define M8xx_CR_OP_CLOSE_RX_BD  (7<<8)  /* SCC, SMC UART, SPI */
0756 #define M8xx_CR_OP_SET_GRP_ADDR (8<<8)  /* SCC */
0757 #define M8xx_CR_OP_SET_TIMER    (8<<8)  /* Timer */
0758 #define M8xx_CR_OP_GCI_TIMEOUT  (9<<8)  /* SMC GCI */
0759 #define M8xx_CR_OP_RESERT_BCS   (10<<8) /* SCC */
0760 #define M8xx_CR_OP_GCI_ABORT    (10<<8) /* SMC GCI */
0761 #define M8xx_CR_OP_STOP_IDMA    (11<<8) /* IDMA */
0762 #define M8xx_CR_OP_START_DSP    (12<<8) /* DSP */
0763 #define M8xx_CR_OP_INIT_DSP     (13<<8) /* DSP */
0764
0765 #define M8xx_CR_CHAN_SCC1       (0<<4)  /* Channel selection */
0766 #define M8xx_CR_CHAN_I2C        (1<<4)
0767 #define M8xx_CR_CHAN_IDMA1      (1<<4)
0768 #define M8xx_CR_CHAN_SCC2       (4<<4)
0769 #define M8xx_CR_CHAN_SPI        (5<<4)
0770 #define M8xx_CR_CHAN_IDMA2      (5<<4)
0771 #define M8xx_CR_CHAN_TIMER      (5<<4)
0772 #define M8xx_CR_CHAN_SCC3       (8<<4)
0773 #define M8xx_CR_CHAN_SMC1       (9<<4)
0774 #define M8xx_CR_CHAN_DSP1       (9<<4)
0775 #define M8xx_CR_CHAN_SCC4       (12<<4)
0776 #define M8xx_CR_CHAN_SMC2       (13<<4)
0777 #define M8xx_CR_CHAN_DSP2       (13<<4)
0778 #define M8xx_CR_FLG             (1<<0)  /* Command flag */
0779
0780 /*
0781 *************************************************************************
0782 *                 System Protection Control Register (SYPCR)            *
0783 *************************************************************************
0784 */
0785 #define M8xx_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
0786 #define M8xx_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
0787 #define M8xx_SYPCR_BME          (1<<7)      /* Bus monitor enable */
0788 #define M8xx_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
0789 #define M8xx_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
0790 #define M8xx_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
0791 #define M8xx_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
0792
0793 /*
0794 *************************************************************************
0795 *                 PCMCIA Control Registers
0796 *************************************************************************
0797 */
0798 #define M8xx_PCMCIA_POR_BSIZE_1B    (0x00 << (31-4))
0799 #define M8xx_PCMCIA_POR_BSIZE_2B    (0x01 << (31-4))
0800 #define M8xx_PCMCIA_POR_BSIZE_4B    (0x03 << (31-4))
0801 #define M8xx_PCMCIA_POR_BSIZE_8B    (0x02 << (31-4))
0802 #define M8xx_PCMCIA_POR_BSIZE_16B   (0x06 << (31-4))
0803 #define M8xx_PCMCIA_POR_BSIZE_32B   (0x07 << (31-4))
0804 #define M8xx_PCMCIA_POR_BSIZE_64B   (0x05 << (31-4))
0805 #define M8xx_PCMCIA_POR_BSIZE_128B  (0x04 << (31-4))
0806 #define M8xx_PCMCIA_POR_BSIZE_256B  (0x0C << (31-4))
0807 #define M8xx_PCMCIA_POR_BSIZE_512B  (0x0D << (31-4))
0808 #define M8xx_PCMCIA_POR_BSIZE_1KB   (0x0F << (31-4))
0809 #define M8xx_PCMCIA_POR_BSIZE_2KB   (0x0E << (31-4))
0810 #define M8xx_PCMCIA_POR_BSIZE_4KB   (0x0A << (31-4))
0811 #define M8xx_PCMCIA_POR_BSIZE_8KB   (0x0B << (31-4))
0812 #define M8xx_PCMCIA_POR_BSIZE_16KB  (0x09 << (31-4))
0813 #define M8xx_PCMCIA_POR_BSIZE_32KB  (0x08 << (31-4))
0814 #define M8xx_PCMCIA_POR_BSIZE_64KB  (0x18 << (31-4))
0815 #define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4))
0816 #define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4))
0817 #define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4))
0818 #define M8xx_PCMCIA_POR_BSIZE_1MB   (0x1E << (31-4))
0819 #define M8xx_PCMCIA_POR_BSIZE_2MB   (0x1F << (31-4))
0820 #define M8xx_PCMCIA_POR_BSIZE_4MB   (0x1D << (31-4))
0821 #define M8xx_PCMCIA_POR_BSIZE_8MB   (0x1C << (31-4))
0822 #define M8xx_PCMCIA_POR_BSIZE_16MB  (0x14 << (31-4))
0823 #define M8xx_PCMCIA_POR_BSIZE_32MB  (0x15 << (31-4))
0824 #define M8xx_PCMCIA_POR_BSIZE_64MB  (0x17 << (31-4))
0825
0826 #define M8xx_PCMCIA_POR_PSHT(x)     (((x) & 0x0f) << (31-15))
0827 #define M8xx_PCMCIA_POR_PSST(x)     (((x) & 0x0f) << (31-19))
0828 #define M8xx_PCMCIA_POR_PSL(x)      (((x) & 0x1f) << (31-24))
0829 #define M8xx_PCMCIA_POR_PPS_8       ((0) << (31-19))
0830 #define M8xx_PCMCIA_POR_PPS_16      ((1) << (31-19))
0831
0832 #define M8xx_PCMCIA_POR_PRS_MEM     ((0) << (31-28))
0833 #define M8xx_PCMCIA_POR_PRS_ATT     ((2) << (31-28))
0834 #define M8xx_PCMCIA_POR_PRS_IO      ((3) << (31-28))
0835 #define M8xx_PCMCIA_POR_PRS_DMA     ((4) << (31-28))
0836 #define M8xx_PCMCIA_POR_PRS_DML     ((5) << (31-28))
0837
0838 #define M8xx_PCMCIA_POR_PSLOT_A     ((0) << (31-29))
0839 #define M8xx_PCMCIA_POR_PSLOT_B     ((1) << (31-29))
0840
0841 #define M8xx_PCMCIA_POR_WP          ((1) << (31-30))
0842 #define M8xx_PCMCIA_POR_VALID       ((1) << (31-31))
0843
0844 #define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7))
0845 #define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15))
0846 #define M8xx_PCMCIA_PGCR_CDRQ_OFF    ((0) << (31-17))
0847 #define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17))
0848 #define M8xx_PCMCIA_PGCR_CDRQ_SPKR   ((3) << (31-17))
0849 #define M8xx_PCMCIA_PGCR_COE         ((1) << (31-24))
0850 #define M8xx_PCMCIA_PGCR_CRESET      ((1) << (31-25))
0851
0852 #define M8xx_PCMCIA_PIPR_CAVS1      ((1) << (31- 0))
0853 #define M8xx_PCMCIA_PIPR_CAVS2      ((1) << (31- 1))
0854 #define M8xx_PCMCIA_PIPR_CAWP       ((1) << (31- 2))
0855 #define M8xx_PCMCIA_PIPR_CACD2      ((1) << (31- 3))
0856 #define M8xx_PCMCIA_PIPR_CACD1      ((1) << (31- 4))
0857 #define M8xx_PCMCIA_PIPR_CABVD2     ((1) << (31- 5))
0858 #define M8xx_PCMCIA_PIPR_CABVD1     ((1) << (31- 6))
0859 #define M8xx_PCMCIA_PIPR_CARDY      ((1) << (31- 7))
0860 #define M8xx_PCMCIA_PIPR_CBVS1      ((1) << (31-16))
0861 #define M8xx_PCMCIA_PIPR_CBVS2      ((1) << (31-17))
0862 #define M8xx_PCMCIA_PIPR_CBWP       ((1) << (31-18))
0863 #define M8xx_PCMCIA_PIPR_CBCD2      ((1) << (31-19))
0864 #define M8xx_PCMCIA_PIPR_CBCD1      ((1) << (31-20))
0865 #define M8xx_PCMCIA_PIPR_CBBVD2     ((1) << (31-21))
0866 #define M8xx_PCMCIA_PIPR_CBBVD1     ((1) << (31-22))
0867 #define M8xx_PCMCIA_PIPR_CBRDY      ((1) << (31-23))
0868
0869
0870 #define M8xx_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
0871 #define M8xx_SYPCR_BME          (1<<7)      /* Bus monitor enable */
0872 #define M8xx_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
0873 #define M8xx_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
0874 #define M8xx_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
0875 #define M8xx_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
0876
0877 /*
0878 *************************************************************************
0879 *                        Memory Control Registers                       *
0880 *************************************************************************
0881 */
0882 #define M8xx_UPM_AMX_8col       (0<<20) /* 8 column DRAM */
0883 #define M8xx_UPM_AMX_9col       (1<<20) /* 9 column DRAM */
0884 #define M8xx_UPM_AMX_10col      (2<<20) /* 10 column DRAM */
0885 #define M8xx_UPM_AMX_11col      (3<<20) /* 11 column DRAM */
0886 #define M8xx_UPM_AMX_12col      (4<<20) /* 12 column DRAM */
0887 #define M8xx_UPM_AMX_13col      (5<<20) /* 13 column DRAM */
0888 #define M8xx_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
0889 #define M8xx_MSR_WPER           (1<<7)  /* Write protection error */
0890 #define M8xx_MPTPR_PTP(x)       ((x)<<8) /* Periodic timer prescaler */
0891 #define M8xx_BR_BA(x)           ((x)&0xffff8000) /* Base address */
0892 #define M8xx_BR_AT(x)           ((x)<<12) /* Address type */
0893 #define M8xx_BR_PS8             (1<<10)  /* 8 bit port */
0894 #define M8xx_BR_PS16            (2<<10)  /* 16 bit port */
0895 #define M8xx_BR_PS32            (0<<10)  /* 32 bit port */
0896 #define M8xx_BR_PARE            (1<<9)   /* Parity checking enable */
0897 #define M8xx_BR_WP              (1<<8)   /* Write protect */
0898 #define M8xx_BR_MS_GPCM         (0<<6)   /* GPCM */
0899 #define M8xx_BR_MS_UPMA         (2<<6)   /* UPM A */
0900 #define M8xx_BR_MS_UPMB         (3<<6)   /* UPM B */
0901 #define M8xx_MEMC_BR_V          (1<<0)  /* Base/Option register are valid */
0902
0903 #define M8xx_MEMC_OR_32K        0xffff8000      /* Address range */
0904 #define M8xx_MEMC_OR_64K        0xffff0000
0905 #define M8xx_MEMC_OR_128K       0xfffe0000
0906 #define M8xx_MEMC_OR_256K       0xfffc0000
0907 #define M8xx_MEMC_OR_512K       0xfff80000
0908 #define M8xx_MEMC_OR_1M         0xfff00000
0909 #define M8xx_MEMC_OR_2M         0xffe00000
0910 #define M8xx_MEMC_OR_4M         0xffc00000
0911 #define M8xx_MEMC_OR_8M         0xff800000
0912 #define M8xx_MEMC_OR_16M        0xff000000
0913 #define M8xx_MEMC_OR_32M        0xfe000000
0914 #define M8xx_MEMC_OR_64M        0xfc000000
0915 #define M8xx_MEMC_OR_128        0xf8000000
0916 #define M8xx_MEMC_OR_256M       0xf0000000
0917 #define M8xx_MEMC_OR_512M       0xe0000000
0918 #define M8xx_MEMC_OR_1G         0xc0000000
0919 #define M8xx_MEMC_OR_2G         0x80000000
0920 #define M8xx_MEMC_OR_4G         0x00000000
0921 #define M8xx_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
0922 #define M8xx_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
0923 #define M8xx_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
0924 #define M8xx_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
0925 #define M8xx_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
0926 #define M8xx_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
0927 #define M8xx_MEMC_OR_BI         (1<<8)      /* Burst inhibit */
0928 #define M8xx_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
0929 #define M8xx_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
0930 #define M8xx_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
0931 #define M8xx_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */
0932
0933 /*
0934 *************************************************************************
0935 *                         UPM Registers (MxMR)                          *
0936 *************************************************************************
0937 */
0938 #define M8xx_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
0939 #define M8xx_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
0940 #define M8xx_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
0941 #define M8xx_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
0942 #define M8xx_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
0943 #define M8xx_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
0944 #define M8xx_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
0945 #define M8xx_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
0946 /*
0947 *************************************************************************
0948 *                         Memory Command Register (MCR)                 *
0949 *************************************************************************
0950 */
0951 #define M8xx_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
0952 #define M8xx_MEMC_MCR_READ      (1<<30)     /* READ command */
0953 #define M8xx_MEMC_MCR_RUN       (2<<30)     /* RUN command */
0954 #define M8xx_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
0955 #define M8xx_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
0956 #define M8xx_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
0957 #define M8xx_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
0958 #define M8xx_MEMC_MCR_MAD(x)    (x)         /* Machine address */
0959
0960
0961
0962 /*
0963 *************************************************************************
0964 *                         SI Mode Register (SIMODE)                     *
0965 *************************************************************************
0966 */
0967 #define M8xx_SI_SMC2_BITS       0xFFFF0000      /* All SMC2 bits */
0968 #define M8xx_SI_SMC2_TDM        (1<<31) /* Multiplexed SMC2 */
0969 #define M8xx_SI_SMC2_BRG1       (0<<28) /* SMC2 clock souce */
0970 #define M8xx_SI_SMC2_BRG2       (1<<28)
0971 #define M8xx_SI_SMC2_BRG3       (2<<28)
0972 #define M8xx_SI_SMC2_BRG4       (3<<28)
0973 #define M8xx_SI_SMC2_CLK5       (0<<28)
0974 #define M8xx_SI_SMC2_CLK6       (1<<28)
0975 #define M8xx_SI_SMC2_CLK7       (2<<28)
0976 #define M8xx_SI_SMC2_CLK8       (3<<28)
0977 #define M8xx_SI_SMC1_BITS       0x0000FFFF      /* All SMC1 bits */
0978 #define M8xx_SI_SMC1_TDM        (1<<15) /* Multiplexed SMC1 */
0979 #define M8xx_SI_SMC1_BRG1       (0<<12) /* SMC1 clock souce */
0980 #define M8xx_SI_SMC1_BRG2       (1<<12)
0981 #define M8xx_SI_SMC1_BRG3       (2<<12)
0982 #define M8xx_SI_SMC1_BRG4       (3<<12)
0983 #define M8xx_SI_SMC1_CLK1       (0<<12)
0984 #define M8xx_SI_SMC1_CLK2       (1<<12)
0985 #define M8xx_SI_SMC1_CLK3       (2<<12)
0986 #define M8xx_SI_SMC1_CLK4       (3<<12)
0987
0988 /*
0989 *************************************************************************
0990 *                  SDMA Configuration Register (SDCR)                   *
0991 *************************************************************************
0992 */
0993 #define M8xx_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
0994 #define M8xx_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */
0995
0996 /*
0997 *************************************************************************
0998 *                  SDMA Status Register (SDSR)                          *
0999 *************************************************************************
1000 */
1001 #define M8xx_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
1002 #define M8xx_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
1003 #define M8xx_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */
1004
1005 /*
1006 *************************************************************************
1007 *                      Baud (sic) Rate Generators                       *
1008 *************************************************************************
1009 */
1010 #define M8xx_BRG_RST            (1<<17)         /* Reset generator */
1011 #define M8xx_BRG_EN             (1<<16)         /* Enable generator */
1012 #define M8xx_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
1013 #define M8xx_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
1014 #define M8xx_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
1015 #define M8xx_BRG_ATB            (1<<13)         /* Autobaud */
1016 #define M8xx_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
1017 #define M8xx_BRG_57600          (32<<1)
1018 #define M8xx_BRG_38400          (64<<1)
1019 #define M8xx_BRG_19200          (129<<1)
1020 #define M8xx_BRG_9600           (259<<1)
1021 #define M8xx_BRG_4800           (520<<1)
1022 #define M8xx_BRG_2400           (1040<<1)
1023 #define M8xx_BRG_1200           (2082<<1)
1024 #define M8xx_BRG_600            ((259<<1) | 1)
1025 #define M8xx_BRG_300            ((520<<1) | 1)
1026 #define M8xx_BRG_150            ((1040<<1) | 1)
1027 #define M8xx_BRG_75             ((2080<<1) | 1)
1028
1029 #define M8xx_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
1030 #define M8xx_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
1031 #define M8xx_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
1032 #define M8xx_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
1033 #define M8xx_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
1034 #define M8xx_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
1035 #define M8xx_TGCR_STP1          (1<<1)    /* Stop timer */
1036 #define M8xx_TGCR_STP2          (1<<5)    /* Stop timer */
1037 #define M8xx_TGCR_STP3          (1<<9)    /* Stop timer */
1038 #define M8xx_TGCR_STP4          (1<<13)   /* Stop timer */
1039 #define M8xx_TGCR_RST1          (1<<0)    /* Enable timer */
1040 #define M8xx_TGCR_RST2          (1<<4)    /* Enable timer */
1041 #define M8xx_TGCR_RST3          (1<<8)    /* Enable timer */
1042 #define M8xx_TGCR_RST4          (1<<12)   /* Enable timer */
1043 #define M8xx_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
1044 #define M8xx_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */
1045
1046 #define M8xx_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
1047 #define M8xx_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
1048 #define M8xx_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
1049 #define M8xx_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
1050 #define M8xx_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
1051 #define M8xx_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
1052 #define M8xx_TMR_RESTART        (1<<3)    /* Restart timer after reference */
1053 #define M8xx_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
1054 #define M8xx_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
1055 #define M8xx_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
1056 #define M8xx_TMR_TGATE          (1<<0)    /* TGATE controls timer */
1057
1058 #define M8xx_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
1059 #define M8xx_PISCR_PS           (1<<7)    /* PIT Interrupt state */
1060 #define M8xx_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
1061 #define M8xx_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
1062 #define M8xx_PISCR_PTE          (1<<0)    /* PIT enable */
1063
1064 #define M8xx_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
1065 #define M8xx_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
1066 #define M8xx_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
1067 #define M8xx_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
1068 #define M8xx_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
1069 #define M8xx_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
1070 #define M8xx_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
1071
1072 #define M8xx_SIMASK_IRM0        (1<<31)
1073 #define M8xx_SIMASK_LVM0        (1<<30)
1074 #define M8xx_SIMASK_IRM1        (1<<29)
1075 #define M8xx_SIMASK_LVM1        (1<<28)
1076 #define M8xx_SIMASK_IRM2        (1<<27)
1077 #define M8xx_SIMASK_LVM2        (1<<26)
1078 #define M8xx_SIMASK_IRM3        (1<<25)
1079 #define M8xx_SIMASK_LVM3        (1<<24)
1080 #define M8xx_SIMASK_IRM4        (1<<23)
1081 #define M8xx_SIMASK_LVM4        (1<<22)
1082 #define M8xx_SIMASK_IRM5        (1<<21)
1083 #define M8xx_SIMASK_LVM5        (1<<20)
1084 #define M8xx_SIMASK_IRM6        (1<<19)
1085 #define M8xx_SIMASK_LVM6        (1<<18)
1086 #define M8xx_SIMASK_IRM7        (1<<17)
1087 #define M8xx_SIMASK_LVM7        (1<<16)
1088
1089 #define M8xx_SIUMCR_EARB        (1<<31)
1090 #define M8xx_SIUMCR_EARP0       (0<<28)
1091 #define M8xx_SIUMCR_EARP1       (1<<28)
1092 #define M8xx_SIUMCR_EARP2       (2<<28)
1093 #define M8xx_SIUMCR_EARP3       (3<<28)
1094 #define M8xx_SIUMCR_EARP4       (4<<28)
1095 #define M8xx_SIUMCR_EARP5       (5<<28)
1096 #define M8xx_SIUMCR_EARP6       (6<<28)
1097 #define M8xx_SIUMCR_EARP7       (7<<28)
1098 #define M8xx_SIUMCR_DSHW        (1<<23)
1099 #define M8xx_SIUMCR_DBGC0       (0<<21)
1100 #define M8xx_SIUMCR_DBGC1       (1<<21)
1101 #define M8xx_SIUMCR_DBGC2       (2<<21)
1102 #define M8xx_SIUMCR_DBGC3       (3<<21)
1103 #define M8xx_SIUMCR_DBPC0       (0<<19)
1104 #define M8xx_SIUMCR_DBPC1       (1<<19)
1105 #define M8xx_SIUMCR_DBPC2       (2<<19)
1106 #define M8xx_SIUMCR_DBPC3       (3<<19)
1107 #define M8xx_SIUMCR_FRC         (1<<17)
1108 #define M8xx_SIUMCR_DLK         (1<<16)
1109 #define M8xx_SIUMCR_PNCS        (1<<15)
1110 #define M8xx_SIUMCR_OPAR        (1<<14)
1111 #define M8xx_SIUMCR_DPC         (1<<13)
1112 #define M8xx_SIUMCR_MPRE        (1<<12)
1113 #define M8xx_SIUMCR_MLRC0       (0<<10)
1114 #define M8xx_SIUMCR_MLRC1       (1<<10)
1115 #define M8xx_SIUMCR_MLRC2       (2<<10)
1116 #define M8xx_SIUMCR_MLRC3       (3<<10)
1117 #define M8xx_SIUMCR_AEME        (1<<9)
1118 #define M8xx_SIUMCR_SEME        (1<<8)
1119 #define M8xx_SIUMCR_BSC         (1<<7)
1120 #define M8xx_SIUMCR_GB5E        (1<<6)
1121 #define M8xx_SIUMCR_B2DD        (1<<5)
1122 #define M8xx_SIUMCR_B3DD        (1<<4)
1123
1124 /*
1125  *  Value to write to a key register to unlock the corresponding SIU register
1126  */
1127 #define M8xx_UNLOCK_KEY         0x55CCAA33
1128
1129 /*
1130 *************************************************************************
1131 *   MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address)   *
1132 *************************************************************************
1133 */
1134 typedef struct m8xx_ {
1135
1136   /*
1137    * SIU Block
1138    */
1139   uint32_t        siumcr;
1140   uint32_t        sypcr;
1141 #if defined(mpc860)
1142   uint32_t        swt;
1143 #elif defined(mpc821)
1144   uint32_t        _pad70;
1145 #endif
1146   uint16_t        _pad0;
1147   uint16_t        swsr;
1148   uint32_t        sipend;
1149   uint32_t        simask;
1150   uint32_t        siel;
1151   uint32_t        sivec;
1152   uint32_t        tesr;
1153   uint32_t        _pad1[3];
1154   uint32_t        sdcr;
1155   uint8_t         _pad2[0x80-0x34];
1156
1157   /*
1158    * PCMCIA Block
1159    */
1160   uint32_t        pbr0;
1161   uint32_t        por0;
1162   uint32_t        pbr1;
1163   uint32_t        por1;
1164   uint32_t        pbr2;
1165   uint32_t        por2;
1166   uint32_t        pbr3;
1167   uint32_t        por3;
1168   uint32_t        pbr4;
1169   uint32_t        por4;
1170   uint32_t        pbr5;
1171   uint32_t        por5;
1172   uint32_t        pbr6;
1173   uint32_t        por6;
1174   uint32_t        pbr7;
1175   uint32_t        por7;
1176   uint8_t         _pad3[0xe0-0xc0];
1177   uint32_t        pgcra;
1178   uint32_t        pgcrb;
1179   uint32_t        pscr;
1180   uint32_t        _pad4;
1181   uint32_t        pipr;
1182   uint32_t        _pad5;
1183   uint32_t        per;
1184   uint32_t        _pad6;
1185
1186   /*
1187    * MEMC Block
1188    */
1189   m8xxMEMCRegisters_t   memc[8];
1190   uint8_t         _pad7[0x164-0x140];
1191   uint32_t        mar;
1192   uint32_t        mcr;
1193   uint32_t        _pad8;
1194   uint32_t        mamr;
1195   uint32_t        mbmr;
1196   uint16_t        mstat;
1197   uint16_t        mptpr;
1198   uint32_t        mdr;
1199   uint8_t         _pad9[0x200-0x180];
1200
1201   /*
1202    * System integration timers
1203    */
1204   uint16_t        tbscr;
1205   uint16_t        _pad10;
1206   uint32_t        tbreff0;
1207   uint32_t        tbreff1;
1208   uint8_t         _pad11[0x220-0x20c];
1209   uint16_t        rtcsc;
1210   uint16_t        _pad12;
1211   uint32_t        rtc;
1212   uint32_t        rtsec;
1213   uint32_t        rtcal;
1214   uint32_t        _pad13[4];
1215   uint16_t        piscr;
1216   uint16_t        _pad14;
1217   uint16_t        pitc;
1218   uint16_t        _pad_14_1;
1219   uint16_t        pitr;
1220   uint16_t        _pad_14_2;
1221   uint8_t         _pad15[0x280-0x24c];
1222
1223
1224   /*
1225    * Clocks and Reset
1226    */
1227   uint32_t        sccr;
1228   uint32_t        plprcr;
1229   uint32_t        rsr;
1230   uint8_t         _pad16[0x300-0x28c];
1231
1232
1233   /*
1234    * System integration timers keys
1235    */
1236   uint32_t        tbscrk;
1237   uint32_t        tbreff0k;
1238   uint32_t        tbreff1k;
1239   uint32_t        tbk;
1240   uint32_t        _pad17[4];
1241   uint32_t        rtcsk;
1242   uint32_t        rtck;
1243   uint32_t        rtseck;
1244   uint32_t        rtcalk;
1245   uint32_t        _pad18[4];
1246   uint32_t        piscrk;
1247   uint32_t        pitck;
1248   uint8_t         _pad19[0x380-0x348];
1249
1250   /*
1251    * Clocks and Reset Keys
1252    */
1253   uint32_t        sccrk;
1254   uint32_t        plprck;
1255   uint32_t        rsrk;
1256   uint8_t         _pad20[0x400-0x38c];
1257   uint8_t         _pad21[0x800-0x400];
1258   uint8_t         _pad22[0x860-0x800];
1259
1260
1261   /*
1262    * I2C
1263    */
1264   uint8_t         i2mod;
1265   uint8_t         _pad23[3];
1266   uint8_t         i2add;
1267   uint8_t         _pad24[3];
1268   uint8_t         i2brg;
1269   uint8_t         _pad25[3];
1270   uint8_t         i2com;
1271   uint8_t         _pad26[3];
1272   uint8_t         i2cer;
1273   uint8_t         _pad27[3];
1274   uint8_t         i2cmr;
1275   uint8_t         _pad28[0x900-0x875];
1276
1277   /*
1278    * DMA Block
1279    */
1280   uint32_t        _pad29;
1281   uint32_t        sdar;
1282   uint8_t         sdsr;
1283   uint8_t         _pad30[3];
1284   uint8_t         sdmr;
1285   uint8_t         _pad31[3];
1286   uint8_t         idsr1;
1287   uint8_t         _pad32[3];
1288   uint8_t         idmr1;
1289   uint8_t         _pad33[3];
1290   uint8_t         idsr2;
1291   uint8_t         _pad34[3];
1292   uint8_t         idmr2;
1293   uint8_t         _pad35[0x930-0x91d];
1294
1295   /*
1296    * CPM Interrupt Control Block
1297    */
1298   uint16_t        civr;
1299   uint8_t         _pad36[14];
1300   uint32_t        cicr;
1301   uint32_t        cipr;
1302   uint32_t        cimr;
1303   uint32_t        cisr;
1304
1305   /*
1306    * I/O Port Block
1307    */
1308   uint16_t        padir;
1309   uint16_t        papar;
1310   uint16_t        paodr;
1311   uint16_t        padat;
1312   uint8_t         _pad37[8];
1313   uint16_t        pcdir;
1314   uint16_t        pcpar;
1315   uint16_t        pcso;
1316   uint16_t        pcdat;
1317   uint16_t        pcint;
1318   uint8_t         _pad39[6];
1319   uint16_t        pddir;
1320   uint16_t        pdpar;
1321   uint16_t        _pad40;
1322   uint16_t        pddat;
1323   uint8_t         _pad41[8];
1324
1325   /*
1326    * CPM Timers Block
1327    */
1328   uint16_t        tgcr;
1329   uint8_t         _pad42[14];
1330   uint16_t        tmr1;
1331   uint16_t        tmr2;
1332   uint16_t        trr1;
1333   uint16_t        trr2;
1334   uint16_t        tcr1;
1335   uint16_t        tcr2;
1336   uint16_t        tcn1;
1337   uint16_t        tcn2;
1338   uint16_t        tmr3;
1339   uint16_t        tmr4;
1340   uint16_t        trr3;
1341   uint16_t        trr4;
1342   uint16_t        tcr3;
1343   uint16_t        tcr4;
1344   uint16_t        tcn3;
1345   uint16_t        tcn4;
1346   uint16_t        ter1;
1347   uint16_t        ter2;
1348   uint16_t        ter3;
1349   uint16_t        ter4;
1350   uint8_t         _pad43[8];
1351
1352   /*
1353    * CPM Block
1354    */
1355   uint16_t        cpcr;
1356   uint16_t        _pad44;
1357   uint16_t        rccr;
1358   uint8_t         _pad45;
1359   uint8_t         rmds;
1360   uint32_t        rmdr;
1361   uint16_t        rctr1;
1362   uint16_t        rctr2;
1363   uint16_t        rctr3;
1364   uint16_t        rctr4;
1365   uint16_t        _pad46;
1366   uint16_t        rter;
1367   uint16_t        _pad47;
1368   uint16_t        rtmr;
1369   uint8_t         _pad48[0x9f0-0x9dc];
1370
1371   /*
1372    * BRG Block
1373    */
1374   uint32_t        brgc1;
1375   uint32_t        brgc2;
1376   uint32_t        brgc3;
1377   uint32_t        brgc4;
1378
1379   /*
1380    * SCC Block
1381    */
1382   m8xxSCCRegisters_t    scc1;
1383   m8xxSCCRegisters_t    scc2;
1384 #if defined(mpc860)
1385   m8xxSCCRegisters_t    scc3;
1386   m8xxSCCRegisters_t    scc4;
1387 #elif defined(mpc821)
1388   uint8_t   _pad72[0xa80-0xa40];
1389 #endif
1390
1391   /*
1392    * SMC Block
1393    */
1394   m8xxSMCRegisters_t    smc1;
1395   m8xxSMCRegisters_t    smc2;
1396
1397   /*
1398    * SPI Block
1399    */
1400   uint16_t        spmode;
1401   uint16_t        _pad49[2];
1402   uint8_t         spie;
1403   uint8_t         _pad50;
1404   uint16_t        _pad51;
1405   uint8_t         spim;
1406   uint8_t         _pad52[2];
1407   uint8_t         spcom;
1408   uint16_t        _pad53[2];
1409
1410   /*
1411    * PIP Block
1412    */
1413   uint16_t        pipc;
1414   uint16_t        _pad54;
1415   uint16_t        ptpr;
1416   uint32_t        pbdir;
1417   uint32_t        pbpar;
1418   uint16_t        _pad55;
1419   uint16_t        pbodr;
1420   uint32_t        pbdat;
1421   uint32_t        _pad56[6];
1422
1423   /*
1424    * SI Block
1425    */
1426   uint32_t        simode;
1427   uint8_t         sigmr;
1428   uint8_t         _pad57;
1429   uint8_t         sistr;
1430   uint8_t         sicmr;
1431   uint32_t        _pad58;
1432   uint32_t        sicr;
1433   uint16_t        sirp[2];
1434   uint32_t        _pad59[3];
1435   uint8_t         _pad60[0xc00-0xb00];
1436   uint8_t         siram[512];
1437 #if defined(mpc860)
1438   /*
1439    * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC)
1440    */
1441   m8xxFECRegisters_t    fec;
1442 #elif defined(mpc821)
1443   uint8_t         lcdram[512];
1444 #endif
1445   uint8_t         _pad62[0x2000-0x1000];
1446
1447   /*
1448    * Dual-port RAM
1449    */
1450   uint8_t         dpram0[0x200];  /* BD/DATA/UCODE */
1451   uint8_t         dpram1[0x200];  /* BD/DATA/UCODE */
1452   uint8_t         dpram2[0x400];  /* BD/DATA/UCODE */
1453   uint8_t         dpram3[0x600];  /* BD/DATA*/
1454   uint8_t         dpram4[0x200];  /* BD/DATA/UCODE */
1455   uint8_t         _pad63[0x3c00-0x3000];
1456
1457   /* When using SCC1 for ethernet, we lose the use of I2C since
1458    *  their parameters would overlap. Motorola has a microcode
1459    *  patch to move parameters around so that both can be used
1460    *  together. It is available on their web site somewhere
1461    *  under http://www.mot.com/mpc8xx. If ethernet is used on
1462    *  one (or more) of the other SCCs, then other CPM features
1463    *  will be unavailable:
1464    *    SCC2    -> lose SPI
1465    *    SCC3    -> lose SMC1
1466    *    SCC4    -> lose SMC2
1467    *  However, Ethernet only works on SCC1 on the 8xx.
1468    */
1469   m8xxSCCENparms_t      scc1p;
1470   uint8_t         _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)];
1471   m8xxMiscParms_t       miscp;
1472   uint8_t         _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)];
1473   m8xxIDMAparms_t       idma1p;
1474   uint8_t         _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)];
1475
1476   m8xxSCCparms_t        scc2p;
1477   uint8_t         _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)];
1478   m8xxSPIparms_t        spip;
1479   uint8_t         _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)];
1480   m8xxTimerParms_t      tmp;
1481   uint8_t         _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)];
1482   m8xxIDMAparms_t       idma2p;
1483   uint8_t         _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)];
1484
1485   m8xxSCCparms_t        scc3p; /* Not available on MPC821 */
1486   uint8_t         _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)];
1487   m8xxSMCparms_t        smc1p;
1488   uint8_t         _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)];
1489   m8xxDSPparms_t        dsp1p;
1490   uint8_t         _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)];
1491
1492   m8xxSCCparms_t        scc4p; /* Not available on MPC821 */
1493   uint8_t         _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)];
1494   m8xxSMCparms_t        smc2p;
1495   uint8_t         _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)];
1496   m8xxDSPparms_t        dsp2p;
1497   uint8_t         _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)];
1498 } m8xx_t;
1499
1500 extern volatile m8xx_t m8xx;
1501
1502 #ifdef __cplusplus
1503 }
1504 #endif
1505
1506 #endif /* ASM */
1507
1508 #endif /* _MPC8XX_H */