File indexing completed on 2025-05-11 08:23:53
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0014 #ifndef _MPC8260_CPM_H
0015 #define _MPC8260_CPM_H
0016
0017 #ifdef __cplusplus
0018 extern "C" {
0019 #endif
0020
0021
0022 #define M8xx_BRG_1 (1U << 0)
0023 #define M8xx_BRG_2 (1U << 1)
0024 #define M8xx_BRG_3 (1U << 2)
0025 #define M8xx_BRG_4 (1U << 3)
0026 #define M8xx_BRG_5 (1U << 4)
0027 #define M8xx_BRG_6 (1U << 5)
0028 #define M8xx_BRG_7 (1U << 6)
0029 #define M8xx_BRG_8 (1U << 7)
0030
0031
0032 #define M8260_SCC_BRGS (M8xx_BRG_1 | M8xx_BRG_2 | M8xx_BRG_3 | M8xx_BRG_4)
0033 #define M8260_FCC_BRGS (M8xx_BRG_5 | M8xx_BRG_6 | M8xx_BRG_7 | M8xx_BRG_8)
0034 #define M8260_SMC1_BRGS (M8xx_BRG_1|M8xx_BRG_7)
0035 #define M8260_SMC2_BRGS (M8xx_BRG_2|M8xx_BRG_8)
0036
0037
0038 #define M8xx_CLK_1 (1U << 0)
0039 #define M8xx_CLK_2 (1U << 1)
0040 #define M8xx_CLK_3 (1U << 2)
0041 #define M8xx_CLK_4 (1U << 3)
0042 #define M8xx_CLK_5 (1U << 4)
0043 #define M8xx_CLK_6 (1U << 5)
0044 #define M8xx_CLK_7 (1U << 6)
0045 #define M8xx_CLK_8 (1U << 7)
0046 #define M8xx_CLK_9 (1U << 8)
0047 #define M8xx_CLK_10 (1U << 9)
0048 #define M8xx_CLK_11 (1U << 10)
0049 #define M8xx_CLK_12 (1U << 11)
0050 #define M8xx_CLK_13 (1U << 12)
0051 #define M8xx_CLK_14 (1U << 13)
0052 #define M8xx_CLK_15 (1U << 14)
0053 #define M8xx_CLK_16 (1U << 15)
0054 #define M8xx_CLK_17 (1U << 16)
0055 #define M8xx_CLK_18 (1U << 17)
0056 #define M8xx_CLK_19 (1U << 18)
0057 #define M8xx_CLK_20 (1U << 19)
0058
0059 #define M8260_BRG1_CLKS (M8xx_CLK_3 | M8xx_CLK_5 )
0060 #define M8260_BRG2_CLKS (M8xx_CLK_3 | M8xx_CLK_5 )
0061 #define M8260_BRG3_CLKS (M8xx_CLK_9 | M8xx_CLK_15 )
0062 #define M8260_BRG4_CLKS (M8xx_CLK_9 | M8xx_CLK_15 )
0063 #define M8260_BRG5_CLKS (M8xx_CLK_3 | M8xx_CLK_5 )
0064 #define M8260_BRG6_CLKS (M8xx_CLK_3 | M8xx_CLK_5 )
0065 #define M8260_BRG7_CLKS (M8xx_CLK_9 | M8xx_CLK_15 )
0066 #define M8260_BRG8_CLKS (M8xx_CLK_9 | M8xx_CLK_15 )
0067
0068 #define M8260_SCC1_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12)
0069 #define M8260_SCC2_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12)
0070 #define M8260_SCC3_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 )
0071 #define M8260_SCC4_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 )
0072
0073 #define M8260_FCC1_CLKS (M8xx_CLK_9 | M8xx_CLK_10 | M8xx_CLK_11 | M8xx_CLK_12)
0074 #define M8260_FCC2_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16)
0075 #define M8260_FCC3_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16)
0076
0077 #define M8260_TDM_RXA1 (M8xx_CLK_1 | M8xx_CLK_19 )
0078 #define M8260_TDM_RXB1 (M8xx_CLK_3 | M8xx_CLK_9 )
0079 #define M8260_TDM_RXC1 (M8xx_CLK_5 | M8xx_CLK_13 )
0080 #define M8260_TDM_RXD1 (M8xx_CLK_7 | M8xx_CLK_15 )
0081 #define M8260_TDM_TXA1 (M8xx_CLK_2 | M8xx_CLK_20 )
0082 #define M8260_TDM_TXB1 (M8xx_CLK_4 | M8xx_CLK_10 )
0083 #define M8260_TDM_TXC1 (M8xx_CLK_6 | M8xx_CLK_14 )
0084 #define M8260_TDM_TXD1 (M8xx_CLK_8 | M8xx_CLK_16 )
0085
0086 #define M8260_TDM_RXA2 (M8xx_CLK_13 | M8xx_CLK_5 )
0087 #define M8260_TDM_RXB2 (M8xx_CLK_15 | M8xx_CLK_17 )
0088 #define M8260_TDM_RXC2 (M8xx_CLK_3 | M8xx_CLK_17 )
0089 #define M8260_TDM_RXD2 (M8xx_CLK_1 | M8xx_CLK_19 )
0090 #define M8260_TDM_TXA2 (M8xx_CLK_14 | M8xx_CLK_6 )
0091 #define M8260_TDM_TXB2 (M8xx_CLK_16 | M8xx_CLK_18 )
0092 #define M8260_TDM_TXC2 (M8xx_CLK_4 | M8xx_CLK_18 )
0093 #define M8260_TDM_TXD2 (M8xx_CLK_2 | M8xx_CLK_20 )
0094
0095
0096
0097
0098
0099 void m8xx_cp_execute_cmd( uint32_t command );
0100 void *m8xx_dpram_allocate( unsigned int byte_count );
0101
0102 #define m8xx_bd_allocate(count) \
0103 m8xx_dpram_allocate( (count) * sizeof(m8260BufferDescriptor_t) )
0104 #define m8xx_RISC_timer_table_allocate(count) \
0105 m8xx_dpram_allocate( (count) * 4 )
0106
0107
0108
0109 int m8xx_get_brg_cd (int baud);
0110 int m8xx_get_brg(unsigned brgmask, int baud);
0111 void m8xx_free_brg(int brg_num);
0112
0113
0114 int m8xx_get_clk( unsigned clkmask );
0115 void m8xx_free_clk( int clk_num );
0116
0117
0118 #ifdef __cplusplus
0119 }
0120 #endif
0121
0122 #endif
0123