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File indexing completed on 2025-05-11 08:23:54 

0001 /* buggy version of CPU */
0002 #define REV_0_2
0003 
0004 /*
0005 **************************************************************************
0006 **************************************************************************
0007 **                                                                      **
0008 **  MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER    **
0009 **                             POWERQUICC II                            **
0010 **                                                                      **
0011 **                        HARDWARE DECLARATIONS                         **
0012 **                                                                      **
0013 **                                                                      **
0014 **  Submitted by:                           **
0015 **      Andy Dachs                          **                          **
0016 **  Surrey Satellite Technology Limited             **                  **
0017 **  http://www.sstl.co.uk                       **                      **
0018 **  a.dachs@sstl.co.uk                      **                              **
0019 **                                                                      **
0020 **  Based on previous submissions for other PPC variants by:            **
0021 **                                      **
0022 **  Submitted By:                                                       **
0023 **                                                                      **
0024 **      Eric Norum <eric.norum.ca>                                      **
0025 **                                                                      **
0026 **  Modified for use with the MPC860 (original code was for MC68360)    **
0027 **  by                                                                  **
0028 **      Jay Monkman                                                     **
0029 **      Frasca International, Inc.                                      **
0030 **      906 E. Airport Rd.                                              **
0031 **      Urbana, IL, 61801                                               **
0032 **                                                                      **
0033 **      jmonkman@frasca.com                                             **
0034 **                                                                      **
0035 **                                                                      **
0036 **************************************************************************
0037 **************************************************************************
0038 */
0039 
0040 #ifndef _MPC8260_H
0041 #define _MPC8260_H
0042 
0043 #ifndef ASM
0044 /*
0045   Macros for SPRs
0046 */
0047 
0048 
0049 
0050 
0051 /*
0052 *************************************************************************
0053 *                         REGISTER SUBBLOCKS                            *
0054 *************************************************************************
0055 */
0056 
0057 
0058 /*
0059  * Memory controller registers
0060  */
0061 typedef struct m8260MEMCRegisters_ {
0062   uint32_t          br;
0063   uint32_t          _or;  /* or is a C++ keyword :( */
0064 } m8260MEMCRegisters_t;
0065 
0066 
0067 /*
0068  * Fast Communication Controller Registers
0069 */
0070 typedef struct m8260FCCRegisters_ {
0071   uint32_t      gfmr;
0072   uint32_t        fpsmr;
0073   uint16_t        ftodr;
0074   uint8_t     fcc_pad0[2];
0075   uint16_t        fdsr;
0076   uint8_t     fcc_pad1[2];
0077   uint32_t        fcce;
0078   uint32_t        fccm;
0079   uint8_t     fccs;
0080   uint8_t     fcc_pad2[3];
0081   uint8_t     ftirr_phy0;           /* n/a on FCC3 */
0082   uint8_t     ftirr_phy1;           /* n/a on FCC3 */
0083   uint8_t     ftirr_phy2;           /* n/a on FCC3 */
0084   uint8_t     ftirr_phy3;           /* n/a on FCC3 */
0085 } m8260FCCRegisters_t;
0086 
0087 
0088 /*
0089  * Serial Communications Controller registers
0090  */
0091 typedef struct m8260SCCRegisters_ {
0092   uint32_t          gsmr_l;
0093   uint32_t          gsmr_h;
0094   uint16_t          psmr;
0095   uint8_t           scc_pad0[2];
0096   uint16_t          todr;
0097   uint16_t          dsr;
0098   uint16_t          scce;
0099   uint8_t     scc_pad2[2];
0100   uint16_t          sccm;
0101   uint8_t     scc_pad3[1];
0102   uint8_t           sccs;
0103   uint8_t           scc_pad1[8];
0104 } m8260SCCRegisters_t;
0105 
0106 /*
0107  * Serial Management Controller registers
0108  */
0109 typedef struct m8260SMCRegisters_ {
0110   uint8_t           smc_pad0[2];
0111   uint16_t          smcmr;
0112   uint8_t     smc_pad2[2];
0113   uint8_t           smce;
0114   uint8_t     smc_pad3[3];
0115   uint8_t           smcm;
0116   uint8_t           smc_pad1[5];
0117 } m8260SMCRegisters_t;
0118 
0119 
0120 /*
0121  * Serial Interface With Time Slot Assigner Registers
0122  */
0123 typedef struct m8260SIRegisters_ {
0124   uint16_t        siamr;
0125   uint16_t        sibmr;
0126   uint16_t        sicmr;
0127   uint16_t        sidmr;
0128   uint8_t     sigmr;
0129   uint8_t     si_pad0[1];
0130   uint8_t     sicmdr;
0131   uint8_t     si_pad1[1];
0132   uint8_t     sistr;
0133   uint8_t     si_pad2[1];
0134   uint16_t        sirsr;
0135 } m8260SIRegisters_t;
0136 
0137 
0138 /*
0139  * Multi Channel Controller registers
0140  */
0141 typedef struct m8260MCCRegisters_ {
0142   uint16_t        mcce;
0143   uint8_t     mcc_pad2[2];
0144   uint16_t        mccm;
0145   uint16_t        mcc_pad0;
0146   uint8_t     mccf;
0147   uint8_t     mcc_pad1[7];
0148 } m8260MCCRegisters_t;
0149 
0150 
0151 /*
0152 *************************************************************************
0153 *                              RISC Timers                              *
0154 *************************************************************************
0155 */
0156 /*
0157 typedef struct m8260TimerParms_ {
0158   uint16_t          tm_base;
0159   uint16_t          _tm_ptr;
0160   uint16_t          _r_tmr;
0161   uint16_t          _r_tmv;
0162   uint32_t          tm_cmd;
0163   uint32_t          tm_cnt;
0164 } m8260TimerParms_t;
0165 */
0166 
0167 /*
0168  * RISC Controller Configuration Register (RCCR)
0169  * All other bits in this register are reserved.
0170  */
0171 #define M8260_RCCR_TIME          (1<<31)    /* Enable timer */
0172 #define M8260_RCCR_TIMEP(x)      ((x)<<24)  /* Timer period */
0173 #define M8260_RCCR_DR1M          (1<<23)    /* IDMA Rqst 1 Mode */
0174 #define M8260_RCCR_DR2M          (1<<22)    /* IDMA Rqst 2 Mode */
0175 #define M8260_RCCR_DR1QP(x)      ((x)<<20)  /* IDMA1 Rqst Priority */
0176 #define M8260_RCCR_EIE           (1<<19)    /* External Interrupt Enable */
0177 #define M8260_RCCR_SCD           (1<<18)    /* Scheduler Configuration */
0178 #define M8260_RCCR_DR2QP(x)      ((x)<<16)  /* IDMA2 Rqst Priority */
0179 #define M8260_RCCR_ERAM(x)       ((x)<<13)  /* Enable RAM Microcode */
0180 #define M8260_RCCR_EDM1          (1<<11)    /* DRQ1 Edge detect mode */
0181 #define M8260_RCCR_EDM2          (1<<10)    /* DRQ2 Edge detect mode */
0182 #define M8260_RCCR_EDM3          (1<<9)     /* DRQ3 Edge detect mode */
0183 #define M8260_RCCR_EDM4          (1<<8)     /* DRQ4 Edge detect mode */
0184 #define M8260_RCCR_DR3M          (1<<7)     /* IDMA Rqst 1 Mode */
0185 #define M8260_RCCR_DR4M          (1<<6)     /* IDMA Rqst 2 Mode */
0186 #define M8260_RCCR_DR3QP(x)      ((x)<<4)   /* IDMA3 Rqst Priority */
0187 #define M8260_RCCR_DEM12         (1<<3)     /* DONE1,2 Edge detect mode */
0188 #define M8260_RCCR_DEM34         (1<<2)     /* DONE3,4 Edge detect mode */
0189 #define M8260_RCCR_DR4QP(x)      (x)        /* IDMA4 Rqst Priority */
0190 
0191 
0192 
0193 /*
0194  * Command register
0195  * Set up this register before issuing a M8260_CR_OP_SET_TIMER command.
0196  */
0197 #if 0
0198 #define M8260_TM_CMD_V           (1<<31)         /* Set to enable timer */
0199 #define M8260_TM_CMD_R           (1<<30)         /* Set for automatic restart */
0200 #define M8260_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
0201 #define M8260_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
0202 #define M8260_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */
0203 #endif
0204 
0205 /*
0206 *************************************************************************
0207 *                               DMA Controllers                         *
0208 *************************************************************************
0209 */
0210 typedef struct m8260IDMAparms_ {
0211   uint16_t          ibase;
0212   uint16_t          dcm;
0213   uint16_t            ibdptr;
0214   uint16_t            dpr_buf;
0215   uint16_t            _buf_inv;
0216   uint16_t            ssmax;
0217   uint16_t            _dpr_in_ptr;
0218   uint16_t            sts;
0219   uint16_t            _dpr_out_ptr;
0220   uint16_t            seob;
0221   uint16_t            deob;
0222   uint16_t            dts;
0223   uint16_t            _ret_add;
0224   uint16_t            reserved;
0225   uint32_t            _bd_cnt;
0226   uint32_t            _s_ptr;
0227   uint32_t            _d_ptr;
0228   uint32_t            istate;
0229 } m8260IDMAparms_t;
0230 
0231 
0232 /*
0233 *************************************************************************
0234 *                   Serial Communication Controllers                    *
0235 *************************************************************************
0236 */
0237 
0238 
0239 typedef struct m8260SCCparms_ {
0240   uint16_t          rbase;
0241   uint16_t          tbase;
0242   uint8_t           rfcr;
0243   uint8_t           tfcr;
0244   uint16_t          mrblr;
0245   uint32_t          _rstate;
0246   uint32_t          _pad0;
0247   uint16_t          _rbptr;
0248   uint16_t          _pad1;
0249   uint32_t          _pad2;
0250   uint32_t          _tstate;
0251   uint32_t          _pad3;
0252   uint16_t          _tbptr;
0253   uint16_t          _pad4;
0254   uint32_t          _pad5;
0255   uint32_t          _rcrc;
0256   uint32_t          _tcrc;
0257   union {
0258     struct {
0259       uint32_t          _res0;
0260       uint32_t          _res1;
0261       uint16_t          max_idl;
0262       uint16_t          idlc;
0263       uint16_t          brkcr;
0264       uint16_t          parec;
0265       uint16_t          frmec;
0266       uint16_t          nosec;
0267       uint16_t          brkec;
0268       uint16_t          brklen;
0269       uint16_t          uaddr[2];
0270       uint16_t          rtemp;
0271       uint16_t          toseq;
0272       uint16_t          character[8];
0273       uint16_t          rccm;
0274       uint16_t          rccr;
0275       uint16_t          rlbc;
0276     } uart;
0277     struct {
0278       uint32_t            _pad0;
0279       uint32_t            c_mask;
0280       uint32_t            c_pres;
0281       uint16_t            disfc;
0282       uint16_t            crcec;
0283       uint16_t            abtsc;
0284       uint16_t            nmarc;
0285       uint16_t            retrc;
0286       uint16_t            mflr;
0287       uint16_t            _max_cnt;
0288       uint16_t            rfthr;
0289       uint16_t            _rfcnt;
0290       uint16_t            hmask;
0291       uint16_t            haddr1;
0292       uint16_t            haddr2;
0293       uint16_t            haddr3;
0294       uint16_t            haddr4;
0295       uint16_t            _tmp;
0296       uint16_t            _tmp_mb;
0297     } hdlc;
0298     struct {
0299       uint32_t          _pad0;
0300       uint32_t          crcc;
0301       uint16_t          prcrc;
0302       uint16_t          ptcrc;
0303       uint16_t          parec;
0304       uint16_t          bsync;
0305       uint16_t          bdle;
0306       uint16_t          character[8];
0307       uint16_t          rccm;
0308     } bisync;
0309     struct {
0310       uint32_t            _crc_p;
0311       uint32_t            _crc_c;
0312     } transparent;
0313     struct {
0314       uint32_t          c_pres;
0315       uint32_t          c_mask;
0316       uint32_t          crcec;
0317       uint32_t          alec;
0318       uint32_t          disfc;
0319       uint16_t          pads;
0320       uint16_t          ret_lim;
0321       uint16_t          _ret_cnt;
0322       uint16_t          mflr;
0323       uint16_t          minflr;
0324       uint16_t          maxd1;
0325       uint16_t          maxd2;
0326       uint16_t          _maxd;
0327       uint16_t          _dma_cnt;
0328       uint16_t          _max_b;
0329       uint16_t          gaddr1;
0330       uint16_t          gaddr2;
0331       uint16_t          gaddr3;
0332       uint16_t          gaddr4;
0333       uint32_t          _tbuf0data0;
0334       uint32_t          _tbuf0data1;
0335       uint32_t          _tbuf0rba0;
0336       uint32_t          _tbuf0crc;
0337       uint16_t          _tbuf0bcnt;
0338       uint16_t          paddr_h;
0339       uint16_t          paddr_m;
0340       uint16_t          paddr_l;
0341       uint16_t          p_per;
0342       uint16_t          _rfbd_ptr;
0343       uint16_t          _tfbd_ptr;
0344       uint16_t          _tlbd_ptr;
0345       uint32_t          _tbuf1data0;
0346       uint32_t          _tbuf1data1;
0347       uint32_t          _tbuf1rba0;
0348       uint32_t          _tbuf1crc;
0349       uint16_t          _tbuf1bcnt;
0350       uint16_t          _tx_len;
0351       uint16_t          iaddr1;
0352       uint16_t          iaddr2;
0353       uint16_t          iaddr3;
0354       uint16_t          iaddr4;
0355       uint16_t          _boff_cnt;
0356       uint16_t          taddr_l;
0357       uint16_t          taddr_m;
0358       uint16_t          taddr_h;
0359     } ethernet;
0360   } un;
0361 } m8260SCCparms_t;
0362 
0363 
0364 /*
0365  * Event and mask registers (SCCE, SCCM)
0366  */
0367 #define M8260_SCCE_BRKE  (1<<6)
0368 #define M8260_SCCE_BRK   (1<<5)
0369 #define M8260_SCCE_TXE   (1<<4)
0370 #define M8260_SCCE_RXF   (1<<3)
0371 #define M8260_SCCE_BSY   (1<<2)
0372 #define M8260_SCCE_TX    (1<<1)
0373 #define M8260_SCCE_RX    (1<<0)
0374 
0375 
0376 /*
0377 *************************************************************************
0378 *                   Fast Serial Communication Controllers               *
0379 *************************************************************************
0380 */
0381 
0382 
0383 typedef struct m8260FCCparms_ {
0384   uint16_t          riptr;
0385   uint16_t          tiptr;
0386   uint16_t          _pad0;
0387   uint16_t          mrblr;
0388   uint32_t          rstate;
0389   uint32_t          rbase;
0390   uint16_t          _rbdstat;
0391   uint16_t          _rbdlen;
0392   uint32_t          _rdptr;
0393   uint32_t          tstate;
0394   uint32_t          tbase;
0395   uint16_t          _tbdstat;
0396   uint16_t          _tbdlen;
0397   uint32_t          _tdptr;
0398   uint32_t          _rbptr;
0399   uint32_t          _tbptr;
0400   uint32_t          _rcrc;
0401   uint32_t          _pad1;
0402   uint32_t          _tcrc;
0403 
0404   union {
0405     struct {
0406       uint32_t            _pad0;
0407       uint32_t            _pad1;
0408       uint32_t            c_mask;
0409       uint32_t            c_pres;
0410       uint16_t            disfc;
0411       uint16_t            crcec;
0412       uint16_t            abtsc;
0413       uint16_t            nmarc;
0414       uint32_t            _max_cnt;
0415       uint16_t            mflr;
0416       uint16_t            rfthr;
0417       uint16_t            rfcnt;
0418       uint16_t            hmask;
0419       uint16_t            haddr1;
0420       uint16_t            haddr2;
0421       uint16_t            haddr3;
0422       uint16_t            haddr4;
0423       uint16_t            _ts_tmp;
0424       uint16_t            _tmp_mb;
0425     } hdlc;
0426     struct {
0427       uint32_t            _pad0;
0428       uint32_t            _pad1;
0429       uint32_t            c_mask;
0430       uint32_t            c_pres;
0431       uint16_t            disfc;
0432       uint16_t            crcec;
0433       uint16_t            abtsc;
0434       uint16_t            nmarc;
0435       uint32_t            _max_cnt;
0436       uint16_t            mflr;
0437       uint16_t            rfthr;
0438       uint16_t            rfcnt;
0439       uint16_t            hmask;
0440       uint16_t            haddr1;
0441       uint16_t            haddr2;
0442       uint16_t            haddr3;
0443       uint16_t            haddr4;
0444       uint16_t            _ts_tmp;
0445       uint16_t            _tmp_mb;
0446     } transparent;
0447     struct {
0448       uint32_t          _stat_buf;
0449       uint32_t          cam_ptr;
0450       uint32_t          c_mask;
0451       uint32_t          c_pres;
0452       uint32_t          crcec;
0453       uint32_t          alec;
0454       uint32_t          disfc;
0455       uint16_t          ret_lim;
0456       uint16_t          _ret_cnt;
0457       uint16_t          p_per;
0458       uint16_t          _boff_cnt;
0459       uint32_t          gaddr_h;
0460       uint32_t          gaddr_l;
0461       uint16_t          tfcstat;
0462       uint16_t          tfclen;
0463       uint32_t          tfcptr;
0464       uint16_t          mflr;
0465       uint16_t          paddr1_h;
0466       uint16_t          paddr1_m;
0467       uint16_t          paddr1_l;
0468       uint16_t          _ibd_cnt;
0469       uint16_t          _ibd_start;
0470       uint16_t          _ibd_end;
0471       uint16_t          _tx_len;
0472       uint16_t          _ibd_base;
0473       uint32_t          iaddr_h;
0474       uint32_t          iaddr_l;
0475       uint16_t          minflr;
0476       uint16_t          taddr_h;
0477       uint16_t          taddr_m;
0478       uint16_t          taddr_l;
0479       uint16_t          pad_ptr;
0480       uint16_t          _pad0;
0481       uint16_t          _cf_range;
0482       uint16_t          _max_b;
0483       uint16_t          maxd1;
0484       uint16_t          maxd2;
0485       uint16_t          _maxd;
0486       uint16_t          _dma_cnt;
0487       uint32_t          octc;
0488       uint32_t          colc;
0489       uint32_t          broc;
0490       uint32_t          mulc;
0491       uint32_t          uspc;
0492       uint32_t          frgc;
0493       uint32_t          ospc;
0494       uint32_t          jbrc;
0495       uint32_t          p64c;
0496       uint32_t          p65c;
0497       uint32_t          p128c;
0498       uint32_t          p256c;
0499       uint32_t          p512c;
0500       uint32_t          p1024c;
0501       uint32_t          _cam_buf;
0502       uint32_t          _pad1;
0503     } ethernet;
0504   } un;
0505 } m8260FCCparms_t;
0506 
0507 
0508 /*
0509  * Receive and transmit function code register bits
0510  * These apply to the function code registers of all devices, not just SCC.
0511  */
0512 #define M8260_RFCR_BO(x)         ((x)<<3)
0513 #define M8260_RFCR_MOT           (2<<3)
0514 #define M8260_RFCR_LOCAL_BUS     (2)
0515 #define M8260_RFCR_60X_BUS   (0)
0516 #define M8260_TFCR_BO(x)         ((x)<<3)
0517 #define M8260_TFCR_MOT           (2<<3)
0518 #define M8260_TFCR_LOCAL_BUS     (2)
0519 #define M8260_TFCR_60X_BUS   (0)
0520 
0521 /*
0522 *************************************************************************
0523 *                     Serial Management Controllers                     *
0524 *************************************************************************
0525 */
0526 typedef struct m8260SMCparms_ {
0527   uint16_t          rbase;
0528   uint16_t          tbase;
0529   uint8_t           rfcr;
0530   uint8_t           tfcr;
0531   uint16_t          mrblr;
0532   uint32_t          _rstate;
0533   uint32_t          _pad0;
0534   uint16_t          _rbptr;
0535   uint16_t          _pad1;
0536   uint32_t          _pad2;
0537   uint32_t          _tstate;
0538   uint32_t          _pad3;
0539   uint16_t          _tbptr;
0540   uint16_t          _pad4;
0541   uint32_t          _pad5;
0542   union {
0543     struct {
0544       uint16_t        max_idl;
0545       uint16_t        _idlc;
0546       uint16_t        _brkln;
0547       uint16_t        brkec;
0548       uint16_t        brkcr;
0549       uint16_t        _r_mask;
0550     } uart;
0551     struct {
0552       uint16_t        _pad0[6];
0553     } transparent;
0554   } un;
0555   uint32_t        _pad6;
0556 } m8260SMCparms_t;
0557 
0558 /*
0559  * Mode register
0560  */
0561 #define M8260_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
0562 #define M8260_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
0563 #define M8260_SMCMR_PARITY               (1<<9)       /* Enable parity */
0564 #define M8260_SMCMR_EVEN                 (1<<8)       /* Even parity */
0565 #define M8260_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
0566 #define M8260_SMCMR_SM_UART              (2<<4)       /* UART Mode */
0567 #define M8260_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
0568 #define M8260_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
0569 #define M8260_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
0570 #define M8260_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
0571 #define M8260_SMCMR_REN                  (1<<0)       /* Enable receiver */
0572 
0573 /*
0574  * Event and mask registers (SMCE, SMCM)
0575  */
0576 #define M8260_SMCE_TXE   (1<<4)
0577 #define M8260_SMCE_BSY   (1<<2)
0578 #define M8260_SMCE_TX    (1<<1)
0579 #define M8260_SMCE_RX    (1<<0)
0580 
0581 /*
0582 *************************************************************************
0583 *                      Serial Peripheral Interface                      *
0584 *************************************************************************
0585 */
0586 typedef struct m8260SPIparms_ {
0587   uint16_t          rbase;
0588   uint16_t          tbase;
0589   uint8_t           rfcr;
0590   uint8_t           tfcr;
0591   uint16_t          mrblr;
0592   uint32_t          _rstate;
0593   uint32_t          _pad0;
0594   uint16_t          _rbptr;
0595   uint16_t          _pad1;
0596   uint32_t          _pad2;
0597   uint32_t          _tstate;
0598   uint32_t          _pad3;
0599   uint16_t          _tbptr;
0600   uint16_t          _pad4;
0601   uint32_t          _pad5;
0602 } m8260SPIparms_t;
0603 
0604 /*
0605  * Mode register (SPMODE)
0606  */
0607 #define M8260_SPMODE_LOOP                (1<<14)  /* Local loopback mode */
0608 #define M8260_SPMODE_CI                  (1<<13)  /* Clock invert */
0609 #define M8260_SPMODE_CP                  (1<<12)  /* Clock phase */
0610 #define M8260_SPMODE_DIV16               (1<<11)  /* Divide BRGCLK by 16 */
0611 #define M8260_SPMODE_REV                 (1<<10)  /* Reverse data */
0612 #define M8260_SPMODE_MASTER              (1<<9)   /* SPI is master */
0613 #define M8260_SPMODE_EN                  (1<<8)   /* Enable SPI */
0614 #define M8260_SPMODE_CLEN(x)             ((x)<<4) /* Character length */
0615 #define M8260_SPMODE_PM(x)               (x)      /* Prescaler modulus */
0616 
0617 /*
0618  * Mode register (SPCOM)
0619  */
0620 #define M8260_SPCOM_STR                  (1<<7)  /* Start transmit */
0621 
0622 /*
0623  * Event and mask registers (SPIE, SPIM)
0624  */
0625 #define M8260_SPIE_MME   (1<<5)          /* Multi-master error */
0626 #define M8260_SPIE_TXE   (1<<4)          /* Tx error */
0627 #define M8260_SPIE_BSY   (1<<2)          /* Busy condition*/
0628 #define M8260_SPIE_TXB   (1<<1)          /* Tx buffer */
0629 #define M8260_SPIE_RXB   (1<<0)          /* Rx buffer */
0630 
0631 /*
0632 *************************************************************************
0633 *                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
0634 *************************************************************************
0635 */
0636 typedef struct m8260BufferDescriptor_ {
0637   uint16_t          status;
0638   uint16_t          length;
0639   volatile void           *buffer;
0640 } m8260BufferDescriptor_t;
0641 
0642 /*
0643  * Bits in receive buffer descriptor status word
0644  */
0645 #define M8260_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
0646 #define M8260_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
0647 #define M8260_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
0648 #define M8260_BD_LAST            (1<<11) /* Ethernet, SPI */
0649 #define M8260_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
0650 #define M8260_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
0651 #define M8260_BD_ADDRESS         (1<<10) /* SCC UART */
0652 #define M8260_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
0653 #define M8260_BD_MISS            (1<<8)  /* Ethernet */
0654 #define M8260_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
0655 #define M8260_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
0656 #define M8260_BD_LONG            (1<<5)  /* Ethernet, SCC HDLC */
0657 #define M8260_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
0658 #define M8260_BD_NONALIGNED      (1<<4)  /* Ethernet, SCC HDLC */
0659 #define M8260_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
0660 #define M8260_BD_SHORT           (1<<3)  /* Ethernet */
0661 #define M8260_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
0662 #define M8260_BD_ABORT       (1<<3)  /* SCC HDLC */
0663 #define M8260_BD_CRC_ERROR       (1<<2)  /* Ethernet, SCC HDLC */
0664 #define M8260_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
0665 #define M8260_BD_COLLISION       (1<<0)  /* Ethernet */
0666 #define M8260_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
0667 #define M8260_BD_MASTER_ERROR    (1<<0)  /* SPI */
0668 
0669 #define M8xx_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
0670 #define M8xx_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
0671 #define M8xx_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
0672 #define M8xx_BD_LAST            (1<<11) /* Ethernet, SPI */
0673 #define M8xx_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
0674 #define M8xx_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
0675 #define M8xx_BD_ADDRESS         (1<<10) /* SCC UART */
0676 #define M8xx_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
0677 #define M8xx_BD_MISS            (1<<8)  /* Ethernet */
0678 #define M8xx_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
0679 #define M8xx_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
0680 #define M8xx_BD_LONG            (1<<5)  /* Ethernet, SCC HDLC */
0681 #define M8xx_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
0682 #define M8xx_BD_NONALIGNED      (1<<4)  /* Ethernet, SCC HDLC */
0683 #define M8xx_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
0684 #define M8xx_BD_SHORT           (1<<3)  /* Ethernet */
0685 #define M8xx_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
0686 #define M8xx_BD_ABORT        (1<<3)  /* SCC HDLC */
0687 #define M8xx_BD_CRC_ERROR       (1<<2)  /* Ethernet, SCC HDLC */
0688 #define M8xx_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
0689 #define M8xx_BD_COLLISION       (1<<0)  /* Ethernet */
0690 #define M8xx_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
0691 #define M8xx_BD_MASTER_ERROR    (1<<0)  /* SPI */
0692 
0693 /*
0694  * Bits in transmit buffer descriptor status word
0695  * Many bits have the same meaning as those in receiver buffer descriptors.
0696  */
0697 #define M8260_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
0698 #define M8260_BD_PAD             (1<<14) /* Ethernet */
0699 #define M8260_BD_CTS_REPORT      (1<<11) /* SCC UART */
0700 #define M8260_BD_TX_CRC          (1<<10) /* Ethernet */
0701 #define M8260_BD_DEFER           (1<<9)  /* Ethernet */
0702 #define M8260_BD_HEARTBEAT       (1<<8)  /* Ethernet */
0703 #define M8260_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
0704 #define M8260_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
0705 #define M8260_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
0706 #define M8260_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
0707 #define M8260_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
0708 #define M8260_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI, SCC HDLC */
0709 #define M8260_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
0710 #define M8260_BD_CTS_LOST        (1<<0)  /* SCC UART, SCC HDLC */
0711 
0712 #define M8xx_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
0713 #define M8xx_BD_PAD             (1<<14) /* Ethernet */
0714 #define M8xx_BD_CTS_REPORT      (1<<11) /* SCC UART */
0715 #define M8xx_BD_TX_CRC          (1<<10) /* Ethernet */
0716 #define M8xx_BD_DEFER           (1<<9)  /* Ethernet */
0717 #define M8xx_BD_HEARTBEAT       (1<<8)  /* Ethernet */
0718 #define M8xx_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
0719 #define M8xx_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
0720 #define M8xx_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
0721 #define M8xx_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
0722 #define M8xx_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
0723 #define M8xx_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI, SCC HDLC */
0724 #define M8xx_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
0725 #define M8xx_BD_CTS_LOST        (1<<0)  /* SCC UART, SCC HDLC */
0726 
0727 /*
0728 *************************************************************************
0729 *                           IDMA Buffer Descriptors                     *
0730 *************************************************************************
0731 */
0732 typedef struct m8260IDMABufferDescriptor_ {
0733   uint16_t          status;
0734   uint8_t           dfcr;
0735   uint8_t           sfcr;
0736   uint32_t          length;
0737   void                    *source;
0738   void                    *destination;
0739 } m8260IDMABufferDescriptor_t;
0740 
0741 /*
0742 *************************************************************************
0743 *       RISC Communication Processor Module Command Register (CR)       *
0744 *************************************************************************
0745 */
0746 #define M8260_CR_RST             (1<<31)         /* Reset communication processor */
0747 
0748 #define M8260_CR_FCC1        ((4<<26)|(16<<21))  /* FCC1 page and code */
0749 #define M8260_CR_FCC1_ATM    ((4<<26)|(14<<21))  /* FCC1 ATM mode page and code */
0750 #define M8260_CR_FCC2        ((5<<26)|(17<<21))  /* FCC2 page and code */
0751 #define M8260_CR_FCC2_ATM    ((5<<26)|(14<<21))  /* FCC2 ATM mode page and code */
0752 #define M8260_CR_FCC3        ((6<<26)|(18<<21))  /* FCC3 page and code */
0753 #define M8260_CR_SCC1        ((0<<26)|(4<<21))   /* SCC1 page and code */
0754 #define M8260_CR_SCC2        ((1<<26)|(5<<21))   /* SCC2 page and code */
0755 #define M8260_CR_SCC3        ((2<<26)|(6<<21))   /* SCC3 page and code */
0756 #define M8260_CR_SCC4        ((3<<26)|(7<<21))   /* SCC4 page and code */
0757 #define M8260_CR_SMC1        ((7<<26)|(8<<21))   /* SMC1 page and code */
0758 #define M8260_CR_SMC2        ((8<<26)|(9<<21))   /* SMC2 page and code */
0759 #define M8260_CR_RAND        ((10<<26)|(14<<21)) /* SMC2 page and code */
0760 #define M8260_CR_SPI         ((9<<26)|(10<<21))  /* SPI page and code */
0761 #define M8260_CR_I2C         ((10<<26)|(11<<21)) /* I2C page and code */
0762 #define M8260_CR_TMR         ((10<<26)|(15<<21)) /* Timer page and code */
0763 #define M8260_CR_MCC1        ((7<<26)|(28<<21))  /* MCC1 page and code */
0764 #define M8260_CR_MCC2        ((8<<26)|(29<<21))  /* MCC2 page and code */
0765 #define M8260_CR_IDMA1       ((7<<26)|(20<<21))  /* IDMA1 page and code */
0766 #define M8260_CR_IDMA2       ((8<<26)|(21<<21))  /* IDMA2 page and code */
0767 #define M8260_CR_IDMA3       ((9<<26)|(22<<21))  /* IDMA3 page and code */
0768 #define M8260_CR_IDMA4       ((10<<26)|(23<<21)) /* IDMA4 page and code */
0769 
0770 #define M8260_CR_FLG         (1<<16)   /* Command sempahore flag */
0771 
0772 #define M8260_CR_MCC_CHAN(x)     ((x)<<6)  /* MCC channel number */
0773 #define M8260_CR_FCC_HDLC    (0<<6)    /* FCC HDLC/Transparent protocol code */
0774 #define M8260_CR_FCC_ATM     (10<<6)   /* FCC ATM protocol code */
0775 #define M8260_CR_FCC_ETH     (12<<6)   /* FCC Ethernet protocol code */
0776 
0777 #define M8260_CR_OP_INIT_RX_TX   (0)       /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */
0778 #define M8260_CR_OP_INIT_RX      (1)       /* FCC, SCC, SMC UART, SPI, I2C, MCC */
0779 #define M8260_CR_OP_INIT_TX      (2)       /* FCC, SCC, SMC UART, SPI, I2C, MCC */
0780 #define M8260_CR_OP_INIT_HUNT    (3)       /* FCC, SCC, SMC UART */
0781 #define M8260_CR_OP_STOP_TX      (4)       /* FCC, SCC, SMC UART, MCC */
0782 #define M8260_CR_OP_GR_STOP_TX   (5)       /* FCC, SCC */
0783 #define M8260_CR_OP_RESTART_TX   (6)       /* FCC, SCC, SMC UART */
0784 #define M8260_CR_OP_CLOSE_RX_BD  (7)       /* FCC, SCC, SMC UART, SPI, I2C */
0785 #define M8260_CR_OP_SET_GRP_ADDR (8)       /* FCC, SCC */
0786 #define M8260_CR_OP_SET_TIMER    (8)       /* Timer */
0787 #define M8260_CR_OP_GCI_TIMEOUT  (9)       /* SMC GCI */
0788 #define M8260_CR_OP_START_IDMA   (9)       /* IDMA */
0789 #define M8260_CR_OP_STOP_RX      (9)       /* MCC */
0790 #define M8260_CR_OP_ATM_TX       (10)      /* FCC */
0791 #define M8260_CR_OP_RESET_BCS    (10)      /* SCC */
0792 #define M8260_CR_OP_GCI_ABORT    (10)      /* SMC GCI */
0793 #define M8260_CR_OP_STOP_IDMA    (11)      /* IDMA */
0794 #define M8260_CR_OP_RANDOM       (12)      /* RAND */
0795 
0796 /*
0797 *************************************************************************
0798 *                 System Protection Control Register (SYPCR)            *
0799 *************************************************************************
0800 */
0801 #define M8260_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
0802 #define M8260_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
0803 #define M8260_SYPCR_BME          (1<<7)      /* Bus monitor enable */
0804 #define M8260_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
0805 #define M8260_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
0806 #define M8260_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
0807 #define M8260_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
0808 
0809 /*
0810 *************************************************************************
0811 *                        Memory Control Registers                       *
0812 *************************************************************************
0813 */
0814 #define M8260_UPM_AMX_8col       (0<<20)   /* 8 column DRAM */
0815 #define M8260_UPM_AMX_9col       (1<<20)   /* 9 column DRAM */
0816 #define M8260_UPM_AMX_10col      (2<<20)   /* 10 column DRAM */
0817 #define M8260_UPM_AMX_11col      (3<<20)   /* 11 column DRAM */
0818 #define M8260_UPM_AMX_12col      (4<<20)   /* 12 column DRAM */
0819 #define M8260_UPM_AMX_13col      (5<<20)   /* 13 column DRAM */
0820 #define M8260_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
0821 #define M8260_MSR_WPER           (1<<7)    /* Write protection error */
0822 #define M8260_MPTPR_PTP(x)       ((x)<<8)  /* Periodic timer prescaler */
0823 #define M8260_BR_BA(x)           ((x)&0xffff8000) /* Base address */
0824 #define M8260_BR_AT(x)           ((x)<<12) /* Address type */
0825 #define M8260_BR_PS8             (1<<10)   /* 8 bit port */
0826 #define M8260_BR_PS16            (2<<10)   /* 16 bit port */
0827 #define M8260_BR_PS32            (0<<10)   /* 32 bit port */
0828 #define M8260_BR_PARE            (1<<9)    /* Parity checking enable */
0829 #define M8260_BR_WP              (1<<8)    /* Write protect */
0830 #define M8260_BR_MS_GPCM         (0<<6)    /* GPCM */
0831 #define M8260_BR_MS_UPMA         (2<<6)    /* UPM A */
0832 #define M8260_BR_MS_UPMB         (3<<6)    /* UPM B */
0833 #define M8260_MEMC_BR_V          (1<<0)    /* Base/Option register are valid */
0834 
0835 #define M8260_MEMC_OR_32K        0xffff8000      /* Address range */
0836 #define M8260_MEMC_OR_64K        0xffff0000
0837 #define M8260_MEMC_OR_128K       0xfffe0000
0838 #define M8260_MEMC_OR_256K       0xfffc0000
0839 #define M8260_MEMC_OR_512K       0xfff80000
0840 #define M8260_MEMC_OR_1M         0xfff00000
0841 #define M8260_MEMC_OR_2M         0xffe00000
0842 #define M8260_MEMC_OR_4M         0xffc00000
0843 #define M8260_MEMC_OR_8M         0xff800000
0844 #define M8260_MEMC_OR_16M        0xff000000
0845 #define M8260_MEMC_OR_32M        0xfe000000
0846 #define M8260_MEMC_OR_64M        0xfc000000
0847 #define M8260_MEMC_OR_128        0xf8000000
0848 #define M8260_MEMC_OR_256M       0xf0000000
0849 #define M8260_MEMC_OR_512M       0xe0000000
0850 #define M8260_MEMC_OR_1G         0xc0000000
0851 #define M8260_MEMC_OR_2G         0x80000000
0852 #define M8260_MEMC_OR_4G         0x00000000
0853 #define M8260_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
0854 #define M8260_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
0855 #define M8260_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
0856 #define M8260_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
0857 #define M8260_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
0858 #define M8260_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
0859 #define M8260_MEMC_OR_BI         (1<8)       /* Burst inhibit */
0860 #define M8260_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
0861 #define M8260_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
0862 #define M8260_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
0863 #define M8260_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */
0864 
0865 /*
0866 *************************************************************************
0867 *                         UPM Registers (MxMR)                          *
0868 *************************************************************************
0869 */
0870 #define M8260_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
0871 #define M8260_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
0872 #define M8260_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
0873 #define M8260_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
0874 #define M8260_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
0875 #define M8260_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
0876 #define M8260_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
0877 #define M8260_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
0878 /*
0879 *************************************************************************
0880 *                         Memory Command Register (MCR)                 *
0881 *************************************************************************
0882 */
0883 #define M8260_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
0884 #define M8260_MEMC_MCR_READ      (1<<30)     /* READ command */
0885 #define M8260_MEMC_MCR_RUN       (2<<30)     /* RUN command */
0886 #define M8260_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
0887 #define M8260_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
0888 #define M8260_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
0889 #define M8260_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
0890 #define M8260_MEMC_MCR_MAD(x)    (x)         /* Machine address */
0891 
0892 
0893 
0894 /*
0895 *************************************************************************
0896 *                         SI Mode Register (SIMODE)                     *
0897 *************************************************************************
0898 */
0899 #define M8260_SI_SMC2_BITS       0xFFFF0000 /* All SMC2 bits */
0900 #define M8260_SI_SMC2_TDM        (1<<31)    /* Multiplexed SMC2 */
0901 #define M8260_SI_SMC2_BRG1       (0<<28)    /* SMC2 clock souce */
0902 #define M8260_SI_SMC2_BRG2       (1<<28)
0903 #define M8260_SI_SMC2_BRG3       (2<<28)
0904 #define M8260_SI_SMC2_BRG4       (3<<28)
0905 #define M8260_SI_SMC2_CLK5       (0<<28)
0906 #define M8260_SI_SMC2_CLK6       (1<<28)
0907 #define M8260_SI_SMC2_CLK7       (2<<28)
0908 #define M8260_SI_SMC2_CLK8       (3<<28)
0909 #define M8260_SI_SMC1_BITS       0x0000FFFF /* All SMC1 bits */
0910 #define M8260_SI_SMC1_TDM        (1<<15)    /* Multiplexed SMC1 */
0911 #define M8260_SI_SMC1_BRG1       (0<<12)    /* SMC1 clock souce */
0912 #define M8260_SI_SMC1_BRG2       (1<<12)
0913 #define M8260_SI_SMC1_BRG3       (2<<12)
0914 #define M8260_SI_SMC1_BRG4       (3<<12)
0915 #define M8260_SI_SMC1_CLK1       (0<<12)
0916 #define M8260_SI_SMC1_CLK2       (1<<12)
0917 #define M8260_SI_SMC1_CLK3       (2<<12)
0918 #define M8260_SI_SMC1_CLK4       (3<<12)
0919 
0920 /*
0921 *************************************************************************
0922 *                  SDMA Configuration Register (SDCR)                   *
0923 *************************************************************************
0924 */
0925 #define M8260_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
0926 #define M8260_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */
0927 
0928 /*
0929 *************************************************************************
0930 *                  SDMA Status Register (SDSR)                          *
0931 *************************************************************************
0932 */
0933 #define M8260_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
0934 #define M8260_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
0935 #define M8260_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */
0936 
0937 /*
0938 *************************************************************************
0939 *                      Baud (sic) Rate Generators                       *
0940 *************************************************************************
0941 */
0942 #define M8260_BRG_RST            (1<<17)         /* Reset generator */
0943 #define M8260_BRG_EN             (1<<16)         /* Enable generator */
0944 #define M8260_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
0945 #define M8260_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
0946 #define M8260_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
0947 #define M8260_BRG_ATB            (1<<13)         /* Autobaud */
0948 #define M8260_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
0949 #define M8260_BRG_57600          (32<<1)
0950 #define M8260_BRG_38400          (64<<1)
0951 #define M8260_BRG_19200          (129<<1)
0952 #define M8260_BRG_9600           (259<<1)
0953 #define M8260_BRG_4800           (520<<1)
0954 #define M8260_BRG_2400           (1040<<1)
0955 #define M8260_BRG_1200           (2082<<1)
0956 #define M8260_BRG_600            ((259<<1) | 1)
0957 #define M8260_BRG_300            ((520<<1) | 1)
0958 #define M8260_BRG_150            ((1040<<1) | 1)
0959 #define M8260_BRG_75             ((2080<<1) | 1)
0960 
0961 #define M8xx_BRG_RST             (1<<17)         /* Reset generator */
0962 #define M8xx_BRG_EN              (1<<16)         /* Enable generator */
0963 #define M8xx_BRG_EXTC_BRGCLK     (0<<14)         /* Source is BRGCLK */
0964 
0965 #define M8260_BRG1      (1<<7)
0966 #define M8260_BRG2      (1<<6)
0967 #define M8260_BRG3      (1<<5)
0968 #define M8260_BRG4      (1<<4)
0969 #define M8260_BRG5      (1<<3)
0970 #define M8260_BRG6      (1<<2)
0971 #define M8260_BRG7      (1<<1)
0972 #define M8260_BRG8      (1<<0)
0973 
0974 
0975 
0976 #define M8260_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
0977 #define M8260_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
0978 #define M8260_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
0979 #define M8260_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
0980 #define M8260_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
0981 #define M8260_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
0982 #define M8260_TGCR_STP1          (1<<1)    /* Stop timer */
0983 #define M8260_TGCR_STP2          (1<<5)    /* Stop timer */
0984 #define M8260_TGCR_STP3          (1<<9)    /* Stop timer */
0985 #define M8260_TGCR_STP4          (1<<13)   /* Stop timer */
0986 #define M8260_TGCR_RST1          (1<<0)    /* Enable timer */
0987 #define M8260_TGCR_RST2          (1<<4)    /* Enable timer */
0988 #define M8260_TGCR_RST3          (1<<8)    /* Enable timer */
0989 #define M8260_TGCR_RST4          (1<<12)   /* Enable timer */
0990 #define M8260_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
0991 #define M8260_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */
0992 
0993 #define M8260_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
0994 #define M8260_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
0995 #define M8260_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
0996 #define M8260_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
0997 #define M8260_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
0998 #define M8260_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
0999 #define M8260_TMR_RESTART        (1<<3)    /* Restart timer after reference */
1000 #define M8260_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
1001 #define M8260_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
1002 #define M8260_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
1003 #define M8260_TMR_TGATE          (1<<0)    /* TGATE controls timer */
1004 
1005 #ifdef REV_0_2
1006 #define M8260_PISCR_PS           (1<<6)    /* PIT Interrupt state */
1007 #else
1008 #define M8260_PISCR_PS           (1<<7)    /* PIT Interrupt state */
1009 #endif
1010 #define M8260_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
1011 #define M8260_PISCR_PTF          (1<<1)    /* Stop timer when freeze asserted */
1012 #define M8260_PISCR_PTE          (1<<0)    /* PIT enable */
1013 
1014 #if 0
1015 #define M8260_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
1016 #define M8260_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
1017 #define M8260_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
1018 #define M8260_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
1019 #define M8260_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
1020 #define M8260_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
1021 #define M8260_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
1022 #endif
1023 
1024 #define M8260_TMCNTSC_SEC    (1<<7)    /* per second flag */
1025 #define M8260_TMCNTSC_ALR    (1<<6)    /* Alarm interrupt flag */
1026 #define M8260_TMCNTSC_SIE    (1<<3)    /* per second interrupt enable */
1027 #define M8260_TMCNTSC_ALE    (1<<2)    /* Alarm interrupt enable */
1028 #define M8260_TMCNTSC_TCF    (1<<1)    /* Time count frequency */
1029 #define M8260_TMCNTSC_TCE    (1<<0)    /* Time count enable */
1030 
1031 #define M8260_SIMASK_PC0         (1<<31)
1032 #define M8260_SIMASK_PC1         (1<<30)
1033 #define M8260_SIMASK_PC2         (1<<29)
1034 #define M8260_SIMASK_PC3         (1<<28)
1035 #define M8260_SIMASK_PC4         (1<<27)
1036 #define M8260_SIMASK_PC5         (1<<26)
1037 #define M8260_SIMASK_PC6         (1<<25)
1038 #define M8260_SIMASK_PC7         (1<<24)
1039 #define M8260_SIMASK_PC8         (1<<23)
1040 #define M8260_SIMASK_PC9         (1<<22)
1041 #define M8260_SIMASK_PC10        (1<<21)
1042 #define M8260_SIMASK_PC11        (1<<20)
1043 #define M8260_SIMASK_PC12        (1<<19)
1044 #define M8260_SIMASK_PC13        (1<<18)
1045 #define M8260_SIMASK_PC14        (1<<17)
1046 #define M8260_SIMASK_PC15        (1<<16)
1047 #define M8260_SIMASK_IRQ1        (1<<14)
1048 #define M8260_SIMASK_IRQ2        (1<<13)
1049 #define M8260_SIMASK_IRQ3        (1<<12)
1050 #define M8260_SIMASK_IRQ4        (1<<11)
1051 #define M8260_SIMASK_IRQ5        (1<<10)
1052 #define M8260_SIMASK_IRQ6        (1<<9)
1053 #define M8260_SIMASK_IRQ7        (1<<8)
1054 #define M8260_SIMASK_TMCNT       (1<<2)
1055 #define M8260_SIMASK_PIT         (1<<1)
1056 
1057 #define M8260_SIMASK_FCC1        (1<<31)
1058 #define M8260_SIMASK_FCC2        (1<<30)
1059 #define M8260_SIMASK_FCC3        (1<<29)
1060 #define M8260_SIMASK_MCC1        (1<<27)
1061 #define M8260_SIMASK_MCC2        (1<<26)
1062 #define M8260_SIMASK_SCC1        (1<<23)
1063 #define M8260_SIMASK_SCC2        (1<<22)
1064 #define M8260_SIMASK_SCC3        (1<<21)
1065 #define M8260_SIMASK_SCC4        (1<<20)
1066 #define M8260_SIMASK_I2C         (1<<15)
1067 #define M8260_SIMASK_SPI         (1<<14)
1068 #define M8260_SIMASK_RTT         (1<<13)
1069 #define M8260_SIMASK_SMC1        (1<<12)
1070 #define M8260_SIMASK_SMC2        (1<<11)
1071 #define M8260_SIMASK_IDMA1       (1<<10)
1072 #define M8260_SIMASK_IDMA2       (1<<9)
1073 #define M8260_SIMASK_IDMA3       (1<<8)
1074 #define M8260_SIMASK_IDMA4       (1<<7)
1075 #define M8260_SIMASK_SDMA        (1<<6)
1076 #define M8260_SIMASK_TIMER1      (1<<4)
1077 #define M8260_SIMASK_TIMER2      (1<<3)
1078 #define M8260_SIMASK_TIMER3      (1<<2)
1079 #define M8260_SIMASK_TIMER4      (1<<1)
1080 
1081 #define M8260_SIUMCR_EARB        (1<<31)
1082 #define M8260_SIUMCR_EARP0       (0<<28)
1083 #define M8260_SIUMCR_EARP1       (1<<28)
1084 #define M8260_SIUMCR_EARP2       (2<<28)
1085 #define M8260_SIUMCR_EARP3       (3<<28)
1086 #define M8260_SIUMCR_EARP4       (4<<28)
1087 #define M8260_SIUMCR_EARP5       (5<<28)
1088 #define M8260_SIUMCR_EARP6       (6<<28)
1089 #define M8260_SIUMCR_EARP7       (7<<28)
1090 #define M8260_SIUMCR_DSHW        (1<<23)
1091 #define M8260_SIUMCR_DBGC0       (0<<21)
1092 #define M8260_SIUMCR_DBGC1       (1<<21)
1093 #define M8260_SIUMCR_DBGC2       (2<<21)
1094 #define M8260_SIUMCR_DBGC3       (3<<21)
1095 #define M8260_SIUMCR_DBPC0       (0<<19)
1096 #define M8260_SIUMCR_DBPC1       (1<<19)
1097 #define M8260_SIUMCR_DBPC2       (2<<19)
1098 #define M8260_SIUMCR_DBPC3       (3<<19)
1099 #define M8260_SIUMCR_FRC         (1<<17)
1100 #define M8260_SIUMCR_DLK         (1<<16)
1101 #define M8260_SIUMCR_PNCS        (1<<15)
1102 #define M8260_SIUMCR_OPAR        (1<<14)
1103 #define M8260_SIUMCR_DPC         (1<<13)
1104 #define M8260_SIUMCR_MPRE        (1<<12)
1105 #define M8260_SIUMCR_MLRC0       (0<<10)
1106 #define M8260_SIUMCR_MLRC1       (1<<10)
1107 #define M8260_SIUMCR_MLRC2       (2<<10)
1108 #define M8260_SIUMCR_MLRC3       (3<<10)
1109 #define M8260_SIUMCR_AEME        (1<<9)
1110 #define M8260_SIUMCR_SEME        (1<<8)
1111 #define M8260_SIUMCR_BSC         (1<<7)
1112 #define M8260_SIUMCR_GB5E        (1<<6)
1113 #define M8260_SIUMCR_B2DD        (1<<5)
1114 #define M8260_SIUMCR_B3DD        (1<<4)
1115 
1116 /*
1117 *************************************************************************
1118 *                 MPC8260 DUAL-PORT RAM AND REGISTERS                   *
1119 *************************************************************************
1120 */
1121 typedef struct m8260_ {
1122 
1123   /*
1124    * CPM Dual-Port RAM
1125    */
1126   uint8_t     dpram1[16384];        /* 0x0000 - 0x3FFF BD/data/ucode */
1127   uint8_t   cpm_pad0[16384];    /* 0x4000 - 0x7FFF Reserved      */
1128 
1129   m8260SCCparms_t   scc1p;
1130   uint8_t   pad_scc1[256-sizeof(m8260SCCparms_t)];
1131   m8260SCCparms_t   scc2p;
1132   uint8_t   pad_scc2[256-sizeof(m8260SCCparms_t)];
1133   m8260SCCparms_t   scc3p;
1134   uint8_t   pad_scc3[256-sizeof(m8260SCCparms_t)];
1135   m8260SCCparms_t   scc4p;
1136   uint8_t   pad_scc4[256-sizeof(m8260SCCparms_t)];
1137 
1138   m8260FCCparms_t   fcc1p;
1139   uint8_t   pad_fcc1[256-sizeof(m8260FCCparms_t)];
1140   m8260FCCparms_t   fcc2p;
1141   uint8_t   pad_fcc2[256-sizeof(m8260FCCparms_t)];
1142   m8260FCCparms_t   fcc3p;
1143   uint8_t   pad_fcc3[256-sizeof(m8260FCCparms_t)];
1144 
1145   uint8_t   mcc1p[128];
1146   uint8_t   pad_mcc1[124];
1147   uint16_t      smc1_base;
1148   uint16_t      idma1_base;
1149   uint8_t   mcc2p[128];
1150   uint8_t   pad_mcc2[124];
1151   uint16_t      smc2_base;
1152   uint16_t      idma2_base;
1153   uint8_t   pad_spi[252];
1154   uint16_t      spi_base;
1155   uint16_t      idma3_base;
1156   uint8_t   pad_risc[224];
1157   uint8_t   risc_timers[16];
1158   uint16_t      rev_num;
1159   uint16_t      cpm_pad7;
1160   uint32_t      cpm_pad8;
1161   uint16_t      rand;
1162   uint16_t      i2c_base;
1163   uint16_t      idma4_base;
1164   uint8_t   cpm_pad9[1282];
1165 
1166   uint8_t   cpm_pad1[8192];     /* 0x9000 - 0xAFFF Reserved      */
1167 
1168   m8260SMCparms_t   smc1p;
1169   m8260SMCparms_t   smc2p;
1170   uint8_t   dpram3[4096-2*sizeof(m8260SMCparms_t)];
1171 
1172   uint8_t   cpm_pad2[16384];    /* 0xC000 - 0xFFFF Reserved      */
1173 
1174 
1175   /*
1176    * General SIU Block
1177    */
1178   uint32_t        siumcr;
1179   uint32_t        sypcr;
1180   uint8_t         siu_pad0[6];
1181   uint16_t        swsr;
1182   uint8_t         siu_pad1[20];
1183   uint32_t          bcr;
1184   uint8_t       ppc_acr;
1185   uint8_t       siu_pad4[3];
1186   uint32_t          ppc_alrh;
1187   uint32_t          ppc_alr1;
1188   uint8_t       lcl_acr;
1189   uint8_t       siu_pad5[3];
1190   uint32_t          lcl_alrh;
1191   uint32_t          lcl_alr1;
1192   uint32_t          tescr1;
1193   uint32_t          tescr2;
1194   uint32_t          l_tescr1;
1195   uint32_t          l_tescr2;
1196   uint32_t          pdtea;
1197   uint8_t       pdtem;
1198   uint8_t       siu_pad2[3];
1199   uint32_t          ldtea;
1200   uint8_t       ldtem;
1201   uint8_t       siu_pad3[163];
1202 
1203 
1204   /*
1205    * Memory Controller Block
1206    */
1207   m8260MEMCRegisters_t  memc[12];
1208   uint8_t         mem_pad0[8];
1209   uint32_t        mar;
1210   uint8_t         mem_pad1[4];
1211   uint32_t        mamr;
1212   uint32_t        mbmr;
1213   uint32_t        mcmr;
1214   uint32_t          mdmr;
1215   uint8_t         mem_pad2[4];
1216   uint16_t        mptpr;
1217   uint8_t       mem_pad5[2];
1218   uint32_t        mdr;
1219   uint8_t         mem_pad3[4];
1220   uint32_t        psdmr;
1221   uint32_t        lsdmr;
1222   uint8_t       purt;
1223   uint8_t       mem_pad6[3];
1224   uint8_t       psrt;
1225   uint8_t       mem_pad7[3];
1226   uint8_t       lurt;
1227   uint8_t       mem_pad8[3];
1228   uint8_t       lsrt;
1229   uint8_t       mem_pad9[3];
1230   uint32_t        immr;
1231   uint8_t         mem_pad4[84];
1232 
1233 
1234   /*
1235    * System integration timers
1236    */
1237   uint8_t       sit_pad0[32];
1238   uint16_t        tmcntsc;
1239   uint8_t       sit_pad6[2];
1240   uint32_t        tmcnt;
1241   uint32_t          tmcntsec;
1242   uint32_t        tmcntal;
1243   uint8_t       sit_pad2[16];
1244   uint16_t        piscr;
1245   uint8_t       sit_pad5[2];
1246   uint32_t        pitc;
1247   uint32_t        pitr;
1248   uint8_t       sit_pad3[94];
1249   uint8_t       sit_pad4[2390];
1250 
1251 
1252   /*
1253    * Interrupt Controller
1254    */
1255   uint16_t          sicr;
1256   uint8_t       ict_pad1[2];
1257   uint32_t          sivec;
1258   uint32_t          sipnr_h;
1259   uint32_t          sipnr_l;
1260   uint32_t          siprr;
1261   uint32_t          scprr_h;
1262   uint32_t          scprr_l;
1263   uint32_t          simr_h;
1264   uint32_t          simr_l;
1265   uint32_t          siexr;
1266   uint8_t       ict_pad0[88];
1267 
1268 
1269   /*
1270    * Clocks and Reset
1271    */
1272   uint32_t        sccr;
1273   uint8_t       clr_pad1[4];
1274   uint32_t        scmr;
1275   uint8_t       clr_pad2[4];
1276   uint32_t        rsr;
1277   uint32_t        rmr;
1278   uint8_t         clr_pad0[104];
1279 
1280 
1281   /*
1282    * Input/ Output Port
1283    */
1284   uint32_t        pdira;
1285   uint32_t        ppara;
1286   uint32_t        psora;
1287   uint32_t        podra;
1288   uint32_t        pdata;
1289   uint8_t         iop_pad0[12];
1290   uint32_t        pdirb;
1291   uint32_t        pparb;
1292   uint32_t        psorb;
1293   uint32_t        podrb;
1294   uint32_t        pdatb;
1295   uint8_t         iop_pad1[12];
1296   uint32_t        pdirc;
1297   uint32_t        pparc;
1298   uint32_t        psorc;
1299   uint32_t        podrc;
1300   uint32_t        pdatc;
1301   uint8_t         iop_pad2[12];
1302   uint32_t        pdird;
1303   uint32_t        ppard;
1304   uint32_t        psord;
1305   uint32_t        podrd;
1306   uint32_t        pdatd;
1307   uint8_t         iop_pad3[12];
1308 
1309 
1310   /*
1311    * CPM Timers
1312    */
1313   uint8_t         tgcr1;
1314   uint8_t         cpt_pad0[3];
1315   uint8_t         tgcr2;
1316   uint8_t         cpt_pad1[11];
1317   uint16_t        tmr1;
1318   uint16_t        tmr2;
1319   uint16_t        trr1;
1320   uint16_t        trr2;
1321   uint16_t        tcr1;
1322   uint16_t        tcr2;
1323   uint16_t        tcn1;
1324   uint16_t        tcn2;
1325   uint16_t        tmr3;
1326   uint16_t        tmr4;
1327   uint16_t        trr3;
1328   uint16_t        trr4;
1329   uint16_t        tcr3;
1330   uint16_t        tcr4;
1331   uint16_t        tcn3;
1332   uint16_t        tcn4;
1333   uint16_t        ter1;
1334   uint16_t        ter2;
1335   uint16_t        ter3;
1336   uint16_t        ter4;
1337   uint8_t         cpt_pad2[608];
1338 
1339 
1340   /*
1341    * DMA Block
1342    */
1343   uint8_t         sdsr;
1344   uint8_t         dma_pad0[3];
1345   uint8_t         sdmr;
1346   uint8_t         dma_pad1[3];
1347 
1348   uint8_t         idsr1;
1349   uint8_t         dma_pad2[3];
1350   uint8_t         idmr1;
1351   uint8_t         dma_pad3[3];
1352   uint8_t         idsr2;
1353   uint8_t         dma_pad4[3];
1354   uint8_t         idmr2;
1355   uint8_t         dma_pad5[3];
1356   uint8_t         idsr3;
1357   uint8_t         dma_pad6[3];
1358   uint8_t         idmr3;
1359   uint8_t         dma_pad7[3];
1360   uint8_t         idsr4;
1361   uint8_t         dma_pad8[3];
1362   uint8_t         idmr4;
1363   uint8_t         dma_pad9[707];
1364 
1365 
1366   /*
1367    * FCC Block
1368    */
1369   m8260FCCRegisters_t   fcc1;
1370   m8260FCCRegisters_t   fcc2;
1371   m8260FCCRegisters_t   fcc3;
1372 
1373   uint8_t       fcc_pad0[656];
1374 
1375   /*
1376    * BRG 5-8 Block
1377    */
1378   uint32_t        brgc5;
1379   uint32_t        brgc6;
1380   uint32_t        brgc7;
1381   uint32_t        brgc8;
1382   uint8_t       brg_pad0[608];
1383 
1384 
1385   /*
1386    * I2C
1387    */
1388   uint8_t         i2mod;
1389   uint8_t         i2m_pad0[3];
1390   uint8_t         i2add;
1391   uint8_t         i2m_pad1[3];
1392   uint8_t         i2brg;
1393   uint8_t         i2m_pad2[3];
1394   uint8_t         i2com;
1395   uint8_t         i2m_pad3[3];
1396   uint8_t         i2cer;
1397   uint8_t         i2m_pad4[3];
1398   uint8_t         i2cmr;
1399   uint8_t         i2m_pad5[331];
1400 
1401 
1402   /*
1403    * CPM Block
1404    */
1405   uint32_t        cpcr;
1406   uint32_t        rccr;
1407   uint8_t         cpm_pad3[14];
1408   uint16_t        rter;
1409   uint8_t       cpm_pad[2];
1410   uint16_t        rtmr;
1411   uint16_t        rtscr;
1412   uint8_t         cpm_pad4[2];
1413   uint32_t        rtsr;
1414   uint8_t         cpm_pad5[12];
1415 
1416 
1417   /*
1418    * BRG 1-4 Block
1419    */
1420   uint32_t        brgc1;
1421   uint32_t        brgc2;
1422   uint32_t        brgc3;
1423   uint32_t        brgc4;
1424 
1425 
1426   /*
1427    * SCC Block
1428    */
1429   m8260SCCRegisters_t   scc1;
1430   m8260SCCRegisters_t   scc2;
1431   m8260SCCRegisters_t   scc3;
1432   m8260SCCRegisters_t   scc4;
1433 
1434 
1435   /*
1436    * SMC Block
1437    */
1438   m8260SMCRegisters_t    smc1;
1439   m8260SMCRegisters_t    smc2;
1440 
1441 
1442   /*
1443    * SPI Block
1444    */
1445   uint16_t        spmode;
1446   uint8_t         spi_pad0[4];
1447   uint8_t         spie;
1448   uint8_t         spi_pad1[3];
1449   uint8_t         spim;
1450   uint8_t         spi_pad2[2];
1451   uint8_t         spcom;
1452   uint8_t         spi_pad3[82];
1453 
1454 
1455   /*
1456    * CPM Mux Block
1457    */
1458   uint8_t         cmxsi1cr;
1459   uint8_t         cmx_pad0[1];
1460   uint8_t         cmxsi2cr;
1461   uint8_t         cmx_pad1[1];
1462   uint32_t        cmxfcr;
1463   uint32_t        cmxscr;
1464   uint8_t         cmxsmr;
1465   uint8_t         cmx_pad2[1];
1466   uint16_t        cmxuar;
1467   uint8_t         cmx_pad3[16];
1468 
1469 
1470   /*
1471    * SI & MCC Blocks
1472    */
1473   m8260SIRegisters_t    si1;
1474   m8260MCCRegisters_t   mcc1;
1475   m8260SIRegisters_t    si2;
1476   m8260MCCRegisters_t   mcc2;
1477 
1478   uint8_t   mcc_pad0[1152];
1479 
1480   /*
1481    * SI1 RAM
1482    */
1483   uint8_t       si1txram[512];
1484   uint8_t       ram_pad0[512];
1485   uint8_t       si1rxram[512];
1486   uint8_t       ram_pad1[512];
1487 
1488 
1489   /*
1490    * SI2 RAM
1491    */
1492   uint8_t       si2txram[512];
1493   uint8_t       ram_pad2[512];
1494   uint8_t       si2rxram[512];
1495   uint8_t       ram_pad3[512];
1496 
1497 
1498 } m8260_t;
1499 
1500 extern volatile m8260_t m8260;
1501 #endif /* ASM */
1502 
1503 #endif /* _MPC8260_H */
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