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0001 /*
0002  *
0003  * MPC5xx Internal I/O Definitions
0004  */
0005 
0006 /*
0007  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
0008  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
0009  *
0010  *  Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h:
0011  *
0012  *  Submitted By:                                                        *
0013  *                                                                       *
0014  *      Eric Norum <eric@norum.ca>                                       *
0015  *                                                                       *
0016  *  Modified for use with the MPC860 (original code was for MC68360)     *
0017  *  by                                                                   *
0018  *      Jay Monkman                                                      *
0019  *      Frasca International, Inc.                                       *
0020  *      906 E. Airport Rd.                                               *
0021  *      Urbana, IL, 61801                                                *
0022  *                                                                       *
0023  *      jmonkman@frasca.com                                              *
0024  *                                                                       *
0025  *  Modified further for use with the MPC821 by:                         *
0026  *      Andrew Bray <andy@chaos.org.uk>                                  *
0027  *                                                                       *
0028  *  With some corrections/additions by:                                  *
0029  *      Darlene A. Stewart and                                           *
0030  *      Charles-Antoine Gauthier                                         *
0031  *      Institute for Information Technology                             *
0032  *      National Research Council of Canada                              *
0033  *      Ottawa, ON  K1A 0R6                                              *
0034  *                                                                       *
0035  *      Darlene.Stewart@iit.nrc.ca                                       *
0036  *      charles.gauthier@iit.nrc.ca                                      *
0037  *                                                                       *
0038  *      Corrections/additions:                                           *
0039  *        Copyright (c) 1999, National Research Council of Canada        *
0040  *
0041  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
0042  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
0043  *
0044  *  The license and distribution terms for this file may be
0045  *  found in the file LICENSE in this distribution or at
0046  *  http://www.rtems.org/license/LICENSE.
0047  */
0048 
0049 #ifndef _MPC5XX_H
0050 #define _MPC5XX_H
0051 
0052 #include <libcpu/spr.h>
0053 
0054 
0055 #ifndef ASM
0056 
0057 #ifdef __cplusplus
0058 extern "C" {
0059 #endif
0060 
0061 /*
0062  * Macros for accessing Special Purpose Registers (SPRs)
0063  */
0064 
0065 #define _eieio   __asm__ volatile ("eieio\n"::)
0066 #define _sync    __asm__ volatile ("sync\n"::)
0067 #define _isync   __asm__ volatile ("isync\n"::)
0068 
0069 /*
0070  * Core Registers (SPRs)
0071  */
0072 #define DER             149     /* Debug Enable Register */
0073 #define IMMR            638     /* Internal Memory Map Register */
0074 #define IMMR_FLEN   (1<<11)    /* Internal flash ROM enabled */
0075 
0076 /*
0077  * Interrupt Control Registers (SPRs)
0078  */
0079 #define EIE              80     /* External Interrupt Enable Register */
0080 #define EID              81     /* External Interrupt Disable Register */
0081 #define NRI              82     /* Non-Recoverable Interrupt Register */
0082 
0083 #define ECR             148     /* Exception Cause Register */
0084 
0085 /*
0086  * Bus Control Registers (SPRs)
0087  */
0088 #define LCTRL1          156     /* L-Bus Support Control Register 1 */
0089 #define LCTRL2          157     /* L-Bus Support Control Register 2 */
0090 #define ICTRL           158     /* I-Bus Support Control Register */
0091 
0092 /*
0093  * Burst Buffer Control Registers (SPRs)
0094  */
0095 #define BBCMCR          560     /* Burst Buffer Configuration Register */
0096 #define BBCMCR_BE       (1<<13) /* Burst enable */
0097 #define BBCMCR_ETRE     (1<<12) /* Exception table relocation enable */
0098 
0099 #define MI_RBA0         784     /* Region 0 Address Register */
0100 #define MI_RBA1         785     /* Region 1 Address Register */
0101 #define MI_RBA2         786     /* Region 2 Address Register */
0102 #define MI_RBA3         787     /* Region 3 Address Register */
0103 
0104 #define MI_RA0          816     /* Region 0 Attribute Register */
0105 #define MI_RA1          817     /* Region 1 Attribute Register */
0106 #define MI_RA2          818     /* Region 2 Attribute Register */
0107 #define MI_RA3          819     /* Region 3 Attribute Register */
0108 #define MI_GRA          528     /* Region Global Attribute Register */
0109 #define MI_RA_PP    (3 << 10)   /* Protection bits: */
0110 #define MI_RA_PP_SUPV   (1 << 10)   /*   Supervisor */
0111 #define MI_RA_PP_USER   (2 << 10)   /*   User */
0112 #define MI_RA_G     (1 << 6)    /* Guarded region */
0113 
0114 
0115 /*
0116  * L-Bus to U-Bus Interface (L2U) Registers (SPRs)
0117  */
0118 #define L2U_MCR         568     /* L2U Module Configuration Register */
0119 
0120 #define L2U_RBA0        792     /* L2U Region 0 Address Register */
0121 #define L2U_RBA1        793     /* L2U Region 1 Address Register */
0122 #define L2U_RBA2        794     /* L2U Region 2 Address Register */
0123 #define L2U_RBA3        795     /* L2U Region 3 Address Register */
0124 
0125 #define L2U_RA0         824     /* L2U Region 0 Attribute Register */
0126 #define L2U_RA1         825     /* L2U Region 1 Attribute Register */
0127 #define L2U_RA2         826     /* L2U Region 2 Attribute Register */
0128 #define L2U_RA3         827     /* L2U Region 3 Attribute Register */
0129 #define L2U_GRA         536     /* L2U Global Region Attribute Register */
0130 #define L2U_RA_PP   (3 << 10)   /* Protection bits: */
0131 #define L2U_RA_PP_SUPV  (1 << 10)   /*   Supervisor */
0132 #define L2U_RA_PP_USER  (2 << 10)   /*   User */
0133 #define L2U_RA_G    (1 << 6)    /* Guarded region */
0134 
0135 
0136 /*
0137  *************************************************************************
0138  *                         REGISTER SUBBLOCKS                            *
0139  *************************************************************************
0140  */
0141 
0142 /*
0143  *************************************************************************
0144  *                 System Protection Control Register (SYPCR)            *
0145  *************************************************************************
0146  */
0147 #define USIU_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
0148 #define USIU_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
0149 #define USIU_SYPCR_BME          (1<<7)      /* Bus monitor enable */
0150 #define USIU_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
0151 #define USIU_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
0152 #define USIU_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
0153 #define USIU_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
0154 
0155 #define USIU_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
0156 #define USIU_SYPCR_BME          (1<<7)      /* Bus monitor enable */
0157 #define USIU_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
0158 #define USIU_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
0159 #define USIU_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
0160 #define USIU_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
0161 
0162 /*
0163  *************************************************************************
0164  *                 Software Service Register (SWSR)                      *
0165  *************************************************************************
0166  */
0167 #define TICKLE_WATCHDOG()       \
0168 do {                    \
0169   usiu.swsr = 0x556C;           \
0170   usiu.swsr = 0xAA39;           \
0171 } while (0)             \
0172 
0173 /*
0174  *************************************************************************
0175  *                        Memory Control Registers                       *
0176  *************************************************************************
0177  */
0178 #define USIU_MEMC_BR_BA(x)      (((uint32_t)x)&0xffff8000)
0179                      /* Base address */
0180 #define USIU_MEMC_BR_AT(x)      ((x)<<12) /* Address type */
0181 #define USIU_MEMC_BR_PS8        (1<<10)  /* 8 bit port */
0182 #define USIU_MEMC_BR_PS16       (2<<10)  /* 16 bit port */
0183 #define USIU_MEMC_BR_PS32       (0<<10)  /* 32 bit port */
0184 #define USIU_MEMC_BR_WP         (1<<8)   /* Write protect */
0185 #define USIU_MEMC_BR_WEBS       (1<<5)   /* Write enable/byte select */
0186 #define USIU_MEMC_BR_TBDIP      (1<<4)   /* Toggle-Burst data in progress*/
0187 #define USIU_MEMC_BR_LBDIP      (1<<3)   /* Late-burst data in progress */
0188 #define USIU_MEMC_BR_SETA       (1<<2)   /* External transfer acknowledge */
0189 #define USIU_MEMC_BR_BI         (1<<1)   /* Burst inhibit */
0190 #define USIU_MEMC_BR_V          (1<<0)   /* Base/Option register are valid */
0191 
0192 #define USIU_MEMC_OR_32K        0xffff8000      /* Address range */
0193 #define USIU_MEMC_OR_64K        0xffff0000
0194 #define USIU_MEMC_OR_128K       0xfffe0000
0195 #define USIU_MEMC_OR_256K       0xfffc0000
0196 #define USIU_MEMC_OR_512K       0xfff80000
0197 #define USIU_MEMC_OR_1M         0xfff00000
0198 #define USIU_MEMC_OR_2M         0xffe00000
0199 #define USIU_MEMC_OR_4M         0xffc00000
0200 #define USIU_MEMC_OR_8M         0xff800000
0201 #define USIU_MEMC_OR_16M        0xff000000
0202 #define USIU_MEMC_OR_32M        0xfe000000
0203 #define USIU_MEMC_OR_64M        0xfc000000
0204 #define USIU_MEMC_OR_128        0xf8000000
0205 #define USIU_MEMC_OR_256M       0xf0000000
0206 #define USIU_MEMC_OR_512M       0xe0000000
0207 #define USIU_MEMC_OR_1G         0xc0000000
0208 #define USIU_MEMC_OR_2G         0x80000000
0209 #define USIU_MEMC_OR_4G         0x00000000
0210 #define USIU_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
0211 #define USIU_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
0212 #define USIU_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
0213 #define USIU_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
0214 #define USIU_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
0215 #define USIU_MEMC_OR_ETHR       (1<<8)      /* Extended hold time on reads */
0216 #define USIU_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
0217 #define USIU_MEMC_OR_BSCY(x)    ((x)<<1)    /* Burst beat length in clocks */
0218 #define USIU_MEMC_OR_TRLX       (1<<0)      /* Relaxed timing in GPCM */
0219 
0220 /*
0221  *************************************************************************
0222  *                      Clocks and Reset Controlmer                      *
0223  *************************************************************************
0224  */
0225 
0226 #define USIU_SCCR_DBCT          (1<<31)    /* Disable backup clock for timers */
0227 #define USIU_SCCR_COM(x)    ((x)<<29)  /* Clock output mode */
0228 #define USIU_SCCR_RTDIV         (1<<24)    /* RTC, PIT divide by 256, not 4 */
0229 #define USIU_PRQEN              (1<<21)    /* MSR[POW] controls frequency */
0230 #define USIU_SCCR_EBDF(x)       ((x)<<17)  /* External bus division factor */
0231 #define USIU_LME                (1<<16)    /* Enable limp mode */
0232 #define USIU_ENGDIV(x)          ((x)<<9)   /* Set engineering clock divisor */
0233 
0234 #define USIU_PLPRCR_MF(x)   (((x)-1)<<20)   /* PLL mult. factor (true) */
0235 #define USIU_PLPRCR_SPLS        (1<<16)    /* System PLL locked */
0236 #define USIU_PLPRCR_TEXPS   (1<<14)    /* Assert TEXP always */
0237 
0238 /*
0239  *************************************************************************
0240  *                      Programmable Interval Timer                      *
0241  *************************************************************************
0242  */
0243 #define USIU_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
0244 #define USIU_PISCR_PS           (1<<7)    /* PIT Interrupt state */
0245 #define USIU_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
0246 #define USIU_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
0247 #define USIU_PISCR_PTE          (1<<0)    /* PIT enable */
0248 
0249 /*
0250  *************************************************************************
0251  *                             Time Base                                 *
0252  *************************************************************************
0253  */
0254 #define USIU_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
0255 #define USIU_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
0256 #define USIU_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
0257 #define USIU_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
0258 #define USIU_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
0259 #define USIU_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
0260 #define USIU_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
0261 
0262 /*
0263  *************************************************************************
0264  *                       SIU Interrupt Mask                              *
0265  *************************************************************************
0266  */
0267 #define USIU_SIMASK_IRM0        (1<<31)
0268 #define USIU_SIMASK_LVM0        (1<<30)
0269 #define USIU_SIMASK_IRM1        (1<<29)
0270 #define USIU_SIMASK_LVM1        (1<<28)
0271 #define USIU_SIMASK_IRM2        (1<<27)
0272 #define USIU_SIMASK_LVM2        (1<<26)
0273 #define USIU_SIMASK_IRM3        (1<<25)
0274 #define USIU_SIMASK_LVM3        (1<<24)
0275 #define USIU_SIMASK_IRM4        (1<<23)
0276 #define USIU_SIMASK_LVM4        (1<<22)
0277 #define USIU_SIMASK_IRM5        (1<<21)
0278 #define USIU_SIMASK_LVM5        (1<<20)
0279 #define USIU_SIMASK_IRM6        (1<<19)
0280 #define USIU_SIMASK_LVM6        (1<<18)
0281 #define USIU_SIMASK_IRM7        (1<<17)
0282 #define USIU_SIMASK_LVM7        (1<<16)
0283 
0284 /*
0285  *************************************************************************
0286  *                       SIU Module Control                              *
0287  *************************************************************************
0288  */
0289 #define USIU_SIUMCR_EARB        (1<<31)
0290 #define USIU_SIUMCR_EARP0       (0<<28)
0291 #define USIU_SIUMCR_EARP1       (1<<28)
0292 #define USIU_SIUMCR_EARP2       (2<<28)
0293 #define USIU_SIUMCR_EARP3       (3<<28)
0294 #define USIU_SIUMCR_EARP4       (4<<28)
0295 #define USIU_SIUMCR_EARP5       (5<<28)
0296 #define USIU_SIUMCR_EARP6       (6<<28)
0297 #define USIU_SIUMCR_EARP7       (7<<28)
0298 #define USIU_SIUMCR_DSHW        (1<<23)
0299 #define USIU_SIUMCR_DBGC0       (0<<21)
0300 #define USIU_SIUMCR_DBGC1       (1<<21)
0301 #define USIU_SIUMCR_DBGC2       (2<<21)
0302 #define USIU_SIUMCR_DBGC3       (3<<21)
0303 #define USIU_SIUMCR_DBPC        (1<<20)
0304 #define USIU_SIUMCR_ATWC        (1<<19)
0305 #define USIU_SIUMCR_GPC0        (0<<17)
0306 #define USIU_SIUMCR_GPC1        (1<<17)
0307 #define USIU_SIUMCR_GPC2        (2<<17)
0308 #define USIU_SIUMCR_GPC3        (3<<17)
0309 #define USIU_SIUMCR_DLK         (1<<16)
0310 #define USIU_SIUMCR_SC0         (0<<13)
0311 #define USIU_SIUMCR_SC1         (1<<13)
0312 #define USIU_SIUMCR_SC2         (2<<13)
0313 #define USIU_SIUMCR_SC3         (3<<13)
0314 #define USIU_SIUMCR_RCTX        (1<<12)
0315 #define USIU_SIUMCR_MLRC0       (0<<10)
0316 #define USIU_SIUMCR_MLRC1       (1<<10)
0317 #define USIU_SIUMCR_MLRC2       (2<<10)
0318 #define USIU_SIUMCR_MLRC3       (3<<10)
0319 #define USIU_SIUMCR_MTSC        (1<<7)
0320 
0321 /*
0322  *  Value to write to a key register to unlock the corresponding SIU register
0323  */
0324 #define USIU_UNLOCK_KEY         0x55CCAA33
0325 
0326 /*
0327  *************************************************************************
0328  *                       UIMB Module Control                             *
0329  *************************************************************************
0330  */
0331 #define UIMB_UMCR_STOP          (1<<31)
0332 #define UIMB_UMCR_IRQMUX(x)     ((x)<<29)
0333 #define UIMB_UMCR_HSPEED        (1<<28)
0334 
0335 /*
0336  *************************************************************************
0337  *              QSMCM Serial Communications Interface (SCI)              *
0338  *************************************************************************
0339  */
0340 
0341 
0342 #define QSMCM_ILDSCI(x)        ((x)<<8)    /* SCI interrupt level */
0343 
0344 #define QSMCM_SCI_BAUD(x)      ((x)&0x1FFF) /* Baud rate field */
0345 
0346 #define QSMCM_SCI_LOOPS        (1<<14)     /* Loopback test mode */
0347 #define QSMCM_SCI_WOMS         (1<<13)     /* Wire-or mode select */
0348 #define QSMCM_SCI_ILT          (1<<12)     /* Idle-line detect type */
0349 #define QSMCM_SCI_PT           (1<<11)     /* Parity type */
0350 #define QSMCM_SCI_PE           (1<<10)     /* Parity enable */
0351 #define QSMCM_SCI_M            (1<<9)      /* 11-bit mode */
0352 #define QSMCM_SCI_WAKE         (1<<8)      /* Wakeup mode */
0353 
0354 #define QSMCM_SCI_TIE          (1<<7)      /* Transmitter interrupt enable */
0355 #define QSMCM_SCI_TCIE         (1<<6)      /* Transmit complete intr. enable */
0356 #define QSMCM_SCI_RIE          (1<<5)      /* Receiver interrupt enable */
0357 #define QSMCM_SCI_ILIE         (1<<4)      /* Idle line interrupt enable */
0358 #define QSMCM_SCI_TE           (1<<3)      /* Transmitter enable */
0359 #define QSMCM_SCI_RE           (1<<2)      /* Receiver enable */
0360 #define QSMCM_SCI_RWU          (1<<1)      /* Receiver wake-up enable */
0361 #define QSMCM_SCI_SBK          (1<<0)      /* Send break */
0362 
0363 #define QSMCM_SCI_TDRE         (1<<8)      /* Transmit data register empty */
0364 #define QSMCM_SCI_TC           (1<<7)      /* Transmit complete */
0365 #define QSMCM_SCI_RDRF         (1<<6)      /* Receive data register full */
0366 #define QSMCM_SCI_RAF          (1<<5)      /* Receiver active flag */
0367 #define QSMCM_SCI_IDLE         (1<<4)      /* Idle line detected */
0368 #define QSMCM_SCI_OR           (1<<3)      /* Receiver overrun error */
0369 #define QSMCM_SCI_NF           (1<<2)      /* Receiver noise error flag */
0370 #define QSMCM_SCI_FE           (1<<1)      /* Receiver framing error */
0371 #define QSMCM_SCI_PF           (1<<0)      /* Receiver parity error */
0372 
0373 /*
0374  *************************************************************************
0375  *   Unified System Interface Unit                                       *
0376  *************************************************************************
0377  */
0378 
0379 /*
0380  * Memory controller registers
0381  */
0382 typedef struct m5xxMEMCRegisters_ {
0383   uint32_t        _br;
0384   uint32_t        _or;    /* Used to be called 'or'; reserved ANSI C++ keyword */
0385 } m5xxMEMCRegisters_t;
0386 
0387 /*
0388  * USIU itself
0389  */
0390 typedef struct usiu_ {
0391   /*
0392    * SIU Block
0393    */
0394   uint32_t      siumcr;
0395   uint32_t      sypcr;
0396   uint32_t      _pad70;
0397   uint16_t      _pad0;
0398   uint16_t      swsr;
0399   uint32_t      sipend;
0400   uint32_t      simask;
0401   uint32_t      siel;
0402   uint32_t      sivec;
0403   uint32_t      tesr;
0404   uint32_t      sgpiodt1;
0405   uint32_t      sgpiodt2;
0406   uint32_t      sgpiocr;
0407   uint32_t      emcr;
0408   uint8_t   _pad71[0x03C-0x034];
0409   uint32_t      pdmcr;
0410   uint8_t       _pad2[0x100-0x40];
0411 
0412   /*
0413    * MEMC Block
0414    */
0415   m5xxMEMCRegisters_t   memc[4];
0416   uint8_t       _pad7[0x140-0x120];
0417   uint32_t      dmbr;
0418   uint32_t      dmor;
0419   uint8_t       _pad8[0x178-0x148];
0420   uint16_t      mstat;
0421   uint8_t       _pad9[0x200-0x17A];
0422 
0423   /*
0424    * System integration timers
0425    */
0426   uint16_t      tbscr;
0427   uint16_t      _pad10;
0428   uint32_t      tbreff0;
0429   uint32_t      tbreff1;
0430   uint8_t       _pad11[0x220-0x20c];
0431   uint16_t      rtcsc;
0432   uint16_t      _pad12;
0433   uint32_t      rtc;
0434   uint32_t      rtsec;
0435   uint32_t      rtcal;
0436   uint32_t      _pad13[4];
0437   uint16_t      piscr;
0438   uint16_t      _pad14;
0439   uint16_t      pitc;
0440   uint16_t      _pad_14_1;
0441   uint16_t      pitr;
0442   uint16_t      _pad_14_2;
0443   uint8_t       _pad15[0x280-0x24c];
0444 
0445   /*
0446    * Clocks and Reset
0447    */
0448   uint32_t      sccr;
0449   uint32_t      plprcr;
0450   uint16_t      rsr;
0451   uint16_t  _pad72;
0452   uint16_t  colir;
0453   uint16_t  _pad73;
0454   uint16_t  vsrmcr;
0455   uint8_t       _pad16[0x300-0x292];
0456 
0457   /*
0458    * System integration timers keys
0459    */
0460   uint32_t      tbscrk;
0461   uint32_t      tbreff0k;
0462   uint32_t      tbreff1k;
0463   uint32_t      tbk;
0464   uint32_t      _pad17[4];
0465   uint32_t      rtcsk;
0466   uint32_t      rtck;
0467   uint32_t      rtseck;
0468   uint32_t      rtcalk;
0469   uint32_t      _pad18[4];
0470   uint32_t      piscrk;
0471   uint32_t      pitck;
0472   uint8_t       _pad19[0x380-0x348];
0473 
0474   /*
0475    * Clocks and Reset Keys
0476    */
0477   uint32_t      sccrk;
0478   uint32_t      plprck;
0479   uint32_t      rsrk;
0480   uint8_t       _pad20[0x400-0x38c];
0481 } usiu_t;
0482 
0483 extern volatile usiu_t usiu;    /* defined in linkcmds */
0484 
0485 /*
0486  *************************************************************************
0487  *   Inter-Module Bus and Devices                                        *
0488  *************************************************************************
0489  */
0490 
0491 /*
0492  * Dual-Port TPU RAM (DPTRAM)
0493  */
0494 typedef struct m5xxDPTRAMRegisters_ {
0495   uint8_t   pad[0x4000];        /* define later */
0496 } m5xxDPTRAMRegisters_t;
0497 
0498 /*
0499  * Time Processor Unit (TPU)
0500  */
0501 typedef struct m5xxTPU3Registers_ {
0502   uint8_t   pad[0x400];     /* define later */
0503 } m5xxTPU3Registers_t;
0504 
0505 /*
0506  * Queued A/D Converter (QADC)
0507  */
0508 typedef struct m5xxQADC64Registers_ {
0509   uint8_t   pad[0x400];     /* define later */
0510 } m5xxQADC64Registers_t;
0511 
0512 /*
0513  * Serial Communications Interface (SCI)
0514  */
0515 typedef struct m5xxSCIRegisters_ {
0516   uint16_t        sccr0;
0517   uint16_t        sccr1;
0518   uint16_t        scsr;
0519   uint16_t        scdr;
0520 } m5xxSCIRegisters_t;
0521 
0522 /*
0523  * Serial Peripheral Interface (SPI)
0524  */
0525 typedef struct m5xxSPIRegisters_ {
0526   uint16_t        spcr0;
0527   uint16_t        spcr1;
0528   uint16_t        spcr2;
0529   uint8_t         spcr3;
0530   uint8_t         spsr;
0531 } m5xxSPIRegisters_t;
0532 
0533 /*
0534  * Queued Serial Multi-Channel Module (QSMCM)
0535  */
0536 typedef struct m5xxQSMCMRegisters_ {
0537   uint16_t      qsmcmmcr;
0538   uint16_t      qtest;
0539   uint16_t      qdsci_il;
0540   uint16_t      qspi_il;
0541 
0542   m5xxSCIRegisters_t    sci1;
0543 
0544   uint8_t       _pad10[0x14-0x10];
0545 
0546   uint16_t      portqs;
0547   uint16_t      pqspar;
0548   m5xxSPIRegisters_t    spi;
0549 
0550   m5xxSCIRegisters_t    sci2;
0551 
0552   uint16_t      qsci1cr;
0553   uint16_t      qsci1sr;
0554   uint16_t      sctq[0x10];
0555   uint16_t      scrq[0x10];
0556 
0557   uint8_t       _pad6C[0x140-0x06C];
0558 
0559   uint16_t      recram[0x20];
0560   uint16_t      tranram[0x20];
0561   uint16_t      comdram[0x20];
0562 } m5xxQSMCMRegisters_t;
0563 
0564 /*
0565  * Modular Input/Output System (MIOS)
0566  */
0567 typedef struct m5xxMIOS1Registers_ {
0568   uint8_t   pad[0x1000];        /* define later */
0569 } m5xxMIOS1Registers_t;
0570 
0571 /*
0572  * Can 2.0B Controller (TouCAN)
0573  */
0574 typedef struct m5xxTouCANRegisters_ {
0575   uint8_t   pad[0x400];     /* define later */
0576 } m5xxTouCANRegisters_t;
0577 
0578 /*
0579  * U-Bus to IMB3 Bus Interface Module (UIMB)
0580  */
0581 typedef struct m5xxUIMBRegisters_ {
0582   uint32_t      umcr;
0583   uint32_t      utstcreg;
0584   uint32_t      uipend;
0585 } m5xxUIMBRegisters_t;
0586 
0587 /*
0588  * IMB itself
0589  */
0590 typedef struct imb_ {
0591   m5xxDPTRAMRegisters_t dptram;
0592   m5xxTPU3Registers_t   tpu[2];
0593   m5xxQADC64Registers_t qadc[2];
0594   m5xxQSMCMRegisters_t  qsmcm;
0595   uint8_t       _pad5200[0x6000-0x5200];
0596   m5xxMIOS1Registers_t  mios;
0597   m5xxTouCANRegisters_t toucan[2];
0598   uint8_t       _pad7800[0x7F80-0x7800];
0599   m5xxUIMBRegisters_t   uimb;
0600 } imb_t;
0601 
0602 extern volatile imb_t imb;      /* defined in linkcmds */
0603 
0604 
0605 /*
0606  * Methods shared across libcpu and the BSP.
0607  */
0608 void clockOn(void* unused);
0609 void clockOff(void* unused);
0610 int clockIsOn(void* unused);
0611 rtems_isr Clock_isr(rtems_vector_number vector);
0612 
0613 #ifdef __cplusplus
0614 }
0615 #endif
0616 
0617 #endif /* ASM */
0618 
0619 #endif /* _MPC5XX_H */
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