include/libcpu/mmu.h

0001 /*
0002  * mmu.h
0003  *
0004  *  PowerPC memory management structures
0005  *
0006  * It is a stripped down version of linux ppc file...
0007  *
0008  * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
0009  *                     Canon Centre Recherche France.
0010  *
0011  *  The license and distribution terms for this file may be
0012  *  found in the file LICENSE in this distribution or at
0013  *  http://www.rtems.org/license/LICENSE.
0014  */
0015
0016 #ifndef _LIBCPU_MMU_H
0017 #define _LIBCPU_MMU_H
0018
0019 #ifndef ASM
0020 /* Hardware Page Table Entry */
0021 typedef struct _PTE {
0022     unsigned long v:1;  /* Entry is valid */
0023     unsigned long vsid:24;  /* Virtual segment identifier */
0024     unsigned long h:1;  /* Hash algorithm indicator */
0025     unsigned long api:6;    /* Abbreviated page index */
0026     unsigned long rpn:20;   /* Real (physical) page number */
0027     unsigned long    :3;    /* Unused */
0028     unsigned long r:1;  /* Referenced */
0029     unsigned long c:1;  /* Changed */
0030     unsigned long w:1;  /* Write-thru cache mode */
0031     unsigned long i:1;  /* Cache inhibited */
0032     unsigned long m:1;  /* Memory coherence */
0033     unsigned long g:1;  /* Guarded */
0034     unsigned long  :1;  /* Unused */
0035     unsigned long pp:2; /* Page protection */
0036 } PTE;
0037
0038 /* Values for PP (assumes Ks=0, Kp=1) */
0039 #define PP_RWXX 0   /* Supervisor read/write, User none */
0040 #define PP_RWRX 1   /* Supervisor read/write, User read */
0041 #define PP_RWRW 2   /* Supervisor read/write, User read/write */
0042 #define PP_RXRX 3   /* Supervisor read,       User read */
0043
0044 /* Segment Register */
0045 typedef struct _SEGREG {
0046     unsigned long t:1;  /* Normal or I/O  type */
0047     unsigned long ks:1; /* Supervisor 'key' (normally 0) */
0048     unsigned long kp:1; /* User 'key' (normally 1) */
0049     unsigned long n:1;  /* No-execute */
0050     unsigned long :4;   /* Unused */
0051     unsigned long vsid:24;  /* Virtual Segment Identifier */
0052 } SEGREG;
0053
0054 /* Block Address Translation (BAT) Registers */
0055 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
0056     unsigned long bepi:15;  /* Effective page index (virtual address) */
0057     unsigned long :8;   /* unused */
0058     unsigned long w:1;
0059     unsigned long i:1;  /* Cache inhibit */
0060     unsigned long m:1;  /* Memory coherence */
0061     unsigned long ks:1; /* Supervisor key (normally 0) */
0062     unsigned long kp:1; /* User key (normally 1) */
0063     unsigned long pp:2; /* Page access protections */
0064 } P601_BATU;
0065
0066 typedef struct _BATU {      /* Upper part of BAT (all except 601) */
0067     unsigned long bepi:15;  /* Effective page index (virtual address) */
0068     unsigned long :4;   /* Unused */
0069     unsigned long bl:11;    /* Block size mask */
0070     unsigned long vs:1; /* Supervisor valid */
0071     unsigned long vp:1; /* User valid */
0072 } BATU;
0073
0074 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
0075     unsigned long brpn:15;  /* Real page index (physical address) */
0076     unsigned long :10;  /* Unused */
0077     unsigned long v:1;  /* Valid bit */
0078     unsigned long bl:6; /* Block size mask */
0079 } P601_BATL;
0080
0081 typedef struct _BATL {      /* Lower part of BAT (all except 601) */
0082     unsigned long brpn:15;  /* Real page index (physical address) */
0083     unsigned long :10;  /* Unused */
0084     unsigned long w:1;  /* Write-thru cache */
0085     unsigned long i:1;  /* Cache inhibit */
0086     unsigned long m:1;  /* Memory coherence */
0087     unsigned long g:1;  /* Guarded (MBZ in IBAT) */
0088     unsigned long :1;   /* Unused */
0089     unsigned long pp:2; /* Page access protections */
0090 } BATL;
0091
0092 typedef struct _BAT {
0093     BATU batu;      /* Upper register */
0094     BATL batl;      /* Lower register */
0095 } BAT;
0096
0097 typedef struct _P601_BAT {
0098     P601_BATU batu;     /* Upper register */
0099     P601_BATL batl;     /* Lower register */
0100 } P601_BAT;
0101
0102 /* Block size masks */
0103 #define BL_128K 0x000
0104 #define BL_256K 0x001
0105 #define BL_512K 0x003
0106 #define BL_1M   0x007
0107 #define BL_2M   0x00F
0108 #define BL_4M   0x01F
0109 #define BL_8M   0x03F
0110 #define BL_16M  0x07F
0111 #define BL_32M  0x0FF
0112 #define BL_64M  0x1FF
0113 #define BL_128M 0x3FF
0114 #define BL_256M 0x7FF
0115
0116 /* BAT Access Protection */
0117 #define BPP_XX  0x00        /* No access */
0118 #define BPP_RX  0x01        /* Read only */
0119 #define BPP_RW  0x02        /* Read/write */
0120
0121 /*
0122  * Simulated two-level MMU.  This structure is used by the kernel
0123  * to keep track of MMU mappings and is used to update/maintain
0124  * the hardware HASH table which is really a cache of mappings.
0125  *
0126  * The simulated structures mimic the hardware available on other
0127  * platforms, notably the 80x86 and 680x0.
0128  */
0129
0130 typedef struct _pte {
0131     unsigned long page_num:20;
0132     unsigned long flags:12;     /* Page flags (some unused bits) */
0133 } pte;
0134
0135 #define PD_SHIFT (10+12)        /* Page directory */
0136 #define PD_MASK  0x03FF
0137 #define PT_SHIFT (12)           /* Page Table */
0138 #define PT_MASK  0x03FF
0139 #define PG_SHIFT (12)           /* Page Entry */
0140
0141
0142 /* MMU context */
0143
0144 typedef struct _MMU_context {
0145     SEGREG  segs[16];   /* Segment registers */
0146     pte **pmap;     /* Two-level page-map structure */
0147 } MMU_context;
0148
0149 /* Used to set up SDR1 register */
0150 #define HASH_TABLE_SIZE_64K 0x00010000
0151 #define HASH_TABLE_SIZE_128K    0x00020000
0152 #define HASH_TABLE_SIZE_256K    0x00040000
0153 #define HASH_TABLE_SIZE_512K    0x00080000
0154 #define HASH_TABLE_SIZE_1M  0x00100000
0155 #define HASH_TABLE_SIZE_2M  0x00200000
0156 #define HASH_TABLE_SIZE_4M  0x00400000
0157 #define HASH_TABLE_MASK_64K 0x000
0158 #define HASH_TABLE_MASK_128K    0x001
0159 #define HASH_TABLE_MASK_256K    0x003
0160 #define HASH_TABLE_MASK_512K    0x007
0161 #define HASH_TABLE_MASK_1M  0x00F
0162 #define HASH_TABLE_MASK_2M  0x01F
0163 #define HASH_TABLE_MASK_4M  0x03F
0164
0165 /* invalidate a TLB entry */
0166 static inline void _tlbie(unsigned long va)
0167 {
0168     asm volatile ("tlbie %0, 0" : : "r"(va));
0169 }
0170
0171 extern void _tlbia(void);       /* invalidate all TLB entries */
0172 #endif /* ASM */
0173
0174 /* Control/status registers for the MPC8xx.
0175  * A write operation to these registers causes serialized access.
0176  * During software tablewalk, the registers used perform mask/shift-add
0177  * operations when written/read.  A TLB entry is created when the Mx_RPN
0178  * is written, and the contents of several registers are used to
0179  * create the entry.
0180  */
0181 #define MI_CTR      784 /* Instruction TLB control register */
0182 #define MI_GPM      0x80000000  /* Set domain manager mode */
0183 #define MI_PPM      0x40000000  /* Set subpage protection */
0184 #define MI_CIDEF    0x20000000  /* Set cache inhibit when MMU dis */
0185 #define MI_RSV4I    0x08000000  /* Reserve 4 TLB entries */
0186 #define MI_PPCS     0x02000000  /* Use MI_RPN prob/priv state */
0187 #define MI_IDXMASK  0x00001f00  /* TLB index to be loaded */
0188 #define MI_RESETVAL 0x00000000  /* Value of register at reset */
0189
0190 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
0191  * Ks = 0, Kp = 1.
0192  */
0193 #define MI_AP       786
0194 #define MI_Ks       0x80000000  /* Should not be set */
0195 #define MI_Kp       0x40000000  /* Should always be set */
0196
0197 /* The effective page number register.  When read, contains the information
0198  * about the last instruction TLB miss.  When MI_RPN is written, bits in
0199  * this register are used to create the TLB entry.
0200  */
0201 #define MI_EPN      787
0202 #define MI_EPNMASK  0xfffff000  /* Effective page number for entry */
0203 #define MI_EVALID   0x00000200  /* Entry is valid */
0204 #define MI_ASIDMASK 0x0000000f  /* ASID match value */
0205                     /* Reset value is undefined */
0206
0207 /* A "level 1" or "segment" or whatever you want to call it register.
0208  * For the instruction TLB, it contains bits that get loaded into the
0209  * TLB entry when the MI_RPN is written.
0210  */
0211 #define MI_TWC      789
0212 #define MI_APG      0x000001e0  /* Access protection group (0) */
0213 #define MI_GUARDED  0x00000010  /* Guarded storage */
0214 #define MI_PSMASK   0x0000000c  /* Mask of page size bits */
0215 #define MI_PS8MEG   0x0000000c  /* 8M page size */
0216 #define MI_PS512K   0x00000004  /* 512K page size */
0217 #define MI_PS4K_16K 0x00000000  /* 4K or 16K page size */
0218 #define MI_SVALID   0x00000001  /* Segment entry is valid */
0219                     /* Reset value is undefined */
0220
0221 /* Real page number.  Defined by the pte.  Writing this register
0222  * causes a TLB entry to be created for the instruction TLB, using
0223  * additional information from the MI_EPN, and MI_TWC registers.
0224  */
0225 #define MI_RPN      790
0226
0227 /* Define an RPN value for mapping kernel memory to large virtual
0228  * pages for boot initialization.  This has real page number of 0,
0229  * large page size, shared page, cache enabled, and valid.
0230  * Also mark all subpages valid and write access.
0231  */
0232 #define MI_BOOTINIT 0x000001fd
0233
0234 #define MD_CTR      792 /* Data TLB control register */
0235 #define MD_GPM      0x80000000  /* Set domain manager mode */
0236 #define MD_PPM      0x40000000  /* Set subpage protection */
0237 #define MD_CIDEF    0x20000000  /* Set cache inhibit when MMU dis */
0238 #define MD_WTDEF    0x10000000  /* Set writethrough when MMU dis */
0239 #define MD_RSV4I    0x08000000  /* Reserve 4 TLB entries */
0240 #define MD_TWAM     0x04000000  /* Use 4K page hardware assist */
0241 #define MD_PPCS     0x02000000  /* Use MI_RPN prob/priv state */
0242 #define MD_IDXMASK  0x00001f00  /* TLB index to be loaded */
0243 #define MD_RESETVAL 0x04000000  /* Value of register at reset */
0244
0245 #define M_CASID     793 /* Address space ID (context) to match */
0246 #define MC_ASIDMASK 0x0000000f  /* Bits used for ASID value */
0247
0248
0249 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
0250  * Ks = 0, Kp = 1.
0251  */
0252 #define MD_AP       794
0253 #define MD_Ks       0x80000000  /* Should not be set */
0254 #define MD_Kp       0x40000000  /* Should always be set */
0255
0256 /* The effective page number register.  When read, contains the information
0257  * about the last instruction TLB miss.  When MD_RPN is written, bits in
0258  * this register are used to create the TLB entry.
0259  */
0260 #define MD_EPN      795
0261 #define MD_EPNMASK  0xfffff000  /* Effective page number for entry */
0262 #define MD_EVALID   0x00000200  /* Entry is valid */
0263 #define MD_ASIDMASK 0x0000000f  /* ASID match value */
0264                     /* Reset value is undefined */
0265
0266 /* The pointer to the base address of the first level page table.
0267  * During a software tablewalk, reading this register provides the address
0268  * of the entry associated with MD_EPN.
0269  */
0270 #define M_TWB       796
0271 #define M_L1TB      0xfffff000  /* Level 1 table base address */
0272 #define M_L1INDX    0x00000ffc  /* Level 1 index, when read */
0273                     /* Reset value is undefined */
0274
0275 /* A "level 1" or "segment" or whatever you want to call it register.
0276  * For the data TLB, it contains bits that get loaded into the TLB entry
0277  * when the MD_RPN is written.  It is also provides the hardware assist
0278  * for finding the PTE address during software tablewalk.
0279  */
0280 #define MD_TWC      797
0281 #define MD_L2TB     0xfffff000  /* Level 2 table base address */
0282 #define MD_L2INDX   0xfffffe00  /* Level 2 index (*pte), when read */
0283 #define MD_APG      0x000001e0  /* Access protection group (0) */
0284 #define MD_GUARDED  0x00000010  /* Guarded storage */
0285 #define MD_PSMASK   0x0000000c  /* Mask of page size bits */
0286 #define MD_PS8MEG   0x0000000c  /* 8M page size */
0287 #define MD_PS512K   0x00000004  /* 512K page size */
0288 #define MD_PS4K_16K 0x00000000  /* 4K or 16K page size */
0289 #define MD_WT       0x00000002  /* Use writethrough page attribute */
0290 #define MD_SVALID   0x00000001  /* Segment entry is valid */
0291                     /* Reset value is undefined */
0292
0293
0294 /* Real page number.  Defined by the pte.  Writing this register
0295  * causes a TLB entry to be created for the data TLB, using
0296  * additional information from the MD_EPN, and MD_TWC registers.
0297  */
0298 #define MD_RPN      798
0299
0300 /* This is a temporary storage register that could be used to save
0301  * a processor working register during a tablewalk.
0302  */
0303 #define M_TW        799
0304 #endif /* _LIBCPU_MMU_H */