include/libcpu/irq.h

0001 /*
0002  * irq.h
0003  *
0004  *  This include file describe the data structure and the functions implemented
0005  *  by rtems to write interrupt handlers.
0006  *
0007  *
0008  *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
0009  *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
0010  *
0011  *  Derived from libbsp/powerpc/mbx8xx/irq/irq.h:
0012  *
0013  *  CopyRight (C) 1999 valette@crf.canon.fr
0014  *
0015  *  This code is heavilly inspired by the public specification of STREAM V2
0016  *  that can be found at :
0017  *
0018  *      <http://www.chorus.com/Documentation/index.html> by following
0019  *  the STREAM API Specification Document link.
0020  *
0021  *  The license and distribution terms for this file may be
0022  *  found in the file LICENSE in this distribution or at
0023  *  http://www.rtems.org/license/LICENSE.
0024  */
0025
0026 #ifndef _LIBCPU_IRQ_H
0027 #define _LIBCPU_IRQ_H
0028
0029 #include <rtems/irq.h>
0030
0031 #define CPU_ASM_IRQ_VECTOR_BASE 0x0
0032
0033 #ifndef ASM
0034
0035 extern volatile unsigned int ppc_cached_irq_mask;
0036
0037 /*
0038  * Symblolic IRQ names and related definitions.
0039  */
0040
0041   /*
0042    * Base vector for our USIU IRQ handlers.
0043    */
0044 #define CPU_USIU_VECTOR_BASE    (CPU_ASM_IRQ_VECTOR_BASE)
0045   /*
0046    * USIU IRQ handler related definitions
0047    */
0048 #define CPU_USIU_IRQ_COUNT      (16) /* 16 reserved but in the future... */
0049 #define CPU_USIU_IRQ_MIN_OFFSET (0)
0050 #define CPU_USIU_IRQ_MAX_OFFSET (CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1)
0051   /*
0052    * UIMB IRQ handlers related definitions
0053    */
0054 #define CPU_UIMB_IRQ_COUNT  (32 - 8) /* first 8 overlap USIU */
0055 #define CPU_UIMB_IRQ_MIN_OFFSET (CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE)
0056 #define CPU_UIMB_IRQ_MAX_OFFSET (CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1)
0057   /*
0058    * PowerPc exceptions handled as interrupt where a rtems managed interrupt
0059    * handler might be connected
0060    */
0061 #define CPU_PROC_IRQ_COUNT  (1)
0062 #define CPU_PROC_IRQ_MIN_OFFSET (CPU_UIMB_IRQ_MAX_OFFSET + 1)
0063 #define CPU_PROC_IRQ_MAX_OFFSET (CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1)
0064   /*
0065    * Summary
0066    */
0067 #define CPU_IRQ_COUNT       (CPU_PROC_IRQ_MAX_OFFSET + 1)
0068 #define CPU_MIN_OFFSET      (CPU_USIU_IRQ_MIN_OFFSET)
0069 #define CPU_MAX_OFFSET      (CPU_PROC_IRQ_MAX_OFFSET)
0070   /*
0071    * USIU IRQ symbolic name definitions.
0072    */
0073 #define CPU_USIU_EXT_IRQ_0      (CPU_USIU_IRQ_MIN_OFFSET + 0)
0074 #define CPU_USIU_INT_IRQ_0      (CPU_USIU_IRQ_MIN_OFFSET + 1)
0075
0076 #define CPU_USIU_EXT_IRQ_1      (CPU_USIU_IRQ_MIN_OFFSET + 2)
0077 #define CPU_USIU_INT_IRQ_1      (CPU_USIU_IRQ_MIN_OFFSET + 3)
0078
0079 #define CPU_USIU_EXT_IRQ_2      (CPU_USIU_IRQ_MIN_OFFSET + 4)
0080 #define CPU_USIU_INT_IRQ_2      (CPU_USIU_IRQ_MIN_OFFSET + 5)
0081
0082 #define CPU_USIU_EXT_IRQ_3      (CPU_USIU_IRQ_MIN_OFFSET + 6)
0083 #define CPU_USIU_INT_IRQ_3      (CPU_USIU_IRQ_MIN_OFFSET + 7)
0084
0085 #define CPU_USIU_EXT_IRQ_4      (CPU_USIU_IRQ_MIN_OFFSET + 8)
0086 #define CPU_USIU_INT_IRQ_4      (CPU_USIU_IRQ_MIN_OFFSET + 9)
0087
0088 #define CPU_USIU_EXT_IRQ_5      (CPU_USIU_IRQ_MIN_OFFSET + 10)
0089 #define CPU_USIU_INT_IRQ_5      (CPU_USIU_IRQ_MIN_OFFSET + 11)
0090
0091 #define CPU_USIU_EXT_IRQ_6      (CPU_USIU_IRQ_MIN_OFFSET + 12)
0092 #define CPU_USIU_INT_IRQ_6      (CPU_USIU_IRQ_MIN_OFFSET + 13)
0093
0094 #define CPU_USIU_EXT_IRQ_7      (CPU_USIU_IRQ_MIN_OFFSET + 14)
0095 #define CPU_USIU_INT_IRQ_7      (CPU_USIU_IRQ_MIN_OFFSET + 15)
0096
0097   /*
0098    * Symbolic names for UISU interrupt sources.
0099    */
0100 #define CPU_PERIODIC_TIMER  (CPU_USIU_INT_IRQ_6)
0101 #define CPU_UIMB_INTERRUPT  (CPU_USIU_INT_IRQ_7)
0102
0103   /*
0104    * UIMB IRQ symbolic name definitions.  The first 8 sources are aliases to
0105    * the USIU interrupts of the same number, because they are detected in
0106    * the USIU pending register rather than the UIMB pending register.
0107    */
0108 #define CPU_UIMB_IRQ_0      (CPU_USIU_INT_IRQ_0)
0109 #define CPU_UIMB_IRQ_1      (CPU_USIU_INT_IRQ_1)
0110 #define CPU_UIMB_IRQ_2      (CPU_USIU_INT_IRQ_2)
0111 #define CPU_UIMB_IRQ_3      (CPU_USIU_INT_IRQ_3)
0112 #define CPU_UIMB_IRQ_4      (CPU_USIU_INT_IRQ_4)
0113 #define CPU_UIMB_IRQ_5      (CPU_USIU_INT_IRQ_5)
0114 #define CPU_UIMB_IRQ_6      (CPU_USIU_INT_IRQ_6)
0115 #define CPU_UIMB_IRQ_7      (CPU_USIU_INT_IRQ_7)
0116
0117 #define CPU_UIMB_IRQ_8          (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
0118 #define CPU_UIMB_IRQ_9          (CPU_UIMB_IRQ_MIN_OFFSET+ 1)
0119 #define CPU_UIMB_IRQ_10         (CPU_UIMB_IRQ_MIN_OFFSET+ 2)
0120 #define CPU_UIMB_IRQ_11         (CPU_UIMB_IRQ_MIN_OFFSET+ 3)
0121 #define CPU_UIMB_IRQ_12         (CPU_UIMB_IRQ_MIN_OFFSET+ 4)
0122 #define CPU_UIMB_IRQ_13         (CPU_UIMB_IRQ_MIN_OFFSET+ 5)
0123 #define CPU_UIMB_IRQ_14         (CPU_UIMB_IRQ_MIN_OFFSET+ 6)
0124 #define CPU_UIMB_IRQ_15         (CPU_UIMB_IRQ_MIN_OFFSET+ 7)
0125 #define CPU_UIMB_IRQ_16         (CPU_UIMB_IRQ_MIN_OFFSET+ 8)
0126 #define CPU_UIMB_IRQ_17         (CPU_UIMB_IRQ_MIN_OFFSET+ 9)
0127 #define CPU_UIMB_IRQ_18         (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
0128 #define CPU_UIMB_IRQ_19         (CPU_UIMB_IRQ_MIN_OFFSET+11)
0129 #define CPU_UIMB_IRQ_20         (CPU_UIMB_IRQ_MIN_OFFSET+12)
0130 #define CPU_UIMB_IRQ_21         (CPU_UIMB_IRQ_MIN_OFFSET+13)
0131 #define CPU_UIMB_IRQ_22         (CPU_UIMB_IRQ_MIN_OFFSET+14)
0132 #define CPU_UIMB_IRQ_23         (CPU_UIMB_IRQ_MIN_OFFSET+15)
0133 #define CPU_UIMB_IRQ_24         (CPU_UIMB_IRQ_MIN_OFFSET+16)
0134 #define CPU_UIMB_IRQ_25         (CPU_UIMB_IRQ_MIN_OFFSET+17)
0135 #define CPU_UIMB_IRQ_26         (CPU_UIMB_IRQ_MIN_OFFSET+18)
0136 #define CPU_UIMB_IRQ_27         (CPU_UIMB_IRQ_MIN_OFFSET+19)
0137 #define CPU_UIMB_IRQ_28         (CPU_UIMB_IRQ_MIN_OFFSET+20)
0138 #define CPU_UIMB_IRQ_29         (CPU_UIMB_IRQ_MIN_OFFSET+21)
0139 #define CPU_UIMB_IRQ_30         (CPU_UIMB_IRQ_MIN_OFFSET+22)
0140 #define CPU_UIMB_IRQ_31         (CPU_UIMB_IRQ_MIN_OFFSET+23)
0141
0142   /*
0143    * Symbolic names for UIMB interrupt sources.
0144    */
0145 #define CPU_IRQ_SCI     (CPU_UIMB_IRQ_5)
0146
0147   /*
0148    * Processor exceptions handled as rtems IRQ symbolic name definitions.
0149    */
0150 #define CPU_DECREMENTER     (CPU_PROC_IRQ_MIN_OFFSET)
0151
0152 /*
0153  * Convert an rtems_irq_number constant to an interrupt level
0154  * suitable for programming into an I/O device's interrupt level field.
0155  */
0156 int CPU_irq_level_from_symbolic_name(const rtems_irq_number name);
0157
0158 /*-------------------------------------------------------------------------+
0159 | Function Prototypes.
0160 +--------------------------------------------------------------------------*/
0161
0162 extern void CPU_rtems_irq_mng_init(unsigned cpuId);
0163
0164 typedef struct MPC5XX_Interrupt_frame {
0165     uint32_t   stacklink;   /* Ensure this is a real frame (also reg1 save) */
0166     uint32_t   calleeLr;    /* link register used by callees: SVR4/EABI */
0167
0168     /* This is what is left out of the primary contexts */
0169     uint32_t   gpr0;
0170     uint32_t   gpr2;        /* play safe */
0171     uint32_t   gpr3;
0172     uint32_t   gpr4;
0173     uint32_t   gpr5;
0174     uint32_t   gpr6;
0175     uint32_t   gpr7;
0176     uint32_t   gpr8;
0177     uint32_t   gpr9;
0178     uint32_t   gpr10;
0179     uint32_t   gpr11;
0180     uint32_t   gpr12;
0181     uint32_t   gpr13;   /* Play safe */
0182     uint32_t   gpr28;   /* For internal use by the IRQ handler */
0183     uint32_t   gpr29;   /* For internal use by the IRQ handler */
0184     uint32_t   gpr30;   /* For internal use by the IRQ handler */
0185     uint32_t   gpr31;   /* For internal use by the IRQ handler */
0186     uint32_t   cr;  /* Bits of this are volatile, so no-one may save */
0187     uint32_t   ctr;
0188     uint32_t   xer;
0189     uint32_t   lr;
0190     uint32_t   pc;
0191     uint32_t   msr;
0192     uint32_t   pad[3];
0193 } MPC5XX_Interrupt_frame;
0194
0195 void C_dispatch_irq_handler(MPC5XX_Interrupt_frame *frame, unsigned int excNum);
0196
0197 #endif
0198
0199 #endif