include/libcpu/bat.h

0001 /*
0002  * bat.h
0003  *
0004  *      This file contains declaration of C function to
0005  *          Instantiate 60x/7xx ppc Block Address Translation (BAT) registers.
0006  *      More detailed information can be found on motorola
0007  *      site and more precisely in the following book :
0008  *
0009  *      MPC750
0010  *      Risc Microporcessor User's Manual
0011  *      Motorola REF : MPC750UM/AD 8/97
0012  *
0013  * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
0014  *                     Canon Centre Recherche France.
0015  *
0016  *  The license and distribution terms for this file may be
0017  *  found in the file LICENSE in this distribution or at
0018  *  http://www.rtems.org/license/LICENSE.
0019  */
0020
0021 #ifndef _LIBCPU_BAT_H
0022 #define _LIBCPU_BAT_H
0023
0024 #include <libcpu/mmu.h>
0025 #include <libcpu/pgtable.h>
0026
0027 #define IO_PAGE (_PAGE_NO_CACHE | _PAGE_GUARDED | _PAGE_RW)
0028
0029 #ifndef ASM
0030 /* Take no risks -- the essential parts of this routine run with
0031  * interrupts disabled!
0032  *
0033  * The routine does basic parameter checks:
0034  *   - Index must be 0..3 (0..7 on 7455, 7457).
0035  *     If an index > 3 is requested the 745x is
0036  *     programmed to enable the higher BATs.
0037  *   - Size must be a power of two and <= 1<<28
0038  *     (<=1<<31 on 7455, 7457. Also, on these processors
0039  *     the special value 0xffffffff is allowed which stands
0040  *     for 1<<32).
0041  *     If a size > 1<<28 is requested, the 745x is
0042  *     programmed to enable the larger block sizes.
0043  *   - Bat ranges must not overlap.
0044  *   - Physical & virtual addresses must be aligned
0045  *     to the size.
0046  *
0047  * RETURNS: zero on success, nonzero on failure.
0048  */
0049 extern int setdbat(int bat_index, unsigned long virt, unsigned long phys,
0050             unsigned int size, int flags);
0051
0052 /* Same as setdbat but sets IBAT */
0053 extern int setibat(int bat_index, unsigned long virt, unsigned long phys,
0054             unsigned int size, int flags);
0055
0056 /* read DBAT # 'idx' into *pu / *pl. NULL pointers may be passed.
0057  * If pu and pl are NULL, the bat contents are dumped to the console (printk).
0058  *
0059  * RETURNS: upper BAT contents or (-1) if index is invalid
0060  */
0061 extern int getdbat(int bat_index, unsigned long *pu, unsigned long *pl);
0062
0063 /* Same as getdbat but reads IBAT */
0064 extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl);
0065
0066 /* Do not use the asm-routines; they are obsolete; use setdbat() instead */
0067 extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart);
0068 extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart);
0069 extern void asm_setdbat2(unsigned int uperPart, unsigned int lowerPart);
0070 extern void asm_setdbat3(unsigned int uperPart, unsigned int lowerPart);
0071 #else
0072
0073 /* Initialize all bats (upper and lower) to zero. This routine should *only*
0074  * be called during early BSP initialization when no C-ABI is available
0075  * yet.
0076  * This routine clobbers r3 and r4.
0077  * NOTE: on 7450 CPUs all 8 dbat/ibat units are cleared. On 601 CPUs only
0078  *       4 ibats.
0079  */
0080     .globl CPU_clear_bats_early
0081     .type  CPU_clear_bats_early,@function
0082
0083 #endif
0084
0085 #endif /* _LIBCPU_BAT_H */