include/bsp/uart.h

0001
0002 /*
0003  * This software is Copyright (C) 1998 by T.sqware - all rights limited
0004  * It is provided in to the public domain "as is", can be freely modified
0005  * as far as this copyight notice is kept unchanged, but does not imply
0006  * an endorsement by T.sqware of the product in which it is included.
0007  */
0008
0009 #ifndef _BSPUART_H
0010 #define _BSPUART_H
0011
0012 #include <bsp/irq.h>
0013
0014 #include <sys/ioctl.h>
0015 #include <rtems/libio.h>
0016
0017 void     BSP_uart_init(int uart, int baud, int hwFlow);
0018 void     BSP_uart_set_baud(int uart, int baud);
0019 void     BSP_uart_intr_ctrl(int uart, int cmd);
0020 void     BSP_uart_throttle(int uart);
0021 void     BSP_uart_unthrottle(int uart);
0022 int      BSP_uart_polled_status(int uart);
0023 void     BSP_uart_polled_write(int uart, int val);
0024 int      BSP_uart_polled_read(int uart);
0025 void     BSP_uart_termios_set(int uart, void *ttyp);
0026 ssize_t  BSP_uart_termios_write_com(int minor, const char *buf, size_t len);
0027 int      BSP_uart_termios_read_com (int minor);
0028 void     BSP_uart_termios_isr_com1(void *unused);
0029 void     BSP_uart_termios_isr_com2(void *unused);
0030 void     BSP_uart_dbgisr_com1(void);
0031 void     BSP_uart_dbgisr_com2(void);
0032 int      BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
0033 int      BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
0034 ssize_t BSP_uart_termios_write_polled(int minor, const char *buf, size_t len);
0035 int      BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
0036 int      BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
0037
0038 extern unsigned BSP_poll_char_via_serial(void);
0039 extern void BSP_output_char_via_serial(const char val);
0040 extern int BSPConsolePort;
0041 extern int BSPBaseBaud;
0042
0043 /* Special IOCTLS to install a lowlevel 'BREAK' handler */
0044
0045 /* pass a BSP_UartBreakCb pointer to ioctl when retrieving
0046  * or installing break callback
0047  */
0048 typedef void (*BSP_UartBreakCbProc)(
0049   int uartMinor,
0050   unsigned uartRBRLSRStatus,
0051   void  *termiosPrivatePtr,
0052   void  *private
0053 );
0054
0055 typedef struct BSP_UartBreakCbRec_ {
0056   BSP_UartBreakCbProc  handler; /* NOTE: handler runs in INTERRUPT CONTEXT */
0057   void     *private; /* closure pointer which is passed to the callback  */
0058 } BSP_UartBreakCbRec, *BSP_UartBreakCb;
0059
0060 #define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec))
0061 #define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec))
0062
0063 /*
0064  * Command values for BSP_uart_intr_ctrl(),
0065  * values are strange in order to catch errors
0066  * with assert
0067  */
0068 #define BSP_UART_INTR_CTRL_DISABLE  (0)
0069 #define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
0070 #define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
0071 #define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
0072
0073 /* Return values for uart_polled_status() */
0074 #define BSP_UART_STATUS_ERROR    (-1) /* No character */
0075 #define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
0076 #define BSP_UART_STATUS_CHAR     (1)  /* Character present */
0077 #define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
0078
0079 /* PC UART definitions */
0080 #define BSP_UART_COM1            (0)
0081 #define BSP_UART_COM2            (1)
0082
0083 /*
0084  * Offsets from base
0085  */
0086
0087 /* DLAB 0 */
0088 #define RBR  (0)    /* Rx Buffer Register (read) */
0089 #define THR  (0)    /* Tx Buffer Register (write) */
0090 #define IER  (1)    /* Interrupt Enable Register */
0091
0092 /* DLAB X */
0093 #define IIR  (2)    /* Interrupt Ident Register (read) */
0094 #define FCR  (2)    /* FIFO Control Register (write) */
0095 #define LCR  (3)    /* Line Control Register */
0096 #define MCR  (4)    /* Modem Control Register */
0097 #define LSR  (5)    /* Line Status Register */
0098 #define MSR  (6)    /* Modem Status  Register */
0099 #define SCR  (7)    /* Scratch register */
0100
0101 /* DLAB 1 */
0102 #define DLL  (0)    /* Divisor Latch, LSB */
0103 #define DLM  (1)    /* Divisor Latch, MSB */
0104 #define AFR  (2)    /* Alternate Function register */
0105
0106 /*
0107  * Interrupt source definition via IIR
0108  */
0109 #define MODEM_STATUS                       0
0110 #define NO_MORE_INTR                       1
0111 #define TRANSMITTER_HODING_REGISTER_EMPTY  2
0112 #define RECEIVER_DATA_AVAIL                4
0113 #define RECEIVER_ERROR                     6
0114 #define CHARACTER_TIMEOUT_INDICATION      12
0115
0116 /*
0117  * Bits definition of IER
0118  */
0119 #define RECEIVE_ENABLE          0x1
0120 #define TRANSMIT_ENABLE         0x2
0121 #define RECEIVER_LINE_ST_ENABLE 0x4
0122 #define MODEM_ENABLE            0x8
0123 #define INTERRUPT_DISABLE       0x0
0124
0125 /*
0126  * Bits definition of the Line Status Register (LSR)
0127  */
0128 #define DR     0x01 /* Data Ready */
0129 #define OE     0x02 /* Overrun Error */
0130 #define PE     0x04 /* Parity Error */
0131 #define FE     0x08 /* Framing Error */
0132 #define BI     0x10 /* Break Interrupt */
0133 #define THRE   0x20 /* Transmitter Holding Register Empty */
0134 #define TEMT   0x40 /* Transmitter Empty */
0135 #define ERFIFO 0x80 /* Error receive Fifo */
0136
0137 /*
0138  * Bits definition of the MODEM Control Register (MCR)
0139  */
0140 #define DTR   0x01 /* Data Terminal Ready */
0141 #define RTS   0x02 /* Request To Send */
0142 #define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */
0143 #define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */
0144 #define LB    0x10 /* Enable Internal Loop Back */
0145
0146 /*
0147  * Bits definition of the Line Control Register (LCR)
0148  */
0149 #define CHR_5_BITS 0
0150 #define CHR_6_BITS 1
0151 #define CHR_7_BITS 2
0152 #define CHR_8_BITS 3
0153
0154 #define WL   0x03 /* Word length mask */
0155 #define STB  0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
0156 #define PEN  0x08 /* Parity Enabled */
0157 #define EPS  0x10 /* Even Parity Select, otherwise Odd */
0158 #define SP   0x20 /* Stick Parity */
0159 #define BCB  0x40 /* Break Control Bit */
0160 #define DLAB 0x80 /* Enable Divisor Latch Access */
0161
0162 /*
0163  * Bits definition of the MODEM Status Register (MSR)
0164  */
0165 #define DCTS 0x01 /* Delta Clear To Send */
0166 #define DDSR 0x02 /* Delta Data Set Ready */
0167 #define TERI 0x04 /* Trailing Edge Ring Indicator */
0168 #define DDCD 0x08 /* Delta Carrier Detect Indicator */
0169 #define CTS  0x10 /* Clear To Send (when loop back is active) */
0170 #define DSR  0x20 /* Data Set Ready (when loop back is active) */
0171 #define RI   0x40 /* Ring Indicator (when loop back is active) */
0172 #define DCD  0x80 /* Data Carrier Detect (when loop back is active) */
0173
0174 /*
0175  * Bits definition of the FIFO Control Register : WD16C552 or NS16550
0176  */
0177
0178 #define FIFO_CTRL  0x01 /* Set to 1 permit access to other bits */
0179 #define FIFO_EN    0x01 /* Enable the FIFO */
0180 #define XMIT_RESET 0x02 /* Transmit FIFO Reset */
0181 #define RCV_RESET  0x04 /* Receive FIFO Reset */
0182 #define FCR3       0x08 /* do not understand manual! */
0183
0184 #define RECEIVE_FIFO_TRIGGER1  0x00 /* trigger RX interrupt after 1 byte  */
0185 #define RECEIVE_FIFO_TRIGGER4  0x40 /* trigger RX interrupt after 4 bytes  */
0186 #define RECEIVE_FIFO_TRIGGER8  0x80 /* trigger RX interrupt after 8 bytes  */
0187 #define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */
0188 #define TRIG_LEVEL             0xc0 /* Mask for the trigger level   */
0189
0190 #endif /* _BSPUART_H */