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File indexing completed on 2025-05-11 08:23:53
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /* 0004 * RTEMS support for MPC83xx 0005 * 0006 * This file declares the MPC83xx TSEC networking driver. 0007 */ 0008 0009 /* 0010 * Copyright (c) 2007 embedded brains GmbH & Co. KG 0011 * 0012 * Redistribution and use in source and binary forms, with or without 0013 * modification, are permitted provided that the following conditions 0014 * are met: 0015 * 1. Redistributions of source code must retain the above copyright 0016 * notice, this list of conditions and the following disclaimer. 0017 * 2. Redistributions in binary form must reproduce the above copyright 0018 * notice, this list of conditions and the following disclaimer in the 0019 * documentation and/or other materials provided with the distribution. 0020 * 0021 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 0022 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 0023 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 0024 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 0025 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 0026 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 0027 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0028 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0029 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 0030 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 0031 * POSSIBILITY OF SUCH DAMAGE. 0032 */ 0033 0034 #ifndef LIBCPU_POWERPC_TSEC_H 0035 #define LIBCPU_POWERPC_TSEC_H 0036 0037 #include <stdint.h> 0038 0039 #include <bsp/irq.h> 0040 #include <bsp/tsec-config.h> 0041 0042 #ifdef __cplusplus 0043 extern "C" { 0044 #endif /* __cplusplus */ 0045 0046 /* 0047 * this enumeration defines the index 0048 * of a given rmon mib counter 0049 * in the tsec_rmon_mib array 0050 */ 0051 typedef enum { 0052 /* TSEC1 Transmit and Receive Counters */ 0053 TSEC_RMON_TR64, /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */ 0054 TSEC_RMON_TR127, /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */ 0055 TSEC_RMON_TR255, /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */ 0056 TSEC_RMON_TR511, /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */ 0057 TSEC_RMON_TR1K, /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */ 0058 TSEC_RMON_TRMAX, /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */ 0059 TSEC_RMON_TRMGV, /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */ 0060 /* TSEC1 Receive Counters */ 0061 TSEC_RMON_RBYT, /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */ 0062 TSEC_RMON_RPKT, /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */ 0063 TSEC_RMON_RFCS, /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */ 0064 TSEC_RMON_RMCA, /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */ 0065 TSEC_RMON_RBCA, /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */ 0066 TSEC_RMON_RXCF, /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */ 0067 TSEC_RMON_RXPF, /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */ 0068 TSEC_RMON_RXUO, /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */ 0069 TSEC_RMON_RALN, /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */ 0070 TSEC_RMON_RFLR, /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */ 0071 TSEC_RMON_RCDE, /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */ 0072 TSEC_RMON_RCSE, /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */ 0073 TSEC_RMON_RUND, /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */ 0074 TSEC_RMON_ROVR, /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */ 0075 TSEC_RMON_RFRG, /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */ 0076 TSEC_RMON_RJBR, /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */ 0077 TSEC_RMON_RDRP, /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */ 0078 /* TSEC1 Transmit Counters */ 0079 TSEC_RMON_TBYT, /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */ 0080 TSEC_RMON_TPKT, /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */ 0081 TSEC_RMON_TMCA, /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */ 0082 TSEC_RMON_TBCA, /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */ 0083 TSEC_RMON_TXPF, /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */ 0084 TSEC_RMON_TDFR, /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */ 0085 TSEC_RMON_TEDF, /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */ 0086 TSEC_RMON_TSCL, /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */ 0087 TSEC_RMON_TMCL, /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */ 0088 TSEC_RMON_TLCL, /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */ 0089 TSEC_RMON_TXCL, /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */ 0090 TSEC_RMON_TNCL, /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */ 0091 TSEC_RESERVED1, /* 0x2_4710 Reserved, should be cleared R 0x0000_0000 */ 0092 TSEC_RMON_TDRP, /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */ 0093 TSEC_RMON_TJBR, /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */ 0094 TSEC_RMON_TFCS, /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */ 0095 TSEC_RMON_TXCF, /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */ 0096 TSEC_RMON_TOVR, /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */ 0097 TSEC_RMON_TUND, /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */ 0098 TSEC_RMON_TFRG, /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */ 0099 TSEC_RMON_CNT 0100 } tsec_rmon_idx; 0101 0102 /* TSEC1/2 General Control and Status Registers */ 0103 typedef struct { 0104 uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */ 0105 uint32_t ievent; /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */ 0106 uint32_t imask; /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */ 0107 uint32_t edis; /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */ 0108 uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */ 0109 uint32_t ecntrl; /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */ 0110 uint32_t minflr; /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */ 0111 uint32_t ptv; /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */ 0112 uint32_t dmactrl; /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */ 0113 uint32_t tbipa; /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */ 0114 uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */ 0115 /* TSEC1 FIFO Control and Status Registers */ 0116 uint32_t fifo_tx_thr; /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */ 0117 uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */ 0118 uint32_t fifo_tx_sp; /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */ 0119 uint32_t fifo_tx_starve; /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */ 0120 uint32_t fifo_tx_starve_shutoff; /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */ 0121 uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */ 0122 /* TSEC1 Transmit Control and Status Registers */ 0123 uint32_t tctrl; /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */ 0124 uint32_t tstat; /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */ 0125 uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */ 0126 uint32_t txic; /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */ 0127 uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */ 0128 uint32_t ctbptr; /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */ 0129 uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */ 0130 uint32_t tbptr; /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */ 0131 uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */ 0132 uint32_t tbase; /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */ 0133 uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */ 0134 uint32_t ostbd; /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */ 0135 uint32_t ostbdp; /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */ 0136 uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */ 0137 /* TSEC1 Receive Control and Status Registers */ 0138 uint32_t rctrl; /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */ 0139 uint32_t rstat; /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */ 0140 uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000 */ 0141 uint32_t rbdlen; /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */ 0142 uint32_t rxic; /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */ 0143 uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */ 0144 uint32_t crbptr; /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */ 0145 uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */ 0146 uint32_t mrblr; /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */ 0147 uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */ 0148 uint32_t rbptr; /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */ 0149 uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */ 0150 uint32_t rbase; /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */ 0151 uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */ 0152 /* TSEC1 MAC Registers */ 0153 uint32_t maccfg1; /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */ 0154 uint32_t maccfg2; /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */ 0155 uint32_t ipgifg; /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */ 0156 uint32_t hafdup; /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */ 0157 uint32_t maxfrm; /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */ 0158 uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */ 0159 uint32_t miimcfg; /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */ 0160 uint32_t miimcom; /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */ 0161 uint32_t miimadd; /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */ 0162 uint32_t miimcon; /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */ 0163 uint32_t miimstat; /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */ 0164 uint32_t miimind; /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */ 0165 uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared $ $ */ 0166 uint32_t ifstat; /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */ 0167 uint32_t macstnaddr[2]; /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */ 0168 uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */ 0169 0170 /* TSEC1 RMON MIB Registers */ 0171 uint32_t rmon_mib[TSEC_RMON_CNT]; 0172 0173 /* TSEC1 General Registers */ 0174 uint32_t car[2]; /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */ 0175 uint32_t cam[2]; /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */ 0176 uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */ 0177 0178 /* TSEC1 Hash Function Registers */ 0179 uint32_t iaddr[8]; /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */ 0180 uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */ 0181 uint32_t gaddr[8]; /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */ 0182 uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */ 0183 0184 /* TSEC1 Attribute Registers */ 0185 uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */ 0186 uint32_t attr; /* 0x2_4BF8 Attribute register R 0x0000_0000 */ 0187 uint32_t attreli; /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */ 0188 uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */ 0189 } tsec_registers; 0190 0191 /* 0192 * TSEC IEVENT/IMASK bit definitions 0193 */ 0194 #define TSEC_IEVENT_BABR (1<<(31- 0)) 0195 #define TSEC_IEVENT_RXC (1<<(31- 1)) 0196 #define TSEC_IEVENT_BSY (1<<(31- 2)) 0197 #define TSEC_IEVENT_EBERR (1<<(31- 3)) 0198 #define TSEC_IEVENT_MSRO (1<<(31- 5)) 0199 #define TSEC_IEVENT_GTSC (1<<(31- 6)) 0200 #define TSEC_IEVENT_BABT (1<<(31- 7)) 0201 #define TSEC_IEVENT_TXC (1<<(31- 8)) 0202 #define TSEC_IEVENT_TXE (1<<(31- 9)) 0203 #define TSEC_IEVENT_TXB (1<<(31-10)) 0204 #define TSEC_IEVENT_TXF (1<<(31-11)) 0205 #define TSEC_IEVENT_LC (1<<(31-13)) 0206 #define TSEC_IEVENT_CRL_XDA (1<<(31-14)) 0207 #define TSEC_IEVENT_XFUN (1<<(31-15)) 0208 #define TSEC_IEVENT_RXB (1<<(31-16)) 0209 #define TSEC_IEVENT_MMRD (1<<(31-21)) 0210 #define TSEC_IEVENT_MMWR (1<<(31-22)) 0211 #define TSEC_IEVENT_GRSC (1<<(31-23)) 0212 #define TSEC_IEVENT_RXF (1<<(31-24)) 0213 0214 /* 0215 * TSEC DMACTRL bit definitions 0216 */ 0217 #define TSEC_DMACTL_TDSEN (1<<(31-24)) 0218 #define TSEC_DMACTL_TBDSEN (1<<(31-25)) 0219 #define TSEC_DMACTL_GRS (1<<(31-27)) 0220 #define TSEC_DMACTL_GTS (1<<(31-28)) 0221 #define TSEC_DMACTL_WWR (1<<(31-30)) 0222 #define TSEC_DMACTL_WOP (1<<(31-31)) 0223 0224 /* 0225 * TSEC TSTAT bit definitions 0226 */ 0227 #define TSEC_TSTAT_THLT (1<<(31-0)) 0228 0229 /* 0230 * TSEC RSTAT bit definitions 0231 */ 0232 #define TSEC_RSTAT_QHLT (1<<(31-8)) 0233 /* 0234 * TSEC ECNTRL bit positions 0235 */ 0236 #define TSEC_ECNTRL_CLRCNT (1 << (31-17)) /* Clear stat counters */ 0237 #define TSEC_ECNTRL_AUTOZ (1 << (31-18)) /* auto-zero read counters */ 0238 #define TSEC_ECNTRL_STEN (1 << (31-19)) /* enable statistics */ 0239 #define TSEC_ECNTRL_TBIM (1 << (31-26)) /* ten-bit-interface */ 0240 #define TSEC_ECNTRL_RPM (1 << (31-27)) /* reduced signal mode */ 0241 #define TSEC_ECNTRL_R100M (1 << (31-28)) /* RGMII100 mode */ 0242 /* 0243 * TSEC EDIS bit positions 0244 */ 0245 #define TSEC_EDIS_BSYDIS (1 << (31- 2)) /* Busy disable */ 0246 #define TSEC_EDIS_EBERRDIS (1 << (31- 3)) /* bus error disable */ 0247 #define TSEC_EDIS_TXEDIS (1 << (31- 9)) /* Tx error disable */ 0248 #define TSEC_EDIS_LCDIS (1 << (31-13)) /* Late collision disable */ 0249 #define TSEC_EDIS_CRLXDADIS (1 << (31-14)) /* Collision Retry disable */ 0250 #define TSEC_EDIS_FUNDIS (1 << (31-15)) /* Tx FIFO underrun disable*/ 0251 0252 /* 0253 * TSEC RCTRL bit positions 0254 */ 0255 #define TSEC_RCTRL_BC_REJ (1 << (31-27)) /* Broadcast Reject */ 0256 #define TSEC_RCTRL_PROM (1 << (31-28)) /* Promiscuous */ 0257 #define TSEC_RCTRL_RSF (1 << (31-29)) /* Receive short frames */ 0258 0259 /* 0260 * TSEC TXIC bit positions 0261 */ 0262 #define TSEC_TXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ 0263 #define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ 0264 #define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ 0265 0266 /* 0267 * TSEC RXIC bit positions 0268 */ 0269 #define TSEC_RXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ 0270 #define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ 0271 #define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ 0272 0273 /* 0274 * TSEC MACCFG1 bit positions 0275 */ 0276 #define TSEC_MACCFG1_SOFTRST (1 << (31- 0)) /* Soft Reset */ 0277 #define TSEC_MACCFG1_RES_RXMC (1 << (31-12)) /* Reset Rx MAC block */ 0278 #define TSEC_MACCFG1_RES_TXMC (1 << (31-13)) /* Reset Tx MAC block */ 0279 #define TSEC_MACCFG1_RES_RXFUN (1 << (31-14)) /* Reset Rx function blk*/ 0280 #define TSEC_MACCFG1_RES_TXFUN (1 << (31-15)) /* Reset Tx function blk*/ 0281 #define TSEC_MACCFG1_LOOPBACK (1 << (31-23)) /* Loopback mode */ 0282 #define TSEC_MACCFG1_RX_FLOW (1 << (31-26)) /* Receive Flow Ctrl */ 0283 #define TSEC_MACCFG1_TX_FLOW (1 << (31-27)) /* Transmit Flow Ctrl */ 0284 #define TSEC_MACCFG1_SYNVRXEN (1 << (31-28)) /* Sync Receive Enable */ 0285 #define TSEC_MACCFG1_RXEN (1 << (31-29)) /* Receive Enable */ 0286 #define TSEC_MACCFG1_SYNVTXEN (1 << (31-30)) /* Sync Transmit Enable */ 0287 #define TSEC_MACCFG1_TXEN (1 << (31-31)) /* Transmit Enable */ 0288 0289 /* 0290 * TSEC MACCFG2 bit positions 0291 */ 0292 #define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19)) /* Preamble len*/ 0293 0294 #define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask */ 0295 #define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode */ 0296 #define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode */ 0297 0298 #define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame */ 0299 #define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check */ 0300 #define TSEC_MACCFG2_PAD_CRC (1 << (31-29)) /* MAC adds PAD/CRC */ 0301 #define TSEC_MACCFG2_CRC_EN (1 << (31-30)) /* CRC enable */ 0302 #define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode */ 0303 0304 /* 0305 * TSEC MIIMADD bit positions 0306 */ 0307 #define TSEC_MIIMADD_PHY(n) (((n) & 0x3f)<<(31- 23)) /* PHY addr */ 0308 #define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31)) /* PHY addr */ 0309 0310 /* 0311 * TSEC MIIMCOM bit positions 0312 */ 0313 #define TSEC_MIIMCOM_SCAN (1 << (31-30)) /* Scan command */ 0314 #define TSEC_MIIMCOM_READ (1 << (31-31)) /* Read command */ 0315 0316 /* 0317 * TSEC MIIMIND bit positions 0318 */ 0319 #define TSEC_MIIMIND_NVAL (1 << (31-29)) /* not valid */ 0320 #define TSEC_MIIMIND_SCAN (1 << (31-30)) /* Scan in progress */ 0321 #define TSEC_MIIMIND_BUSY (1 << (31-31)) /* Acc. in progress */ 0322 0323 /* 0324 * TSEC ATTR bit positions 0325 */ 0326 #define TSEC_ATTR_RDSEN (1 << (31-24)) /* read data snoop */ 0327 #define TSEC_ATTR_RBDSEN (1 << (31-25)) /* read BD snoop */ 0328 0329 typedef struct { 0330 volatile uint16_t status; 0331 volatile uint16_t length; 0332 volatile void *buffer; 0333 } PQBufferDescriptor_t; 0334 0335 /* 0336 * Bits in receive buffer descriptor status word 0337 */ 0338 #define BD_EMPTY (1<<15) 0339 #define BD_RO1 (1<<14) 0340 #define BD_WRAP (1<<13) 0341 #define BD_INTERRUPT (1<<12) 0342 #define BD_LAST (1<<11) 0343 #define BD_CONTROL_CHAR (1<<11) 0344 #define BD_FIRST_IN_FRAME (1<<10) 0345 #define BD_MISS (1<<8) 0346 #define BD_BROADCAST (1<<7) 0347 #define BD_MULTICAST (1<<6) 0348 #define BD_LONG (1<<5) 0349 #define BD_NONALIGNED (1<<4) 0350 #define BD_SHORT (1<<3) 0351 #define BD_CRC_ERROR (1<<2) 0352 #define BD_OVERRUN (1<<1) 0353 #define BD_COLLISION (1<<0) 0354 0355 /* 0356 * Bits in transmit buffer descriptor status word 0357 * Many bits have the same meaning as those in receiver buffer descriptors. 0358 */ 0359 #define BD_READY (1<<15) 0360 #define BD_PAD_CRC (1<<14) 0361 /* WRAP/Interrupt as in Rx BDs */ 0362 #define BD_TX_CRC (1<<10) 0363 #define BD_DEFER (1<<9) 0364 #define BD_TO1 (1<<8) 0365 #define BD_HFE_ (1<<7) 0366 #define BD_LATE_COLLISION (1<<7) 0367 #define BD_RETRY_LIMIT (1<<6) 0368 #define BD_RETRY_COUNT(x) (((x)&0x3C)>>2) 0369 #define BD_UNDERRUN (1<<1) 0370 #define BD_TXTRUNC (1<<0) 0371 0372 struct rtems_bsdnet_ifconfig; 0373 0374 typedef struct { 0375 int unit_number; 0376 char *unit_name; 0377 volatile tsec_registers *reg_ptr; 0378 volatile tsec_registers *mdio_ptr; 0379 rtems_vector_number irq_num_tx; 0380 rtems_vector_number irq_num_rx; 0381 rtems_vector_number irq_num_err; 0382 int phy_default; 0383 } tsec_config; 0384 0385 int tsec_driver_attach_detach( 0386 struct rtems_bsdnet_ifconfig *config, 0387 int attaching 0388 ); 0389 0390 #ifdef __cplusplus 0391 } 0392 #endif /* __cplusplus */ 0393 0394 #endif /* LIBCPU_POWERPC_TSEC_H */
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