include/bsp/openpic.h

0001 /*
0002  *  openpic.h -- OpenPIC definitions
0003  *
0004  *  Copyright (C) 1997 Geert Uytterhoeven
0005  *
0006  *  This file is based on the following documentation:
0007  *
0008  *  The Open Programmable Interrupt Controller (PIC)
0009  *  Register Interface Specification Revision 1.2
0010  *
0011  *  Issue Date: October 1995
0012  *
0013  *  Issued jointly by Advanced Micro Devices and Cyrix Corporation
0014  *
0015  *  AMD is a registered trademark of Advanced Micro Devices, Inc.
0016  *  Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
0017  *  All Rights Reserved.
0018  *
0019  *  To receive a copy of this documentation, send an email to openpic@amd.com.
0020  *
0021  *  This file is subject to the terms and conditions of the GNU General Public
0022  *  License.  See the file COPYING in the main directory of this archive
0023  *  for more details.
0024  *
0025  *  Modified to compile in RTEMS development environment
0026  *  by Eric Valette
0027  *
0028  *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
0029  *
0030  *  The license and distribution terms for this file may be
0031  *  found in the file LICENSE in this distribution or at
0032  *  http://www.rtems.org/license/LICENSE.
0033  */
0034
0035 #ifndef _RTEMS_OPENPIC_H
0036 #define _RTEMS_OPENPIC_H
0037
0038     /*
0039      *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
0040      */
0041 #define OPENPIC_MAX_SOURCES 2048
0042 #define OPENPIC_MAX_PROCESSORS  32
0043
0044 #define OPENPIC_NUM_TIMERS  4
0045 #define OPENPIC_NUM_IPI     4
0046 #define OPENPIC_NUM_PRI     16
0047 #define OPENPIC_NUM_VECTORS 256
0048
0049     /*
0050      *  Vector numbers
0051      */
0052
0053 #define OPENPIC_VEC_SOURCE      0x10    /* and up */
0054 #define OPENPIC_VEC_TIMER       0x40    /* and up */
0055 #define OPENPIC_VEC_IPI         0x50    /* and up */
0056 #define OPENPIC_VEC_SPURIOUS    99
0057
0058     /*
0059      *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
0060      */
0061
0062 typedef struct _OpenPIC_Reg {
0063     unsigned int Reg;                   /* Little endian! */
0064     char Pad[0xc];
0065 } OpenPIC_Reg;
0066
0067     /*
0068      *  Per Processor Registers
0069      */
0070
0071 typedef struct _OpenPIC_Processor {
0072     /*
0073      *  Private Shadow Registers (for SLiC backwards compatibility)
0074      */
0075     unsigned int IPI0_Dispatch_Shadow;          /* Write Only */
0076     char Pad1[0x4];
0077     unsigned int IPI0_Vector_Priority_Shadow;       /* Read/Write */
0078     char Pad2[0x34];
0079     /*
0080      *  Interprocessor Interrupt Command Ports
0081      */
0082     OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
0083     /*
0084      *  Current Task Priority Register
0085      */
0086     OpenPIC_Reg _Current_Task_Priority;     /* Read/Write */
0087     char Pad3[0x10];
0088     /*
0089      *  Interrupt Acknowledge Register
0090      */
0091     OpenPIC_Reg _Interrupt_Acknowledge;     /* Read Only */
0092     /*
0093      *  End of Interrupt (EOI) Register
0094      */
0095     OpenPIC_Reg _EOI;               /* Read/Write */
0096     char Pad5[0xf40];
0097 } OpenPIC_Processor;
0098
0099     /*
0100      *  Timer Registers
0101      */
0102
0103 typedef struct _OpenPIC_Timer {
0104     OpenPIC_Reg _Current_Count;         /* Read Only */
0105     OpenPIC_Reg _Base_Count;            /* Read/Write */
0106     OpenPIC_Reg _Vector_Priority;       /* Read/Write */
0107     OpenPIC_Reg _Destination;           /* Read/Write */
0108 } OpenPIC_Timer;
0109
0110     /*
0111      *  Global Registers
0112      */
0113
0114 typedef struct _OpenPIC_Global {
0115     /*
0116      *  Feature Reporting Registers
0117      */
0118     OpenPIC_Reg _Feature_Reporting0;        /* Read Only */
0119     OpenPIC_Reg _Feature_Reporting1;        /* Future Expansion */
0120     /*
0121      *  Global Configuration Registers
0122      */
0123     OpenPIC_Reg _Global_Configuration0;     /* Read/Write */
0124     OpenPIC_Reg _Global_Configuration1;     /* Future Expansion */
0125     /*
0126      *  Vendor Specific Registers
0127      */
0128     OpenPIC_Reg _Vendor_Specific[4];
0129     /*
0130      *  Vendor Identification Register
0131      */
0132     OpenPIC_Reg _Vendor_Identification;     /* Read Only */
0133     /*
0134      *  Processor Initialization Register
0135      */
0136     OpenPIC_Reg _Processor_Initialization;  /* Read/Write */
0137     /*
0138      *  IPI Vector/Priority Registers
0139      */
0140     OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
0141     /*
0142      *  Spurious Vector Register
0143      */
0144     OpenPIC_Reg _Spurious_Vector;       /* Read/Write */
0145     /*
0146      *  Global Timer Registers
0147      */
0148     OpenPIC_Reg _Timer_Frequency;       /* Read/Write */
0149     OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
0150     char Pad1[0xee00];
0151 } OpenPIC_Global;
0152
0153     /*
0154      *  Interrupt Source Registers
0155      */
0156
0157 typedef struct _OpenPIC_Source {
0158     OpenPIC_Reg _Vector_Priority;       /* Read/Write */
0159     OpenPIC_Reg _Destination;           /* Read/Write */
0160 } OpenPIC_Source;
0161
0162     /*
0163      *  OpenPIC Register Map
0164      */
0165
0166 struct OpenPIC {
0167     char Pad1[0x1000];
0168     /*
0169      *  Global Registers
0170      */
0171     OpenPIC_Global Global;
0172     /*
0173      *  Interrupt Source Configuration Registers
0174      */
0175     OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
0176     /*
0177      *  Per Processor Registers
0178      */
0179     OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
0180 };
0181
0182 extern volatile struct OpenPIC *OpenPIC;
0183
0184     /*
0185      *  Current Task Priority Register
0186      */
0187
0188 #define OPENPIC_CURRENT_TASK_PRIORITY_MASK  0x0000000f
0189
0190     /*
0191      *  Who Am I Register
0192      */
0193
0194 #define OPENPIC_WHO_AM_I_ID_MASK        0x0000001f
0195
0196     /*
0197      *  Feature Reporting Register 0
0198      */
0199
0200 #define OPENPIC_FEATURE_LAST_SOURCE_MASK    0x07ff0000
0201 #define OPENPIC_FEATURE_LAST_SOURCE_SHIFT   16
0202 #define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00
0203 #define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
0204 #define OPENPIC_FEATURE_VERSION_MASK        0x000000ff
0205
0206     /*
0207      *  Global Configuration Register 0
0208      */
0209
0210 #define OPENPIC_CONFIG_RESET            0x80000000
0211 #define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
0212 #define OPENPIC_CONFIG_BASE_MASK        0x000fffff
0213
0214     /*
0215      *  Vendor Identification Register
0216      */
0217
0218 #define OPENPIC_VENDOR_ID_STEPPING_MASK     0x00ff0000
0219 #define OPENPIC_VENDOR_ID_STEPPING_SHIFT    16
0220 #define OPENPIC_VENDOR_ID_DEVICE_ID_MASK    0x0000ff00
0221 #define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT   8
0222 #define OPENPIC_VENDOR_ID_VENDOR_ID_MASK    0x000000ff
0223
0224     /*
0225      *  Vector/Priority Registers
0226      */
0227
0228 #define OPENPIC_MASK                0x80000000
0229 #define OPENPIC_ACTIVITY            0x40000000  /* Read Only */
0230 #define OPENPIC_PRIORITY_MASK           0x000f0000
0231 #define OPENPIC_PRIORITY_SHIFT          16
0232 #define OPENPIC_VECTOR_MASK         0x000000ff
0233
0234     /*
0235      *  Interrupt Source Registers
0236      */
0237
0238 #define OPENPIC_SENSE_POLARITY          0x00800000  /* Undoc'd */
0239 #define OPENPIC_SENSE_LEVEL         0x00400000
0240
0241     /*
0242      *  Timer Registers
0243      */
0244
0245 #define OPENPIC_COUNT_MASK          0x7fffffff
0246 #define OPENPIC_TIMER_TOGGLE            0x80000000
0247 #define OPENPIC_TIMER_COUNT_INHIBIT     0x80000000
0248
0249     /*
0250      *  Aliases to make life simpler
0251      */
0252
0253 /* Per Processor Registers */
0254 #define IPI_Dispatch(i)         _IPI_Dispatch[i].Reg
0255 #define Current_Task_Priority       _Current_Task_Priority.Reg
0256 #define Interrupt_Acknowledge       _Interrupt_Acknowledge.Reg
0257 #define EOI             _EOI.Reg
0258
0259 /* Global Registers */
0260 #define Feature_Reporting0      _Feature_Reporting0.Reg
0261 #define Feature_Reporting1      _Feature_Reporting1.Reg
0262 #define Global_Configuration0       _Global_Configuration0.Reg
0263 #define Global_Configuration1       _Global_Configuration1.Reg
0264 #define Vendor_Specific(i)      _Vendor_Specific[i].Reg
0265 #define Vendor_Identification       _Vendor_Identification.Reg
0266 #define Processor_Initialization    _Processor_Initialization.Reg
0267 #define IPI_Vector_Priority(i)      _IPI_Vector_Priority[i].Reg
0268 #define Spurious_Vector         _Spurious_Vector.Reg
0269 #define Timer_Frequency         _Timer_Frequency.Reg
0270
0271 /* Timer Registers */
0272 #define Current_Count           _Current_Count.Reg
0273 #define Base_Count          _Base_Count.Reg
0274 #define Vector_Priority         _Vector_Priority.Reg
0275 #define Destination         _Destination.Reg
0276
0277 /* Interrupt Source Registers */
0278 #define Vector_Priority         _Vector_Priority.Reg
0279 #define Destination         _Destination.Reg
0280
0281     /*
0282      *  Vendor and Device IDs
0283      */
0284
0285 #define OPENPIC_VENDOR_ID_APPLE     0x14
0286 #define OPENPIC_DEVICE_ID_APPLE_HYDRA   0x46
0287
0288     /*
0289      *  OpenPIC Operations
0290      */
0291
0292 /*
0293  * Handle EPIC differences. Unfortunately, I don't know of an easy
0294  * way to tell an EPIC from a normal PIC at run-time. Therefore,
0295  * the BSP must enable a few quirks if it knows that an EPIC is being
0296  * used:
0297  *  - If the BSP uses the serial interrupt mode / 'multiplexer' then
0298  *    EOI must be delayed by at least 16 SRAM_CLK cycles to avoid
0299  *    spurious interrupts.
0300  *    It is the BSP's responsibility to set up an appropriate delay
0301  *    (in timebase-clock cycles) at init time using
0302  *    'openpic_set_eoi_delay()'. This is ONLY necessary when using
0303  *    an EPIC in serial mode.
0304  *  - The EPIC sources start at an offset of 16 in the register
0305  *    map, i.e., on an EPIC you'd say Sources[ x + 16 ] where
0306  *    on a PIC you would say Sources[ x ].
0307  *    Again, the BSP can set an offset that is used by the
0308  *    calls dealing with 'Interrupt Sources'
0309  *      openpic_enable_irq()
0310  *      openpic_disable_irq()
0311  *      openpic_initirq()
0312  *      openpic_mapirq()
0313  *      openpic_set_sense()
0314  *      openpic_get_source_priority()
0315  *      openpic_set_source_priority()
0316  *    the desired source offset parameter is passed to openpic_init().
0317  *
0318  * The routine 'openpic_set_eoi_delay()' returns the previous/old
0319  * value of the delay parameter.
0320  */
0321 extern unsigned openpic_set_eoi_delay(unsigned tb_cycles);
0322
0323
0324 /* Global Operations */
0325
0326 /* num_sources: number of sources to use; if zero this value
0327  * is read from the device, if nonzero the value read from
0328  * the device is overridden.
0329  * 'polarities' and 'senses' are arrays defining the desired
0330  * polarities (active hi [nonzero]/lo [zero]) and
0331  * senses (level [nonzero]/edge [zero]).
0332  * Either of the two array pointers may be NULL resulting
0333  * in the driver choosing default values of: 'active low'
0334  * and 'level sensitive', respectively.
0335  * NOTE: if you do pass arrays then their size must either
0336  *       match the number of sources read from the device or
0337  *       that value must be overridden by specifying
0338  *       a non-zero 'num_sources' parameter.
0339  *
0340  * Nonzero 'epic_freq' activates the EOI delay if the EPIC is
0341  * configured in serial mode (driver assumes firmware performs initial
0342  * EPIC setup). The BSP must pass the clock frequency of the EPIC
0343  * serial interface here.
0344  */
0345 extern void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq);
0346
0347 extern void openpic_reset(void);
0348 extern void openpic_enable_8259_pass_through(void);
0349 extern void openpic_disable_8259_pass_through(void);
0350 extern unsigned int openpic_irq(unsigned int cpu);
0351 extern void openpic_eoi(unsigned int cpu);
0352 extern unsigned int openpic_get_priority(unsigned int cpu);
0353 extern void openpic_set_priority(unsigned int cpu, unsigned int pri);
0354 extern unsigned int openpic_get_spurious(void);
0355 extern void openpic_set_spurious(unsigned int vector);
0356 extern void openpic_init_processor(unsigned int cpumask);
0357
0358 /* Interprocessor Interrupts */
0359 extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector);
0360 extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask);
0361
0362 /* Timer Interrupts */
0363 extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector);
0364 extern void openpic_settimer(unsigned int timer, unsigned int base_count, int irq_enable);
0365 extern unsigned int openpic_gettimer(unsigned int timer);
0366 extern void openpic_maptimer(unsigned int timer, unsigned int cpumask);
0367
0368 /* Interrupt Sources */
0369 extern void openpic_enable_irq(unsigned int irq);
0370 extern int  openpic_disable_irq(unsigned int irq);
0371 extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity,
0372                 int is_level);
0373 extern void openpic_mapirq(unsigned int irq, unsigned int cpumask);
0374 extern void openpic_set_sense(unsigned int irq, int sense);
0375 extern unsigned int openpic_get_source_priority(unsigned int irq);
0376 extern void openpic_set_source_priority(unsigned int irq, unsigned int pri);
0377
0378 #endif /* RTEMS_OPENPIC_H */