gen5200/start/cpuinit.c

0001 /*
0002  * RTEMS generic MPC5200 BSP
0003  *
0004  * This file contains the code to initialize the cpu.
0005  */
0006
0007 /*
0008  * Copyright (c) 2003 IPR Engineering
0009  * Copyright (c) 2005 embedded brains GmbH & Co. KG
0010  *
0011  * The license and distribution terms for this file may be
0012  * found in the file LICENSE in this distribution or at
0013  * http://www.rtems.org/license/LICENSE.
0014  */
0015
0016 #include <stdbool.h>
0017 #include <string.h>
0018
0019 #include <libcpu/powerpc-utility.h>
0020 #include <libcpu/mmu.h>
0021
0022 #include <bsp.h>
0023 #include <bsp/mpc5200.h>
0024
0025 #define SET_DBAT( n, uv, lv) \
0026   do { \
0027     PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \
0028     PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \
0029   } while (0)
0030
0031 static void calc_dbat_regvals(
0032   BAT *bat_ptr,
0033   uint32_t base_addr,
0034   uint32_t size,
0035   bool flg_w,
0036   bool flg_i,
0037   bool flg_m,
0038   bool flg_g,
0039   uint32_t flg_bpp
0040 )
0041 {
0042   uint32_t block_mask = 0xffffffff;
0043   uint32_t end_addr = base_addr + size - 1;
0044
0045   /* Determine block mask, that overlaps the whole block */
0046   while ((end_addr & block_mask) != (base_addr & block_mask)) {
0047     block_mask <<= 1;
0048   }
0049
0050   bat_ptr->batu.bepi = base_addr >> (32 - 15);
0051   bat_ptr->batu.bl   = ~(block_mask >> (28 - 11));
0052   bat_ptr->batu.vs   = 1;
0053   bat_ptr->batu.vp   = 1;
0054
0055   bat_ptr->batl.brpn = base_addr  >> (32 - 15);
0056   bat_ptr->batl.w    = flg_w;
0057   bat_ptr->batl.i    = flg_i;
0058   bat_ptr->batl.m    = flg_m;
0059   bat_ptr->batl.g    = flg_g;
0060   bat_ptr->batl.pp   = flg_bpp;
0061 }
0062
0063 static inline void enable_bat_4_to_7(void)
0064 {
0065   PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID2, BSP_BBIT32(13));
0066 }
0067
0068 static void cpu_init_bsp(void)
0069 {
0070   BAT dbat;
0071
0072 #if defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L)
0073   calc_dbat_regvals(
0074     &dbat,
0075     (uint32_t) bsp_ram_start,
0076     (uint32_t) bsp_ram_size,
0077     false,
0078     false,
0079     false,
0080     false,
0081     BPP_RW
0082   );
0083   SET_DBAT(0,dbat.batu,dbat.batl);
0084
0085   calc_dbat_regvals(
0086     &dbat,
0087     (uint32_t) bsp_rom_start,
0088     (uint32_t) bsp_rom_size,
0089     false,
0090     false,
0091     false,
0092     false,
0093     BPP_RX
0094   );
0095   SET_DBAT(1,dbat.batu,dbat.batl);
0096
0097   calc_dbat_regvals(
0098     &dbat,
0099     (uint32_t) MBAR,
0100     128 * 1024,
0101     false,
0102     true,
0103     false,
0104     true,
0105     BPP_RW
0106   );
0107   SET_DBAT(2,dbat.batu,dbat.batl);
0108 #elif defined (HAS_UBOOT)
0109   uint32_t start = 0;
0110
0111   /*
0112    * Accesses (also speculative accesses) outside of the RAM area are a
0113    * disaster especially in combination with the BestComm.  For safety reasons
0114    * we make the available RAM a little bit smaller to have an unused area at
0115    * the end.
0116    */
0117   bsp_uboot_board_info.bi_memsize -= 4 * 1024;
0118
0119   /*
0120    * Program BAT0 for RAM
0121    */
0122   calc_dbat_regvals(
0123     &dbat,
0124     bsp_uboot_board_info.bi_memstart,
0125     bsp_uboot_board_info.bi_memsize,
0126     false,
0127     false,
0128     false,
0129     false,
0130     BPP_RW
0131   );
0132   SET_DBAT(0,dbat.batu,dbat.batl);
0133
0134   /*
0135    * Program BAT1 for Flash
0136    *
0137    * WARNING!! Some Freescale LITE5200B boards ship with a version of
0138    * U-Boot that lies about the starting address of Flash.  This check
0139    * corrects that.
0140    */
0141   if ((bsp_uboot_board_info.bi_flashstart + bsp_uboot_board_info.bi_flashsize)
0142     < bsp_uboot_board_info.bi_flashstart) {
0143     start = 0 - bsp_uboot_board_info.bi_flashsize;
0144   } else {
0145     start = bsp_uboot_board_info.bi_flashstart;
0146   }
0147   calc_dbat_regvals(
0148     &dbat,
0149     start,
0150     bsp_uboot_board_info.bi_flashsize,
0151     false,
0152     false,
0153     false,
0154     false,
0155     BPP_RX
0156   );
0157   SET_DBAT(1,dbat.batu,dbat.batl);
0158
0159   /*
0160    * Program BAT2 for the MBAR
0161    */
0162   calc_dbat_regvals(
0163     &dbat,
0164     (uint32_t) MBAR,
0165     128 * 1024,
0166     false,
0167     true,
0168     false,
0169     true,
0170     BPP_RW
0171   );
0172   SET_DBAT(2,dbat.batu,dbat.batl);
0173
0174   /*
0175    * If there is SRAM, program BAT3 for that memory
0176    */
0177   if (bsp_uboot_board_info.bi_sramsize != 0) {
0178     calc_dbat_regvals(
0179       &dbat,
0180       bsp_uboot_board_info.bi_sramstart,
0181       bsp_uboot_board_info.bi_sramsize,
0182       false,
0183       true,
0184       true,
0185       true,
0186       BPP_RW
0187     );
0188     SET_DBAT(3,dbat.batu,dbat.batl);
0189   }
0190 #else
0191 #warning "Using BAT register values set by environment"
0192 #endif
0193
0194 #if defined(MPC5200_BOARD_DP2)
0195   enable_bat_4_to_7();
0196
0197   /* FPGA */
0198   calc_dbat_regvals(
0199     &dbat,
0200     0xf0020000,
0201     128 * 1024,
0202     false,
0203     true,
0204     false,
0205     true,
0206     BPP_RW
0207   );
0208   SET_DBAT(4, dbat.batu, dbat.batl);
0209 #elif defined(MPC5200_BOARD_PM520_ZE30)
0210   enable_bat_4_to_7();
0211
0212   /* External CC770 CAN controller available in version 2 */
0213   calc_dbat_regvals(
0214     &dbat,
0215     0xf2000000,
0216     128 * 1024,
0217     false,
0218     true,
0219     false,
0220     true,
0221     BPP_RW
0222   );
0223   SET_DBAT(4, dbat.batu, dbat.batl);
0224 #elif defined(MPC5200_BOARD_BRS5L)
0225   calc_dbat_regvals(
0226     &dbat,
0227     (uint32_t) bsp_dpram_start,
0228     128 * 1024,
0229     false,
0230     true,
0231     false,
0232     true,
0233     BPP_RW
0234   );
0235   SET_DBAT(3,dbat.batu,dbat.batl);
0236 #elif defined(MPC5200_BOARD_BRS6L)
0237   enable_bat_4_to_7();
0238
0239   /* FPGA */
0240   calc_dbat_regvals(
0241     &dbat,
0242     MPC5200_BRS6L_FPGA_BEGIN,
0243     MPC5200_BRS6L_FPGA_SIZE,
0244     false,
0245     true,
0246     false,
0247     true,
0248     BPP_RW
0249   );
0250   SET_DBAT(3,dbat.batu,dbat.batl);
0251
0252   /* MRAM */
0253   calc_dbat_regvals(
0254     &dbat,
0255     MPC5200_BRS6L_MRAM_BEGIN,
0256     MPC5200_BRS6L_MRAM_SIZE,
0257     true,
0258     false,
0259     false,
0260     false,
0261     BPP_RW
0262   );
0263   SET_DBAT(4,dbat.batu,dbat.batl);
0264 #endif
0265 }
0266
0267 void cpu_init(void)
0268 {
0269   uint32_t msr;
0270
0271   #if BSP_INSTRUCTION_CACHE_ENABLED
0272     rtems_cache_enable_instruction();
0273   #endif
0274
0275   /* Set up DBAT registers in MMU */
0276   cpu_init_bsp();
0277
0278   #if defined(SHOW_MORE_INIT_SETTINGS)
0279     { extern void ShowBATS(void);
0280       ShowBATS();
0281     }
0282   #endif
0283
0284   /* Read MSR */
0285   msr = ppc_machine_state_register();
0286
0287   /* Enable data MMU in MSR */
0288   msr |= MSR_DR;
0289
0290   /* Update MSR */
0291   ppc_set_machine_state_register( msr);
0292
0293   #if BSP_DATA_CACHE_ENABLED
0294     rtems_cache_enable_data();
0295   #endif
0296 }