gen5200/start/bspstart.c

0001 /*
0002  * RTEMS generic MPC5200 BSP
0003  *
0004  * This file contains the BSP initialization code
0005  *
0006  * This routine starts the application. It includes
0007  * application, board, and monitor specific
0008  * initialization and configuration. The generic CPU
0009  * dependent initialization has been performed before
0010  * this routine is invoked.
0011  *
0012  * The MPC860 specific stuff was written by Jay Monkman.
0013  * Modified for the MPC8260ADS board by Andy Dachs.
0014  *
0015  * A 40MHz system clock is assumed.
0016  * The PON. RST.CONF. Dip switches (DS1) are
0017  * 1 - Off
0018  * 2 - On
0019  * 3 - Off
0020  * 4 - On
0021  * 5 - Off
0022  * 6 - Off
0023  * 7 - Off
0024  * 8 - Off
0025  * Dip switches on DS2 and DS3 are all set to ON
0026  * The LEDs on the board are used to signal panic and fatal_error
0027  * conditions.
0028  * The mmu is unused at this time.
0029  */
0030
0031 /*
0032  * Copyright (c) 1989, 2007 On-Line Applications Research Corporation (OAR).
0033  *
0034  * Copyright (c) Jay Monkman (jmonkman@frasca.com)
0035  *
0036  * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>
0037  * Surrey Satellite Technology Limited
0038  *
0039  * Copyright (c) 2003 IPR Engineering
0040  *
0041  * Copyright (c) 2005 embedded brains GmbH & Co. KG
0042  *
0043  * The license and distribution terms for this file may be
0044  * found in the file LICENSE in this distribution or at
0045  * http://www.rtems.org/license/LICENSE.
0046  */
0047
0048 #include <rtems.h>
0049 #include <rtems/counter.h>
0050
0051 #include <libcpu/powerpc-utility.h>
0052
0053 #include <bsp.h>
0054 #include <bsp/vectors.h>
0055 #include <bsp/bootcard.h>
0056 #include <bsp/irq.h>
0057 #include <bsp/irq-generic.h>
0058 #include <bsp/mpc5200.h>
0059
0060 /* Configuration parameter for clock driver */
0061 uint32_t bsp_time_base_frequency;
0062
0063 /* Legacy */
0064 uint32_t bsp_clicks_per_usec;
0065
0066 uint32_t _CPU_Counter_frequency(void)
0067 {
0068   return bsp_time_base_frequency;
0069 }
0070
0071 void bsp_start(void)
0072 {
0073   /*
0074    * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
0075    * function store the result in global variables so that it can be used
0076    * later...
0077    */
0078   get_ppc_cpu_type();
0079   get_ppc_cpu_revision();
0080
0081   #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS)
0082     {
0083       void dumpUBootBDInfo( bd_t * );
0084       dumpUBootBDInfo( &bsp_uboot_board_info );
0085     }
0086   #endif
0087
0088   cpu_init();
0089
0090   if(get_ppc_cpu_revision() >= 0x2014) {
0091     /* Special settings for MPC5200B (B variant) */
0092     uint32_t xlb_cfg = mpc5200.config;
0093
0094     /* XXX: The Freescale documentation for BSDIS seems to be wrong */
0095     xlb_cfg |= XLB_CFG_BSDIS;
0096
0097     xlb_cfg &= ~XLB_CFG_PLDIS;
0098
0099     mpc5200.config = xlb_cfg;
0100   }
0101
0102   bsp_time_base_frequency = XLB_CLOCK / 4;
0103   bsp_clicks_per_usec    = (XLB_CLOCK/4000000);
0104
0105   /* Initialize exception handler */
0106   ppc_exc_cache_wb_check = 0;
0107   ppc_exc_initialize();
0108   ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
0109
0110   /* Initialize interrupt support */
0111   bsp_interrupt_initialize();
0112
0113   /*
0114    *  If the BSP was built with IRQ benchmarking enabled,
0115    *  then intialize it.
0116    */
0117   #if (BENCHMARK_IRQ_PROCESSING == 1)
0118     BSP_IRQ_Benchmarking_Reset();
0119   #endif
0120
0121   #ifdef SHOW_MORE_INIT_SETTINGS
0122     printk("Exit from bspstart\n");
0123   #endif
0124 }