gen5200/nvram/m93cxx.h

0001 /*
0002  * RTEMS generic MPC5200 BSP
0003  *
0004  * This file contains definitions for the M93Cxx EEPROM devices.
0005  *
0006  * M93C46 is a serial microwire EEPROM which contains
0007  * 1Kbit (128 bytes/64 words) of non-volatile memory.
0008  * The device can be configured for byte- or word-
0009  * access. The driver provides a file-like interface
0010  * to this memory.
0011  *
0012  * MPC5x00 PIN settings:
0013  *
0014  * PSC3_6 (output) -> MC93C46 serial data in    (D)
0015  * PSC3_7 (input)  -> MC93C46 serial data out   (Q)
0016  * PSC3_8 (output) -> MC93C46 chip select input (S)
0017  * PSC3_9 (output) -> MC93C46 serial clock      (C)
0018  */
0019
0020 /*
0021  * Copyright (c) 2005 embedded brains GmbH & Co. KG
0022  * Copyright (c) 2003 IPR Engineering
0023  *
0024  * The license and distribution terms for this file may be
0025  * found in the file LICENSE in this distribution or at
0026  * http://www.rtems.org/license/LICENSE.
0027  */
0028
0029 #ifndef __M93CXX_H__
0030 #define __M93CXX_H__
0031
0032 #ifdef __cplusplus
0033 extern "C" {
0034 #endif
0035
0036 static void m93cxx_enable_write(void);
0037 static void m93cxx_disable_write(void);
0038 static void m93cxx_write_byte(uint32_t, uint8_t);
0039 static uint8_t m93cxx_read_byte(uint32_t);
0040 void wait_usec(unsigned long);
0041
0042 #define M93CXX_MODE_WORD
0043 /*#define M93C46_MODE_BYTE*/
0044 #define M93C46
0045 #define M93C46_NVRAM_SIZE 128
0046
0047 #define GPIO_PSC3_6 (1 << 12)
0048 #define GPIO_PSC3_7 (1 << 13)
0049 #define GPIO_PSC3_8 (1 << 26)
0050 #define GPIO_PSC3_9 (1 << 26)
0051
0052 #define START_BIT    0x1
0053 #define EWDS_OPCODE  0x0
0054 #define WRAL_OPCODE  0x1
0055 #define ERAL_OPCODE  0x2
0056 #define EWEN_OPCODE  0x3
0057 #define WRITE_OPCODE 0x4
0058 #define READ_OPCODE  0x8
0059 #define ERASE_OPCODE 0xC
0060
0061 #define WAIT(i) wait_usec(i)
0062
0063 #define ENABLE_CHIP_SELECT        mpc5200.gpiosido |= GPIO_PSC3_8
0064 #define DISABLE_CHIP_SELECT       mpc5200.gpiosido &= ~GPIO_PSC3_8
0065 #define SET_DATA_BIT_HIGH         mpc5200.gpiosdo  |= GPIO_PSC3_6
0066 #define SET_DATA_BIT_LOW          mpc5200.gpiosdo  &= ~GPIO_PSC3_6
0067
0068 #ifdef M93CXX_MODE_BYTE
0069 #define GET_DATA_BYTE_SHIFT(val)  ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
0070                                   ((val) <<= 1)
0071 #define SET_DATA_BYTE_SHIFT(val)  (((val) & 0x80) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
0072                                   ((val) <<= 1)
0073 #else
0074 #define GET_DATA_WORD_SHIFT(val)  ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
0075                                   ((val) <<= 1)
0076 #define SET_DATA_WORD_SHIFT(val)  (((val) & 0x8000) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
0077                                   ((val) <<= 1)
0078 #endif
0079
0080 #define MASK_HEAD_SHIFT(head)     ((((head) & 0x80000000) >> 31) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
0081                                   ((head) <<= 1)
0082 #define DO_CLOCK_CYCLE            mpc5200.gpiowdo  |= GPIO_PSC3_9; \
0083                                   WAIT(1000); \
0084                                   mpc5200.gpiowdo  &= ~GPIO_PSC3_9
0085 #define CHECK_WRITE_BUSY          while(!(mpc5200.gpiosdi & GPIO_PSC3_7))
0086
0087
0088 #ifdef M93CXX_MODE_BYTE
0089 #ifdef M93C46
0090 #define M93C46_EWDS         ((START_BIT << 31) | (EWDS_OPCODE << 27))
0091 #define M93C46_WRAL         ((START_BIT << 31) | (WRAL_OPCODE << 27))
0092 #define M93C46_ERAL         ((START_BIT << 31) | (ERAL_OPCODE << 27))
0093 #define M93C46_EWEN         ((START_BIT << 31) | (EWEN_OPCODE << 27))
0094 #define M93C46_READ(addr)   ((START_BIT << 31) | (READ_OPCODE << 27)  | ((addr) << 22))
0095 #define M93C46_WRITE(addr)  ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 22))
0096 #define M93C46_ERASE(addr)  ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 22))
0097 #define M93C46_CLOCK_CYCLES 10
0098 #endif
0099 #else
0100 #ifdef M93C46
0101 #define M93C46_EWDS         ((START_BIT << 31) | (EWDS_OPCODE << 27))
0102 #define M93C46_WRAL         ((START_BIT << 31) | (WRAL_OPCODE << 27))
0103 #define M93C46_ERAL         ((START_BIT << 31) | (ERAL_OPCODE << 27))
0104 #define M93C46_EWEN         ((START_BIT << 31) | (EWEN_OPCODE << 27))
0105 #define M93C46_READ(addr)   ((START_BIT << 31) | (READ_OPCODE << 27)  | ((addr) << 23))
0106 #define M93C46_WRITE(addr)  ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 23))
0107 #define M93C46_ERASE(addr)  ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 23))
0108 #define M93C46_CLOCK_CYCLES 9
0109 #endif
0110 #endif
0111
0112 #ifdef __cplusplus
0113 }
0114 #endif
0115
0116 #endif /* __M93CXX_H__ */