gen5200/include/tm27.h

0001 /*
0002  * @file
0003  * @ingroup powerpc_gen5200
0004  * @brief Implementations for interrupt mechanisms for Time Test 27
0005  */
0006
0007 /*
0008  *  The license and distribution terms for this file may be
0009  *  found in the file LICENSE in this distribution or at
0010  *  http://www.rtems.org/license/LICENSE.
0011  */
0012
0013 #ifndef _RTEMS_TMTEST27
0014 #error "This is an RTEMS internal file you must not include directly."
0015 #endif
0016
0017 #ifndef __tm27_h
0018 #define __tm27_h
0019
0020 #include <bsp/fatal.h>
0021 #include <bsp/irq.h>
0022
0023 /*
0024  *  Stuff for Time Test 27
0025  */
0026
0027 #define MUST_WAIT_FOR_INTERRUPT 1
0028
0029 static void nullFunc(void) {}
0030
0031 static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
0032                                               0,
0033                                               (rtems_irq_enable) nullFunc,
0034                                               (rtems_irq_disable) nullFunc,
0035                                               (rtems_irq_is_enabled) nullFunc};
0036
0037 static inline void Install_tm27_vector( rtems_interrupt_handler handler )
0038 {
0039   clockIrqData.hdl = handler;
0040   if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
0041     printk("Error installing clock interrupt handler!\n");
0042     bsp_fatal(MPC5200_FATAL_TM27_IRQ_INSTALL);
0043   }
0044 }
0045
0046 #define Cause_tm27_intr()  \
0047   do { \
0048     uint32_t   _clicks = 8; \
0049     __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
0050   } while (0)
0051
0052 #define Clear_tm27_intr() \
0053   do { \
0054     uint32_t   _clicks = 0xffffffff; \
0055     __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
0056   } while (0)
0057
0058 #define Lower_tm27_intr() \
0059   do { \
0060     uint32_t   _msr = 0; \
0061     _ISR_Set_level( 0 ); \
0062     __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
0063     _msr |=  0x8002; \
0064     __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
0065   } while (0)
0066
0067 #endif