include/bsp/irq.h

0001 /*
0002  * RTEMS generic MPC5200 BSP
0003  *
0004  * This file contains declarations for the irq controller handler.
0005  *
0006  * References: MPC8260ads CPU interrupt header file.
0007  * Comment for that:
0008  *
0009  *   This code is heavilly inspired by the public specification of
0010  *   STREAM V2 that can be found at:
0011  *
0012  *   <http://www.chorus.com/Documentation/index.html> by following
0013  *   the STREAM API Specification Document link.
0014  *
0015  *   The interrupt handling on the mpc8260 seems quite different from
0016  *   the 860 (I don't know the 860 well).  Although some interrupts
0017  *   are routed via the CPM irq and some are direct to the SIU they
0018  *   all appear logically the same.Therefore I removed the distinction
0019  *   between SIU and CPM interrupts.
0020  */
0021
0022 /*
0023  * Copyright (C) 1999 valette@crf.canon.fr
0024  *
0025  * Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>
0026  * Surrey Satellite Technology Limited
0027  *
0028  * Copyright (c) 2003 IPR Engineering
0029  *
0030  * Copyright (C) 2005, 2010 embedded brains GmbH & Co. KG
0031  *
0032  * The license and distribution terms for this file may be
0033  * found in the file LICENSE in this distribution or at
0034  * http://www.rtems.org/license/LICENSE.
0035  */
0036
0037 #ifndef LIBBSP_POWERPC_GEN5200_IRQ_H
0038 #define LIBBSP_POWERPC_GEN5200_IRQ_H
0039
0040 #define PMCE_CE_SHADOW (1U << (31 - 31))
0041 #define PMCE_CSE_STICKY (1U << (31 - 21))
0042 #define PMCE_MSE_STICKY (1U << (31 - 10))
0043 #define PMCE_PSE_STICKY (1U << (31 - 2))
0044 #define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U)
0045 #define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU)
0046 #define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU)
0047
0048 /*
0049  * Peripheral IRQ handlers related definitions
0050  */
0051 #define BSP_PER_IRQ_NUMBER      22
0052 #define BSP_PER_IRQ_LOWEST_OFFSET   0
0053 #define BSP_PER_IRQ_MAX_OFFSET      \
0054     (BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */
0055 /*
0056  * Main IRQ handlers related definitions
0057  */
0058 #define BSP_MAIN_IRQ_NUMBER     17
0059 #define BSP_MAIN_IRQ_LOWEST_OFFSET  BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */
0060 #define BSP_MAIN_IRQ_MAX_OFFSET     \
0061     (BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */
0062 /*
0063  * Critical IRQ handlers related definitions
0064  */
0065 #define BSP_CRIT_IRQ_NUMBER     4
0066 #define BSP_CRIT_IRQ_LOWEST_OFFSET  BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */
0067 #define BSP_CRIT_IRQ_MAX_OFFSET     \
0068     (BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */
0069 /*
0070  * Summary of SIU interrupts
0071  */
0072 #define BSP_SIU_IRQ_NUMBER      BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */
0073 #define BSP_SIU_IRQ_LOWEST_OFFSET   BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
0074 #define BSP_SIU_IRQ_MAX_OFFSET      BSP_CRIT_IRQ_MAX_OFFSET  /* 42 */
0075 /*
0076  * Processor IRQ handlers related definitions
0077  */
0078 #define BSP_PROCESSOR_IRQ_NUMBER    3
0079 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44  */
0080 #define BSP_PROCESSOR_IRQ_MAX_OFFSET    \
0081         (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */
0082 /*
0083  * Summary
0084  */
0085 #define BSP_IRQ_NUMBER      BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */
0086 #define BSP_LOWEST_OFFSET   BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
0087 #define BSP_MAX_OFFSET      BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */
0088
0089 #ifndef ASM
0090
0091 #include <rtems.h>
0092 #include <rtems/irq.h>
0093 #include <rtems/irq-extension.h>
0094
0095 /*
0096  * index table for the module specific handlers, a few entries are only placeholders
0097  */
0098 typedef enum {
0099   BSP_SIU_IRQ_SMARTCOMM     = BSP_PER_IRQ_LOWEST_OFFSET + 0,
0100   BSP_SIU_IRQ_PSC1      = BSP_PER_IRQ_LOWEST_OFFSET + 1,
0101   BSP_SIU_IRQ_PSC2      = BSP_PER_IRQ_LOWEST_OFFSET + 2,
0102   BSP_SIU_IRQ_PSC3      = BSP_PER_IRQ_LOWEST_OFFSET + 3,
0103   BSP_SIU_IRQ_PSC6      = BSP_PER_IRQ_LOWEST_OFFSET + 4,
0104   BSP_SIU_IRQ_ETH       = BSP_PER_IRQ_LOWEST_OFFSET + 5,
0105   BSP_SIU_IRQ_USB       = BSP_PER_IRQ_LOWEST_OFFSET + 6,
0106   BSP_SIU_IRQ_ATA       = BSP_PER_IRQ_LOWEST_OFFSET + 7,
0107   BSP_SIU_IRQ_PCI_CRT       = BSP_PER_IRQ_LOWEST_OFFSET + 8,
0108   BSP_SIU_IRQ_PCI_SC_RX         = BSP_PER_IRQ_LOWEST_OFFSET + 9,
0109   BSP_SIU_IRQ_PCI_SC_TX         = BSP_PER_IRQ_LOWEST_OFFSET + 10,
0110   BSP_SIU_IRQ_PSC4      = BSP_PER_IRQ_LOWEST_OFFSET + 11,
0111   BSP_SIU_IRQ_PSC5      = BSP_PER_IRQ_LOWEST_OFFSET + 12,
0112   BSP_SIU_IRQ_SPI_MODF          = BSP_PER_IRQ_LOWEST_OFFSET + 13,
0113   BSP_SIU_IRQ_SPI_SPIF          = BSP_PER_IRQ_LOWEST_OFFSET + 14,
0114   BSP_SIU_IRQ_I2C1      = BSP_PER_IRQ_LOWEST_OFFSET + 15,
0115   BSP_SIU_IRQ_I2C2      = BSP_PER_IRQ_LOWEST_OFFSET + 16,
0116   BSP_SIU_IRQ_MSCAN1        = BSP_PER_IRQ_LOWEST_OFFSET + 17,
0117   BSP_SIU_IRQ_MSCAN2        = BSP_PER_IRQ_LOWEST_OFFSET + 18,
0118   BSP_SIU_IRQ_IR_RX     = BSP_PER_IRQ_LOWEST_OFFSET + 19,
0119   BSP_SIU_IRQ_IR_TX     = BSP_PER_IRQ_LOWEST_OFFSET + 20,
0120   BSP_SIU_IRQ_XLB_ARB       = BSP_PER_IRQ_LOWEST_OFFSET + 21,
0121
0122   /* SL_TIMER1 -- handler entry only used in case of SMI */
0123   BSP_SIU_IRQ_SL_TIMER1         = BSP_MAIN_IRQ_LOWEST_OFFSET + 0,
0124   BSP_SIU_IRQ_IRQ1      = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
0125   BSP_SIU_IRQ_IRQ2      = BSP_MAIN_IRQ_LOWEST_OFFSET + 2,
0126   BSP_SIU_IRQ_IRQ3      = BSP_MAIN_IRQ_LOWEST_OFFSET + 3,
0127   /* LO_INT --  handler entry never used (only placeholder) */
0128   BSP_SIU_IRQ_LO_INT        = BSP_MAIN_IRQ_LOWEST_OFFSET + 4,
0129   BSP_SIU_IRQ_RTC_PER       = BSP_MAIN_IRQ_LOWEST_OFFSET + 5,
0130   BSP_SIU_IRQ_RTC_STW       = BSP_MAIN_IRQ_LOWEST_OFFSET + 6,
0131   BSP_SIU_IRQ_GPIO_STD      = BSP_MAIN_IRQ_LOWEST_OFFSET + 7,
0132   BSP_SIU_IRQ_GPIO_WKUP     = BSP_MAIN_IRQ_LOWEST_OFFSET + 8,
0133   BSP_SIU_IRQ_TMR0      = BSP_MAIN_IRQ_LOWEST_OFFSET + 9,
0134   BSP_SIU_IRQ_TMR1      = BSP_MAIN_IRQ_LOWEST_OFFSET + 10,
0135   BSP_SIU_IRQ_TMR2      = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
0136   BSP_SIU_IRQ_TMR3      = BSP_MAIN_IRQ_LOWEST_OFFSET + 12,
0137   BSP_SIU_IRQ_TMR4      = BSP_MAIN_IRQ_LOWEST_OFFSET + 13,
0138   BSP_SIU_IRQ_TMR5      = BSP_MAIN_IRQ_LOWEST_OFFSET + 14,
0139   BSP_SIU_IRQ_TMR6      = BSP_MAIN_IRQ_LOWEST_OFFSET + 15,
0140   BSP_SIU_IRQ_TMR7      = BSP_MAIN_IRQ_LOWEST_OFFSET + 16,
0141
0142   BSP_SIU_IRQ_IRQ0      = BSP_CRIT_IRQ_LOWEST_OFFSET + 0,
0143   BSP_SIU_IRQ_SL_TIMER0     = BSP_CRIT_IRQ_LOWEST_OFFSET + 1,
0144   /* HI_INT -- handler entry never used (only placeholder) */
0145   BSP_SIU_IRQ_HI_INT        = BSP_CRIT_IRQ_LOWEST_OFFSET + 2,
0146   BSP_SIU_IRQ_CSS_WKUP      = BSP_CRIT_IRQ_LOWEST_OFFSET + 3,
0147
0148   BSP_DECREMENTER       = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
0149   BSP_SYSMGMT           = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
0150   BSP_EXT                   = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
0151 } rtems_irq_symbolic_name;
0152
0153 #define BSP_CRIT_IRQ_PRIO_LEVELS              4
0154 #define BSP_PERIODIC_TIMER                    BSP_SIU_IRQ_TMR6
0155
0156 #define BSP_INTERRUPT_VECTOR_COUNT (BSP_MAX_OFFSET + 1)
0157
0158 #endif
0159
0160 #endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */