gen5200/include/bsp.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsPowerPCGen5200
0007  *
0008  * @brief Global BSP definitions.
0009  */
0010
0011 /*
0012  * RTEMS generic MPC5200 BSP
0013  *
0014  * This file contains board specific definitions.
0015  */
0016
0017 /*
0018  * Copyright (c) 2005 embedded brains GmbH & Co. KG
0019  *
0020  * Redistribution and use in source and binary forms, with or without
0021  * modification, are permitted provided that the following conditions
0022  * are met:
0023  * 1. Redistributions of source code must retain the above copyright
0024  *    notice, this list of conditions and the following disclaimer.
0025  * 2. Redistributions in binary form must reproduce the above copyright
0026  *    notice, this list of conditions and the following disclaimer in the
0027  *    documentation and/or other materials provided with the distribution.
0028  *
0029  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0030  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0031  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0032  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0033  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 #ifndef LIBBSP_POWERPC_GEN5200_BSP_H
0043 #define LIBBSP_POWERPC_GEN5200_BSP_H
0044
0045 /**
0046  * @defgroup RTEMSBSPsPowerPCGen5200 NXP MPC5200
0047  *
0048  * @ingroup RTEMSBSPsPowerPC
0049  *
0050  * @brief NXP MPC5200 Board Support Package.
0051  *
0052  * @{
0053  */
0054
0055 #include <bspopts.h>
0056
0057 #include <libcpu/powerpc-utility.h>
0058
0059 /*
0060  * Some symbols defined in the linker command file.
0061  */
0062
0063 LINKER_SYMBOL(bsp_ram_start);
0064 LINKER_SYMBOL(bsp_ram_end);
0065 LINKER_SYMBOL(bsp_ram_size);
0066
0067 LINKER_SYMBOL(bsp_rom_start);
0068 LINKER_SYMBOL(bsp_rom_end);
0069 LINKER_SYMBOL(bsp_rom_size);
0070
0071 LINKER_SYMBOL(bsp_dpram_start);
0072 LINKER_SYMBOL(bsp_dpram_end);
0073 LINKER_SYMBOL(bsp_dpram_size);
0074
0075 LINKER_SYMBOL(bsp_section_text_start);
0076 LINKER_SYMBOL(bsp_section_text_end);
0077 LINKER_SYMBOL(bsp_section_text_size);
0078
0079 LINKER_SYMBOL(bsp_section_data_start);
0080 LINKER_SYMBOL(bsp_section_data_end);
0081 LINKER_SYMBOL(bsp_section_data_size);
0082
0083 LINKER_SYMBOL(bsp_section_bss_start);
0084 LINKER_SYMBOL(bsp_section_bss_end);
0085 LINKER_SYMBOL(bsp_section_bss_size);
0086
0087 LINKER_SYMBOL(bsp_work_area_start);
0088
0089 LINKER_SYMBOL(MBAR);
0090
0091 /* Provide legacy defines */
0092
0093 #ifdef MPC5200_BOARD_PM520_ZE30
0094 #define PM520_ZE30
0095 #endif
0096
0097 #ifdef MPC5200_BOARD_PM520_CR825
0098 #define PM520_CR825
0099 #endif
0100
0101 #ifdef MPC5200_BOARD_ICECUBE
0102 #define icecube
0103 #endif
0104
0105 #ifdef MPC5200_BOARD_BRS5L
0106 #define BRS5L
0107 #endif
0108
0109 /*
0110  * distinguish board characteristics
0111  */
0112 /*
0113  * for PM520 mdule on a ZE30 carrier
0114  */
0115 #if defined(MPC5200_BOARD_PM520_ZE30)
0116 #define PM520
0117 #endif
0118 /*
0119  * for PM520 mdule on a CR825 carrier
0120  */
0121 #if defined(MPC5200_BOARD_PM520_CR825)
0122 #define PM520
0123 #endif
0124
0125 #if !defined(HAS_UBOOT)
0126   /* we need the low level initialization in start.S*/
0127   #define NEED_LOW_LEVEL_INIT
0128 #endif
0129
0130 #if defined(MPC5200_BOARD_BRS5L)
0131 /*
0132  * IMD Custom Board BRS5L
0133  */
0134
0135 #define HAS_NVRAM_93CXX
0136
0137 #elif defined(MPC5200_BOARD_BRS6L)
0138   #define MPC5200_BRS6L_FPGA_BEGIN 0x800000
0139   #define MPC5200_BRS6L_FPGA_SIZE (64 * 1024)
0140   #define MPC5200_BRS6L_FPGA_END \
0141     (MPC5200_BRS6L_FPGA_BEGIN + MPC5200_BRS6L_FPGA_SIZE)
0142
0143   #define MPC5200_BRS6L_MRAM_BEGIN 0xff000000
0144   #define MPC5200_BRS6L_MRAM_SIZE (4 * 1024 * 1024)
0145   #define MPC5200_BRS6L_MRAM_END \
0146     (MPC5200_BRS6L_MRAM_BEGIN + MPC5200_BRS6L_MRAM_SIZE)
0147 #elif defined (PM520)
0148
0149 /* Nothing special */
0150
0151 #elif defined (MPC5200_BOARD_ICECUBE)
0152 /*
0153  *  Codename: IceCube
0154  *  Compatible Boards:
0155  *     Freescape MPC5200LITE
0156  *     Embedded Planet EP5200
0157  */
0158
0159 #elif defined (MPC5200_BOARD_DP2)
0160
0161 /* Nothing special */
0162
0163 #else
0164 #error "board type not defined"
0165 #endif
0166
0167 #ifndef ASM
0168
0169 #include <rtems.h>
0170 #include <bsp/i2cdrv.h>
0171 #include <bsp/irq.h>
0172 #include <bsp/vectors.h>
0173 #include <bsp/u-boot.h>
0174 #include <bsp/default-initial-extension.h>
0175
0176 #ifdef __cplusplus
0177 extern "C" {
0178 #endif
0179
0180 /*
0181  * Network driver configuration
0182  */
0183 struct rtems_bsdnet_ifconfig;
0184 extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching);
0185 #define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth1"
0186 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc5200_fec_driver_attach_detach
0187
0188 /* miscellaneous stuff assumed to exist */
0189
0190 /*
0191  * We need to decide how much memory will be non-cacheable. This
0192  * will mainly be memory that will be used in DMA (network and serial
0193  * buffers).
0194  */
0195 /*
0196 #define NOCACHE_MEM_SIZE 512*1024
0197 */
0198
0199 /*
0200  *  Device Driver Table Entries
0201  */
0202
0203 #ifdef HAS_NVRAM_93CXX
0204 #define NVRAM_DRIVER_TABLE_ENTRY \
0205   { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \
0206     nvram_driver_read, nvram_driver_write, NULL }
0207 #endif
0208
0209 /*
0210  * indicate, that BSP has IDE driver
0211  */
0212 #define RTEMS_BSP_HAS_IDE_DRIVER
0213
0214 /* functions */
0215
0216 /* #define SHOW_MORE_INIT_SETTINGS 1 */
0217
0218 /* ata modes */
0219 /* #undef ATA_USE_INT */
0220 #define ATA_USE_INT
0221
0222 /* clock settings */
0223 #if defined(HAS_UBOOT)
0224 #define IPB_CLOCK (bsp_uboot_board_info.bi_ipbfreq)
0225 #define XLB_CLOCK (bsp_uboot_board_info.bi_busfreq)
0226 #define G2_CLOCK  (bsp_uboot_board_info.bi_intfreq)
0227 #elif defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L)
0228 #define IPB_CLOCK 66000000   /* 66 MHz */
0229 #define XLB_CLOCK 132000000  /* 132 MHz */
0230 #define G2_CLOCK  396000000  /* 396 MHz */
0231 #else
0232 #define IPB_CLOCK 33000000   /* 33 MHz */
0233 #define XLB_CLOCK 66000000   /* 66 MHz */
0234 #define G2_CLOCK  231000000  /* 231 MHz */
0235 #endif
0236
0237 #if defined(HAS_UBOOT)
0238 #define GEN5200_CONSOLE_BAUD (bsp_uboot_board_info.bi_baudrate)
0239 #else
0240 #define GEN5200_CONSOLE_BAUD 115200
0241 #endif
0242
0243 /*
0244  *  Convert decrement value to tenths of microsecnds (used by
0245  *  shared timer driver).
0246  *
0247  *    + CPU has a XLB_CLOCK bus,
0248  *    + There are 4 bus cycles per click
0249  *    + We return value in 1/10 microsecond units.
0250  *   Modified following equation to integer equation to remove
0251  *   floating point math.
0252  *   (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
0253  */
0254
0255 #define BSP_Convert_decrementer( _value ) \
0256   (int) (((_value) * 4000) / (XLB_CLOCK/10000))
0257
0258 /* slicetimer settings */
0259 #define USE_SLICETIMER_0     TRUE
0260 #define USE_SLICETIMER_1     FALSE
0261
0262 void *bsp_idle_thread( uintptr_t ignored );
0263 #define BSP_IDLE_TASK_BODY bsp_idle_thread
0264
0265 /* BSP specific IRQ Benchmarking support */
0266 void BSP_IRQ_Benchmarking_Reset(void);
0267 void BSP_IRQ_Benchmarking_Report(void);
0268
0269 #if defined(HAS_UBOOT)
0270   /* Routine to obtain U-Boot environment variables */
0271   const char *bsp_uboot_getenv(
0272     const char *name
0273   );
0274 #endif
0275
0276 void cpu_init(void);
0277
0278 int mpc5200_eth_mii_read(
0279   int phyAddr,
0280   void *arg,
0281   unsigned regAddr,
0282   uint32_t *retVal
0283 );
0284
0285 #ifdef __cplusplus
0286 }
0287 #endif
0288
0289 #endif /* ASM */
0290
0291 /** @} */
0292
0293 #endif /* GEN5200 */